Substrate, manufacturing method thereof and semiconductor device

Abstract

The invention provides a substrate and a manufacturing method thereof, and a semiconductor device. The substrate comprises a first substrate; the thickness of the second substrate is smaller than that of the first substrate; the first dielectric layer and the second dielectric layer are arranged between the first substrate and the second substrate and connect the first substrate and the second substrate, and the heat conductivity coefficient of the second dielectric layer is higher than that of the first dielectric layer. According to the scheme, the first dielectric layer and the second dielectric layer are formed between the first substrate and the second substrate, the heat conductivity coefficient of the second dielectric layer is higher than that of the first dielectric layer, and the heat dissipation performance of the substrate can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a substrate and a method for manufacturing the same, and a semiconductor device. Background Art

[0002] Silicon-On-Insulator (SOI) technology introduces an insulating layer, such as a silicon oxide layer, between the bottom silicon layer and the top silicon layer. When a semiconductor film layer is formed on the insulating layer of the SOI substrate, the device isolation of the components in the integrated circuit can be achieved due to the formation of the insulating layer, and the parasitic latch effect in the bulk silicon complementary metal oxide semiconductor circuit (CMOS) can be completely eliminated; at the same time, the integrated circuit using the SOI substrate process also has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, and suitable for low voltage and low power consumption circuits.

[0003] However, the heat dissipation performance of the SOI substrate in the related art is poor, and the poor heat dissipation performance will lead to problems such as a decrease in the channel current of the semiconductor device on the SOI substrate and the formation of negative differential resistance. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In order to at least partially solve the above technical problems, the present application provides a substrate, including:

[0006] first base;

[0007] a second substrate, wherein the thickness of the second substrate is smaller than the thickness of the first substrate;

[0008] The first medium layer and the second medium layer are arranged between the first substrate and the second substrate to connect the first substrate and the second substrate, wherein the thermal conductivity of the second medium layer is higher than the thermal conductivity of the first medium layer.

[0009] In one example, the second dielectric layer contacts the second substrate; or

[0010] The second dielectric layer contacts the first substrate; or

[0011] The number of layers of the second dielectric layer is at least two, wherein one layer of the second dielectric layer contacts the first substrate, and one layer of the second dielectric layer contacts the second substrate; or

[0012] The number of the first dielectric layer is at least two, wherein one of the first dielectric layers contacts the first substrate, and one of the first dielectric layers contacts the second substrate.

[0013] In one example, the second dielectric layer includes a main body layer and at least one protrusion protruding from a surface of the main body layer, wherein the main body layer covers the first dielectric layer, and the protrusion is located in the first dielectric layer.

[0014] In one example, when the second dielectric layer has a plurality of the protrusions, the plurality of the protrusions are arranged in an array; and / or

[0015] The distances between two different adjacent protrusions are the same or different; and / or

[0016] The distance between two adjacent protrusions ranges from 4.5 mm to 5.5 mm.

[0017] In one example, the length of the protrusion ranges from 0.9um to 1.1um, the width of the protrusion ranges from 0.4um to 0.6um, and the thickness of the protrusion ranges from 0.4um to 0.6um; and / or

[0018] The thickness of the main layer ranges from 0.15um to 0.25um.

[0019] In one example, the thickness of the main layer is 15% to 25% of the thickness of the first dielectric layer; and / or

[0020] The thickness of the protruding portion is 30% to 70% of the thickness of the first dielectric layer.

[0021] In one example, the material of the first dielectric layer includes silicon oxide;

[0022] The material of the second dielectric layer includes metal oxide, metal nitride or boron nitride, wherein the metal oxide and the metal nitride include at least one of the following: magnesium oxide, aluminum oxide and aluminum nitride.

[0023] Another aspect of the present application provides a method for manufacturing a substrate, the method comprising:

[0024] providing a first substrate and a second substrate;

[0025] forming a first dielectric layer and a second dielectric layer on a surface of at least one of the first substrate and the second substrate, wherein the thermal conductivity of the second dielectric layer is higher than the thermal conductivity of the first dielectric layer;

[0026] Bonding the first substrate to the second substrate, wherein the first dielectric layer and the second dielectric layer are located between the first substrate and the second substrate;

[0027] A predetermined thickness of the second substrate or the first substrate is removed so that a thickness of one of the second substrate and the first substrate is smaller than a thickness of the other.

[0028] In one example, forming a first dielectric layer and a second dielectric layer on a surface of at least one of the first substrate and the second substrate includes:

[0029] forming the first dielectric layer and the second dielectric layer in sequence on the first substrate or the second substrate; or

[0030] forming the second dielectric layer and the first dielectric layer in sequence on the first substrate or the second substrate; or

[0031] forming the first dielectric layer and the second dielectric layer on the first substrate and the second substrate respectively; or

[0032] The second dielectric layer and the first dielectric layer are formed in sequence on the first substrate and the second substrate respectively.

[0033] In another aspect, the present application provides a method for manufacturing a substrate, the method comprising:

[0034] providing a first substrate;

[0035] forming a first dielectric layer and a second dielectric layer on the surface of the first substrate, wherein the thermal conductivity of the second dielectric layer is higher than the thermal conductivity of the first dielectric layer;

[0036] A second substrate is formed by deposition on a side of the first substrate where the first dielectric layer and the second dielectric layer are formed, wherein a thickness of the second substrate is smaller than a thickness of the first substrate.

[0037] In one example, when the first dielectric layer is formed first and the second dielectric layer is formed later, after forming the first dielectric layer and before forming the second dielectric layer, the method further includes:

[0038] The first dielectric layer is etched to form at least one groove in the first dielectric layer, and the second dielectric layer covers the first dielectric layer and fills the groove to form a main layer located on the first dielectric layer and at least one protrusion extending into the first dielectric layer; or,

[0039] When the second dielectric layer is formed first and the first dielectric layer is formed later, after forming the second dielectric layer and before forming the first dielectric layer, the method further includes:

[0040] Etching a portion of the thickness of the second dielectric layer to form a main layer and at least one protrusion protruding from a surface of the main layer;

[0041] After forming the first dielectric layer, the first dielectric layer at least covers the area outside the protrusion and the top surface of the first dielectric layer is not lower than the top surface of the protrusion, so that the protrusion extends into the first dielectric layer.

[0042] In one example, when the first dielectric layer is formed first and the second dielectric layer is formed later, after forming the first dielectric layer and before forming the second dielectric layer, the method further includes:

[0043] The first dielectric layer is etched to form at least one groove in the first dielectric layer, and the second dielectric layer fills the groove to form at least one protrusion extending into the first dielectric layer; or,

[0044] When the second dielectric layer is formed first and the first dielectric layer is formed later, after the second dielectric layer is formed and before the first dielectric layer is formed, the method further includes:

[0045] Etching the second dielectric layer to form at least one protrusion;

[0046] After forming the first dielectric layer, the first dielectric layer covers the area outside the protrusion and the top surface of the first dielectric layer is not lower than the top surface of the protrusion, so that the protrusion extends into the first dielectric layer.

[0047] Another aspect of the present application provides a semiconductor device, including the aforementioned substrate, or including a substrate manufactured using the aforementioned manufacturing method.

[0048] The substrate and its manufacturing method, and the semiconductor device of the present application form a first dielectric layer and a second dielectric layer between the first base and the second base, wherein the thermal conductivity of the second dielectric layer is higher than the thermal conductivity of the first dielectric layer, which can effectively improve the heat dissipation performance of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The following drawings of the present application are used as a part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, which are used to explain the principle of the present application.

[0050] In the attached figure:

[0051] Figure 1 A cross-sectional schematic diagram of a related art SOI substrate is shown;

[0052] Figure 2A-2C A schematic cross-sectional view of a substrate obtained by sequentially implementing a method for manufacturing a substrate according to an exemplary embodiment of the present application is shown;

[0053] Figure 3A-3C A schematic cross-sectional view of a substrate obtained by sequentially implementing a method for manufacturing a substrate according to another exemplary embodiment of the present application is shown;

[0054] Figure 4A-4C A schematic cross-sectional view of a substrate obtained by sequentially implementing a method for manufacturing a substrate according to another exemplary embodiment of the present application is shown;

[0055] Figure 5A-Figure 5C A schematic cross-sectional view of a substrate obtained by sequentially implementing a method for manufacturing a substrate according to another exemplary embodiment of the present application is shown;

[0056] Figure 6 A flow chart showing a method for manufacturing a substrate according to an exemplary embodiment of the present application;

[0057] Figure 7 A flow chart showing a method for manufacturing a substrate according to another exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0058] Next, the present application will be described more completely in conjunction with the accompanying drawings, in which embodiments of the present application are shown. However, the present application can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated. The same reference numerals throughout represent the same elements.

[0059] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0060] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0061] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] Embodiments of the application are described herein with reference to cross-sectional views as schematic diagrams of ideal embodiments (and intermediate structures) of the application. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. Therefore, the zones shown in the figures are schematic in nature, and their shapes are not intended to display the actual shapes of the zones of the device and are not intended to limit the scope of the application.

[0063] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field of this application. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an ideal or overly formal sense unless expressly defined as such herein.

[0064] In order to thoroughly understand the present application, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0065] In related technologies, such as Figure 1 As shown, the SOI substrate includes a bottom silicon layer 110, a top silicon layer 120, and an insulating layer 130 located between the bottom silicon layer 110 and the top silicon layer 120; wherein the top silicon layer 120 is used as a functional layer, and a semiconductor device is formed thereon.

[0066] The insulating layer 130 is generally a silicon oxide layer. However, the thermal conductivity of silicon oxide is low, resulting in low thermal conductivity, which leads to poor heat dissipation performance of the SOI substrate. The poor heat dissipation performance will lead to problems such as a decrease in the channel current of the semiconductor device on the SOI substrate and the formation of negative differential resistance.

[0067] Therefore, in view of the existence of the aforementioned technical problems, the present application proposes a substrate, comprising:

[0068] first base;

[0069] a second substrate, wherein the thickness of the second substrate is smaller than the thickness of the first substrate;

[0070] The first medium layer and the second medium layer are arranged between the first substrate and the second substrate to connect the first substrate and the second substrate, wherein the thermal conductivity of the second medium layer is higher than the thermal conductivity of the first medium layer.

[0071] The substrate of the present application has a first dielectric layer and a second dielectric layer formed between the first base and the second base, wherein the thermal conductivity of the second dielectric layer is higher than that of the first dielectric layer. By using the second dielectric layer with a higher thermal conductivity, the heat dissipation performance of the substrate can be effectively improved, thereby improving the problems of the decrease in channel current of the semiconductor device manufactured on the substrate and the formation of negative differential resistance due to poor heat dissipation.

[0072] Embodiment 1

[0073] Below, reference Figure 2C , Figure 3C , Figure 4C as well as Figure 5C The substrate in the embodiment of the present application is described.

[0074] In one example, if Figure 2C , Figure 3C , Figure 4C as well as Figure 5C As shown, the substrate of the present application includes a first substrate 210, a second substrate 220, a first dielectric layer 230 and a second dielectric layer 240, wherein: the thickness of the second substrate 220 is less than the thickness of the first substrate 210, the second substrate 220 serves as a functional layer, and the semiconductor device is formed on the side where the second substrate 220 is located; the first dielectric layer 230 and the second dielectric layer 240 are arranged between the first substrate 210 and the second substrate 220, and connect the first substrate 210 and the second substrate 220, wherein the thermal conductivity of the second dielectric layer 240 is higher than the thermal conductivity of the first dielectric layer 230, and the heat dissipation performance of the substrate can be effectively improved by using the second dielectric layer with a higher thermal conductivity, thereby improving the problems of the decrease of the channel current of the semiconductor device manufactured on the substrate and the formation of negative differential resistance due to the heat dissipation difference.

[0075] In one example, the substrate may be an SOI substrate, and the first dielectric layer 230 and the second dielectric layer 240 serve as a composite buried layer of the SOI substrate. The materials of the first substrate 210 and the second substrate 220 include, but are not limited to, materials such as Si, SiGe, SiC, or SiGeC. Exemplarily, the thickness of the first substrate 210 is in the range of 750um-800um, and the thickness of the second substrate is in the range of 3um-4um, or any other suitable thickness range may be used, which should be reasonably set according to actual needs.

[0076] In one example, the first dielectric layer 230 and the second dielectric layer 240 can be stacked together to serve as a composite buried layer of the substrate of the present application. Since the thermal conductivity of the second dielectric layer 240 is higher than that of the first dielectric layer 230, the heat dissipation performance of the substrate can be effectively improved, and thus the problems of the decrease in channel current and the formation of negative differential resistance of the semiconductor device fabricated on the substrate caused by the poor heat dissipation performance of the substrate can be further improved.

[0077] It is worth mentioning that the first dielectric layer 230 and the second dielectric layer 240 are arranged between the first substrate 210 and the second substrate 220, which does not mean that only one first dielectric layer 230 and one second dielectric layer 240 are formed between the first substrate 210 and the second substrate 220. One or more layers of the first dielectric layer 230 and one or more layers of the second dielectric layer 240 may be formed between the first substrate 210 and the second substrate 220.

[0078] In one example, if Figure 2C As shown, a first dielectric layer 230 and a second dielectric layer 240 may be formed between the first substrate 210 and the second substrate 220 , wherein the first dielectric layer 230 contacts the first substrate 210 , and the second dielectric layer 240 contacts the second substrate 220 .

[0079] In another example, Figure 3C As shown, a first dielectric layer 230 and a second dielectric layer 240 may be formed between the first substrate 210 and the second substrate 220 , wherein the first dielectric layer 230 contacts the second substrate 220 , and the second dielectric layer 240 contacts the first substrate 210 .

[0080] In one example, the number of layers of the first dielectric layer 230 is at least two, wherein one first dielectric layer 230 contacts the first substrate 210, and one first dielectric layer 230 contacts the second substrate 220. For example, the first dielectric layer 230 having two layers is used for illustration. Figure 4C As shown, two first dielectric layers 230 and two second dielectric layers 240 located between the two first dielectric layers 230 can be formed between the first substrate 210 and the second substrate 220, wherein the two first dielectric layers 230 contact the first substrate 210 and the second substrate 220 respectively, and the two second dielectric layers 240 are connected together by bonding or other processes.

[0081] In one example, the number of layers of the second dielectric layer 240 is at least two, wherein one second dielectric layer 240 contacts the first substrate 210, and one second dielectric layer 240 contacts the second substrate 220. For example, the second dielectric layer 240 having two layers is used for illustration. Figure 5CAs shown, two second dielectric layers 240 and at least one first dielectric layer 230 located between the two second dielectric layers 240 can be formed between the first substrate 210 and the second substrate 220, wherein the two second dielectric layers 240 contact the first substrate 210 and the second substrate 220 respectively, and the two first dielectric layers 230 are connected together by bonding or other processes.

[0082] In one example, if Figure 2C and Figure 5C As shown, a second dielectric layer 240 contacting the second substrate 220 is formed, wherein the second substrate 220 serves as a functional layer. When the substrate is used as a substrate for a semiconductor device, the functional layer can be used to form an active area, etc. The side where the second substrate 220 is located has a higher demand for heat dissipation. By making the second dielectric layer 240 with a higher thermal conductivity contact the second substrate 220, the side where the second substrate 220 is located can be better cooled, thereby further improving the heat dissipation performance of the substrate.

[0083] In one example, the material of the second dielectric layer 240 includes metal oxide, metal nitride or boron nitride, wherein the metal oxide and the metal nitride include at least one of the following: magnesium oxide, aluminum oxide and aluminum nitride. Exemplarily, the first dielectric layer 230 includes a silicon oxide layer. The dielectric constant of the first dielectric layer can be higher than that of the second dielectric layer, so that the dielectric properties of the material are ensured by the first dielectric layer, and the heat dissipation is improved by the second dielectric layer.

[0084] In one example, if Figure 2C , Figure 3C , Figure 4C as well as Figure 5C As shown, the second dielectric layer 240 includes a main body layer 241 and at least one protrusion 242 protruding from the surface of the main body layer 241, wherein the main body layer 241 covers the first dielectric layer 230, the protrusion 242 is connected to the main body layer 241, and at least one protrusion 242 is located in the first dielectric layer 230. The protrusion 242 can increase the surface area of ​​the second dielectric layer 240 and increase the heat dissipation path between the first substrate and the second substrate, thereby further improving the heat dissipation performance. Exemplarily, the protrusion 242 can partially extend into the first dielectric layer 230, or the protrusion 242 can also penetrate the first dielectric layer 230.

[0085] The shape of the protrusion can be reasonably set according to actual needs. For example, it can be a block structure, a columnar structure, or a long strip structure, or a combination of multiple shapes, or any other suitable shape.

[0086] In one example, when the second dielectric layer 240 has a plurality of protrusions 242 , the plurality of protrusions 242 are arranged in an array.

[0087] In one example, when the second dielectric layer 240 has a plurality of protrusions 242 , the spacing between two adjacent protrusions 242 is in the range of 4.5 mm to 5.5 mm, or may be in any other suitable spacing range, which should be reasonably set according to actual heat dissipation requirements.

[0088] In one example, when the second dielectric layer 240 has a plurality of protrusions 242 , the intervals between two adjacent protrusions 242 are the same or different.

[0089] In one example, the length of the protrusion 242 ranges from 0.9um to 1.1um, the width of the protrusion 242 ranges from 0.4um to 0.6um, the thickness of the protrusion 242 ranges from 0.4um to 0.6um, or the length, width and thickness of the protrusion 242 can also be any other suitable numerical range.

[0090] In one example, the thickness of the main body layer 241 is 15% to 25% of the thickness of the first dielectric layer 230; and / or, the thickness of the protrusion 242 is 30% to 70% of the thickness of the first dielectric layer 230. Since the thermal conductivity of the second dielectric layer 240 is higher than that of the first dielectric layer 230, and the thermal conductivity is positively correlated with the dielectric constant, that is, the dielectric constant of the second dielectric layer 240 is higher than that of the first dielectric layer, a high dielectric constant will lead to a larger parasitic capacitance (for example, the thicker the protrusion 242, the larger the parasitic capacitance of the device, and when the protrusion 242 penetrates the first dielectric layer 230, the parasitic capacitance of the device is the largest), and a larger parasitic capacitance will lead to a lower operating speed and increased power consumption of the device; in the embodiment of the present application, by reasonably setting the thickness of the main body layer 241 and the protrusion 242, it is possible to enhance thermal conductivity while avoiding the generation of a larger parasitic capacitance.

[0091] In one example, the thickness of the second dielectric layer 240 (i.e., the main layer 241) on the first dielectric layer 230 is in the range of 0.15um-0.25um, or any other suitable thickness range, wherein the thickness of the second dielectric layer 240 on the first dielectric layer 230 refers to the thickness of the first dielectric layer 230 except the protrusion 242. Exemplarily, the thickness of the first dielectric layer 230 is in the range of 0.9um-1.1um, or any other suitable thickness range, so that the thickness of the first dielectric layer 230 is greater than the thickness of the main layer 241, thereby facilitating the first dielectric layer to maintain good dielectric properties between the first substrate and the second substrate.

[0092] In summary, the substrate of the present application has a first dielectric layer and a second dielectric layer formed between the first substrate and the second substrate, wherein the thermal conductivity of the second dielectric layer is higher than the thermal conductivity of the first dielectric layer, which can effectively improve the heat dissipation performance of the substrate, thereby improving the problems of the decrease in channel current of the semiconductor device made on the substrate and the formation of negative differential resistance due to heat dissipation difference. Exemplarily, the second dielectric layer contacts the second substrate, which can further improve the heat dissipation performance of the substrate. Exemplarily, the second dielectric layer includes a main layer and at least one protrusion extending into the first dielectric layer, which can further improve the heat dissipation performance of the substrate.

[0093] Embodiment 2

[0094] In another embodiment of the present application, a method for manufacturing a substrate is provided. The method is used to manufacture the substrate described in the first embodiment.

[0095] Refer to the following Figures 2A to 6 The method for manufacturing the substrate of the embodiment of the present application is described. Figure 2A-2C The cross-sectional view of a substrate obtained by sequentially implementing a method for manufacturing a substrate according to an exemplary embodiment of the present application is shown. Figure 3A-3C A schematic cross-sectional view of a substrate obtained by sequentially implementing a method for manufacturing a substrate according to another exemplary embodiment of the present application is shown, Figure 4A-4C A schematic cross-sectional view of a substrate obtained by sequentially implementing a method for manufacturing a substrate according to another exemplary embodiment of the present application is shown, Figure 5A-Figure 5C A schematic cross-sectional view of a substrate obtained by sequentially implementing a method for manufacturing a substrate according to another exemplary embodiment of the present application is shown, Figure 6 A flow chart showing a method for manufacturing a substrate according to an exemplary embodiment of the present application is shown.

[0096] First, step S101 is performed to provide a first substrate 210 and a second substrate 220. The second substrate 220 is used as a functional layer or the first substrate 210 is used as a functional layer, and a semiconductor device is formed on a side where the second substrate 220 is located. Exemplarily, the materials of the first substrate 210 and the second substrate 220 include, but are not limited to, materials such as Si, SiGe, SiC or SiGeC.

[0097] Next, step S102 is performed to form a first dielectric layer 230 and a second dielectric layer 240 on the surface of at least one of the first substrate 210 and the second substrate 220 , wherein the thermal conductivity of the second dielectric layer 240 is higher than that of the first dielectric layer 230 .

[0098] In one example, a first dielectric layer 230 and a second dielectric layer 240 are sequentially formed on the first substrate 210 or the second substrate 220. Figure 2AAs shown, taking the example of sequentially forming a first dielectric layer 230 and a second dielectric layer 240 on a first substrate 210, the first dielectric layer 230 and the second dielectric layer 240 can be sequentially formed on the first substrate 210 by conventional deposition processes in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD), etc., which is not limited in the present application; similarly, the first dielectric layer 230 and the second dielectric layer 240 can also be sequentially formed on the second substrate 220, which will not be repeated here.

[0099] In another example, the second dielectric layer 240 and the first dielectric layer 230 are sequentially formed on the first substrate 210 or the second substrate 220. Figure 3A As shown, taking the example of sequentially forming a second dielectric layer 240 and a first dielectric layer 230 on a first substrate 210, the second dielectric layer 240 and the first dielectric layer 230 can be sequentially formed on the first substrate 210 by conventional deposition processes in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD), etc., which are not limited in the present application; similarly, the second dielectric layer 240 and the first dielectric layer 230 can also be sequentially formed on the second substrate 220, which will not be described in detail here.

[0100] In another example, Figure 4A and Figure 4B As shown, a first dielectric layer 230 and a second dielectric layer 240 are sequentially formed on a first substrate 210 and a second substrate 220, respectively. The first dielectric layer 230 and the second dielectric layer 240 can be sequentially formed on the first substrate 210 and the second substrate 220 by conventional deposition processes in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD), etc., and the present application does not limit this.

[0101] In another example, Figure 5A and Figure 5B As shown, a second dielectric layer 240 and a first dielectric layer 230 are sequentially formed on the first substrate 210 and the second substrate 220, respectively. The second dielectric layer 240 and the first dielectric layer 230 can be sequentially formed on the first substrate 210 and the second substrate 220 by conventional deposition processes in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD), etc., and the present application does not limit this.

[0102] In one example, if Figure 2A , Figure 4A and Figure 4BAs shown, when the first dielectric layer 230 is formed first and the second dielectric layer 240 is formed later, after the first dielectric layer 230 is formed and before the second dielectric layer 240 is formed, the method of the present application further includes: after the first dielectric layer 230 is formed, etching the first dielectric layer 230 to form at least one groove 260 in the first dielectric layer 230, and the second dielectric layer 240 formed subsequently covers the first dielectric layer 230 and fills the groove 260, so as to form a main layer 241 located on the first dielectric layer 230 and at least one protrusion 242 extending into the first dielectric layer 230 in the second dielectric layer 240. Exemplarily, the formed groove 260 may partially extend into the first dielectric layer 230, in which case the protrusion 242 partially extends into the first dielectric layer 230; or, the groove may also penetrate the first dielectric layer 230, in which case the protrusion 242 penetrates the first dielectric layer 230. Exemplarily, the first dielectric layer 230 may be etched by an etching process commonly used in the art, such as a photolithography process. In one example, the second dielectric layer 240 is composed of at least one protrusion 242 .

[0103] In one example, if Figure 3A , Figure 5A and Figure 5B As shown, when the second dielectric layer 240 is formed first and the first dielectric layer 230 is formed later, after the second dielectric layer 240 is formed and before the first dielectric layer 230 is formed, the method of the present application further includes: after the second dielectric layer 240 is formed, etching a portion of the second dielectric layer 240 to form a main layer 241 and at least one protrusion 242 protruding from the surface of the main layer 241, and then forming the first dielectric layer 230 on the second dielectric layer 240. After the first dielectric layer 230 is formed, the first dielectric layer 230 at least covers the area outside the protrusion 242 (that is, the first dielectric layer 230 at least covers the surface of the main layer 241 outside the protrusion 242) and the top surface of the first dielectric layer 230 is not lower than the top surface of the protrusion 242, and the protrusion 242 extends into the first dielectric layer 230. Exemplarily, when the top surface of the first dielectric layer 230 is higher than the top surface of the protrusion 242, the first dielectric layer 230 also covers the protrusion 242, and the protrusion 242 partially extends into the first dielectric layer 230; when the top surface of the first dielectric layer 230 is flush with the top surface of the protrusion 242, the protrusion 242 penetrates the first dielectric layer 230. Exemplarily, the second dielectric layer 240 may be etched using an etching process commonly used in the art, such as a photolithography process. In one example, when a plurality of protrusions 242 are formed in the second dielectric layer 240, the plurality of protrusions 242 are arranged in an array.

[0104] In one example, the thickness of the main body layer 241 is 15% to 25% of the thickness of the first dielectric layer 230; and / or, the thickness of the protrusion 242 is 30% to 70% of the thickness of the first dielectric layer 230. Since the thermal conductivity of the second dielectric layer 240 is higher than that of the first dielectric layer 230, and the thermal conductivity is positively correlated with the dielectric constant, that is, the dielectric constant of the second dielectric layer 240 is higher than that of the first dielectric layer, a high dielectric constant will lead to a larger parasitic capacitance (for example, the thicker the protrusion 242, the larger the parasitic capacitance of the device, and when the protrusion 242 penetrates the first dielectric layer 230, the parasitic capacitance of the device is the largest), and a larger parasitic capacitance will lead to a lower operating speed and increased power consumption of the device; in the embodiment of the present application, by reasonably setting the thickness of the main body layer 241 and the protrusion 242, it is possible to enhance thermal conductivity while avoiding the generation of a larger parasitic capacitance.

[0105] At the same time, when the first dielectric layer 230 is formed first and the second dielectric layer 240 is formed later, if the thickness of the protrusion 242 is too thick, the first dielectric layer 230 needs to be etched to form a deeper groove 260, and the depth of the groove 260 is too deep, which is not conducive to filling the second dielectric layer 240 into the groove 260, and it is easy to cause problems such as filling voids, thereby causing device performance degradation; when the second dielectric layer 240 is formed first and the first dielectric layer 230 is formed later, if the thickness of the protrusion 242 is too thick, it is necessary to etch the second dielectric layer 240 with a deeper thickness. When the first dielectric layer 230 is formed, the first dielectric layer 230 covering the area outside the protrusion 242 is prone to problems such as filling voids, thereby causing device performance degradation. In the embodiment of the present application, by controlling the thickness of the protrusion 242, the generation of filling voids can be limited, thereby improving device performance.

[0106] In one example, when a plurality of protrusions 242 are formed in the second dielectric layer 240 , the spacing between two adjacent protrusions 242 ranges from 4.5 mm to 5.5 mm, or may be any other suitable spacing range, which should be reasonably set according to actual heat dissipation requirements.

[0107] In one example, the protrusion 242 can increase the surface area of ​​the second dielectric layer 240 , thereby further improving the heat dissipation performance.

[0108] In one example, when a plurality of protrusions 242 are formed in the second dielectric layer 240 , the intervals between two adjacent protrusions 242 are the same or different.

[0109] In one example, the length of the protrusion 242 ranges from 0.9um to 1.1um, the width of the protrusion 242 ranges from 0.4um to 0.6um, the thickness of the protrusion 242 ranges from 0.4um to 0.6um, or the length, width and thickness of the protrusion 242 can also be any other suitable numerical range.

[0110] In one example, the thickness of the second dielectric layer 240 (i.e., the main layer 241) on the first dielectric layer 230 is in the range of 0.15um-0.25um, or any other suitable thickness range, wherein the thickness of the second dielectric layer 240 on the first dielectric layer 230 refers to the thickness of the first dielectric layer 230 except the protrusion 242. Exemplarily, the thickness of the first dielectric layer 230 is in the range of 0.9um-1.1um, or any other suitable thickness range.

[0111] In one example, the material of the second dielectric layer 240 includes metal oxide, metal nitride or boron nitride, wherein the metal oxide and metal nitride include at least one of the following: magnesium oxide, aluminum oxide and aluminum nitride. Exemplarily, the first dielectric layer 230 includes a silicon oxide layer.

[0112] Next, step S103 is performed to bond the first substrate 210 to the second substrate 220 , wherein the first dielectric layer 230 and the second dielectric layer 240 are located between the first substrate 210 and the second substrate 220 .

[0113] In one example, if Figure 2C As shown, when the first dielectric layer 230 and the second dielectric layer 240 are sequentially formed on the first substrate 210, the bonding step bonds the side of the first substrate 210 formed with the second dielectric layer 240 to the second substrate 220; similarly, when the first dielectric layer 230 and the second dielectric layer 240 are sequentially formed on the second substrate 220, the bonding step bonds the side of the second substrate 220 formed with the first dielectric layer 230 to the first substrate 210. Exemplarily, the bonding step can be performed using a conventional bonding process in the art.

[0114] In one example, if Figure 3C As shown, when the second dielectric layer 240 and the first dielectric layer 230 are sequentially formed on the first substrate 210, the above bonding step bonds the side of the first substrate 210 on which the first dielectric layer 230 is formed to the second substrate 220; similarly, when the second dielectric layer 240 and the first dielectric layer 230 are sequentially formed on the second substrate 220, the above bonding step bonds the side of the second substrate 220 on which the first dielectric layer 230 is formed to the first substrate 210.

[0115] In one example, if Figure 4C As shown, when the first dielectric layer 230 and the second dielectric layer 240 are sequentially formed on the first substrate 210 and the second substrate 220 , the bonding step bonds the side of the first substrate 210 where the second dielectric layer 240 is formed with the side of the second substrate 220 where the second dielectric layer 240 is formed.

[0116] In one example, if Figure 5C As shown, when the second dielectric layer 240 and the first dielectric layer 230 are sequentially formed on the first substrate 210 and the second substrate 220 , the bonding step bonds the side of the first substrate 210 formed with the first dielectric layer 230 to the side of the second substrate 220 formed with the first dielectric layer 230 .

[0117] Finally, step S104 is performed to remove the second substrate 220 or the first substrate 210 of a predetermined thickness, so that the thickness of one of the second substrate 220 and the first substrate 210 is less than the thickness of the other. Exemplarily, taking the removal of a portion of the thickness of the second substrate 220 as an example, the Smart-Cut technology or chemical mechanical grinding and / or etching process can be used to remove the second substrate 220 of a predetermined thickness to thin the second substrate 220, wherein the Smart-Cut technology is used to remove the second substrate 220 of a predetermined thickness, including: performing an ion implantation process on the second substrate 220 to form an ion implantation layer in the second substrate 220 of a predetermined depth, and after the bonding step, performing an annealing process to cause the second substrate 220 to be cracked and separated from the ion implantation layer, thereby removing the second substrate 220 of a predetermined thickness. Exemplarily, the step of flattening the thinned second substrate 220 is also included, for example, performing chemical mechanical polishing (CMP, Chemical Mechanical Polishing) on ​​the thinned second substrate. It is worth mentioning that part of the first substrate can also be removed, and the method is basically similar to the method of removing the second substrate.

[0118] In one example, if Figure 2C and Figure 5C As shown, the second dielectric layer 240 contacts the second substrate 220, wherein the second substrate 220 serves as a functional layer, and the side where the second substrate 220 is located has a higher demand for heat dissipation. By making the second dielectric layer 240 with a higher thermal conductivity contact the second substrate 220, the side where the second substrate 220 is located can be better dissipated, thereby further improving the heat dissipation performance of the substrate.

[0119] In summary, the manufacturing method of the substrate of the present application forms a first dielectric layer and a second dielectric layer located between a first substrate and a second substrate, wherein the thermal conductivity of the second dielectric layer is higher than the thermal conductivity of the first dielectric layer, which can effectively improve the heat dissipation performance of the substrate, thereby improving the problems of the decrease in channel current of the semiconductor device manufactured on the substrate and the formation of negative differential resistance due to heat dissipation difference. Exemplarily, the second dielectric layer contacts the second substrate, which can further improve the heat dissipation performance of the substrate. Exemplarily, the second dielectric layer includes a main layer and at least one protrusion extending into the first dielectric layer, which can further improve the heat dissipation performance of the substrate.

[0120] Embodiment 3

[0121] In another embodiment of the present application, a method for manufacturing a substrate is provided. The method is used to manufacture the substrate described in the first embodiment.

[0122] Refer to the following Figure 2C , Figure 3C , Figure 4C , Figure 5C and Figure 7 The method for manufacturing the substrate of the embodiment of the present application is described. Figure 7 A flow chart showing a method for manufacturing a substrate according to another exemplary embodiment of the present application is shown.

[0123] First, step S201 is performed to provide a first substrate 210. By way of example, the material of the first substrate 210 includes, but is not limited to, materials such as Si, SiGe, SiC or SiGeC.

[0124] Next, step S202 is performed to form a first dielectric layer 230 and a second dielectric layer 240 on the first substrate 210, wherein the thermal conductivity of the second dielectric layer 240 is higher than the thermal conductivity of the first dielectric layer 230. For example, one or more layers of the first dielectric layer 230 and one or more layers of the second dielectric layer 240 may be formed on the first substrate 210.

[0125] In one example, if Figure 2C and Figure 3C As shown, a first dielectric layer 230 and a second dielectric layer 240 may be formed on the first substrate 210. Specifically, as Figure 2C As shown, the first dielectric layer 230 may be formed on the first substrate 210, and then the second dielectric layer 240 may be formed on the first dielectric layer 230; or Figure 3C As shown, the second dielectric layer 240 may be formed on the first substrate 210 first, and then the first dielectric layer 230 may be formed on the second dielectric layer 230 .

[0126] In one example, if Figure 4C and Figure 5CAs shown, two first dielectric layers 230 and two second dielectric layers 240 may be formed on the first substrate 210. Specifically, as Figure 4C As shown, a first dielectric layer 230 may be formed on the first substrate 210, two second dielectric layers 240 may be formed on the first dielectric layer 230, and a first dielectric layer 230 may be formed on the second dielectric layer 240; or Figure 5C As shown, a second dielectric layer 240 may be formed on the first substrate 210, two first dielectric layers 230 may be formed on the second dielectric layer 240, and then a second dielectric layer 240 may be formed on the first dielectric layer 230. By way of example, any number of first dielectric layers 230 and second dielectric layers 240 may be formed on the first substrate 210, and the order of forming the first dielectric layer 230 and the second dielectric layer 240 is not specifically limited. By way of example, the first dielectric layer 230 and the second dielectric layer 240 may be formed on the first substrate 210 by conventional deposition processes in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and the present application does not limit this.

[0127] In one example, when the first dielectric layer 230 is formed first and the second dielectric layer 240 is formed later, after the first dielectric layer 230 is formed and before the second dielectric layer 240 is formed, the method of the present application further includes: after the first dielectric layer 230 is formed, etching the first dielectric layer 230 to form at least one groove 260 in the first dielectric layer 230, and the second dielectric layer 240 formed subsequently covers the first dielectric layer 230 and fills the groove 260, so as to form a main layer 241 located on the first dielectric layer 230 and at least one protrusion 242 extending into the first dielectric layer 230 in the second dielectric layer 240. Exemplarily, the formed groove 260 may partially extend into the first dielectric layer 230, in which case the protrusion 242 partially extends into the first dielectric layer 230; or, the groove may also penetrate the first dielectric layer 230, in which case the protrusion 242 penetrates the first dielectric layer 230. Exemplarily, the first dielectric layer 230 may be etched by an etching process commonly used in the art, such as a photolithography process. In one example, the second dielectric layer 240 is composed of at least one protrusion 242 .

[0128] In one example, when the second dielectric layer 240 is formed first and the first dielectric layer 230 is formed later, after the second dielectric layer 240 is formed and before the first dielectric layer 230 is formed, the method of the present application further includes: after forming the second dielectric layer 240, etching a portion of the thickness of the second dielectric layer 240 to form a main layer 241 and at least one protrusion 242 protruding from the surface of the main layer 241, and then forming the first dielectric layer 230 on the second dielectric layer 240. After forming the first dielectric layer 230, the first dielectric layer 230 at least covers the area outside the protrusion 242 (that is, the first dielectric layer 230 at least covers the surface of the main layer 241 outside the protrusion 242) and the top surface of the first dielectric layer 230 is not lower than the top surface of the protrusion 242, and the protrusion 242 extends into the first dielectric layer 230. Exemplarily, when the top surface of the first dielectric layer 230 is higher than the top surface of the protrusion 242, the first dielectric layer 230 also covers the protrusion 242, and the protrusion 242 partially extends into the first dielectric layer 230; when the top surface of the first dielectric layer 230 is flush with the top surface of the protrusion 242, the protrusion 242 penetrates the first dielectric layer 230. Exemplarily, the second dielectric layer 240 may be etched using an etching process commonly used in the art, such as a photolithography process.

[0129] In one example, the thickness of the main layer 241 is 15% to 25% of the thickness of the first dielectric layer 230; and / or the thickness of the protrusion 242 is 30% to 70% of the thickness of the first dielectric layer 230. In the embodiment of the present application, by reasonably setting the thickness of the main layer 241 and the protrusion 242, it is possible to enhance thermal conductivity while avoiding the generation of greater parasitic capacitance, and by controlling the thickness of the protrusion 242, the generation of filling voids can be limited, thereby improving device performance.

[0130] Finally, step S203 is performed to form a second substrate 220 by deposition on the side of the first substrate 210 where the first dielectric layer 230 and the second dielectric layer 240 are formed, wherein the thickness of the second substrate 220 is less than the thickness of the first substrate 210. Exemplarily, the second substrate 200 serves as a functional layer, and the semiconductor device is formed on the side where the second substrate 220 is located. Exemplarily, the second substrate 220 can be deposited by a conventional deposition process in the art. Exemplarily, the material of the second substrate 220 includes, but is not limited to, materials such as Si, SiGe, SiC, or SiGeC.

[0131] In one example, if Figure 2C and Figure 5CAs shown, the second dielectric layer 240 contacts the second substrate 220, wherein the second substrate 220 serves as a functional layer, and the side where the second substrate 220 is located has a higher demand for heat dissipation. By making the second dielectric layer 240 with a higher thermal conductivity contact the second substrate 220, the side where the second substrate 220 is located can be better dissipated, thereby further improving the heat dissipation performance of the substrate.

[0132] In summary, the manufacturing method of the substrate of the present application forms a first dielectric layer and a second dielectric layer located between a first substrate and a second substrate, wherein the thermal conductivity of the second dielectric layer is higher than the thermal conductivity of the first dielectric layer, which can effectively improve the heat dissipation performance of the substrate, thereby improving the problems of the decrease in channel current of the semiconductor device manufactured on the substrate and the formation of negative differential resistance due to heat dissipation difference. Exemplarily, the second dielectric layer contacts the second substrate, which can further improve the heat dissipation performance of the substrate. Exemplarily, the second dielectric layer includes a main layer and at least one protrusion extending into the first dielectric layer, which can further improve the heat dissipation performance of the substrate.

[0133] Embodiment 4

[0134] In another embodiment of the present application, a semiconductor device is provided, which includes the substrate of the aforementioned embodiment, or includes a substrate manufactured by the manufacturing method of the aforementioned embodiment. Exemplarily, the semiconductor device may also include other components, such as active components located on the substrate, etc., which are not described in detail in the present application.

[0135] The semiconductor device according to the embodiment of the present application has better performance due to the use of the above-mentioned substrate.

[0136] Although multiple embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be conceived by those skilled in the art, all of which will fall within the spirit and scope of the concepts disclosed herein. More particularly, various modifications and changes may be made to the arrangements and / or components of the combined arrangements of the subject matter within the scope of the disclosure, drawings, and appended claims of the present application. In addition to modifications and changes to the components and / or arrangements, the use of alternatives is also an obvious option for those skilled in the art.

Claims

1. A substrate, characterized in that: include: first base; a second substrate, wherein the thickness of the second substrate is smaller than the thickness of the first substrate; The first medium layer and the second medium layer are arranged between the first substrate and the second substrate to connect the first substrate and the second substrate, wherein the thermal conductivity of the second medium layer is higher than the thermal conductivity of the first medium layer.

2. The substrate according to claim 1, characterized in that The second dielectric layer contacts the second substrate; or The second dielectric layer contacts the first substrate; or The number of layers of the second dielectric layer is at least two, wherein one layer of the second dielectric layer contacts the first substrate, and one layer of the second dielectric layer contacts the second substrate; or The number of the first dielectric layer is at least two, wherein one of the first dielectric layers contacts the first substrate, and one of the first dielectric layers contacts the second substrate.

3. The substrate according to claim 1, characterized in that The second dielectric layer includes a main body layer and at least one protrusion protruding from a surface of the main body layer, wherein the main body layer covers the first dielectric layer, and the protrusion is located in the first dielectric layer.

4. The substrate according to claim 3, characterized in that When the second dielectric layer has a plurality of the protrusions, the plurality of the protrusions are arranged in an array; and / or The distances between two different adjacent protrusions are the same or different; and / or The distance between two adjacent protrusions ranges from 4.5 mm to 5.5 mm.

5. The substrate according to claim 3, characterized in that The length of the protrusion is in the range of 0.9um-1.1um, the width of the protrusion is in the range of 0.4um-0.6um, and the thickness of the protrusion is in the range of 0.4um-0.6um; and / or The thickness of the main layer ranges from 0.15um to 0.25um.

6. The substrate according to claim 3, characterized in that The thickness of the main layer is 15% to 25% of the thickness of the first dielectric layer; and / or The thickness of the protruding portion is 30% to 70% of the thickness of the first dielectric layer.

7. The substrate according to claim 1, characterized in that The material of the first dielectric layer includes silicon oxide; The material of the second dielectric layer includes metal oxide, metal nitride or boron nitride, wherein the metal oxide and the metal nitride include at least one of the following: magnesium oxide, aluminum oxide and aluminum nitride.

8. A method for manufacturing a substrate, characterized in that: The method comprises: providing a first substrate and a second substrate; forming a first dielectric layer and a second dielectric layer on a surface of at least one of the first substrate and the second substrate, wherein the thermal conductivity of the second dielectric layer is higher than the thermal conductivity of the first dielectric layer; Bonding the first substrate to the second substrate, wherein the first dielectric layer and the second dielectric layer are located between the first substrate and the second substrate; A predetermined thickness of the second substrate or the first substrate is removed so that a thickness of one of the second substrate and the first substrate is smaller than a thickness of the other.

9. The manufacturing method according to claim 8, characterized in that: Forming a first dielectric layer and a second dielectric layer on a surface of at least one of the first substrate and the second substrate, comprising: forming the first dielectric layer and the second dielectric layer in sequence on the first substrate or the second substrate; or forming the second dielectric layer and the first dielectric layer in sequence on the first substrate or the second substrate; or forming the first dielectric layer and the second dielectric layer on the first substrate and the second substrate respectively; or The second dielectric layer and the first dielectric layer are formed in sequence on the first substrate and the second substrate respectively.

10. A method for manufacturing a substrate, characterized in that: The method comprises: providing a first substrate; forming a first dielectric layer and a second dielectric layer on the surface of the first substrate, wherein the thermal conductivity of the second dielectric layer is higher than the thermal conductivity of the first dielectric layer; A second substrate is formed by deposition on a side of the first substrate where the first dielectric layer and the second dielectric layer are formed, wherein a thickness of the second substrate is smaller than a thickness of the first substrate.

11. The manufacturing method according to claim 8 or 10, characterized in that: When the first dielectric layer is formed first and the second dielectric layer is formed later, after forming the first dielectric layer and before forming the second dielectric layer, the method further includes: The first dielectric layer is etched to form at least one groove in the first dielectric layer, and the second dielectric layer covers the first dielectric layer and fills the groove to form a main layer located on the first dielectric layer and at least one protrusion extending into the first dielectric layer; or, When the second dielectric layer is formed first and the first dielectric layer is formed later, after forming the second dielectric layer and before forming the first dielectric layer, the method further includes: Etching a portion of the thickness of the second dielectric layer to form a main layer and at least one protrusion protruding from a surface of the main layer; After forming the first dielectric layer, the first dielectric layer at least covers the area outside the protrusion and the top surface of the first dielectric layer is not lower than the top surface of the protrusion, so that the protrusion extends into the first dielectric layer.

12. A semiconductor device, characterized in that: The method comprises the substrate according to any one of claims 1 to 7, or comprises a substrate manufactured by the manufacturing method according to any one of claims 8 to 11.

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