Semiconductor device and preparation method thereof, and chip packaging structure

Abstract

The invention provides a semiconductor device, a preparation method thereof and a chip packaging structure, relates to the technical field of semiconductor chips, and is used for reducing the preparation cost of the semiconductor device. A semiconductor device includes a rewiring layer, a plurality of composite structures, and a plurality of conductive pillars. The rewiring layer includes a plurality of first pads. And the plurality of composite structures are located on the rewiring layer and are stacked in the direction perpendicular to the plane where the rewiring layer is located. The composite structure comprises a chip, an insulating layer surrounding the chip, and at least one second bonding pad electrically connected with the chip. The second bonding pad is located on the insulating layer. The positions of the second bonding pads of the plurality of composite structures are different along the first direction. The first direction is perpendicular to the thickness direction of the composite structure. The plurality of conductive columns are positioned in the insulating layer of the at least one composite structure; each conductive column is electrically connected with one second bonding pad and one first bonding pad. The semiconductor device is used for realizing data reading and writing operations.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same, and a chip packaging structure. Background Art

[0002] At present, with the maturity of semiconductor industry technology, the miniaturization of chip packaging structure has become a major development trend. As the characteristic size of the chip inside the chip packaging structure is gradually approaching the lower limit, in order to achieve the miniaturization of the chip packaging structure, the requirements for chip packaging technology are getting higher and higher. Summary of the invention

[0003] The embodiments of the present application provide a semiconductor device and a method for preparing the same, as well as a chip packaging structure, which are used to achieve miniaturized design and high-integration design of the semiconductor device and the chip packaging structure, and can reduce the difficulty and cost of the preparation process of the semiconductor device and the chip packaging structure.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] On the one hand, a semiconductor device is provided, including: a rewiring layer, a plurality of composite structures, and a plurality of conductive pillars. The rewiring layer includes a plurality of first pads; the plurality of composite structures are located on the rewiring layer and are stacked in a direction perpendicular to the plane where the rewiring layer is located; the composite structure includes: a chip, an insulating layer surrounding the chip, and at least one second pad electrically connected to the chip, the second pad being located on the insulating layer; the second pads of the plurality of composite structures are located at different positions along a first direction; the first direction is perpendicular to the thickness direction of the composite structure; the plurality of conductive pillars are located in the insulating layer of at least one composite structure; each conductive pillar is connected to one second pad and one first pad.

[0006] In the semiconductor device provided in the embodiment of the present application, the composite structure includes a second pad, a chip and an insulating layer, a second pad is provided, and is located on the insulating layer surrounding the chip, the second pad is electrically connected to the corresponding chip, the positions of the second pads of the plurality of composite structures along the first direction are different, and a plurality of conductive pillars are provided in the insulating layer of the composite structure, and the conductive pillars are used to realize the electrical connection between the first pad in the rewiring layer and the second pad structure in the composite structure, thereby avoiding the use of punching holes inside the chip to realize the integration of multiple composite structures, and there is no need to occupy the space and area inside the chip, which is conducive to the miniaturization design of the semiconductor device, reduces the difficulty of the preparation process of the semiconductor device, and saves the preparation cost of the semiconductor device. Moreover, since the conductive pillar is located in the insulating layer and the second pad is located on the insulating layer, the integration of each composite structure is not limited by the chip area in each composite structure, so that the integration of the semiconductor device is higher, the integration of each composite structure is simpler, and the combination type of the composite structure in the semiconductor device is more flexible, which greatly broadens the application scenarios of the semiconductor device.

[0007] In some embodiments, the conductive pillars extend in a direction perpendicular to the plane where the re-distribution layer is located, and the plurality of conductive pillars are arranged parallel to each other.

[0008] In some embodiments, the composite structure closest to the rewiring layer among the multiple composite structures is the first composite structure; along the direction perpendicular to the plane where the rewiring layer is located and in the direction away from the rewiring layer, the distance between the conductive column electrically connected to the second pad located on the same side of the chip in each of the composite structures and the chip of the first composite structure gradually increases.

[0009] In some embodiments, the multiple composite structures also include at least one second composite structure located on a side of the first composite structure away from the rewiring layer; along the thickness direction of the composite structure, the chips in each of the composite structures overlap; along the direction perpendicular to the plane where the rewiring layer is located and along the direction from the first composite structure to the second composite structure, the minimum distance between the chip in each of the composite structures and the second pad electrically connected to it gradually increases.

[0010] In some embodiments, the multiple composite structures also include a third composite structure and a fourth composite structure located on a side of the first composite structure away from the rewiring layer, and the third composite structure is closer to the rewiring layer than the fourth composite structure; in a direction from the fourth composite structure to the third composite structure, and along a thickness direction of the fourth composite structure, the chip in the fourth composite structure is opposite to the chip in the third composite structure, and the chip in the fourth composite structure covers the chip in the third composite structure; the distance between the chip in the third composite structure and the second pad electrically connected thereto is equal to the distance between the chip in the fourth composite structure and the second pad electrically connected thereto.

[0011] In some embodiments, in the at least one composite structure, there are multiple second pads electrically connected to the same chip; and the distances between the chip and the multiple second pads electrically connected to the chip are equal.

[0012] In some embodiments, in the at least one composite structure, there are multiple second pads electrically connected to the same chip; and the multiple second pads are located on at least two sides of the chip to which they are electrically connected.

[0013] In some embodiments, the material of the insulating layer includes an organic material.

[0014] In some embodiments, the composite structure further includes: a connecting routing layer; the connecting routing layer is located on a surface of a side of the chip close to the rewiring layer; the connecting routing layer includes connecting routing and a second pad, and the chip is electrically connected to the second pad through the connecting routing.

[0015] In some embodiments, the composite structure further includes: a dielectric layer covering the chip and the insulating layer; the conductive column passes through the insulating layer and the dielectric layer above the corresponding second pad and is electrically connected to the second pad.

[0016] On the other hand, a chip packaging structure is provided, which comprises: a semiconductor device, a packaging substrate and a packaging shell as described in any of the above embodiments; the packaging substrate is connected to a side of a rewiring layer in the semiconductor device away from the composite structure; the packaging shell is buckled on a plurality of the composite structures and connected to the packaging substrate.

[0017] On the other hand, a method for preparing a conductor device is provided, the method comprising: stacking to form a plurality of composite structures, the composite structures comprising: a chip, an insulating layer surrounding the chip, and at least one second pad electrically connected to the chip; the second pad is located on the insulating layer; the positions of the second pads of each composite structure along a first direction are different; the first direction is perpendicular to the thickness direction of the composite structure; using an etching process to etch the insulating layers of the plurality of composite structures to form through holes exposing the second pads; forming a conductive column in each through hole, the conductive column contacting the second pad exposed by the through hole; forming a rewiring layer on the plurality of composite structures, the rewiring layer comprising a plurality of first pads electrically connected to the conductive columns.

[0018] In some embodiments, forming the composite structure includes: providing a carrier substrate; disposing at least one chip on the carrier substrate; forming an insulating layer on the carrier substrate; the insulating layer surrounds the chip and covers the chip; grinding the insulating layer to expose a side surface of the chip away from the carrier substrate; forming a connecting wiring layer on a side surface of the chip away from the carrier substrate, the connecting wiring layer including connecting wiring and a second pad, and the chip is electrically connected to the second pad through the connecting wiring.

[0019] In some embodiments, the multiple composite structures are stacked in sequence on the substrate, including: laminating a temporary substrate on the side of the i-th composite structure away from the carrier substrate; wherein i is an integer and i≥2; removing the carrier substrate; laminating a side surface of the i-th composite structure with a side surface of the i-1-th composite structure away from the substrate; and removing the temporary substrate.

[0020] In some embodiments, when the composite structure includes multiple chips, the multiple chips are arranged at intervals; the rewiring layer has a cutting path, and in a direction perpendicular to the rewiring layer, the cutting path is located between two adjacent chips and separates the pads electrically connected to the two adjacent chips; the preparation method also includes: cutting the multiple composite structures along the cutting path.

[0021] It can be understood that the beneficial effects that can be achieved by the chip packaging structure and the method for preparing the semiconductor device provided in the above embodiments of the present application can be referred to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present application, the actual process of the method, etc.

[0023] Figure 1 is a schematic diagram of a chip packaging structure according to some embodiments of the present application;

[0024] Figure 2 is a structural diagram of a semiconductor device according to some embodiments of the present application;

[0025] Figure 3A is a structural diagram of another semiconductor device according to some embodiments of the present application;

[0026] Figure 3B is a structural diagram of another semiconductor device according to some embodiments of the present application;

[0027] Figure 4 is a structural diagram of another semiconductor device according to some embodiments of the present application;

[0028] Figure 5 is a structural diagram of a chip packaging structure according to some embodiments of the present application;

[0029] Figure 6 is a flow chart of a method for preparing a semiconductor device according to some embodiments of the present application;

[0030] Figure 7 to Figure 10 It is a structural diagram corresponding to each step of a method for preparing a semiconductor device according to some embodiments of the present application;

[0031] Figures 11 to 16 is a step diagram of another method for preparing a semiconductor device according to some embodiments of the present application;

[0032] Figures 17 to 20 It is a structural diagram corresponding to each step of another method for preparing a semiconductor device in some embodiments of the present application;

[0033] Fig.21 It is a structural diagram corresponding to each step of another method for preparing a semiconductor device in some embodiments of the present application. DETAILED DESCRIPTION

[0034] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0035] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "horizontal", "inside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0036] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0037] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0038] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments applied for here are not necessarily limited to the contents of this document.

[0039] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0040] In one embodiment, a chip packaging structure, such as Figure 1 As shown, a conductive structure that runs through each chip is arranged between multiple chips. The conductive structure is formed by a through silicon via (TSV) process. The conductive structure occupies the space inside each chip, which increases the volume of the chip, is not conducive to realizing the miniaturization design and high integration design of the chip packaging structure, and the preparation cost and difficulty of the conductive structure are high.

[0041] like Figure 2 As shown, some embodiments of the present application further provide a semiconductor device 1 , which includes: a rewiring layer 10 , a plurality of composite structures 20 , and a plurality of conductive pillars 30 .

[0042] Exemplarily, the rewiring layer 10 includes a plurality of first pads 11. The plurality of composite structures 20 are located on the rewiring layer 10 and are stacked in a direction perpendicular to the plane where the rewiring layer 10 is located.

[0043] like Figure 2 As shown, the direction perpendicular to the plane where the rewiring layer 10 is located is Figure 2 The third direction Z shown in FIG. 1 and the thickness direction of the composite structure 20 are also Figure 2 The third direction Z in the.

[0044] The composite structure 20 comprises: a chip 201, an insulating layer 202 surrounding the chip 201, and at least one second pad 203 electrically connected to the chip 201. The second pad 203 is located on the insulating layer 202.

[0045] For example, the chip 201 is electrically connected to one second pad 203 , or the chip 201 is electrically connected to a plurality of second pads 203 .

[0046] For example, the chip 201 may be a DRAM (Dynamic Random Access Memory), a CIS (Complementary Metal-Oxide-Semiconductor Transistor Image Sensor), a HMC (Hybrid Memory Cube), or the like.

[0047] Exemplarily, the chips 201 in different composite structures 20 may have the same function, such as storage function, etc. The chips 201 in different composite structures 20 may also have different functions, such as the chips 201 in one part of the composite structures 20 may have the function of controller, and the chips 201 in another part of the composite structures 20 may have the function of storage, etc., so that the chip with the controller function can be used to control the storage process of other chips.

[0048] A plurality of second pads 203 are located around the chip 201. In some examples, such as Figure 2 As shown, taking the first direction X as an example, the positions of the second pads 203 of the plurality of composite structures 20 along the first direction X are different. The first direction X is perpendicular to the thickness direction Z of the composite structure 20. For example, the first direction X can be Figure 2 In the horizontal direction, the first direction X is parallel to the plane where the composite structure 20 is located. In the first direction X, the positions of any two second pads 203 in different composite structures 20 do not overlap.

[0049] Exemplarily, in the first direction X, the orthographic projections of the second pads 203 on the plane where the re-wiring layer 10 is located do not at least partially overlap.

[0050] For example, in the orthographic projection onto the re-wiring layer 10 , each second pad 203 of each composite structure 20 has a non-overlapping portion with each second pad 203 of other composite structures 20 .

[0051] For another example, in the orthographic projection onto the rewiring layer 10, there is no overlap between the second pads 203 of each composite structure 20 and the second pads 203 of other composite structures 20. The second pads 203 of all composite structures 20 are staggered.

[0052] In the composite structure 20 , since the insulating layer 202 surrounds the chip 201 , the second pad 203 disposed on the insulating layer 202 and the chip 201 electrically connected thereto are staggered in the thickness direction of the composite structure 20 .

[0053] In some examples, the plurality of conductive pillars 30 are located in the insulating layer 202 of at least one composite structure 20 ; each conductive pillar 30 is connected to a second pad 203 and a first pad 11 .

[0054] The conductive pillar 30 passes through the insulating layer 202 of at least one composite structure 20 and is electrically connected to the corresponding second pad 203. The conductive pillar 30 is located beside the chip 201 electrically connected to the corresponding second pad 203 and has a certain distance from the chip 201 in the first direction X.

[0055] It is understandable that the heights of the conductive pillars 30 electrically connected to the second pads 203 in different composite structures 20 are different (the height here refers to the size of the conductive pillar 30 in its extension direction, that is, the distance between the end surface of the conductive pillar 30 connected to the first pad 11 and the end surface of the conductive pillar 30 connected to the second pad 203). The conductive pillars 30 electrically connected to the second pad 203 in the same composite structure 20 have the same height because the thickness of the insulating layer 202 they pass through is the same.

[0056] The semiconductor device 1 provided by the above-mentioned embodiment of the present application sets the second pad 203 in the composite structure 20 on the insulating layer 202 surrounding the chip 201, and the second pad 203 is electrically connected to the corresponding chip 201. The positions of the second pads 203 of the plurality of composite structures 20 along the first direction X are different, and a plurality of conductive pillars 30 are set in the insulating layer 202 of the composite structure 20 to realize the electrical connection between the first pad 11 in the rewiring layer 10 and the second pad 203 in the composite structure 20. Since the conductive pillars 30 are located in the insulating layer 202 and the second pad 203 is located on the insulating layer 202, the integration of each composite structure 20 is not limited by the area of ​​the chip 201 in each composite structure 20, so that the number of composite structures 20 that can be integrated in the semiconductor device 1 is large, so that the integration of the semiconductor device 1 is high, the integration of each composite structure 20 is simpler, and the combination type of the plurality of composite structures 20 in the semiconductor device 1 is more flexible, which greatly broadens the application scenarios of the semiconductor device 1. Furthermore, the semiconductor device 1 provided in the embodiment of the present application can avoid the use of drilling holes inside the chip 201 to realize the preparation process and integration method of multiple composite structures 20, and does not need to occupy the space and area inside the chip 201, thereby reducing the difficulty of the preparation process of the semiconductor device 1 and saving the preparation cost of the semiconductor device 1.

[0057] In some examples, such as Figure 2 and Figure 3AAs shown, the conductive pillars 30 extend in a direction perpendicular to the plane where the rewiring layer 10 is located, and the plurality of conductive pillars 30 are arranged parallel to each other. Thus, the arrangement of the plurality of conductive pillars 30 can be more regular, and the preparation of the plurality of conductive pillars 30 can be more convenient.

[0058] There are many shapes and sizes of the conductive pillars 30 , which can be selected and set according to actual conditions, and the present application does not impose any restrictions on this.

[0059] In some examples, the conductive pillar 30 may be cylindrical or substantially cylindrical in shape. The bottom diameter of the cylinder ranges from 2 μm to 50 μm. For example, the bottom diameter of the cylinder is 2 μm, 15 μm, 26 μm, 40 μm or 50 μm.

[0060] In other examples, the conductive column 30 may be in the shape of a prism, such as a quadrangular prism. The quadrangular prism may be in the shape of a straight quadrangular prism. A straight quadrangular prism refers to a quadrangular prism whose side edges are perpendicular to its bottom surface, and thus, the side edges are also perpendicular to the plane where the composite structure 20 is located. The minimum distance between any two side edges of the quadrangular prism ranges from 2 μm to 50 μm. For example, the minimum distance between any two side edges of the quadrangular prism is 2 μm, 19 μm, 31 μm, 40 μm or 50 μm.

[0061] For example, the above-mentioned right quadrangular prism may be a cuboid.

[0062] It is understandable that, due to manufacturing process errors and process limitations, the shape of the conductive pillar 30 is not a strict cylindrical shape or a straight quadrangular pillar.

[0063] In some embodiments, Figure 2 and Figure 3A As shown, in at least one composite structure 20 , there are multiple second pads 203 electrically connected to the same chip 201 .

[0064] For example, among the multiple composite structures 20 , the number of the second pads 203 in each composite structure 20 may be the same or different.

[0065] In some examples, in at least one composite structure 20 , the distances between the chip 201 and the plurality of second pads 203 electrically connected thereto are equal.

[0066] The above-mentioned “distance” may be a minimum distance.

[0067] For example, in each composite structure 20, the minimum distances between the chip 201 and the plurality of second pads 203 electrically connected thereto are all equal. Thus, the plurality of second pads 203 can be arranged more evenly, thereby reducing the design difficulty of the semiconductor device 1 and simplifying the manufacturing process of the semiconductor device 1.

[0068] For another example, among the multiple composite structures 20, the minimum distances between the chip 201 and the multiple second pads 203 electrically connected thereto in one composite structure 20 are all equal, while the minimum distances between the chip 201 and the multiple second pads 203 electrically connected thereto in another composite structure 20 are not equal. Thus, the arrangement positions of the second pads 203 can be made more flexible.

[0069] It is understandable that in the same composite structure, the relative positions of the plurality of second pads 203 and the chip 201 can be set in a variety of ways, and can be selected and set according to actual conditions, and the present application does not impose any limitation on this.

[0070] In some examples, such as Figure 2 and Figure 3A As shown, in at least one composite structure 20 , a plurality of second pads 203 are located on at least two sides of a chip 201 electrically connected thereto.

[0071] For example, the number of the second pads 203 electrically connected to one chip 201 is two, and the two pads are located at two opposite sides of the chip 201 along the first direction X.

[0072] With the above configuration, the second pads 203 electrically connected to the same chip 201 can be distributed more dispersedly, and the distance between two adjacent second pads 203 is larger, thereby reducing the risk of short circuit caused by the small distance between adjacent second pads 203.

[0073] For another example, in at least one composite structure 20 , the plurality of second pads 203 are located on three sides of the chip 201 electrically connected thereto, and the plurality of second pads 203 surround the chip 201 .

[0074] In some embodiments, Figure 2 and Figure 3A As shown, the composite structure 20 further includes: a connection wiring layer 204 .

[0075] The connection wiring layer 204 is located on a surface of the chip 201 close to the rewiring layer 10. The connection wiring layer 204 includes connection wiring 205 and a second pad 203. The chip 201 is electrically connected to the second pad 203 via the connection wiring 205.

[0076] The connection trace 205 in the second composite structure 22 extends onto the insulating layer 202 and is electrically connected to the second pad 203 on the insulating layer 202 .

[0077] In some embodiments, Figure 2As shown, the plurality of composite structures 20 include a first composite structure 21 and at least one second composite structure 22. The composite structure closest to the rewiring layer 10 among the composite structures 20 is the first composite structure 21. The chip 201 in the first composite structure 21 is a target chip 201A.

[0078] It is understandable that there are multiple locations for the second pad 203 in the first composite structure 21, which can be selected according to actual needs, and the present application does not impose any limitation on this.

[0079] In some examples, such as Figure 4 As shown, in the above-mentioned first composite structure 21, the second pad 203 is located on the chip 201. The orthographic projection of the second pad 203 on the rewiring layer 10 is located within the orthographic projection range of the chip 201 on the rewiring layer 10. That is to say, in the thickness direction of the first composite structure 21, the second pad 203 is directly opposite to the chip 201 electrically connected thereto. In the second composite structure 22, the orthographic projection of the second pad 203 on the rewiring layer 10 does not overlap with the orthographic projection of the chip 201 on the rewiring layer 10. At this time, the second pad 203 of the first composite structure 21 and the second pad 203 of the second composite structure 22 are arranged at different positions. In the first composite structure 21, the orthographic projection of the conductive column 30 electrically connected to the second pad 203 on the rewiring layer 10 is also located within the orthographic projection range of the chip 201 on the rewiring layer 10.

[0080] By adopting the above-mentioned setting method, the second pad 203 and the conductive column 30 in the first composite structure 21 can be directly opposite to the chip 201 in the first composite structure 21, avoiding the conductive column and the second pad 203 from occupying the space outside the chip 201 alone, thereby facilitating the miniaturization design and high integration design of the semiconductor device 1.

[0081] In other examples, such as Figure 2 As shown, the second pad 203 in the first composite structure 21 can be located on the insulating layer 202, and the corresponding conductive column 30 is located between the second pad 203 and the first pad 11 of the rewiring layer 10. Thus, the relative position of the second pad 203 and the chip 201 in the first composite structure 21 can be the same as the relative position of the second pad 203 and the chip 201 in the second composite structure 22, which can simplify the preparation process of each composite structure 20, thereby optimizing the preparation process of the semiconductor device 1.

[0082] The following is an introduction by taking the case where the second pad 203 in the first composite structure 21 is also located on the insulating layer 202 as an example.

[0083] There are many relative positions between the second pad 203 and the chip 201 to which it is electrically connected, and this application does not limit this. For example, each second pad 203 in the partial composite structure 20 is located on the same side of the chip 201 to which it is electrically connected. For another example, each second pad 203 in the partial composite structure 20 is located on opposite sides of the chip 201 to which it is electrically connected.

[0084] For example, Figure 2 As shown, along the direction perpendicular to the plane where the redistribution layer 10 is located and in the direction away from the redistribution layer 10, the distance between the conductive column 30 connected to the second pad 203 located on the same side of the chip 201 in each composite structure 20 and the chip of the first composite structure gradually increases.

[0085] For example, Figure 2 As shown, the “same side” is the left side or the right side along the second direction Y. In any two composite structures 20 except the first composite structure 21, the conductive pillars 30 connected to the same side of the chip of the composite structure 20 farther from the rewiring layer 10 have a greater distance from the target chip 201A.

[0086] Figure 2 In FIG. 2 , L1 and L2 are distances between the conductive pillars 30 connected by the two composite structures 20 and the target chip 201A.

[0087] With the above arrangement, the second pads 203 and the conductive pillars 30 corresponding to the second pads 203 can be arranged more regularly, which is conducive to simplifying the preparation process of the semiconductor device 1. In addition, along the thickness direction of the composite structure 20, the second pads 203 in different composite structures 20 can be relatively staggered to avoid the conductive pillars 30 (except the conductive pillars 30 electrically connected to the second pads 203 of the first composite structure 21) from short-circuiting with the connecting traces 205 in other composite structures 20 when passing through the corresponding insulating layer 202, thereby affecting the function of the semiconductor device 1.

[0088] It is understandable that the sizes of the chips 201 in different composite structures 20 can be the same or different, and the present application does not limit this. In the case where the sizes of the chips 201 in each composite structure 20 are different, since the present application arranges the second pad 203 and the conductive column 30 on the insulating layer 202 outside the chip 201, each composite structure 20 can flexibly select its relative position in the semiconductor device 1 without being limited by the size of the chip 201.

[0089] For example, the smallest composite structure 20 of chip 201 can be used as the first composite structure 21 in semiconductor device 1, that is, arranged at the position closest to rewiring layer 10. The smallest composite structure 20 of chip 201 can also be arranged at other positions in semiconductor device 1.

[0090] In some embodiments, Figure 3A As shown, the plurality of composite structures 20 further include a third composite structure 23 and a fourth composite structure 24 located on a side of the first composite structure 21 away from the re-distribution layer 10. Compared with the fourth composite structure 24, the third composite structure 23 is closer to the re-distribution layer 10.

[0091] Exemplarily, along the direction from the fourth composite structure 24 to the third composite structure 23, and along the thickness direction of the fourth composite structure 24, the chip 201 in the fourth composite structure 24 is directly opposite to the chip 201 in the third composite structure 23, and the chip 201 in the fourth composite structure 24 covers the chip 201 in the third composite structure 23. In other words, the line connecting the center of the chip 201 in the third composite structure 23 and the center of the chip 201 in the fourth composite structure 24 is substantially perpendicular to the plane where the third composite structure 23 is located, and the orthographic projection of the chip 201 in the third composite structure 23 on the rewiring layer 10 is located within the orthographic projection range of the chip 201 in the fourth composite structure 24 on the rewiring layer 10.

[0092] In some examples, such as Figure 3A As shown, the distance between the chip 201 in the third composite structure 23 and the second pad 203 electrically connected thereto is equal to the distance between the chip 201 in the fourth composite structure 24 and the second pad 203 electrically connected thereto.

[0093] Therefore, it is convenient to design the second pad 203 of the third composite structure 23 and the second pad 203 of the fourth composite structure 24 , and the manufacturing process is simplified.

[0094] Of course, in some possible examples, such as Figure 3B As shown, the distance between the chip 201 in the third composite structure 23 and the second pad 203 electrically connected thereto is not equal to the distance between the chip 201 in the fourth composite structure 24 and the second pad 203 electrically connected thereto.

[0095] In some other examples, such as Figure 2 As shown, the chips 201 in each composite structure 20 overlap along the thickness direction of the composite structure 20. The orthographic projections of the chips 201 in each composite structure 20 on the plane where the rewiring layer 10 is located overlap.

[0096] Exemplarily, along the direction perpendicular to the plane where the rewiring layer 10 is located and along the direction from the first composite structure 21 to the second composite structure 22, the minimum distance between the chip 201 in each composite structure 20 and the second pad 203 electrically connected thereto gradually increases. Thus, the orthographic projections of each second pad 203 on the rewiring layer 10 can be made non-overlapping, and the conductive pillars 30 electrically connected to each second pad 203 can be staggered to avoid short circuit between the conductive pillars 30 and the second pad 203 or the connecting trace 205 on the corresponding insulating layer when the conductive pillars 30 pass through the corresponding insulating layer.

[0097] In the above-mentioned embodiments, the insulating layer 202 in the composite structure 20 may be made of various materials. For example, the insulating layer 202 may be made of inorganic materials or organic materials, which may be selected according to actual needs.

[0098] In some examples, the material of the insulating layer 202 includes an organic material, such as epoxy resin.

[0099] Therefore, the difficulty of the manufacturing process of the conductive pillar 30 can be reduced, and the manufacturing cost of the semiconductor device 1 can be reduced.

[0100] In some other examples, the material of the insulating layer 202 includes an inorganic material, which may be silicon oxide or the like.

[0101] In some embodiments, Figure 2 , Figure 3A and Figure 3B As shown, the composite structure 20 further includes a dielectric layer 206 covering the chip 201 and the insulating layer 202 .

[0102] The dielectric layer 206 covers the connection wiring layer 204, and protects the connection wiring 205 and the second pad 203 in the connection wiring layer 204, and prevents them from being corroded by water and oxygen, etc. The conductive column 30 passes through the insulating layer 202 and the dielectric layer 206 located above the corresponding second pad 203, and is electrically connected to the second pad 203. For example, the material of the dielectric layer 206 is an insulating material.

[0103] The material of the dielectric layer 206 may be the same as that of the insulating layer 202 , for example, epoxy resin or silicon oxide.

[0104] When preparing the conductive pillar, generally, an etching process is used to drill holes in the insulating layer and the dielectric layer, and then fill the holes with metal materials to form the conductive pillar. Since the dielectric layer and the insulating layer are made of the same material, the same etching process can be used to etch the dielectric layer and the insulating layer at the same time, which is conducive to simplifying the preparation process of the conductive pillar 30.

[0105] The material of the dielectric layer 206 and the material of the insulating layer 202 may also be different.

[0106] Some embodiments of the present application also provide a chip packaging structure 2, such as Figure 5 As shown, the chip packaging structure 2 includes: the semiconductor device 1 described in any of the above embodiments, as well as a packaging substrate 3 and a packaging shell 4. The packaging substrate 3 is connected to the side of the rewiring layer 10 away from the composite structure 20. The packaging shell 4 is buckled on multiple composite structures 20 and connected to the packaging substrate 3.

[0107] The packaging substrate 3 is combined with the packaging shell 4 to protect the semiconductor device 1 .

[0108] The beneficial effects of the chip packaging structure 2 provided in the above embodiment of the present application can be referred to the beneficial effects of the method for preparing the semiconductor device 1 mentioned above, which will not be repeated here.

[0109] Some embodiments of the present application also provide a method for preparing a semiconductor device, which is used to prepare the semiconductor device 1 in the above embodiment. Figure 6 As shown, the preparation method includes: S100~S400.

[0110] S100, such as Figure 7 As shown, multiple composite structures 20 are stacked to form the composite structure 20, which includes: a chip 201, an insulating layer 202 surrounding the chip 201, and at least one second pad 203 electrically connected to the chip 201; the second pad 203 is located on the insulating layer 202; the positions of the second pads 203 of each composite structure 20 along the first direction X are different; the first direction X is perpendicular to the thickness direction of the composite structure 20.

[0111] Along the thickness direction of the composite structure 20 , in two adjacent composite structures 20 , the chips 201 in each composite structure 20 are facing each other.

[0112] Each composite structure 20 may include a plurality of chips 201 . At this time, the insulating layer 202 is also filled between two adjacent chips 201 .

[0113] S200, such as Figure 8 As shown, an etching process is adopted to etch the insulating layer 202 of the plurality of composite structures 20 to form a through hole TH exposing each second pad 203 .

[0114] Compared with forming through holes by other processes (such as laser drilling process), the etching process (such as photolithography process) can make the size of each through hole TH smaller and the size accuracy higher, and the alignment degree between each through hole formed and the corresponding second pad 203 is higher, thereby improving the yield rate of the semiconductor device 1.

[0115] S300, such as Fig. 9 As shown, a conductive pillar 30 is formed in each through hole TH, and the conductive pillar 30 is in contact with the second pad 203 exposed by the through hole.

[0116] Exemplarily, the process of forming the conductive pillars 30 in the through holes may be a vapor deposition process, and the material of the conductive pillars 30 may be a metal, such as copper or tungsten.

[0117] By adopting the above-mentioned preparation method to form the through hole TH and the conductive column 30, the preparation method of the through hole TH and the conductive column 30 (such as etching process, etc.) can be made the same as or compatible with the preparation method of some structures of the chip 201, so that the equipment used in the chip preparation process can be used to prepare the above-mentioned through hole and conductive column, avoiding the redesign of a set of semiconductor device preparation methods and the addition of new preparation equipment, thereby simplifying the preparation process of the semiconductor device 1, shortening the preparation cycle of the semiconductor device 1, and reducing the preparation cost of the semiconductor device 1.

[0118] S400, such as Fig.10 As shown, a rewiring layer 10 is formed on a plurality of composite structures 20 . The rewiring layer 10 includes a plurality of first pads 11 . The first pads 11 are electrically connected to the conductive pillars 30 .

[0119] In the embodiment of the present application, multiple composite structures are first stacked to form multiple composite structures, and then an etching process is used to form a through hole exposing the second pad 203 at a position corresponding to the insulating layer 202 of the stacked multiple composite structures 20, and then a conductive column 30 is formed in the through hole, so that the conductive column 30 is electrically connected to the first pad 11 and the second pad 203, thereby avoiding the use of punching inside the chip 201 to realize the preparation process and integration method of multiple composite structures 20, without occupying the space and area inside the chip 201, which is conducive to realizing the miniaturization design of the semiconductor device, and can reduce the preparation cost of the through hole and the conductive column 30, and reduce the difficulty of the preparation process of the semiconductor device 1. It can also make the preparation process of the semiconductor device 1 compatible with the preparation process of the chip 201, which is conducive to simplifying the preparation process of the semiconductor device 1.

[0120] In some embodiments, forming the composite structure 20 includes: S101 - S105 .

[0121] S101, such as Fig.11 As shown, a carrier substrate 101 is provided.

[0122] For example, the material of the carrier substrate 101 may be glass. The carrier substrate 101 may provide support for the composite structure 20 .

[0123] S102, such as Fig.12 As shown, at least one chip 201 is arranged on the carrier substrate 101 .

[0124] Exemplarily, a plurality of chips 201 are fixed on the carrier substrate 101. The plurality of chips 201 are arranged at intervals, and there is a gap between two adjacent chips 201. For example, the plurality of chips 201 are arranged in an array.

[0125] When multiple chips 201 are arranged on the carrier substrate 101, each composite structure 20 can include multiple chips 201. After the conductive pillars are formed, the multiple chips in each layer of the composite structure can be separated along the thickness direction of the composite structure 20, thereby forming multiple semiconductor devices 1 at the same time, thereby shortening the preparation cycle of the semiconductor device 1.

[0126] S103, such as Fig.13 As shown, an insulating layer 202 is formed on the carrier substrate 101 ; the insulating layer 202 surrounds the chip 201 and covers the chip 201 .

[0127] For example, the process for forming the insulating layer 202 includes spin coating, etc. The material of the insulating layer 202 can be referred to the above introduction of the present application, which will not be described here.

[0128] For example, the material of the insulating layer 202 has a certain fluidity, and the material of the insulating layer 202 fills the gap between two adjacent chips 201 and around the chips 201. The surface of the insulating layer 202 away from the carrier substrate 101 is a substantially flat surface.

[0129] S104, such as Fig.14 As shown, the insulating layer 202 is ground to expose a surface of the chip 201 that is away from the carrier substrate 101 .

[0130] This facilitates the electrical connection between the subsequently formed connection wires 205 and the chip 201 .

[0131] For example, the insulating layer 202 may be ground and thinned by using a chemical mechanical polishing (CMP) process or a surface grinding process. After the insulating layer 202 is ground, the surface away from the carrier substrate 101 is flush with the surface of the chip 201 away from the carrier substrate 101.

[0132] S105, such as Fig.15 As shown, a connection wiring layer 204 is formed on a surface of the chip 201 away from the carrier substrate 101 . The connection wiring layer 204 includes connection wiring 205 and a second pad 203 . The chip 201 is electrically connected to the second pad 203 via the connection wiring 205 .

[0133] It is understandable that there are many ways to arrange the connection lines 205, which can be selected and set according to actual needs. Fig.15 In the figure, for the convenience of illustration, the arrangement of the connecting wires 205 is simplified to a straight line, which does not mean that all the connecting wires 205 in the embodiments of the present application are straight lines.

[0134] For example, the connecting wire 205 and the second pad 203 can be of the same layer and the same material. "Same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. Thus, patterning can be performed simultaneously in a single preparation process to simultaneously form the connecting wire 205 and the second pad 203, thereby simplifying the preparation process of the semiconductor device 1.

[0135] For example, Fig.16 As shown, after the connection wiring layer 204 is formed, a dielectric layer 206 is formed on a side of the connection wiring layer 204 away from the carrier substrate 101 , and the dielectric layer 206 covers the connection wiring 205 and the second pad 203 .

[0136] In some embodiments, the stacking to form a plurality of composite structures 20 in the above S100 includes: S110 to S140.

[0137] S110, such as Fig.17 As shown, the temporary substrate 102 is attached to the side of the i-th composite structure 20 away from the carrier substrate 101 ; wherein i is an integer, and i≥2.

[0138] S120, such as Fig.18 As shown, the carrier substrate 101 is removed.

[0139] S130, such as Fig.19 As shown, a side surface of the i-th composite structure 20 away from the temporary substrate 102 is bonded to a side surface of the (i-1)-th composite structure 20 .

[0140] The side surface of the (i-1)th composite structure 20 refers to the surface of the (i-1)th composite structure 20 that is away from the carrier substrate 101 .

[0141] S140, such as Fig. 20 As shown, the temporary substrate 102 is removed.

[0142] For example, the number of the plurality of composite structures 20 is n, where n is an integer, and n≥2, and i≤n.

[0143] Taking n as 4 as an example, i=2, i=3, and i=4 are sequentially selected to stack and form four composite structures 20. Specifically, when i=2, the above S110 to S140 are sequentially executed, and then when i=3, the above S110 to S140 are sequentially executed, and then when i=n=4, the above S110 to S140 are sequentially executed, thereby completing the stacking of four composite structures 20.

[0144] It is understandable that when multiple composite structures 20 are stacked, the carrier substrate of the first composite structure 20 is not removed, and the side surface of the second composite structure 20 away from the temporary substrate 102 is in contact with the side surface of the first composite structure 20 away from the carrier substrate 101. The side surface of the third composite structure 20 away from the temporary substrate is in contact with the surface of the second composite structure 20 away from the first composite structure 20. After the rewiring layer 10 is formed, the carrier substrate 101 of the first composite structure 20 can be removed.

[0145] In some embodiments, Fig.21 As shown, in the case where the composite structure 20 includes a plurality of chips 201, the plurality of chips 201 are arranged at intervals; the rewiring layer 10 has a dicing path 103, and in a direction perpendicular to the rewiring layer 10, the dicing path 103 is located between two adjacent chips 201, and separates the second pads 203 electrically connected to the two adjacent chips 201. The plurality of dicing paths 103 may be in a grid shape, and the chips 201 are located within the grid.

[0146] The preparation method further includes: cutting the plurality of composite structures 20 along the cutting paths 103 .

[0147] Thus, each composite structure 20 of a semiconductor component 1 includes only one chip 201 .

[0148] Some embodiments of the present application further provide an electronic device 5, which includes: the chip packaging structure 2 in any of the above embodiments.

[0149] Exemplarily, the electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0150] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A rewiring layer including a plurality of first pads; A plurality of composite structures are located on the rewiring layer and are stacked in a direction perpendicular to the plane where the rewiring layer is located; the composite structure comprises: a chip, an insulating layer surrounding the chip, and at least one second pad electrically connected to the chip, the second pad being located on the insulating layer; the second pads of the plurality of composite structures are located at different positions along a first direction; the first direction is perpendicular to the thickness direction of the composite structure; A plurality of conductive posts are located in at least one insulating layer of the composite structure; each of the conductive posts is connected to one of the second pads and one of the first pads.

2. The semiconductor device according to claim 1, wherein: The conductive pillars extend in a direction perpendicular to the plane where the rewiring layer is located, and the plurality of conductive pillars are arranged parallel to each other.

3. The semiconductor device according to claim 1, wherein: The composite structure closest to the rewiring layer among the plurality of composite structures is a first composite structure; Along a direction perpendicular to the plane where the rewiring layer is located and in a direction away from the rewiring layer, a distance between a conductive column connected to a second pad located on the same side of the chip in each composite structure and the chip of the first composite structure gradually increases.

4. The semiconductor device according to claim 3, characterized in that The plurality of composite structures further include: at least one second composite structure located on a side of the first composite structure away from the rewiring layer; along the thickness direction of the composite structure, the chips in each composite structure overlap; Along a direction perpendicular to the plane where the rewiring layer is located and along a direction from the first composite structure to the second composite structure, a minimum distance between the chip in each composite structure and a second pad electrically connected thereto gradually increases.

5. The semiconductor device according to claim 3, characterized in that The plurality of composite structures further include a third composite structure and a fourth composite structure located on a side of the first composite structure away from the rewiring layer, wherein the third composite structure is closer to the rewiring layer than the fourth composite structure; In the direction from the fourth composite structure to the third composite structure, and in the thickness direction of the fourth composite structure, the chip in the fourth composite structure is directly opposite to the chip in the third composite structure, and the chip in the fourth composite structure covers the chip in the third composite structure; the distance between the chip in the third composite structure and the second pad electrically connected thereto is equal to the distance between the chip in the fourth composite structure and the second pad electrically connected thereto.

6. The semiconductor device according to claim 1, wherein: In the at least one composite structure, there are multiple second pads electrically connected to the same chip; The chip and a plurality of second pads electrically connected thereto are equidistant from each other.

7. The semiconductor device according to claim 1, wherein: In the at least one composite structure, there are multiple second pads electrically connected to the same chip; The plurality of second bonding pads are located on at least two sides of the chip to which they are electrically connected.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that: The material of the insulating layer includes organic material.

9. The semiconductor device according to any one of claims 1 to 7, characterized in that: The composite structure further comprises: a connection routing layer; The connection wiring layer is located on a surface of one side of the chip close to the rewiring layer; The connection wiring layer includes connection wiring and a second pad, and the chip is electrically connected to the second pad through the connection wiring.

10. The semiconductor device according to any one of claims 1 to 7, characterized in that: The composite structure further comprises: a dielectric layer covering the chip and the insulating layer; The conductive column passes through the insulating layer and the dielectric layer above the corresponding second pad and is electrically connected to the second pad.

11. A chip packaging structure, characterized in that: The chip packaging structure comprises: a packaging substrate, a packaging shell, and a semiconductor device as claimed in any one of claims 1 to 10; The packaging substrate is connected to a side of the rewiring layer in the semiconductor device away from the composite structure; the packaging shell is buckled on a plurality of the composite structures and connected to the packaging substrate.

12. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: A plurality of composite structures are stacked to form the composite structures, the composite structures comprising: a chip, an insulating layer surrounding the chip, and at least one second pad electrically connected to the chip; the second pad is located on the insulating layer; the second pads of each composite structure are located at different positions along a first direction; the first direction is perpendicular to a thickness direction of the composite structure; Using an etching process, etching the insulating layers of the plurality of composite structures to form through holes exposing each of the second pads; forming a conductive column in each of the through holes, wherein the conductive column contacts the second pad exposed by the through hole; A rewiring layer is formed on the plurality of composite structures, wherein the rewiring layer includes a plurality of first pads, and the first pads are electrically connected to the conductive pillars.

13. The preparation method according to claim 12, characterized in that: Forming the composite structure comprises: providing a carrier substrate; disposing at least one chip on the carrier substrate; An insulating layer is formed on the carrier substrate; the insulating layer surrounds the chip and covers the chip; Grinding the insulating layer to expose a surface of the chip that is away from the carrier substrate; A connection wiring layer is formed on a surface of the chip at one side away from the carrier substrate. The connection wiring layer includes connection wiring and a second pad. The chip is electrically connected to the second pad through the connection wiring.

14. The preparation method according to claim 13, characterized in that: The stacking forms a plurality of composite structures, including: Laminating a temporary substrate on a side of the i-th composite structure away from the carrier substrate; wherein i is an integer and i≥2; removing the carrier substrate; Laying a surface of the i-th composite structure away from the temporary substrate to a surface of the i-1-th composite structure; The temporary substrate is removed.

15. The preparation method according to claim 12, characterized in that: In the case where the composite structure includes a plurality of chips, the plurality of chips are arranged at intervals; the rewiring layer has a cutting path, and in a direction perpendicular to the rewiring layer, the cutting path is located between two adjacent chips and separates the second pads electrically connected to the two adjacent chips; The preparation method further comprises: A plurality of the composite structures are cut along the cutting paths.

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