Semiconductor device

Abstract

The invention provides a semiconductor device capable of efficiently supplying a power supply voltage or a ground voltage to the inside of the semiconductor device even in a semiconductor device in which the arrangement interval of pads for connecting bumps is narrow. The semiconductor device includes: a first pad; a first wiring connected to the first pad in a first direction in a plan view; a second wiring connected to the first pad in a second direction different from the first direction in plan view; a second pad; a third wiring connected to the second pad in the first direction in a plan view; and a fourth wiring connected to the second pad in the second direction in plan view, the second wiring being located between the third wiring and the first pad in the second direction, and the fourth wiring being located between the first wiring and the second pad in the second direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] In a semiconductor device, for example, a terminal such as a bump for providing a power supply voltage or a ground voltage from the outside is sometimes arranged at a position overlapping with an input / output circuit. In addition, a power supply wiring for providing a power supply voltage or a ground voltage to the semiconductor device is sometimes arranged in multiple layers.

[0003] <Prior Art Documents>

[0004] <Patent Documents>

[0005] Patent Document 1: (Japanese) Patent Publication No. 2009-164195

[0006] Patent Document 2: (Japanese) Patent Publication No. 2012-234931

[0007] Patent Document 3: International Publication No. 2016 / 063458

[0008] Patent Document 4: U.S. Patent No. 10186504

[0009] Patent Document 5: U.S. Patent No. 7554133

[0010] Patent Document 6: U.S. Patent No. 8549447

[0011] Patent Document 7: U.S. Patent No. 8013362 Summary of the invention

[0012] <Problems to be Solved by the Invention>

[0013] Recently, as the semiconductor device element structure becomes smaller, there is a tendency for the arrangement interval of bumps to become narrower and the space for arranging power wiring to become smaller. Therefore, when the number of arranged power wirings is reduced, it may be difficult to efficiently provide power voltage or ground voltage to the semiconductor device.

[0014] The present invention has been made in order to solve the above problems, and an object of the present invention is to efficiently supply a power supply voltage or a ground voltage to the semiconductor device even in a semiconductor device in which the arrangement intervals of pads for connecting bumps are narrow.

[0015] <Methods for problem solving>

[0016] In one embodiment of the present invention, a semiconductor device includes: a first pad; a first wiring connected to the first pad in a first direction when viewed from above; a second wiring connected to the first pad in a second direction different from the first direction when viewed from above; a second pad; a third wiring connected to the second pad in the first direction when viewed from above; a fourth wiring connected to the second pad in the second direction when viewed from above, the second wiring being located between the third wiring and the first pad in the second direction, and the fourth wiring being located between the first wiring and the second pad in the second direction.

[0017] <Effects of the Invention>

[0018] According to the technology disclosed in the present invention, even in a semiconductor device in which the arrangement intervals of pads for connecting bumps are narrow, a power supply voltage or a ground voltage can be efficiently supplied to the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a diagram showing an overview of the semiconductor device in the first embodiment.

[0020] Figure 2 It is a plan view showing another example of a semiconductor device.

[0021] Figure 3 Yes means Figure 1 A plan view showing an example of a layout of power supply wiring in a circuit region of a semiconductor chip.

[0022] Figure 4 It means along Figure 3 A cross-sectional view of an example of a cross section taken along line X1-X1' and a cross section taken along line Y1-Y1'.

[0023] Figure 5 Yes means Figure 1 A plan view showing another example of the layout of power supply wiring in the circuit region of a semiconductor chip.

[0024] Figure 6 It is a plan view showing an example of the layout of power supply wiring in the semiconductor device according to the second embodiment.

[0025] Explanation of symbols

[0026] BMP Bump

[0027] CA Circuit Area

[0028] CHIP1, CHIP2 semiconductor chips

[0029] EXT external connection terminal

[0030] INS1, INS2 insulation film

[0031] IOC Input Output Unit

[0032] MWL multi-layer wiring layer

[0033] OPEN

[0034] PADL pad layer

[0035] PW power wiring

[0036] SEM semiconductor device

[0037] SUB semiconductor substrate

[0038] VDD power supply voltage, power supply wiring

[0039] VDDa, VDDb, VDDc, VDDd power supply wiring

[0040] VDDPAD power board

[0041] VSS ground voltage, power supply wiring

[0042] VSSa, VSSb, VSSc, VSSd power supply wiring

[0043] VSSPAD Power Board

[0044] VIA Through Hole

[0045] WSUB wiring substrate DETAILED DESCRIPTION

[0046] Hereinafter, the embodiment will be described using the accompanying drawings. Hereinafter, the symbol indicating the power supply voltage is also used as the symbol indicating the power supply wiring or power supply terminal to which the power supply voltage is supplied. In the top view and the cross-sectional view, the ratio of the width to the thickness of each wiring, the wiring spacing, the ratio of the thickness of the wiring layer, and the number of wirings arranged at a position overlapping with the bump BMP in the top view are not limited to those in the drawings.

[0047] (First embodiment)

[0048] Figure 1 The outline of the semiconductor device in the first embodiment is shown. For example, Figure 1 The semiconductor device SEM shown in the cross-sectional view includes a wiring substrate WSUB provided with external connection terminals EXT and a semiconductor chip CHIP1 connected to the wiring substrate WSUB via bumps BMP. The semiconductor chip CHIP1 is connected to the first surface of the wiring substrate WSUB via bumps BMP. The external connection terminals EXT are provided on the second surface opposite to the first surface.

[0049] The semiconductor chip CHIP1 has a semiconductor substrate SUB on which elements such as transistors (not shown) are formed, and a multilayer wiring layer MWL provided on the bump BMP side of the semiconductor substrate SUB. The semiconductor chip CHIP1, as shown in the top view, has a circuit area CA. The circuit area CA has a plurality of power supply wirings PW for providing power supply voltage and ground voltage to elements such as transistors provided in the circuit area CA. Each power supply wiring PW is electrically connected to the bump BMP to which the power supply voltage and ground voltage are provided.

[0050] Figure 2 Another example of a semiconductor device is shown. Figure 2 The semiconductor chip CHIP2 shown includes an input / output unit 10C provided in the chip periphery and a plurality of power supply lines PW for supplying a power supply voltage VDD and a ground voltage VSS to the input / output unit 10C. The power supply voltage VDD is an example of a first power supply voltage, and the ground voltage VSS is an example of a second power supply voltage.

[0051] In addition, the semiconductor chip CHIP2 has a bump BMP for supplying a power supply voltage VDD or a ground voltage VSS from outside the semiconductor chip CHIP2, for example, at a position overlapping with the region where each input / output unit IOC is provided in a plan view. The bump BMP supplied with the power supply voltage VDD is connected to the power supply wiring VDD in the power supply wiring PW. The bump BMP supplied with the ground voltage VSS is connected to the ground wiring VSS in the power supply wiring PW. The semiconductor chip CHIP2 and Figure 1 The semiconductor chip CHIP1 may also include a semiconductor substrate on which elements such as transistors (not shown) are formed and a multilayer wiring layer provided on the bump BMP side of the semiconductor substrate.

[0052] Figure 3 express Figure 1 An example of a layout of power supply wiring in the circuit area CA of the semiconductor chip CHIP1. Figure 1 As shown, in the circuit area CA, the bumps BMP are arranged in a sawtooth shape. Figure 3 And later, it means Figure 1 An example of the layout of the power supply wiring of the semiconductor chip CHIP1, but Figure 3 The layout methods shown below can also be applied to Figure 2 Layout of power supply lines of the semiconductor chip CHIP2.

[0053] The semiconductor chip CHIP1 has power pads VDDPAD and VSSAD and power wirings VDDa, VDDb, VDDc, VSSa, VSSb, and VSSc provided on a pad layer PADL, and the pad layer PADL is arranged on the bump BMP side along the Z direction which is the chip thickness direction. The power pad VDDPAD is an example of the first pad. The power pad VSSAD is an example of the second pad. The power wiring VDDa is an example of the first wiring, the power wiring VDDb is an example of the second wiring, and the power wiring VDDc is an example of the fifth wiring. The power wiring VSSa is an example of the third wiring, the power wiring VSSb is an example of the fourth wiring, and the power wiring VSSc is an example of the sixth wiring.

[0054] The power board VDDPAD is arranged at a position overlapping with a bump BMP (not shown) to which the power voltage VDD is provided in a plan view, and is connected to the bump BMP to which the power voltage VDD is provided. The power board VSSPAD is arranged at a position overlapping with a bump BMP (not shown) to which the ground voltage VSS is provided in a plan view, and is connected to the bump BMP to which the ground voltage VSS is provided. The power board VDDPAD and the power board VSSPAD are arranged in a zigzag shape in a plan view, and are arranged at positions staggered from each other in the X direction and the Y direction. The bump BMP connected to the power board VDDPAD is an example of the first bump, and the bump BMP connected to the power board VSSPAD is an example of the second bump.

[0055] In addition, the semiconductor chip CHIP1 has power wirings VDD and VSS provided on the multilayer wiring layer MWL located on the side of the pad layer PADL opposite to the bump BMP. The pad layer PADL is an example of a first wiring layer, and the multilayer wiring layer MWL is an example of a second wiring layer different from the pad layer PADL. The power wirings VDD and VSS correspond to Figure 1 The power supply wirings VDD and VSS extend in the Y direction and are alternately arranged with intervals in the X direction.

[0056] The power wiring VDD is an example of the seventh wiring, and the power wiring VSS is an example of the eighth wiring. The X direction is an example of the first direction, and the Y direction is an example of the second direction different from the X direction. The arrangement intervals of the power boards VDDPAD and VSPAD and the widths and intervals of the power wirings VDDa, VDDb, VSSa, and VSSb are not limited to Figure 3 In addition, the number of power supply wirings VDD and VSS arranged at positions overlapping with the power supply boards VDDPAD and VSPAD in a plan view is not limited to Figure 3 Example shown.

[0057] For example, the power supply pads VDDPAD and VSPAD and the power supply wirings VDDa, VDDb, VDDc, VSSa, VSSb, and VSSc are simultaneously formed by a semiconductor process for forming wirings on the pad layer PADL. For example, the power supply wirings VDD and VSS are simultaneously formed by a semiconductor process for forming wirings on the multilayer wiring layer MWL.

[0058] The power wiring VDDa is arranged at a position crossing the power board VDDPAD along the X direction in a plan view, and is connected to the power board VDDPAD. The power wiring VDDb is arranged on both sides of the power board VDDPAD in the Y direction along the X direction in a plan view, and is adjacent to the power wiring VSSa at a predetermined interval in the Y direction. The power wiring VDDc is arranged on both sides of the power board VDDPAD in the Y direction in a plan view, and is provided between the power board VDDPAD and the power wiring VDDb, and connects the power wiring VDDb to the power board VDDPAD.

[0059] The width of the power wiring VDDb in the Y direction and the width of the power wiring VDDc in the X direction are set to be less than the upper limit of the width of the power wiring in the layout rule. Therefore, the power wiring VDDb having a wider width in the X direction can be connected to the power board VDDPAD without violating the layout rule. The power wirings VDDa and VDDb are connected to the power wiring VDD of the multilayer wiring layer MWL through a plurality of through holes VIA respectively. The through hole VIA that connects the power wirings VDDa and VDDb to the power wiring VDD is an example of the first through hole.

[0060] The power wiring VSSa is arranged at a position crossing the power board VSPAD along the X direction in a plan view, and is connected to the power board VSPAD. The power wiring VSSb is arranged on both sides of the power board VSPAD in the Y direction along the X direction in a plan view, and is adjacent to the power wiring VDDa at a predetermined interval in the Y direction. The power wiring VSSc is arranged on both sides of the power board VSPAD in the Y direction in a plan view, and is provided between the power board VSPAD and the power wiring VSSb, and connects the power wiring VSSb to the power board VSPAD.

[0061] The width of the power wiring VSSb in the Y direction and the width of the power wiring VSSc in the X direction are set to be less than the upper limit of the width of the power wiring in the layout rule. Therefore, the power wiring VSSb with a wider width in the X direction can be connected to the power board VSPAD without violating the layout rule. The power wirings VSSa and VSSb are connected to the power wiring VSS of the multilayer wiring layer MWL through a plurality of vias VIA. The vias VIA that connect the power wirings VSSa and VSSb to the power wiring VSS are an example of the second via.

[0062] The power wiring VDDb is arranged at a position overlapping with the power board VSPAD and the power wirings VSSb and VSSc when extending in the X direction. That is, a part of the position of the power wiring VDDb in the Y direction coincides with the position of the power wiring VSSb in the Y direction, and another part of the position of the power wiring VDDb in the Y direction coincides with the position of the power board VSPAD in the Y direction.

[0063] The power wiring VSSb is arranged at a position overlapping with the power board VDDPAD and the power wirings VDDb and VDDc when extending in the X direction. That is, a part of the position of the power wiring VSSb in the Y direction coincides with the position of the power wiring VDDb in the Y direction, and another part of the position of the power wiring VSSb in the Y direction coincides with the position of the power board VDDPAD in the Y direction.

[0064] In addition, the interval W0 between the power boards VDDPAD and VSPAD in the Y direction is smaller than the width WVDDb of the power wiring VDDb in the Y direction and the width WVSSb of the power wiring VSSb in the Y direction. However, in this embodiment, the power wiring VDDb is arranged in the gap between the power board VDDPAD and the power wiring VSSa, and the power wiring VSSb is arranged in the gap between the power board VSPAD and the power wiring VDDa.

[0065] Thus, the power wirings VDDb and VSSb having widths WVDDb and WVSSb larger than the interval W0 between the power planes VDDPAD and VSPAD can be efficiently arranged in an empty area where the power planes VDDPAD and VSPAD and the power wirings VDDa and VSSa are not arranged.

[0066] Therefore, the power supply voltage VDD provided by each bump BMP to the power supply board VDDPAD can be efficiently distributed to the power supply wiring VDD of the multilayer wiring layer MWL through the power supply wirings VDDa and VDDb of the pad layer PADL. Similarly, the ground voltage VSS provided by each bump BMP to the power supply board VSPAD can be efficiently distributed to the power supply wiring VSS of the multilayer wiring layer MWL through the power supply wirings VSSa and VSSb of the pad layer PADL. That is, when the bumps BMP are arranged in a zigzag shape, the power supply resistance of the path for providing the power supply voltage VDD and the ground voltage VSS from each bump BMP to the power supply wirings VDD and VSS of the multilayer wiring layer MWL can be reduced.

[0067] On the other hand, for example, when connecting the auxiliary power wiring extending in the X direction to the power wiring VDDc and connecting the auxiliary power wiring extending in the X direction to the power wiring VSSc, the width of each auxiliary power wiring becomes thinner, or it becomes difficult to arrange the wires themselves. In addition, even when the auxiliary power wiring can be arranged, the size of the through hole VIA for connecting each auxiliary power wiring to the power wiring VDD and VSS of the multi-layer wiring layer MWL becomes smaller.

[0068] In this case, the power supply voltages VDD and VSS provided by each bump BMP cannot be efficiently distributed to the power supply wirings VDD and VSS of the multilayer wiring layer MWL, making it difficult to reduce the power supply resistance from each bump BMP to the power supply wirings VDD and VSS. Recently, with the miniaturization of semiconductor processes, the configuration pitch of the bumps BMP tends to become smaller, and the space between the power supply wirings VDDa and VSSa tends to become smaller. Therefore, it becomes increasingly difficult to reduce the power supply resistance.

[0069] Figure 4 Indicates along Figure 3 Examples of a cross section along line X1-X1' and a cross section along line Y1-Y1'. Figure 4 The cross section shown is Figure 1 The cross section of the semiconductor chip CHIP1 is inverted upside down. Figure 4 In the figure, elements such as transistors formed on the semiconductor substrate SUB are omitted. The semiconductor chip CHIP1 has a multilayer wiring layer MWL, a pad layer PADL and an insulating film INS1 sequentially arranged on the semiconductor substrate SUB. The bump BMP is connected to the power supply board VDDPAD exposed at the opening OPEN of the insulating film INS1. In addition, the insulating film INS1 can also be formed by stacking a plurality of insulating films.

[0070] In the cross section along the X1-X1' line, on the insulating film INS2 on the pad layer PADL side of the multilayer wiring layer MWL, a through hole VIA connected to the power wiring VDDa provided on the pad layer PADL, a power wiring VDD connected to the through hole VIA, and a power wiring VSS are formed. Furthermore, in the multilayer wiring layer MWL, not only power wiring but also signal wiring can be formed. In addition, in the multilayer wiring layer MWL, in the area closer to the semiconductor substrate SUB side than the insulating film INS2, not only wiring but also elements such as transistors can be formed. In addition, the insulating film INS2 can also be formed by stacking a plurality of insulating films.

[0071] In the cross section along the line Y1-Y1', a through hole VIA connected to the power wiring VSSa provided in the pad layer PADL and a power wiring VSS connected to the through hole VIA are formed in the insulating film INS2 on the pad layer PADL side of the multilayer wiring layer MWL. The power wiring VSSa is arranged between two power wirings VDDb respectively connected to the two bumps BMP (VDD) through the power wirings VDDa and VDDc.

[0072] Figure 5 express Figure 1 Another example of the layout of the power supply wiring in the circuit area CA of the semiconductor chip CHIP1 in FIG. Figure 3 The same or similar layout is omitted in detail. Figure 5 The layout shown in the figure has the following differences except that the number of through holes VIA connected to the power wirings VDDa and VDDb varies depending on the distance in the X direction of the power board VDDPAD, and the number of through holes VIA connected to the power wirings VSSa and VSSb varies depending on the distance in the X direction of the power board VSPAD. Figure 3 The layout is the same.

[0073] The number of through holes VIA connecting the power wirings VDDa and VDDb to the power wiring VDD increases as the distance from the power board VDDPAD in the X direction increases. The number of through holes VIA connecting the power wirings VSSa and VSSb to the power wiring VSS increases as the distance from the power board VSPAD in the X direction increases. Therefore, the configuration density of the power wiring VDD increases as the distance from the power board VDDPAD in the X direction increases, and the configuration density of the power wiring VSS increases as the distance from the power board VSPAD in the X direction increases.

[0074] Thus, it is possible to suppress the difference in supply capability when supplying the power supply voltage VDD to the power supply wiring VDD arranged far in the X direction relative to the power supply board VDDPAD in a plan view and the power supply voltage VDD arranged near the X direction. Similarly, it is possible to suppress the difference in supply capability when supplying the ground voltage VSS to the power supply wiring VSS arranged far in the X direction relative to the power supply board VSPAD in a plan view and the ground voltage VSS arranged near the X direction.

[0075] Since a uniform power supply voltage VDD can be provided to each power supply wiring VDD, and a uniform ground voltage VSS can be provided to each power supply wiring VSS, the difference in electrical characteristics (performance) of the circuit formed in the semiconductor chip CHIP1 due to the positions of the power boards VDDPAD and VSPAD can be suppressed. For example, the performance of the semiconductor device SEM is determined by the circuit with the lowest performance. In this embodiment, the reduction in circuit performance can be suppressed, so the performance of the semiconductor device SEM can be improved, and thus the yield of the semiconductor device SEM can be improved.

[0076] As described above, in the first embodiment, the power supply voltage VDD provided by each bump BMP to the power supply board VDDPAD can be efficiently distributed to the power supply wiring VDD of the multilayer wiring layer MWL through the power supply wirings VDDa and VDDb of the pad layer PADL. Similarly, the ground voltage VSS provided by each bump BMP to the power supply board VSPAD can be efficiently distributed to the power supply wiring VSS of the multilayer wiring layer MWL through the power supply wirings VSSa and VSSb of the pad layer PADL. That is, when the bumps BMP are arranged in a zigzag shape, the power supply resistance of the path for providing the power supply voltage VDD and the ground voltage VSS from each bump BMP to the power supply wirings VDD and VSS of the multilayer wiring layer MWL can be reduced.

[0077] The power wiring VDDb is arranged between the power board VDDPAD and the power wiring VSSa, and the power wiring VSSb is arranged between the power board VSPAD and the power wiring VDDa. Thus, the power wirings VDDb and VSSb having widths WVDDb and WVSSb greater than the interval W0 between the power boards VDDPAD and VSPAD can be efficiently arranged in an empty area where the power boards VDDPAD and VSPAD and the power wirings VDDa and VSSa are not arranged.

[0078] By setting the width of the power wiring VDDc in the X direction to be less than the upper limit of the width of the power wiring in the layout rule, the power wiring VDDb having a relatively wide width in the X direction can be connected to the power board VDDPAD. Similarly, by setting the width of the power wiring VSSc in the X direction to be less than the upper limit of the width of the power wiring in the layout rule, the power wiring VSSb having a relatively wide width in the X direction can be connected to the power board VSPAD.

[0079] A portion of the position of the power wiring VDDb in the Y direction coincides with the position of the power wiring VSSb in the Y direction, and another portion of the position of the power wiring VDDb in the Y direction coincides with the position of the power board VSPAD in the Y direction. Thus, the power wirings VDDb and VSSb can be efficiently arranged in an empty area where the zigzag power boards VDDPAD and VSPAD and the power wirings VDDa and VSSa are not arranged.

[0080] The number of vias VIA connecting power wirings VDDa and VDDb to power wiring VDD increases as the distance from power board VDDPAD in the X direction increases. The number of vias VIA connecting power wirings VSSa and VSSb to power wiring VSS increases as the distance from power board VSPAD in the X direction increases.

[0081] Thus, it is possible to suppress the difference in supply capability when supplying the power supply voltage VDD to the power supply wiring VDD arranged far in the X direction relative to the power supply board VDDPAD in a plan view and the power supply voltage VDD arranged near the X direction. Similarly, it is possible to suppress the difference in supply capability when supplying the ground voltage VSS to the power supply wiring VSS arranged far in the X direction relative to the power supply board VSPAD in a plan view and the ground voltage VSS arranged near the X direction.

[0082] Since a uniform power supply voltage VDD can be provided to each power supply wiring VDD, and a uniform ground voltage VSS can be provided to each power supply wiring VSS, the difference in electrical characteristics (performance) of the circuit formed in the semiconductor chip CHIP1 due to the positions of the power boards VDDPAD and VSPAD can be suppressed. For example, the performance of the semiconductor device SEM is determined by the circuit with the lowest performance. In this embodiment, the reduction in circuit performance can be suppressed, so the performance of the semiconductor device SEM can be improved, and thus the yield of the semiconductor device SEM can be improved.

[0083] (Second embodiment)

[0084] Figure 6 An example of a layout of power supply wiring in a semiconductor device according to the second embodiment is shown. Figure 3 The same or similar layout is omitted in detail. Figure 6 The layout shown in the figure is similar to the layout shown in the figure except that the power supply wiring VDDd is arranged instead of the power supply wiring VDDb and VDDc, and the power supply wiring VSSd is arranged instead of the power supply wiring VSSb and VSSc. Figure 3 The layout is the same.

[0085] Two power wirings VDDd are provided on both sides of the power board VDDPAD in the Y direction, and their front ends are adjacent to the power wiring VSSa at a predetermined interval. Two power wirings VSSd are provided on both sides of the power board VSPAD in the Y direction, and their front ends are adjacent to the power wiring VDDa at a predetermined interval. The width of the power wirings VDDd and VSSd in the X direction is set to be less than the upper limit of the width of the power wiring in the layout rule.

[0086] By extending the power wirings VDDd and VSSd in the Y direction, the length of the vias VIA connected to the power wirings VDDd and VSSd in the Y direction can be made shorter than Figure 3 The length of the through hole VIA connected to the power wiring VDDb and VSSb in the Y direction is longer. Figure 3 In terms of the layout, the power supply resistance of the path for supplying the power supply voltage VDD and the ground voltage VSS from each bump BMP to the power supply wirings VDD and VSS of the multilayer wiring layer MWL can be further reduced.

[0087] As described above, in the second embodiment, the same effects as those of the first embodiment can be obtained. For example, the power supply voltage VDD provided by the bump BMP to the power supply board VDDPAD can be efficiently distributed to the power supply wiring VDD, and the ground voltage VSS provided by the bump BMP to the power supply board VSPAD can be efficiently distributed to the power supply wiring VSS. That is, compared with the case where the power supply wirings VDDb and VSSb are not provided, the power supply resistance of the path for providing the power supply voltage VDD and the ground voltage VSS from each bump BMP to the power supply wirings VDD and VSS of the multilayer wiring layer MWL can be reduced.

[0088] Furthermore, in the second embodiment, by extending the power wirings VDDd and VSSd in the Y direction, the length of the vias VIA connected to the power wirings VDDd and VSSd in the Y direction can be made shorter than Figure 3 The length of the through hole VIA connected to the power wiring VDDb and VSSb in the Y direction is longer. Figure 3 In terms of the layout, the power supply resistance of the path for supplying the power supply voltage VDD and the ground voltage VSS from each bump BMP to the power supply wirings VDD and VSS of the multilayer wiring layer MWL can be further reduced.

[0089] As mentioned above, the present invention has been described based on each embodiment, but the present invention is not limited to the requirements shown in the above embodiment. In this regard, changes can be made within the scope that does not depart from the gist of the present invention and can be appropriately determined according to the application mode.

Claims

1. A semiconductor device comprising: 1st pad; a first wiring connected to the first pad in a first direction in a plan view; a second wiring connected to the first pad in a second direction different from the first direction in a plan view; The second pad; a third wiring connected to the second pad in the first direction in a plan view; and a fourth wiring connected to the second pad in the second direction in a plan view, The second wiring is located between the third wiring and the first pad in the second direction, The fourth wiring is located between the first wiring and the second pad in the second direction.

2. The semiconductor device according to claim 1, wherein The second pad is arranged at a position offset from the first pad along the first direction and the second direction.

3. The semiconductor device according to claim 1, wherein A distance between the first pad and the second pad in the second direction is smaller than a width of the second wiring in the second direction.

4. The semiconductor device according to claim 3, wherein: A distance between the first pad and the second pad in the second direction is smaller than a width of the fourth wiring in the second direction.

5. The semiconductor device according to claim 1, wherein A first power supply voltage is supplied to the first pad, A second power supply voltage different from the first power supply voltage is supplied to the second pad.

6. The semiconductor device according to claim 1, further comprising: a fifth wiring, provided between the first pad and the second wiring, and connecting the first pad and the second wiring; and a sixth wiring, which is provided between the second pad and the fourth wiring and connects the second pad and the fourth wiring, The width of the fifth wiring in the first direction is smaller than the width of the second wiring in the first direction. The width of the sixth wiring in the first direction is smaller than the width of the fourth wiring in the first direction.

7. The semiconductor device according to claim 1, wherein A portion of the position of the second wiring in the second direction coincides with the position of the fourth wiring in the second direction.

8. The semiconductor device according to any one of claims 1 to 7, further comprising: a seventh wiring and an eighth wiring, which are arranged at intervals in the first direction and extend in the second direction in a second wiring layer different from the first wiring layer in which the first wiring, the second wiring, the third wiring, and the fourth wiring are arranged; a first through hole connecting the first wiring and the second wiring to the seventh wiring; and The second through hole connects the third wiring and the fourth wiring to the eighth wiring, The number of the first through holes connecting the first wiring and the second wiring to the seventh wiring increases as the distance from the first pad in the first direction increases. The number of the second through holes that connect the third wiring and the fourth wiring to the eighth wiring increases as the distance from the second pad in the first direction increases.

9. The semiconductor device according to claim 1, wherein: On both sides of the first pad in the second direction, there are a plurality of second wirings extending along the second direction, respectively. The second pad has a plurality of fourth wirings extending along the second direction on both sides thereof.

10. The semiconductor device according to claim 1, further comprising: a first bump connected to the first pad; and The second bump is connected to the second pad.

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