Semiconductor device, preparation method and electronic equipment
By covering the protection layer with interface energy on the contact hole of the semiconductor device, the problem of damage caused by the increasing pore pores in traditional technologies in the traditional technology, and improved the reliability and electrical of the device.
Patent Information
- Application Number
- CN202411479318.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2025-01-21
AI Technical Summary
In traditional technology, removing natural oxides in contact holes will cause the top aperture of the contact hole to become larger, thereby damaging the semiconductor device and reducing its reliability.
The top surface of the protection stack of at least three layers of protective layers covers the interconnected medium structure. The interface capacity between the protective layers is there to protect its top surface from carved injuries in the case of cleaning and interconnection. The top width of the connecting holes is equal to the bottom width.
Effectively prevent plasma damage caused by excessive exposure holes, and improve the electrical and reliability of semiconductor devices.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method and an electronic device. Background Art
[0002] In the contact hole cleaning process, after the contact hole is formed, in order to prevent the natural oxide in the contact hole from affecting the contact resistance of the contact hole, the contact hole will be etched to remove the natural oxide before the plasma layer is formed. In traditional technology, the plasma sputtering process is used to remove the natural oxide in the contact hole and remove the impurity residue on the oxide.
[0003] However, the traditional technology of removing the natural oxide in the contact hole will cause damage to the contact hole and the interlayer dielectric layer, resulting in an increase in the top aperture of the contact hole. The increase in the top aperture increases the amount of plasma entering the contact hole in the subsequent process, and the excess plasma contacts the metal silicide at the bottom of the contact hole, which in turn causes more ions and electrons to be collected by the polysilicon, damaging the semiconductor device and reducing the reliability of the semiconductor device. Summary of the invention
[0004] The purpose of the present application is to provide a semiconductor device, a preparation method and an electronic device, which solves the problem that the removal of natural oxide in the contact hole causes the top aperture of the contact hole to become larger, which in turn causes more ions and electron currents to be collected by polysilicon and damage the semiconductor device, thereby improving the reliability of the semiconductor device.
[0005] To achieve the purpose of this application, this application provides the following technical solutions:
[0006] In a first aspect, the present application provides a semiconductor device, comprising:
[0007] substrate;
[0008] An interconnection dielectric structure, located on the top surface of the substrate, comprising a plurality of interconnection holes spaced apart and distributed along a first direction;
[0009] A protective stack covers the top surface of the interconnect dielectric structure, including at least three protective layers stacked in sequence along a second direction, wherein interface energy exists between the protective layers, so as to protect the top surface of the interconnect hole from being etched when the interconnect hole is cleaned, so that the top width of the interconnect hole is equal to the bottom width of the interconnect hole, wherein the first direction is perpendicular to the second direction.
[0010] The semiconductor device of the present application includes a substrate, an interconnection dielectric structure and a protective stack. The interconnection dielectric structure includes a plurality of interconnection holes spaced apart along a first direction. The protective stack covers the top surface of the interconnection dielectric structure and includes at least three protective layers stacked in sequence along a second direction. Interface energy exists between the protective layers due to different properties such as internal intermolecular forces. When the interconnection holes are cleaned, charged particles will encounter resistance when moving to the interface between the protective layers, thereby blocking the bombardment of plasma sputtering. The protective stack covers the top surface of the interconnection dielectric structure and can also protect the top surface of the interconnection dielectric structure from being damaged by etching, so that the top width of the interconnection hole is equal to the bottom width of the interconnection hole, thereby preventing damage to the semiconductor device caused by plasma in subsequent processes due to the excessively large top hole diameter of the contact hole, thereby improving the electrical properties and reliability of the semiconductor device.
[0011] In one embodiment, the protective layer includes a silicon oxide layer, wherein the number of silicon atoms is greater than the number of oxygen atoms.
[0012] In one embodiment, a dimension of the protection layer along the second direction is 100A-300A.
[0013] In one of the embodiments, under the same etching conditions, the difference between the etching rate of the protective layer and the etching rate of the interconnect dielectric structure is less than or equal to a preset value.
[0014] In one embodiment, the semiconductor device further includes:
[0015] A gate structure is located on the top surface of the substrate, the interconnection dielectric structure covers the gate structure, and the interconnection hole is located above the gate structure, and the interconnection hole and the gate structure are arranged in a one-to-one correspondence;
[0016] A source region is located in the substrate and on one side of the gate structure, the interconnection hole is located above the source region, and the interconnection hole and the source region are arranged in a one-to-one correspondence;
[0017] The drain region is located in the substrate and on a side of the gate structure away from the source region. The interconnection hole is located above the drain region. The interconnection hole and the drain region are arranged in a one-to-one correspondence.
[0018] In a second aspect, the present application further provides an electronic device, comprising: a semiconductor device as described in any one of the first aspects.
[0019] The electronic device of the present application includes: any semiconductor device in the first aspect. Due to the difference in properties such as internal intermolecular forces between the protective layers, there is interface energy. When cleaning the interconnection holes, charged particles will encounter resistance when moving to the interface between the protective layers, thereby blocking the bombardment of plasma sputtering. The protective stack covers the top surface of the interconnection dielectric structure, and can also protect the top surface of the interconnection dielectric structure from etching damage, so that the top width of the interconnection hole is equal to the bottom width of the interconnection hole, thereby preventing damage to the semiconductor device caused by plasma in subsequent processes due to the excessively large top hole diameter of the contact hole, thereby improving the electrical properties and reliability of the semiconductor device.
[0020] In a third aspect, the present application further provides a method for preparing a semiconductor device, comprising:
[0021] providing a substrate;
[0022] forming an interconnection dielectric structure on the top surface of the substrate, wherein the interconnection dielectric structure comprises a plurality of interconnection holes spaced apart and distributed along a first direction;
[0023] A protective stack is formed on the top surface of the interconnect dielectric structure, wherein the protective stack includes at least three protective layers stacked in sequence along a second direction, and interface energy exists between the protective layers, so that when the interconnect hole is cleaned, the top surface of the interconnect hole is protected from etching damage, so that the top width of the interconnect hole is equal to the bottom width of the interconnect hole, wherein the first direction is perpendicular to the second direction.
[0024] The method for preparing a semiconductor device of the present application first provides a substrate, then forms an interconnection dielectric structure on the top surface of the substrate, the interconnection dielectric structure includes a plurality of interconnection holes spaced and distributed along a first direction, and finally forms a protective stack on the top surface of the interconnection dielectric structure, the protective stack includes at least three protective layers stacked in sequence along a second direction, and there is interface energy between each protective layer, so that when the interconnection hole is cleaned, the top surface of the interconnection hole is protected from being damaged by etching, so that the top width of the interconnection hole is equal to the bottom width of the interconnection hole, wherein the first direction and the second direction are perpendicular. Due to the difference in properties such as the internal intermolecular force, there is interface energy between each protective layer, and when the interconnection hole is cleaned, charged particles will encounter resistance when moving to the interface between each protective layer, thereby blocking the bombardment of plasma sputtering, and the protective stack covers the top surface of the interconnection dielectric structure, and can also protect the top surface of the interconnection dielectric structure from being damaged by etching, so that the top width of the interconnection hole is equal to the bottom width of the interconnection hole, thereby preventing the plasma from damaging the semiconductor device in the subsequent process due to the excessively large top hole diameter of the contact hole, thereby improving the electrical properties and reliability of the semiconductor device.
[0025] In one embodiment, the protective layer includes a silicon oxide layer, wherein the number of silicon atoms is greater than the number of oxygen atoms.
[0026] In one embodiment,
[0027] The size of the protective layer along the second direction is 100A-300A;
[0028] Under the same etching conditions, the difference between the etching rate of the protective layer and the etching rate of the interconnect dielectric structure is less than or equal to a preset value.
[0029] In one embodiment, after providing the substrate and before forming the interconnect dielectric structure on the top surface of the substrate, the method further includes:
[0030] A gate structure is formed on the top surface of the substrate, the interconnection dielectric structure covers the gate structure, and the interconnection hole is located above the gate structure, and the interconnection hole and the gate structure are arranged in a one-to-one correspondence;
[0031] A source region is formed in the substrate, the source region is located on one side of the gate structure, and the interconnection hole is located above the source region, and the interconnection hole and the source region are arranged in a one-to-one correspondence;
[0032] A drain region is formed in the substrate, the drain region is located at one side of the gate structure, and the interconnection hole is located above the drain region, and the interconnection hole and the drain region are arranged in a one-to-one correspondence. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0034] FIG1 is a schematic cross-sectional view of a semiconductor device provided in an embodiment;
[0035] FIG2 is a flow chart of a method for preparing a semiconductor device provided in yet another embodiment;
[0036] FIG. 3 is a flow chart of steps S121 to S123 in a method for preparing a semiconductor device provided in yet another embodiment.
[0037] Description of Reference Numerals
[0038] 10. substrate; 20. interconnection dielectric structure; 201. interconnection hole; 202. interconnection dielectric layer; 30. protection stack; 301. protection layer; 40. gate structure; 401. gate dielectric layer; 402. gate conductive layer; 403. first sidewall; 404. second sidewall; 50. source region; 60. drain region; 70. metal silicide layer. DETAILED DESCRIPTION
[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0041] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0043] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0044] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.
[0045] In the contact hole cleaning process, after the contact hole is formed, in order to prevent the natural oxide in the contact hole from affecting the contact resistance of the contact hole, the contact hole will be etched to remove the natural oxide before the plasma layer is formed. In traditional technology, the plasma sputtering process is used to remove the natural oxide in the contact hole and remove the impurity residue on the oxide.
[0046] However, the traditional technology of removing the natural oxide in the contact hole will cause damage to the contact hole and the interlayer dielectric layer, resulting in an increase in the top aperture of the contact hole. The increase in the top aperture increases the amount of plasma entering the contact hole in the subsequent process, and the excess plasma contacts the metal silicide at the bottom of the contact hole, which in turn causes more ions and electrons to be collected by the polysilicon, damaging the semiconductor device and reducing the reliability of the semiconductor device.
[0047] Referring to FIG. 1 , an embodiment of the present application provides a semiconductor device, which includes: a substrate 10, an interconnect dielectric structure 20, and a protective stack 30. The interconnect dielectric structure 20 is located on the top surface of the substrate 10, and includes a plurality of interconnect holes 201 spaced apart along a first direction ox. The protective stack 30 covers the top surface of the interconnect dielectric structure 20, and includes at least three protective layers 301 stacked in sequence along a second direction oy. There is interfacial energy between the protective layers 301, so that when the interconnect holes 201 are cleaned, the top surface of the interconnect holes 201 is protected from being damaged by etching, so that the top width of the interconnect holes 201 is equal to the bottom width of the interconnect holes 201, wherein the first direction ox is perpendicular to the second direction oy.
[0048] The semiconductor device in the embodiment of the present application includes a substrate 10, an interconnection dielectric structure 20 and a protective stack 30. The interconnection dielectric structure 20 includes a plurality of interconnection holes 201 spaced apart along a first direction ox. The protective stack 30 covers the top surface of the interconnection dielectric structure 20 and includes at least three protective layers 301 stacked in sequence along a second direction oy. Due to the different properties such as the internal intermolecular force, there is interface energy between the protective layers 301. When the interconnection holes 201 are cleaned, the charged particles will encounter resistance when moving to the interface between the protective layers 301, thereby blocking the bombardment of plasma sputtering. In addition, the protective stack 30 covers the top surface of the interconnection dielectric structure 20, and can also protect the top surface of the interconnection dielectric structure 20 from being damaged by etching, so that the top width of the interconnection hole 201 is equal to the bottom width of the interconnection hole 201, thereby preventing the plasma from damaging the semiconductor device in the subsequent process due to the excessively large top hole diameter of the contact hole, thereby improving the electrical properties and reliability of the semiconductor device.
[0049] As an example, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate 10 deposited on a germanium silicon wafer; in the present embodiment, the substrate 10 is a silicon substrate.
[0050] As an example, the interconnection dielectric structure 20 is located on the top surface of the substrate 10, and includes a plurality of interconnection holes 201 spaced apart along the first direction ox. The interconnection holes 201 are used to fill the interconnection metal to form a current path between the metal layers. The interconnection dielectric structure 20 may also include an interconnection dielectric layer 202, which may be a stacked interconnection dielectric layer 202 stacked in sequence. The material of the interconnection dielectric layer 202 may be, but is not limited to, silicon oxide (SiO 2) , Silicon Nitride (SiN x ), aluminum oxide (Al2O3), low dielectric constant (Low-k) materials, high dielectric constant (High-k) materials, etc. The interconnect dielectric layer 202 can separate the metal layers to achieve electrical isolation of semiconductor devices, so as to achieve efficient transmission of signals in the multi-layer interconnect structure.
[0051] As an example, the protective stack 30 covers the top surface of the interconnect dielectric structure 20, and includes at least three protective layers 301 stacked in sequence along the second direction oy. For example, the number of protective layers 301 can be 3, 4, 5 or 6. Due to the different properties such as the internal intermolecular force, there is interface energy between the protective layers 301. In the case of cleaning the interconnect hole 201, the charged particles will encounter resistance when moving to the interface between the protective layers 301, thereby blocking the bombardment of plasma sputtering. In addition, the protective stack 30 covers the top surface of the interconnect dielectric structure 20, and can also protect the top surface of the interconnect dielectric structure 20 from being damaged by etching, so that the top width of the interconnect hole 201 is equal to the bottom width of the interconnect hole 201, thereby preventing the plasma from damaging the semiconductor device in the subsequent process due to the excessively large top hole diameter of the contact hole.
[0052] In some embodiments, the protection layer 301 includes a silicon oxide layer, wherein the number of silicon atoms is greater than the number of oxygen atoms.
[0053] As an example, the protective layer 301 may include a silicon oxide layer, which can protect the top surface of the interconnection dielectric structure 20 when the interconnection hole 201 is cleaned, and the number of silicon atoms is greater than the number of oxygen atoms, and the suspended silicon (Si) bonds of the silicon oxide layer itself can block the bombardment of plasma sputtering, effectively protecting the top surface of the interconnection hole 201 from etching damage, so that the top width of the interconnection hole 201 is equal to the bottom width of the interconnection hole 201.
[0054] In some embodiments, the dimension of the protection layer 301 along the second direction oy is 100A-300A.
[0055] As an example, the size of the protection layer 301 along the second direction oy is 100A-300A, for example, the size of the protection layer 301 along the second direction oy can be 100A, 150A, 200A, 250A or 300A. The size of the protection layer 301 along the second direction oy can effectively protect the interconnect dielectric structure 20 from etching damage while ensuring that the electrical properties of the device are not affected.
[0056] In some embodiments, please continue to refer to FIG. 1 , under the same etching conditions, the difference between the etching rate of the protection layer 301 and the etching rate of the interconnect dielectric structure 20 is less than or equal to a preset value.
[0057] As an example, under the same etching conditions, the difference between the etching rate of the protective layer 301 and the etching rate of the interconnect dielectric structure 20 is less than or equal to a preset value. When the contact holes of the interconnect dielectric structure 20 are cleaned, the protective layer 301 can be etched instead of the interconnect dielectric structure 20 to protect the interconnect dielectric structure 20 from etching damage.
[0058] In some embodiments, please continue to refer to Figure 1. The semiconductor device may also include: a gate structure 40, which is located on the top surface of the substrate 10, the interconnection dielectric structure 20 covers the gate structure 40, and the interconnection hole 201 is located above the gate structure 40, and the interconnection hole 201 and the gate structure 40 are arranged in a one-to-one correspondence; a source region 50, which is located in the substrate 10 and on one side of the gate structure 40, and the interconnection hole 201 is located above the source region 50, and the interconnection hole 201 and the source region 50 are arranged in a one-to-one correspondence; a drain region 60, which is located in the substrate 10 and on a side of the gate structure 40 away from the source region 50, and the interconnection hole 201 is located above the drain region 60, and the interconnection hole 201 and the drain region 60 are arranged in a one-to-one correspondence.
[0059] As an example, the gate structure 40 may include a gate dielectric layer 401, a gate conductive layer 402, a first sidewall 403 and a second sidewall 404; as an example, the gate dielectric layer 401 may include but is not limited to an oxide layer, such as a silicon dioxide layer; the gate conductive layer 402 may include but is not limited to a conductive layer, such as a doped polysilicon gate conductive layer 402 or a metal gate conductive layer 402, etc.; the first sidewall 403 and the second sidewall 404 are both insulating sidewalls, for example, the first sidewall 403 may include a silicon oxide sidewall, and the second sidewall 404 may include a silicon nitride sidewall. In other examples, the sidewall of the gate structure 40 may also be a single-layer structure. The interconnection dielectric structure 20 covers the gate structure 40, and the interconnection hole 201 is located above the gate structure 40. The interconnection hole 201 and the gate structure 40 are arranged one by one, and the electrical connection between the gate structure 40 and the interconnection metal layer can be realized through the contact hole to realize the transmission of electrical signals.
[0060] As an example, the conductivity type of the source region 50 may include one of the P-type conductivity type and the N-type conductivity type; the conductivity type of the drain region 60 may include one of the P-type conductivity type and the N-type conductivity type. The interconnection holes 201 and the source regions 50 are arranged in a one-to-one correspondence, and the interconnection holes 201 and the drain regions 60 are arranged in a one-to-one correspondence. The contact holes can realize the electrical connection between the source region 50, the drain region 60 and the metal layer, ensuring that the electrical signal is transferred from the semiconductor layer to the metal interconnection layer, or the electrical signal is transferred from the metal interconnection layer to the semiconductor layer.
[0061] It should be noted that, in some examples, please continue to refer to Figure 1, the preparation method of the semiconductor device of the present application may also include a metal silicide layer 70, and the metal silicide layer 70 is located on the upper surface of the source region 50, the upper surface of the drain region 60 and the upper surface of the gate conductive layer 402; the metal silicide layer 70 can reduce the contact resistance.
[0062] An embodiment of the present application further provides an electronic device, please continue to refer to FIG. 1 , comprising: a semiconductor device according to any one of the above embodiments.
[0063] The electronic device of the present application has interface energy between the protective layers 301 due to the different properties such as the internal intermolecular force. When cleaning the interconnection hole 201, the charged particles will encounter resistance when moving to the interface between the protective layers 301, thereby blocking the bombardment of plasma sputtering. In addition, the protective stack 30 covers the top surface of the interconnection dielectric structure 20, and can also protect the top surface of the interconnection dielectric structure 20 from being damaged by etching, so that the top width of the interconnection hole 201 is equal to the bottom width of the interconnection hole 201, thereby preventing the plasma from damaging the semiconductor device in the subsequent process due to the excessively large top hole diameter of the contact hole, thereby improving the electrical properties and reliability of the semiconductor device.
[0064] The present application also provides a method for preparing a semiconductor device, as shown in FIG2 , comprising:
[0065] S11: providing a substrate.
[0066] S13: forming an interconnection dielectric structure on the top surface of the substrate, wherein the interconnection dielectric structure comprises a plurality of interconnection holes spaced apart and distributed along a first direction.
[0067] S14: forming a protective stack on the top surface of the interconnect dielectric structure, the protective stack comprising at least three protective layers stacked in sequence along the second direction, interface energy existing between the protective layers, so as to protect the top surface of the interconnect hole from being damaged by etching when the interconnect hole is cleaned, so that the top width of the interconnect hole is equal to the bottom width of the interconnect hole, wherein the first direction and the second direction are perpendicular.
[0068] The method for preparing a semiconductor device of the present application first provides a substrate, then forms an interconnection dielectric structure on the top surface of the substrate, the interconnection dielectric structure includes a plurality of interconnection holes spaced and distributed along a first direction, and finally forms a protective stack on the top surface of the interconnection dielectric structure, the protective stack includes at least three protective layers stacked in sequence along a second direction, and there is interface energy between each protective layer, so that when the interconnection hole is cleaned, the top surface of the interconnection hole is protected from being damaged by etching, so that the top width of the interconnection hole is equal to the bottom width of the interconnection hole, wherein the first direction and the second direction are perpendicular. Due to the difference in properties such as the internal intermolecular force, there is interface energy between each protective layer, and when the interconnection hole is cleaned, charged particles will encounter resistance when moving to the interface between each protective layer, thereby blocking the bombardment of plasma sputtering, and the protective stack covers the top surface of the interconnection dielectric structure, and can also protect the top surface of the interconnection dielectric structure from being damaged by etching, so that the top width of the interconnection hole is equal to the bottom width of the interconnection hole, thereby preventing the plasma from damaging the semiconductor device in the subsequent process due to the excessively large top hole diameter of the contact hole, thereby improving the electrical properties and reliability of the semiconductor device.
[0069] As an example, please continue to refer to Figure 1, the substrate 10 may include but is not limited to at least one of a silicon substrate 10, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a germanium silicon wafer; in the present embodiment, the substrate 10 is a silicon substrate.
[0070] In another example, after step S11, the method for preparing the semiconductor device may further include the step of cleaning the substrate 10. In this way, by cleaning the substrate 10, impurities on the surface of the substrate 10 can be removed to prevent the impurities from affecting subsequent processes, thereby ensuring the performance of the device. Specifically, the substrate 10 can be cleaned with a cleaning solution to achieve cleaning of the substrate 10, or the substrate 10 can be purged with a gas such as nitrogen to achieve cleaning of the substrate 10. It should be noted that when the substrate 10 is cleaned with a cleaning solution, the step of drying the substrate 10 is also included after cleaning. Specifically, the substrate 10 can be purged with a gas such as nitrogen to dry the substrate 10, but is not limited to drying the substrate 10.
[0071] In another example, after step S11, the method for preparing the semiconductor device structure may further include making an alignment mark on the substrate 10. In this way, the alignment mark made on the substrate 10 can be used as an alignment reference mark for subsequent preparation processes or measurements, thereby ensuring the accuracy of subsequent preparation processes or measurements.
[0072] As an example, the interconnect dielectric structure 20 may include an interconnect dielectric layer 202 and a plurality of interconnect holes 201 spaced apart along a first direction ox. The interconnect dielectric layer 202 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or an atomic layer deposition process. The material of the interconnect dielectric layer 202 may be, but not limited to, silicon oxide (SiO2), silicon nitride (SiN x ), aluminum oxide (Al2O3), low dielectric constant (Low-k) materials, high dielectric constant (High-k) materials, etc. The interconnect dielectric layer 202 can separate the metal layers to achieve electrical isolation of semiconductor devices, so as to achieve efficient transmission of signals in the multi-layer interconnect structure.
[0073] As an example, the interconnection hole 201 may be formed by, but not limited to, a dry etching process or a wet etching process. The interconnection hole 201 is used to fill the interconnection metal to form a current path between the metal layers.
[0074] As an example, the protection stack 30 may be formed by, but is not limited to, a physical vapor deposition process, a chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or an atomic layer deposition process.
[0075] In some embodiments, please continue to refer to FIG. 1 , the protection layer 301 includes a silicon oxide layer, wherein the number of silicon atoms is greater than the number of oxygen atoms.
[0076] As an example, the protective layer 301 may include a silicon oxide layer, which can protect the top surface of the interconnection dielectric structure 20 when the interconnection hole 201 is cleaned, and the number of silicon atoms is greater than the number of oxygen atoms, and the suspended silicon (Si) bonds of the silicon oxide layer itself can block the bombardment of plasma sputtering, effectively protecting the top surface of the interconnection hole 201 from etching damage, so that the top width of the interconnection hole 201 is equal to the bottom width of the interconnection hole 201.
[0077] In some embodiments, referring to FIG. 1 , the size of the protection layer 301 along the second direction oy is 100A-300A; under the same etching conditions, the difference between the etching rate of the protection layer 301 and the etching rate of the interconnect dielectric structure 20 is less than or equal to a preset value.
[0078] As an example, the size of the protection layer 301 along the second direction oy is 100A-300A, for example, the size of the protection layer 301 along the second direction oy can be 100A, 150A, 200A, 250A or 300A. The size of the protection layer 301 along the second direction oy can effectively protect the interconnect dielectric structure 20 from etching damage while ensuring that the electrical properties of the device are not affected.
[0079] As an example, under the same etching conditions, the difference between the etching rate of the protective layer 301 and the etching rate of the interconnect dielectric structure 20 is less than or equal to a preset value. When the contact holes of the interconnect dielectric structure 20 are cleaned, the protective layer 301 can be etched instead of the interconnect dielectric structure 20 to protect the interconnect dielectric structure 20 from etching damage.
[0080] In some embodiments, referring to FIG. 3 , after providing the substrate 10 and before forming the interconnect dielectric structure 20 on the top surface of the substrate 10 , the following steps may be further included:
[0081] S121: forming a gate structure on the top surface of the substrate, the interconnection dielectric structure covers the gate structure, and the interconnection hole is located above the gate structure, and the interconnection hole and the gate structure are arranged in a one-to-one correspondence.
[0082] S122: forming a source region in the substrate, the source region being located at one side of the gate structure, and the interconnection hole being located above the source region, and the interconnection hole and the source region being arranged in one-to-one correspondence.
[0083] S123: forming a drain region in the substrate, the drain region is located at one side of the gate structure, and the interconnection hole is located above the drain region, and the interconnection hole and the drain region are arranged in a one-to-one correspondence.
[0084] As an example, forming the gate structure 40 may include the following steps: step S1211 to step S1213 .
[0085] S1211: forming a gate dielectric layer on the top surface of the substrate. For example, please continue to refer to FIG. 1 , the gate dielectric layer 401 may be formed on the top surface of the substrate 10 by, but not limited to, oxidation process (Oxidation), molecular beam epitaxy process (MBE), physical vapor deposition process (PVD), chemical vapor deposition (CVD) or atomic layer deposition process (ALD); the gate dielectric layer 401 may include, but not limited to, an oxide layer, such as a silicon dioxide layer.
[0086] S1212: forming a gate conductive layer on the surface of the gate dielectric layer away from the substrate. For example, please continue to refer to FIG1, the gate conductive layer 402 may be formed on the surface of the gate dielectric layer 401601 away from the substrate 10 by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, a low-pressure chemical vapor deposition process, an ion-enhanced chemical vapor deposition process or an atomic layer deposition process; specifically, the gate conductive layer 402 may include, but not limited to, a doped polysilicon layer or a metal layer, etc.
[0087] S1213: forming a first sidewall spacer and a second sidewall spacer on the sidewall of the gate conductive layer. For example, please continue to refer to FIG. 1 , the first sidewall spacer 403 and the second sidewall spacer 404 are both insulating sidewalls, for example, the first sidewall spacer 403 may include a silicon oxide sidewall, and the second sidewall spacer 404 may include a silicon nitride sidewall. In other examples, the sidewall of the gate structure 40 may also be a single-layer structure.
[0088] As an example, the conductivity type of the source region 50 may include one of a P-type conductivity type and an N-type conductivity type. For example, a P-type dopant may be implanted into the substrate 10 by, but not limited to, ion implantation to form a P-type conductivity type source region 50. Specifically, the P-type dopant may include, but not limited to, boron (B), gallium (Ga) or indium (In), etc.; of course, in other examples, an N-type dopant may be implanted into the substrate 10 by, but not limited to, ion implantation to form an N-type conductivity type source region 50. Specifically, the N-type dopant may include, but not limited to, nitrogen (N), phosphorus (P) or arsenic (As), etc.
[0089] As an example, the conductivity type that the drain region 60 may include may include one of a P-type conductivity type and an N-type conductivity type; as an example, a P-type conductivity type drain region 60 may be formed by injecting a P-type dopant into the substrate 10 by means of, but not limited to, ion implantation; of course, in other examples, an N-type conductivity type drain region 60 may be formed by injecting an N-type dopant into the substrate 10 by means of, but not limited to, ion implantation.
[0090] It should be noted that, in some examples, please continue to refer to Figure 1, the preparation method of the semiconductor device of the present application may also include a metal silicide layer 70, and the metal silicide layer 70 is located on the upper surface of the source region 50, the upper surface of the drain region 60 and the upper surface of the gate conductive layer 402; the metal silicide layer 70 can reduce the contact resistance.
[0091] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0092] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A semiconductor device, characterized in that: include: substrate; An interconnection dielectric structure, located on the top surface of the substrate, comprising a plurality of interconnection holes spaced apart and distributed along a first direction; A protective stack covers the top surface of the interconnect dielectric structure, including at least three protective layers stacked in sequence along a second direction, wherein interface energy exists between the protective layers, so as to protect the top surface of the interconnect hole from being etched when the interconnect hole is cleaned, so that the top width of the interconnect hole is equal to the bottom width of the interconnect hole, wherein the first direction is perpendicular to the second direction.
2. The semiconductor device according to claim 1, wherein: The protective layer includes a silicon oxide layer, wherein the number of silicon atoms is greater than the number of oxygen atoms.
3. The semiconductor device according to claim 1, wherein: The size of the protection layer along the second direction is 100A-300A.
4. The semiconductor device according to claim 1, wherein: Under the same etching conditions, the difference between the etching rate of the protective layer and the etching rate of the interconnect dielectric structure is less than or equal to a preset value.
5. The semiconductor device according to claim 1, wherein: Also includes: A gate structure is located on the top surface of the substrate, the interconnection dielectric structure covers the gate structure, and the interconnection hole is located above the gate structure, and the interconnection hole and the gate structure are arranged in a one-to-one correspondence; A source region is located in the substrate and on one side of the gate structure, the interconnection hole is located above the source region, and the interconnection hole and the source region are arranged in a one-to-one correspondence; The drain region is located in the substrate and on a side of the gate structure away from the source region. The interconnection hole is located above the drain region. The interconnection hole and the drain region are arranged in a one-to-one correspondence.
6. An electronic device, characterized in that: include: A semiconductor device as claimed in any one of claims 1 to 5.
7. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming an interconnection dielectric structure on the top surface of the substrate, wherein the interconnection dielectric structure comprises a plurality of interconnection holes spaced apart and distributed along a first direction; A protective stack is formed on the top surface of the interconnect dielectric structure, wherein the protective stack includes at least three protective layers stacked in sequence along a second direction, and interface energy exists between the protective layers, so that when the interconnect hole is cleaned, the top surface of the interconnect hole is protected from etching damage, so that the top width of the interconnect hole is equal to the bottom width of the interconnect hole, wherein the first direction is perpendicular to the second direction.
8. The method for preparing a semiconductor device according to claim 7, characterized in that: The protective layer includes a silicon oxide layer, wherein the number of silicon atoms is greater than the number of oxygen atoms.
9. The method for preparing a semiconductor device according to claim 7, characterized in that: The size of the protective layer along the second direction is 100A-300A; Under the same etching conditions, the difference between the etching rate of the protective layer and the etching rate of the interconnect dielectric structure is less than or equal to a preset value.
10. The method for preparing a semiconductor device according to claim 7, characterized in that: After providing the substrate and before forming the interconnect dielectric structure on the top surface of the substrate, the method further includes: A gate structure is formed on the top surface of the substrate, the interconnection dielectric structure covers the gate structure, and the interconnection hole is located above the gate structure, and the interconnection hole and the gate structure are arranged in a one-to-one correspondence; A source region is formed in the substrate, the source region is located on one side of the gate structure, and the interconnection hole is located above the source region, and the interconnection hole and the source region are arranged in a one-to-one correspondence; A drain region is formed in the substrate, the drain region is located at one side of the gate structure, and the interconnection hole is located above the drain region, and the interconnection hole and the drain region are arranged in a one-to-one correspondence.