Semiconductor chip scale package and method

Abstract

The present invention relates to a semiconductor chip scale package comprising: a semiconductor die comprising: a first main surface and a second main surface opposite to each other; a plurality of sidewalls extending between the first major surface and the second major surface; a plurality of electrical contacts arranged on the second main surface of the semiconductor die; and an insulating material disposed on the plurality of sidewalls and on the first main surface, the insulating material including a machine-readable identifier by which an identification device that reads the machine-readable identifier can identify a semiconductor chip scale package type, the machine-readable identifier including a color component.

Description

[0001] This application is a divisional application of the patent application with application number 2019110859090, application date November 8, 2019, and invention name “Semiconductor chip level package and method”. Technical Field

[0002] The present disclosure relates to a semiconductor chip scale package (CSP) and a method of forming the semiconductor chip scale package. More particularly, the present disclosure relates to a semiconductor CSP marked with a color-coded marking forming a machine and human readable identifier, and a method of forming a semiconductor CSP having such a marking. Background Art

[0003] Semiconductor devices are typically fabricated and packaged as individual devices, such as diodes or transistors, or as integrated circuits (ICs), and each integrated circuit chip typically includes thousands or millions of interconnected electrical devices fabricated on a single compact semiconductor substrate or wafer.

[0004] The fabrication of semiconductor integrated circuits can involve two processing stages: the front-end of the line (FEOL) processing stage and the back-end of the line (BEOL) processing stage. FEOL covers everything but the deposition of metal interconnect layers. In this stage, the individual electronic devices that form part of the integrated circuit are patterned directly onto the semiconductor substrate or wafer. A process known as front-end surface engineering also occurs, which includes the growth of surface oxides to form components such as gate dielectrics, the patterning of such gate devices and / or any necessary electronic components (such as channel, source and drain regions), and the implantation or diffusion of dopants to produce the appropriate charge carriers in the semiconductor material required to achieve the desired device characteristics.

[0005] The BEOL processing phase begins after the FEOL processing is completed. In this phase, electrical contacts or pads, interconnects, vertical electrical connections (vias) through the semiconductor wafer, and dielectric structures are formed. Typically, more than ten metal layers can be added to a modern IC during the BEOL process. This phase also includes cutting or segmenting the finished wafer into individual semiconductor dies. Each separate die is then packaged for structural support, package interconnection, and ingress protection. For example, the separated individual dies can be mounted on a custom package substrate with pins or contact pads for interconnection with other system components. Inside the custom package, the contact pads on the semiconductor die are electrically connected to the contact pads within the package to complete the circuit.

[0006] A chip-scale package (CSP) is an example of an integrated circuit or discrete package that uses FEOL and BEOL processes during manufacturing. According to industry standards, the package area or area / footprint of a CSP should not be greater than 1.2 times the package area or area of ​​the semiconductor die encapsulated in the package, and the CSP must be in the form of a single-die, directly surface-mountable package. CSPs typically do not have a package that includes insulating materials for encapsulating and protecting the semiconductor die. The back or top of the device is exposed to accommodate pattern markings for chip identification purposes. The pattern markings may, for example, include part numbers, manufacturing dates, company logos, manufacturing locations, or any other information.

[0007] Small CSPs have a relatively small surface area on the back or top exposed portions, which can make pattern marking for chip identification using existing marking techniques problematic because of the limited space for such markings. Known pattern marking techniques include, for example, laser ablation, photolithography, or photolithography followed by etching. In laser ablation, a laser beam is focused onto a semiconductor substrate, thereby destroying chemical bonds within the area to which the beam is applied and selectively removing material from the substrate surface. In laser ablation, the laser intensity, pulse length and wavelength, as well as the semiconductor material itself, affect the amount of surface material to be removed. During micromachining, photolithography can also be used to transfer the desired pattern markings to a film or semiconductor substrate by applying light through a photomask to a photosensitive chemical "photoresist" on the semiconductor substrate. Both marking processes are limited by the resolution of the laser used for the ablation process or the resolution of the client-side inspection camera.

[0008] Pattern marks on CSPs smaller than chip package size code 0603 (i.e., package size is approximately 0.6 mm, approximately code ca) are limited by the resolution of the patterning process and the tools used. Small pattern marks are generally expensive and difficult to create. For example, on 0603 products, the back or top of the package generally only provides enough exposed area to accommodate a single patterned character using laser ablation. Therefore, the variability of a single patterned character or a single number is limited to approximately 26 letters and 10 numbers.

[0009] Another problem that can arise involves using optical inspection tools to optically identify product pattern markings in small CSPs. The small features used in such product markings may not have the appropriate resolution to allow optical inspection tools to properly read and identify the CSP product.

[0010] In view of the foregoing, various aspects and embodiments of the present invention have been devised. Summary of the invention

[0011] According to one aspect of the present invention, a semiconductor chip-level package is provided, comprising: a semiconductor die, the semiconductor die comprising: a first main surface and a second main surface opposite to each other; a plurality of side walls extending between the first main surface and the second main surface; a plurality of electrical contacts arranged on the second main surface of the semiconductor die; and an insulating material disposed on the plurality of side walls and the first main surface, the insulating material comprising a machine-readable identifier, an identification device that reads the machine-readable identifier being able to identify the type of the semiconductor chip-level package through the machine-readable identifier, wherein the machine-readable identifier comprises a color component.

[0012] The present disclosure relates to color-coded markings on at least the back / top / side of a CSP. Color coding in this manner may not limit the resolution of any optical identification optics (e.g., an identification device used to identify the type of CSP based on a machine-readable identifier), or any resolution of the optical pattern used for marking creation. Machine-readable markings that allow identification of the type of CSP may be used even in situations where conventional marking types (e.g., characters or other forms of markings) would not be applicable because such marking types would be too small to be legible.

[0013] Using the marking method of the present disclosure, a wavelength spectrum of visible light providing a range of colors can be achieved. This is used to encode / label / mark semiconductor CSPs in the manner described above and below. Observation of such a spectrum by an identification device may require much simpler equipment than required by prior art identification methods, in which more complex equipment may be required to read small-sized patterns and / or characters.

[0014] The color-coded markings of the present disclosure can also be used in combination with, for example, pattern markings, which can increase variability. For example, variability can be increased to (26 letters plus 10 numbers) times the applicable colors.

[0015] Alternatively, the machine-readable identifier may comprise a metal oxide.

[0016] Optionally, the color component may contain a certain metal oxide or said metal oxide.

[0017] Alternatively, the machine-readable identifier may comprise aluminum oxide.

[0018] Alternatively, the machine-readable identifier may comprise titanium dioxide.

[0019] Optionally, the insulating material comprises a thickness of one layer or a combination of multiple layers, wherein the thickness is 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm, 160nm, 165nm, 170nm, 175nm, 180nm, 185nm The thickness may be selected from the group consisting of: a) a thickness of at least one metal oxide layer, b) a thickness of at least one metal oxide layer, and c) a thickness of at least one metal oxide layer. The thickness of the metal oxide layer may be selected from the group consisting of: a) a thickness of at least one metal oxide layer, and b) a thickness of at least one metal oxide layer. The thickness of the metal oxide layer may be selected from the group consisting of: a) a thickness of at least one metal oxide layer, and c) a thickness of at least one metal oxide layer.

[0020] Alternatively, the insulating material may be formed as a conformal layer on the semiconductor die by atomic layer deposition or low temperature PECVD.

[0021] Optionally, the color component may include an additive to the insulating material. Further optionally, the additive may include a dye or a paint.

[0022] Alternatively, the color component may comprise an additive disposed in a layer on the outer surface of the insulating material. Further alternatively, the additive may comprise a dye or a paint.

[0023] Alternatively, the color component may comprise an additive disposed in a layer on the inner surface of the insulating material. Further alternatively, the additive may comprise a dye or a paint.

[0024] Alternatively, surface structures formed in the surface and / or sidewalls of the die may be used to form the color components. Further optionally, the surface structures may include an optical lattice. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] For a more complete understanding of the present disclosure, reference is now made to the following description in conjunction with the accompanying drawings, in which

[0026] In the attached figure:

[0027] Figure 1 The spectrum of colored insulating material layers that can be achieved by forming multiple layers of aluminum oxide (Al2O3) thin films is shown. The thickness of the insulating material layer is in nm;

[0028] Figure 2 Three semiconductor wafers sawn on a frame with three different color-coded markings are shown, each wafer including about 300,000 semiconductor devices (0402 size), the color-coded markings being achieved by forming insulating layers of different thicknesses including aluminum oxide (Al2O3) and titanium dioxide (TiO2);

[0029] Figure 3 Shown are Figure 2 Three sample CSP devices (1006 size) with color-coded markings corresponding to the semiconductor devices shown. The sample CSP devices are also marked using conventional laser marking; and

[0030] Figures 4a to 4e A semiconductor CSP according to one or more embodiments of the present invention is shown. DETAILED DESCRIPTION

[0031] The claimed subject matter provides exemplary semiconductor CSPs including machine-readable identifiers, and methods of forming semiconductor CSPs having color-coded machine-readable identifiers for device identification purposes, wherein the identifiers include color markings (i.e., color-coded machine-readable identifiers). The machine-readable identifiers and methods of forming the same may also be applied to other semiconductor devices, such as, for example, bare dies or generally active semiconductor chips.

[0032] Conventional pattern marking methods impose limitations on the minimum allowable device marking size, which is typically determined by the laser ablation spot size, the resolution of the optical recognition optics, and / or the resolution of the pattern marking. The use of color-coded marking (i.e., by applying color to the device surface for marking) can invalidate these limitations by avoiding the need to use pattern marking all together in cases where the device surface for marking is too small.

[0033] According to the present disclosure, color-coded markings can also be used in combination with pattern markings, for example, where the device surface for marking is large enough to allow a single pattern marking. This can increase the marking variability to (26 letters and 10 numbers) times the applicable colors.

[0034] According to the present disclosure, applying color-coded markings to a surface portion of a CSP may be accomplished by an integrated process step during the fabrication of the CSP or by an additional process step after the fabrication process of the CSP is completed.

[0035] Integrated process step approach

[0036] In an integrated process step approach, color-coded markings can be applied to the CSP package at a final stage during the manufacturing process of the device, in which a layer of insulating material is applied to the outer surface of the CSP package for protective purposes, such as by atomic layer deposition (ALD). Color-coded markings can also be applied to the CSP by introducing the color as a byproduct during the wafer separation stage by plasma scribing / dicing, respectively. During separation by plasma scribing, a surface modification is performed to create an optical scattering lattice. Thus, the surface of the die encapsulated in a transparent insulating layer (to allow observation of the surface of the die) can be colored, the color of which depends on the type of optical scattering lattice.

[0037] ALD is a thin film deposition method in which a film can be grown on a semiconductor substrate or wafer by exposing the surface of the semiconductor substrate or wafer to alternating gaseous species or precursors. During the CSP manufacturing process, thin films can also be applied to the surface of the CSP to protect and seal the device and / or achieve desired optical reflective properties. ALD enables the user to apply a protective layer on the surface of the CSP device while independently adjusting or tuning the optical properties of the surface. Depending on the number of thin film layers and the materials added to the CSP surface during the ALD process, different colors can be achieved on the CSP surface. A detailed discussion of specific ALD processes is beyond the scope of this disclosure, as those skilled in the art will appreciate that the ALD process can allow for the deposition of near-perfect layers through continuous self-limiting surface reactions.

[0038] According to one or more embodiments, aluminum oxide may be deposited on the surface of a CSP by ALD to form an insulating material layer of a fixed thickness (e.g., 65 nm thick) to produce a CSP with a specific color-coded marking on the outer surface, in this case, brown. According to further embodiments, by varying the thickness of the deposited insulating material layer including aluminum oxide, different insulating material layers with different color-coded markings may be achieved, such as Figure 1 For example, four easily distinguishable colored films: purple, blue, green, and orange, can be produced using Al2O3 with thicknesses of 80nm, 110nm, 160nm, and 200nm, respectively.

[0039] An insulating material layer with color-coded markings can also be achieved by mixing aluminum oxide with other materials, such as titanium oxide. Al2O3 alone may be corroded by moisture, so since TiO2 is chemically more stable than Al2O3, the inclusion of a TiO2 layer can improve corrosion resistance. According to one or more embodiments, the insulating material layer is formed by one or more double layers of aluminum oxide and titanium oxide. Color-coded markings can be achieved on such insulating material layers by first applying an aluminum oxide thin film layer on the surface of the CSP and then applying a titanium oxide thin film layer on the first layer to form a double layer. The same double layer can then be repeatedly deposited on the first double layer to establish an insulating material layer of desired thickness to achieve an insulating material layer with desired color-coded markings. The stacking order of the metal oxides can also be changed so that, for example, the first thin film layer applied on the surface of the CSP can be titanium oxide, and the second thin film layer can be aluminum oxide. In addition to aluminum and titanium oxides, any suitable metal oxides can be used alone or in combination to achieve an insulating material layer with color-coded markings. The deposited layer of oxide material can have any suitable thickness to achieve the desired color-coded markings. The color is determined by the sum of the thicknesses of all deposited layers including the protective layer.

[0040] A typical range of insulating material layer thickness may be in the range of 1 nm to 350 nm, thereby enabling a broad spectrum of color-coded markings and keeping the requirement for the total package volume almost the same as the volume of the die.

[0041] For illustration purposes, Figure 2 Three different color-coded semiconductor wafers produced according to the method proposed in the previous paragraph are shown. Each wafer includes about 300 devices (i.e., 0402 size). The coloring of the top surface of these wafers can be achieved by stacking multiple double layers of titanium oxide TiO2 and aluminum oxide Al2O3 using an ALD process. For illustration purposes, Figure 3 A conceptual diagram showing three finished CSP products (size 1006), each of which includes Figure 2 One of three wafer examples shown with color-coded markings.

[0042] To achieve a "purple" color, an insulating layer including Al2O3 and TiO2 with a thickness of 50 nm may be used. To achieve a "blue" color, an insulating layer including Al2O3 and TiO2 with a thickness of 100 nm may be used. To achieve a "yellow" color, an insulating layer including Al2O3 and TiO2 with a thickness of 150 nm may be used.

[0043] In the integrated process step approach, in addition to the ALD process, color-coded markings can also be applied to the CSP as a byproduct during the plasma scribing process. Plasma scribing is a process used to cut or singulate wafers, i.e. separate them during the manufacturing process.

[0044] There are two methods of separation using plasma scribing, called "grinding before dicing" (GBD) and "dicing before grinding" (DBG). Both methods are also applicable to the more common blade scribing. The common process used for plasma scribing is called the "Bosch process". This dry etching process creates fan-shaped side walls on the tube core, which can be used as a light grid by forming grooves parallel to one of the two main surfaces called the back or front. Depending on the size of the grooves and the angle of incidence of the incident light, the surface appears to be colored.

[0045] Plasma scribing uses a dry etching process that utilizes fluorine chemistry. Unlike blade scribing, where contact occurs between the blade and the wafer during cutting, which can cause the wafer to chip or crack, there is no physical contact with plasma scribing. Also, unlike blade scribing, which requires longer blade processing time to perform more cut lines, the scribing process time for plasma scribing remains more or less the same regardless of the chip size. Therefore, plasma is suitable for cutting microchips of 500 square microns or less.

[0046] A byproduct of plasma scribing is the formation of multi-colored stripes on the semiconductor wafer surface during the singulation process. That is, due to some slight process variations and grooves / stripes, the walls of the CSP may appear multi-colored.

[0047] Additional process steps

[0048] In an additional process step approach, the color-coded markings may be applied to the CSP device after the fabrication of the CSP device or semiconductor wafer is completed. In the final manufacturing process step of the CSP, a layer of insulating material is applied to the outer package of the CSP device to encapsulate and protect the semiconductor die within the device. When this process is complete, a separate or additional manufacturing process step may be performed to apply the color-coded markings on top of the insulating material. The color-coded markings may be of the type of paint, dye, etc.

[0049] Figure 4a A semiconductor CSP 100 is shown including a semiconductor die 102 and a plurality of electrical contacts 104. The die 102 is encapsulated in an insulating layer 106, which includes a metal oxide such as, for example, Al2O3, TiO 2，The color of the insulating layer 106 depends on the thickness of the Al2O3 layer or the thickness of the TiO2 layer, or the sum of the thicknesses of the Al2O3 layer and the TiO2 layer (when both materials are present).

[0050] Figure 4b A semiconductor CSP 100 is shown including a semiconductor die 102 and a plurality of electrical contacts 104. The die 102 is encapsulated in an insulating layer 106 that includes an additive. The additive includes a coloring additive that provides the insulating layer 106 with a color component.

[0051] Figure 4c A semiconductor CSP 100 is shown including a semiconductor die 102 and a plurality of electrical contacts 104. The die 102 is encapsulated in an insulating layer 106, the outer surface of which is coated with a layer 108 containing additives. The additives include a coloring additive that provides the insulating layer 106 with a color component.

[0052] Figure 4d A semiconductor CSP 100 is shown including a semiconductor die 102 and a plurality of electrical contacts 104. The die 102 is encapsulated in a layer 112 that includes additives. The additives include a coloring additive that provides a color component to the layer 112. A transparent insulating layer 114 surrounds the layer 112 and allows viewing of the layer 112 below.

[0053] Figure 4e A semiconductor CSP 100 is shown comprising a semiconductor die 102 and a plurality of electrical contacts 104. The die 102 is encapsulated in an insulating layer 116 which comprises surface formations 118 in its outer surface. These surface formations provide a color component. Optionally, the surface formations 118 comprise an optical lattice.

[0054] Particular and preferred aspects of the invention are set out in the accompanying independent claims. Combinations of features from the dependent claims and / or the independent claim may be combined as appropriate and not just as set out in the claims.

[0055] The scope of the present disclosure includes any novel feature or combination of features disclosed therein, explicitly or implicitly, or any generalization thereof, whether or not related to the claimed invention or alleviating any or all problems solved by the invention. The applicant hereby gives notice that new claims may be made to these features during the course of the present application or any such further application derived therefrom. In particular, with reference to the appended claims, features of the dependent claims may be combined with features of the independent claims, and features of the independent claims may be combined in any appropriate manner and not only in the specific combinations listed in the claims.

[0056] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable subcombination.

[0057] The term "comprising" does not exclude other elements or steps and the terms "a", "an" or "an" do not exclude a plurality. Reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A semiconductor chip-level package, comprising: A semiconductor die comprising: a first main surface and a second main surface opposite to each other; a plurality of sidewalls extending between the first main surface and the second main surface; a plurality of electrical contacts disposed on the second major surface of the semiconductor die; an insulating material disposed on the plurality of sidewalls and the first major surface; and A layer including a machine-readable identifier, by which an identification device reading the machine-readable identifier can identify a type of semiconductor chip-scale package, wherein the machine-readable identifier further includes a color component of the color coding on the plurality of sidewalls and on the first major surface.

2. The semiconductor chip-scale package according to claim 1, wherein: The layer comprising the machine-readable identifier is an insulating layer comprising the insulating material.

3. The semiconductor chip-scale package according to claim 2, wherein: The machine-readable identifier also includes a metal oxide.

4. The semiconductor chip-scale package according to claim 2, wherein: The color-coded color component also includes a metal oxide.

5. The semiconductor chip-scale package according to claim 3, wherein: The color-coded color component also includes a metal oxide.

6. The semiconductor chip-scale package according to claim 2, wherein: The machine-readable identifier also includes aluminum oxide.

7. The semiconductor chip-scale package according to claim 2, wherein: The machine-readable identifier also includes titanium dioxide.

8. The semiconductor chip-scale package according to claim 6, wherein: The insulating layer further comprises one or more layers having a total thickness, wherein the total thickness of the insulating layer is selected from the group consisting of 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm, 160nm, 165nm, 170nm, 175nm, 180nm, 1 85nm, 190nm, 195nm, 200nm, 205nm, 210nm, 215nm, 220nm, 225nm, 230nm, 235nm, 240nm, 245nm, 250nm, 255nm, 260nm, 265nm, 270nm, 275nm, 280nm, 285nm, 290nm, 295nm, 300nm, 305nm, 310nm, 315nm, 320nm, 325nm, 330nm, 335nm, 340nm, 345nm, 350nm, and wherein the total thickness of the insulating layer determines the color of the color component of the color code of the machine readable identifier.

9. The semiconductor chip-scale package according to claim 6, wherein: The insulating layer comprises one or more layers having a total thickness of 5 nm to 350 nm, and wherein the total thickness of the insulating layer determines the color of the color component of the color code of the machine-readable identifier.

10. The semiconductor chip-scale package according to claim 7, wherein: The insulating layer comprises one or more layers having a total thickness of 5 nm to 350 nm, and wherein the total thickness of the insulating layer determines the color of the color component of the color code of the machine-readable identifier.

11. The semiconductor chip-scale package according to claim 2, wherein: The insulating material is formed as a conformal layer on the semiconductor die by atomic layer deposition or low temperature PECVD.

12. The semiconductor chip-scale package according to claim 2, wherein: The color-coded color composition also includes an additive to the insulating material.

13. The semiconductor chip-scale package according to claim 12, wherein: The additives also include dyes or paints.

14. The semiconductor chip-scale package according to claim 1, wherein: The layer is disposed on an outer surface of the insulating material, and wherein, The layer includes the color-coded color component, and the color-coded color component further includes an additive.

15. The semiconductor chip-scale package according to claim 14, wherein: The additives also include dyes or paints.

16. The semiconductor chip-scale package according to claim 1, wherein: The layer is disposed on an inner surface of the insulating material, and the layer includes a color component of the color code, and the color component of the color code further includes an additive.

17. The semiconductor chip-scale package according to claim 16, wherein: The additives also include dyes or paints.

18. The semiconductor chip-scale package according to claim 1, wherein: The color components of the color code are formed using surface structures formed in the surface and / or sidewalls of the die.

19. The semiconductor chip-scale package according to claim 18, wherein: The surface structure also includes an optical lattice.

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