Preparation method of high-gain antenna based on metal-assisted chemical etching and high-gain antenna

Abstract

The invention provides a high-gain antenna and a preparation method thereof, the high-gain antenna comprises a substrate, a buried oxide layer and top silicon in sequence, the substrate layer, the buried oxide layer and the top silicon are stacked and connected in sequence, and the buried oxide layer is used for isolating the substrate layer and the top silicon. The preparation method of the metal-assisted chemical etching high-gain antenna comprises the following steps: step 1, cleaning top silicon and smearing photoresist to form a photoresist layer; 2, performing magnetron sputtering on the photoresist layer to form a titanium layer, and depositing a metal layer on the titanium layer; step 3, removing the remaining photoresist, immersing the photoresist in an etching solution, and controlling the thickness of an etched air cavity by controlling the time of immersing the photoresist in the etching solution; and step 4, dissolving the metal falling into the silicon hole by using a dissolving solution to form the silicon microstructure with the air cavity. According to the preparation method of the high-gain antenna, the problem that the depth and the size of the etched cavity are difficult to control can be solved.

Description

Technical Field

[0001] The invention belongs to the technical field of nano devices and relates to a semiconductor manufacturing process, and in particular to a preparation method of a high-gain antenna based on metal-assisted chemical etching and the high-gain antenna. Background Art

[0002] Antennas are part of the transceiver equipment of communication systems. In order to meet the needs of mobile communication systems, antennas are constantly developing towards ultra-high frequency, miniaturization, and high integration. Silicon wafer etching is a key step in the production of silicon substrate patch antennas. The depth of the etched cavity, the verticality of the sidewalls, and the size directly affect the equivalent dielectric constant of the substrate. The traditional micromachining method is to etch a cavity on the high-resistance silicon substrate where the antenna is located to reduce the comprehensive equivalent dielectric constant under the patch. Relevant studies have shown that compared with the unetched high-price dielectric constant silicon substrate, the final antenna bandwidth and efficiency can be increased by etching the high-price dielectric constant silicon substrate, and the comprehensive equivalent dielectric constant of the etched high-price dielectric constant silicon substrate is similar to the antenna performance of the same low-price dielectric constant substrate. Some scholars have shown that the distance between the antenna radiation edge and the edge of the micromechanically etched cavity affects the antenna efficiency. However, due to the anisotropy of chemical etching used in micromechanical etching of silicon wafers, the side walls of the cavity are usually inclined and have low precision. However, silicon wafer etching is a key step in the production of on-chip antennas. The depth and size of the etched cavity directly affect the equivalent dielectric constant of the substrate, making it difficult to accurately control the performance of the final antenna.

[0003] In view of this, it is necessary for the present invention to provide a high-gain antenna and a method for preparing the high-gain antenna to solve the above problems. Summary of the invention

[0004] The purpose of the present invention is to provide a high-gain antenna and a preparation method, which can solve the problem of difficult-to-control etched cavity depth and size; can produce anisotropic high-depth ratio semiconductor microstructures and nanostructures, and can overcome the problems of inclination and low precision of micro-machined cavity side walls.

[0005] In order to solve the above technical problems, the present invention provides a high-gain antenna, which includes a substrate, a buried oxide layer, and a top silicon layer in sequence, wherein the substrate layer, the buried oxide layer and the top silicon layer are stacked and connected in sequence, and the buried oxide layer is used to isolate the substrate layer and the top silicon layer.

[0006] As a further improvement of the present invention, the preparation method is applied to the high-gain antenna in claim 1, and the preparation method comprises:

[0007] Step 1, cleaning the top silicon layer and applying photoresist to form a photoresist layer;

[0008] Step 2, magnetron sputtering a titanium layer on the photoresist layer, and depositing a metal layer on the titanium layer;

[0009] Step 3, removing the remaining photoresist, and immersing in an etching solution, and controlling the thickness of the etched air cavity by controlling the length of time of immersion in the etching solution;

[0010] Step 4: using a dissolving liquid to dissolve the metal that has fallen into the silicon pores to form a silicon microstructure with an air cavity.

[0011] As a further improvement of the present invention, the step 1 specifically comprises:

[0012] Step 1.1, spin-coating AZ5214 photoresist on the entire surface of the top silicon, and transferring the pattern on the first mask to the photoresist coating, covering the photoresist portion to be retained, exposing and developing the photoresist portion to be removed, and obtaining an SOI wafer with a cavity pattern outline on the top silicon;

[0013] Step 1.2, inductively coupled plasma etches the cavity pattern outline on the top silicon and sputters metal; the cavity pattern outline on the top silicon exposed by development is etched by an inductively coupled plasma etching method until the cavity pattern outline is etched, and the middle silicon oxide layer corresponding to the cavity pattern outline is etched away; the photoresist retained before is removed by a degumming liquid at an ambient temperature of 50°C; metal sputtering is used to sputter metal in the cavity outline gap to form a gold-plated outline; and an SOI wafer with a gold-plated outline on the top silicon is obtained.

[0014] As a further improvement of the present invention, the step 2 specifically comprises:

[0015] Step 2.1, performing double-sided exposure, alignment, and development on the SOI wafer to obtain an SOI wafer having four cross alignment mark patterns on the substrate layer;

[0016] Step 2.2, using an inductively coupled plasma etcher, etching four cross-marked grooves of a cavity pattern to be made with a depth of micrometer level on the substrate layer; removing the photoresist with a degumming liquid at an ambient temperature of 50° C. until the photoresist is completely removed;

[0017] Step 2.3, spin-coating photoresist on the base layer, exposing the grid-like pattern with an electron beam in the area defined by the four cross-marked grooves, and developing the grid-like pattern layer;

[0018] Step 2.4, depositing a titanium metal layer; using electron beam evaporation equipment to plate a titanium gold layer on the grid-shaped pattern layer.

[0019] As a further improvement of the present invention, the step 3 comprises:

[0020] Step 3.1, using a stripping solution at an ambient temperature of 70°C to completely remove the photoresist on other parts;

[0021] Step 3.2, metal-assisted chemical etching; place the silicon layer of the base layer upward, put an etching solution on the silicon layer of the base layer, and perform etching at room temperature to etch all the bottom silicon in the gold-plated grid pattern; when etching reaches the middle silicon oxide layer, the silicon connecting the supporting base layer and the middle silicon oxide layer corresponding to the grid pattern are etched away, and the formed nanocolumns float due to lack of support and are removed with the etching solution; a deep cavity structure is formed on the silicon layer of the base layer.

[0022] As a further improvement of the present invention, the metal removed in step 4 is configured as a precious metal; the dissolving solution is configured as a mixture of highly concentrated water, aluminum chloride and aluminum nitrate.

[0023] As a further improvement of the present invention, the dissolving liquid is configured as aqua regia, and the aqua regia is used to dissolve the metal falling into the silicon pores.

[0024] As a further improvement of the present invention, in step 2.4, the thickness of the titanium metal layer is 20 to 100 mm.

[0025] As a further improvement of the present invention, in step 3.2, the etching solution is prepared by uniformly mixing hydrogen peroxide with a concentration of 30%±0.5, hydrofluoric acid with a concentration of 49%±0.5 and deionized water in a ratio of 1:3:1 to 1:6:8.

[0026] As a further improvement of the present invention, the concentration of the hydrogen peroxide is configured to be 30%, and the concentration of the hydrofluoric acid is configured to be 49%.

[0027] As a further improvement of the present invention, the precious metal is configured as gold, platinum or silver.

[0028] The present invention provides a high-gain antenna and a preparation method thereof. The high-gain antenna comprises a substrate, a buried oxide layer, and a top silicon layer in sequence. The substrate layer, the buried oxide layer, and the top silicon layer are stacked and connected in sequence, and the buried oxide layer is used to isolate the substrate layer and the top silicon layer. The preparation method of the high-gain antenna using metal-assisted chemical etching comprises: step 1, cleaning the top silicon layer and applying photoresist to form a photoresist layer; step 2, magnetron sputtering a layer of titanium on the photoresist layer, and depositing a metal layer on the titanium layer; step 3, removing the remaining photoresist, and immersing in an etching solution, and controlling the thickness of the etched air cavity by controlling the length of time immersed in the etching solution; step 4, using a dissolving solution to dissolve the metal falling into the silicon hole to form a silicon microstructure with an air cavity. The preparation method of the high-gain antenna of the present invention can solve the problem that the depth and size of the etched cavity are difficult to control. The present invention uses metal-assisted chemical etching to etch the air cavity with a vertical side wall. At present, the conventional micromechanical etching uses anisotropic chemical etching when etching silicon wafers, and the sidewalls of the cavity are usually tilted and the precision is not high. However, silicon wafer etching is a key step in the production of on-chip antennas. The depth and size of the etched cavity directly affect the equivalent dielectric constant of the substrate, and it is difficult to accurately control the performance of the antenna. The present invention adopts a metal-assisted chemical etching method to produce anisotropic high-depth ratio semiconductor microstructures and nanostructures, which can overcome the problems of tilted sidewalls and low precision of micromechanical processing cavities. The cavity depth and size are easy to control, which is conducive to the stability of antenna performance and can further improve antenna performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the structure of the base layer of the high-gain antenna of the present invention after spin coating of photoresist.

[0030] Figure 2 It is a schematic diagram of the structure of the high-gain antenna of the present invention after photolithography and deposition of precious metals.

[0031] Figure 3 The schematic diagram is a structural diagram of removing the photoresist during the preparation process of the high-gain antenna of the present invention.

[0032] Figure 4 It is a schematic diagram of the structure of the high-gain antenna of the present invention immersed in an etching solution for etching during the preparation process.

[0033] Figure 5 It is a schematic diagram of the structure of the high-gain antenna of the present invention after the precious metal is removed during the preparation process.

[0034] Figure 6 It is a schematic structural diagram of the high-gain antenna of the present invention.

[0035] Figure 7 This is a diagram of the HFSS simulation results of the high-gain antenna of the present invention.

[0036] The descriptions of the reference numerals are as follows:

[0037] Base layer 1, photoresist 2, metal layer 3, etching solution 4, top silicon 5, buried oxide layer 6, substrate silicon 7. DETAILED DESCRIPTION

[0038] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. Especially for communications, the emphasis of each drawing is different, and sometimes different proportions are used.

[0039] Antennas are part of the transceiver equipment of communication systems. In order to meet the needs of mobile communication systems, antennas are constantly developing towards ultra-high frequency, miniaturization, and high precision. Silicon wafer etching is a key step in the production of silicon substrate patch antennas. The depth of the etched cavity, the verticality of the sidewalls, and the size directly affect the equivalent dielectric constant of the substrate. The traditional micromachining method is to etch a cavity on the high-resistance silicon substrate where the antenna is located to reduce the comprehensive equivalent dielectric constant under the patch.

[0040] Metal-assisted chemical etching can produce anisotropic high-depth-ratio semiconductor microstructures and nanostructures, overcoming the problems of inclination and low precision of the side walls of the micromachining cavity mentioned above. The cavity depth and size are easy to control, which is beneficial to the stability of antenna performance and can further improve antenna performance.

[0041] In order to better solve the problem that the depth of the etched cavity is difficult to control and the size is difficult to control, the present invention provides a high-gain antenna and a method for preparing the high-gain antenna based on metal-assisted chemical etching.

[0042] The high-gain antenna of the present invention comprises a base layer 1, a buried oxide layer 6, and a top silicon layer 5 in sequence. The base layer 1, the buried oxide layer 6, and the top silicon layer 5 are stacked and connected in sequence. The buried oxide layer 6 is used to isolate the base layer 1 and the top silicon layer 5.

[0043] The method for preparing a high-gain antenna based on metal-assisted chemical etching of the present invention, that is, the method for preparing a high-gain antenna of the present invention comprises:

[0044] Step 1, cleaning the top silicon layer 5 and applying photoresist 2 to form a photoresist 2 layer;

[0045] Step 2, magnetron sputtering a titanium layer on the photoresist layer 2, and depositing a metal layer 3 on the titanium layer;

[0046] Step 3, removing the remaining photoresist 2, and immersing it in an etching solution 4, and controlling the thickness of the etched air cavity by controlling the length of time of immersion in the etching solution 4;

[0047] Step 4: using a dissolving liquid to dissolve the metal that has fallen into the silicon pores to form a silicon microstructure with an air cavity.

[0048] The step 1 specifically includes:

[0049] Step 1.1, spin-coating the photoresist 2 on the entire surface of the top silicon 5, and transferring the pattern on the first mask to the coating of the photoresist 2, covering the part of the photoresist 2 to be retained, exposing and developing the part of the photoresist 2 to be removed, and obtaining the SOI wafer with the top silicon 5 having the cavity pattern outline;

[0050] Step 1.2, inductively coupled plasma etches the cavity pattern outline on the top silicon 5 and sputters metal; the cavity pattern outline on the top silicon 5 exposed by development is etched by an inductively coupled plasma etching method until the cavity pattern outline is etched, and the middle silicon oxide layer corresponding to the cavity pattern outline is etched away; a degumming solution is used to remove the previously retained photoresist 2 at an ambient temperature of 50°C; metal sputtering is used to sputter metal in the cavity outline gap to form a gold-plated outline; and an SOI wafer with a gold-plated outline on the top silicon 5 is obtained.

[0051] The step 2 specifically includes:

[0052] Step 2.1, performing double-sided exposure, alignment, and development on the SOI wafer to obtain an SOI wafer having four cross alignment mark patterns on the base layer 1;

[0053] Step 2.2, using an inductively coupled plasma etcher, etching four cross-marked grooves with a depth of micrometers on the base layer 1 for the cavity pattern to be made; using a degumming liquid to remove the photoresist 2 at an ambient temperature of 50° C. until the photoresist 2 is completely removed;

[0054] Step 2.3, spin-coating the photoresist 2 on the base layer 1, exposing the grid-like pattern in the area defined by the four cross-marked grooves with an electron beam, and developing the grid-like pattern layer;

[0055] Step 2.4, depositing a titanium metal layer 3; using electron beam evaporation equipment to plate a titanium gold layer on the grid-shaped pattern layer.

[0056] The step 3 specifically includes:

[0057] Step 3.1, using a stripping solution at an ambient temperature of 70° C. to completely remove the photoresist 2 of other parts;

[0058] Step 3.2, metal-assisted chemical etching; place the silicon layer of the base layer 1 upward, put the etching solution 4 on the silicon layer of the base layer 1, and perform etching at room temperature to etch all the bottom silicon in the gold-plated grid pattern; when etching to the middle silicon oxide layer, the middle silicon oxide layer connecting the silicon supporting the base layer 1 and the grid-like pattern is etched away, and the formed nanocolumns float due to lack of support and are removed with the etching solution 4; a deep cavity structure is formed on the silicon layer of the base layer 1.

[0059] Furthermore, the metal removed in step 4 is configured as a precious metal; the dissolving solution is configured as a mixture of highly concentrated water, aluminum chloride and aluminum nitrate.

[0060] Furthermore, the dissolving liquid is configured as aqua regia, and aqua regia is used to dissolve the metal that falls into the silicon pore. In the step 2.4, the thickness of the titanium metal layer 3 is 20 to 100 mm. In the step 3.2, the etching solution 4 is made by mixing hydrogen peroxide with a concentration of 30% ± 0.5, hydrofluoric acid with a concentration of 49% ± 0.5 and deionized water in a ratio of 1:3:1 to 1:6:8. The precious metal is configured as gold, platinum or silver. Preferably, in the present invention, the concentration of hydrogen peroxide is configured to 30%, and the concentration of hydrofluoric acid is configured to 49%. It should be noted that the above-mentioned 1:3:1 to 1:6:8 is a range interval for obtaining maximum and minimum values, and the present invention includes any numerical ratio of this interval.

[0061] That is, the production method includes:

[0062] Prepare the top silicon 5, such as Figure 1 As shown, AZ5214 photoresist 2 is spin-coated on the entire surface of the top silicon layer 5 of the SOI wafer; the pattern on the first mask is transferred to the photoresist 2 coating layer, the photoresist 2 portion to be retained is blocked, and the photoresist 2 portion to be removed is exposed and developed; and an SOI wafer with a cavity pattern outline on the top silicon layer 5 is obtained.

[0063] ICP etches the cavity pattern outline on the top silicon 5 layer and sputters the metal. Figure 2 As shown, the cavity pattern contour on the top silicon layer 5 exposed by development is etched by an inductively coupled plasma etching (ICP) method until the cavity pattern contour is etched, and the middle silicon oxide layer corresponding to the cavity pattern contour is etched away; the photoresist 2 retained before is removed by a degumming liquid at an ambient temperature of 50°C; gold is sputtered in the cavity contour gap by a metal sputtering method to form a gold-plated contour; and an SOI wafer with a gold-plated contour on the top silicon layer 5 is obtained.

[0064] Then, remove the photoresist 2 with a degumming solution at an ambient temperature of 50°C until the photoresist 2 is completely removed; prepare a cavity structure on the bottom silicon layer; set up a grid electron beam exposure and development; spin-coat PMMA photoresist 2 on the bottom silicon layer, and use an electron beam to expose a grid-like pattern in the area defined by the four cross-marked grooves to develop a grid-like pattern layer. Deposit a titanium metal layer 3; Figure 3 As shown, an electron beam evaporation device is used to plate a titanium gold layer on the grid pattern layer; and a degumming liquid NMP (N-methylpyrrolidone) is used to completely remove the PMMA photoresist 2 in other parts at an ambient temperature of 70°C.

[0065] Metal-assisted chemical etching; e.g. Figure 4 As shown, the bottom silicon layer is placed upward, and an etching liquid 4 is placed on the bottom silicon layer. Etching is performed at room temperature to etch all the bottom silicon in the gold-plated grid-like pattern. When etching reaches the middle silicon oxide layer, the middle silicon oxide layer corresponding to the grid-like pattern that is connected to support the bottom silicon is etched away, and the formed nanocolumns float without support and are removed along with the etching liquid 4. A large-area deep cavity structure is formed on the bottom silicon layer.

[0066] Remove precious metals. Figure 5 As shown in Figure 1, aqua regia is used to dissolve the precious metal that has fallen into the silicon pores, ultimately forming a silicon microstructure with air cavities. Figure 6 and Figure 7 As shown, the thickness of the silicon dielectric substrate used in this design is 200 microns. The formula is used to calculate the width of the antenna W0 = 0.984mm and the length L0 = 0.6825mm. The resonant frequency of the antenna reaches 76.5GHz and the gain is 1.27dB. After adjusting the length L0 of the patch and the width W1 of the 1 / 4 wavelength impedance converter, the final size of the antenna is: the length L0 and width W0 of the radiation patch are 603 microns and 984 microns respectively. In order to achieve impedance matching of the antenna, a 1 / 4 wavelength impedance converter is added between the microstrip line and the radiation patch. Its length L1 and width W1 are 445 microns and 6 microns respectively, and the width W2 of the 50Ω microstrip line is 138 microns. As shown Figure 7 As shown, the simulation results of 60GHz patch antenna S11 when the air cavity is etched in the substrate.

[0067] The present invention adopts metal-assisted chemical etching to form an air cavity with vertical side walls; SOI is used as the antenna substrate, and the influence of the metal-assisted chemical etching substrate on the antenna gain and resonant frequency. At present, the conventional micromechanical etching uses anisotropy of chemical etching when etching silicon wafers, and the side walls of the cavity are usually inclined and the precision is not high. However, silicon wafer etching is a key step in the production of on-chip antennas. The depth and size of the etched cavity directly affect the equivalent dielectric constant of the substrate, and it is difficult to accurately control the performance of the final antenna. The present invention adopts a metal-assisted chemical etching method. This method can produce anisotropic semiconductor microstructures and nanostructures with high aspect ratios, overcomes the problems of inclined side walls and low precision of the above-mentioned micromechanical processing cavity, and the cavity depth and size are easy to control, which is conducive to the stability of antenna performance and can further improve antenna performance. The present invention adopts SOI wafer. By comparing antennas with pure silicon substrate and SOI substrate of the same thickness, it is found that the microstrip antenna with SOI substrate has higher gain. The buried oxide layer 6 in SOI isolates the radiation patch of the antenna from the underlying silicon with high dielectric constant, reducing the loss of current by substrate silicon 7, so that the antenna gain is higher than that of the antenna with pure silicon substrate.

[0068] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0069] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high-gain antenna, characterized in that: The high-gain antenna comprises a base layer, a buried oxide layer, and a top silicon layer in sequence. The base layer, the buried oxide layer, and the top silicon layer are stacked and connected in sequence. The buried oxide layer is used to isolate the base layer and the top silicon layer.

2. A method for preparing a high-gain antenna based on metal-assisted chemical etching, characterized in that: The preparation method is applied to the high-gain antenna in claim 1, and the preparation method comprises: Step 1, cleaning the top silicon layer and applying photoresist to form a photoresist layer; Step 2, magnetron sputtering a titanium layer on the photoresist layer, and depositing a metal layer on the titanium layer; Step 3, removing the remaining photoresist, and immersing in an etching solution, and controlling the thickness of the etched air cavity by controlling the length of time of immersion in the etching solution; Step 4: using a dissolving liquid to dissolve the metal that has fallen into the silicon pores to form a silicon microstructure with an air cavity.

3. The preparation method according to claim 2, characterized in that: The step 1 specifically includes: Step 1.1, spin-coating photoresist on the entire surface of the top silicon, and transferring the pattern on the first mask to the coating of the photoresist, covering the photoresist portion to be retained, exposing and developing the photoresist portion to be removed, and obtaining an SOI wafer with a cavity pattern outline on the top silicon; Step 1.2, inductively coupled plasma etches the cavity pattern outline on the top silicon and sputters metal; the cavity pattern outline on the top silicon exposed by development is etched by an inductively coupled plasma etching method until the cavity pattern outline is etched, and the middle silicon oxide layer corresponding to the cavity pattern outline is etched away; the photoresist retained before is removed by a degumming liquid at an ambient temperature of 50°C; metal sputtering is used to sputter metal in the cavity outline gap to form a gold-plated outline; and an SOI wafer with a gold-plated outline on the top silicon is obtained.

4. The preparation method according to claim 2, characterized in that: The step 2 specifically includes: Step 2.1, performing double-sided exposure, alignment, and development on the SOI wafer to obtain an SOI wafer having four cross alignment mark patterns on the substrate layer; Step 2.2, using an inductively coupled plasma etcher, etching four cross-marked grooves of a cavity pattern to be made with a depth of micrometer level on the substrate layer; removing the photoresist with a degumming liquid at an ambient temperature of 50° C. until the photoresist is completely removed; Step 2.3, spin-coating photoresist on the base layer, exposing the grid-like pattern with an electron beam in the area defined by the four cross-marked grooves, and developing the grid-like pattern layer; Step 2.4, depositing a titanium metal layer; using electron beam evaporation equipment to plate a titanium gold layer on the grid-shaped pattern layer.

5. The preparation method according to claim 2, characterized in that: The step 3 comprises: Step 3.1, using a stripping solution at an ambient temperature of 70°C to completely remove the photoresist on other parts; Step 3.2, metal-assisted chemical etching; place the silicon layer of the base layer upward, put an etching solution on the silicon layer of the base layer, and perform etching at room temperature to etch all the bottom silicon in the gold-plated grid pattern; when etching reaches the middle silicon oxide layer, the silicon connecting the supporting base layer and the middle silicon oxide layer corresponding to the grid pattern are etched away, and the formed nanocolumns float due to lack of support and are removed with the etching solution; a deep cavity structure is formed on the silicon layer of the base layer.

6. The preparation method according to claim 2, characterized in that: In the step 4, the metal is removed and the metal is configured as a precious metal; the dissolving solution is configured as a mixture of highly concentrated water, aluminum chloride and aluminum nitrate.

7. The preparation method according to claim 2, characterized in that: The dissolving liquid is aqua regia, and the aqua regia is used to dissolve the metal that has fallen into the silicon pores.

8. The preparation method according to claim 4, characterized in that: In the step 2.4, the thickness of the titanium metal layer is 20 to 100 mm.

9. The preparation method according to claim 5, characterized in that: In the step 3.2, the etching solution is prepared by uniformly mixing hydrogen peroxide with a concentration of 30%±5%, hydrofluoric acid with a concentration of 49%±5%, and deionized water in a ratio of 1:3:1 to 1:6:

8.

10. The preparation method according to claim 9: the concentration of the hydrogen peroxide is 30%, and the concentration of the hydrofluoric acid is 49%.

11. The preparation method according to claim 6, characterized in that: The noble metal is gold, platinum or silver.

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