Bridgeless step-down power factor correction circuit

Abstract

The invention discloses a bridgeless step-down power factor correction circuit, and belongs to the technical field of electric energy conversion, the bridgeless step-down power factor correction circuit comprises a first switch, a second switch, a third switch, a fourth switch, a first winding and a second winding, the first end of the first switch is connected with the first end of alternating current, the second end of the first switch is connected with the first end of the first winding, and the second end of the third switch is connected with the second end of the fourth switch. The second end of the first winding is connected with the first end of the second winding, the second end of the second winding is connected with the second end of the second switch, and the first end of the second switch is connected with the second end of the alternating current; the third switch is connected with a series branch of the first winding and the load in parallel, and the fourth switch is connected with a series branch of the second winding and the load in parallel. According to the invention, the efficiency in the whole wide input voltage range can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electric energy conversion, and in particular to a bridgeless buck type power factor correction circuit. Background Art

[0002] With the development of power electronics technology, the extensive use of input capacitive filters will lead to serious harmonic pollution in the power grid. Therefore, most AC / DC conversion power supplies currently need to use a power factor correction circuit (PFC) to make the input current waveform close to a sine wave. The commonly used boost power factor correction circuit (Boost PFC) can improve the current power factor and reduce current harmonics. However, in wide-range input applications, the boost power factor correction circuit requires a large gain to meet the function realization, so the efficiency is low.

[0003] Compared with the traditional boost power factor correction circuit, the buck power factor correction circuit can maintain a higher efficiency over the entire wide input voltage range. However, since the front stage needs to be connected to a rectifier bridge for AC-DC conversion, there is a problem of low efficiency of the buck power factor correction circuit at low input voltage due to the rectifier bridge. Summary of the invention

[0004] The present invention aims to provide a bridgeless buck power factor correction circuit, which can improve the efficiency within a wide input voltage range.

[0005] To achieve the above object, the technical solution of the present invention is:

[0006] A bridgeless step-down power factor correction circuit, characterized in that it includes a first switch, a second switch, a third switch, a fourth switch, a first winding and a second winding, wherein the first end of the first switch is connected to the first end of the alternating current, the second end of the first switch is connected to the first end of the first winding, the second end of the first winding is connected to the first end of the second winding, the second end of the second winding is connected to the second end of the second switch, and the first end of the second switch is connected to the second end of the alternating current; the third switch is connected in parallel with the series branch of the first winding and the load, and the fourth switch is connected in parallel with the series branch of the second winding and the load.

[0007] The above-mentioned bridgeless buck power factor correction circuit also includes: a first inductor and a second inductor; one end of the first inductor is connected between the first winding and the second winding, and the other end is connected to the load; the second inductor is connected in parallel with the first winding.

[0008] The above-mentioned bridgeless buck power factor correction circuit also includes a first capacitor and a second capacitor, the first capacitor is connected in parallel with the series branch of the first switch and the third switch; the second capacitor is connected in parallel with the series branch of the second switch and the fourth switch.

[0009] The above-mentioned bridgeless buck power factor correction circuit also includes: a third inductor, a first capacitor, a second capacitor and a third capacitor, the third inductor is located between the first switch and the alternating current, the first end of the first switch is connected to the first end of the alternating current via the third inductor, the first capacitor is connected in parallel with the series branch of the first switch and the third switch, the second capacitor is connected in parallel with the series branch of the second switch and the fourth switch, the first end of the third capacitor is connected between the third inductor and the first end of the first switch, and the second end of the third capacitor is connected between the second end of the alternating current and the first end of the second switch.

[0010] The above-mentioned bridgeless buck power factor correction circuit also includes a third winding, a third diode, a fourth diode, a fifth diode and a sixth diode, the first end of the third winding is connected to the anode of the fifth diode and the cathode of the sixth diode, the second end of the third winding is connected to the anode of the third diode and the cathode of the fourth diode, the cathode of the third diode is connected to the cathode of the fifth diode, the anode of the fourth diode is connected to the anode of the sixth diode, the cathode of the fifth diode is connected to the first end of the load, and the anode of the sixth diode is connected to the second end of the load.

[0011] In a specific embodiment, the third switch and the fourth switch are diodes.

[0012] Furthermore, the number of turns of the first winding is equal to that of the second winding, and the first end of the third winding is a same-name end.

[0013] Furthermore, the first end of the first winding and the first end of the second winding are the same end.

[0014] In a specific embodiment, the first switch and the second switch are MOSFETs, the first end of the first switch is the drain of the MOSFET, and the second end of the first switch is the source of the MOSFET; the first end of the second switch is the drain of the MOSFET, and the second end of the second switch is the source of the MOSFET.

[0015] The above-mentioned bridgeless buck power factor correction circuit also includes: a first inductor, a second inductor, a first capacitor and a second capacitor, the first inductor is located between the first switch and the alternating current, the first end of the first switch is connected to the first end of the alternating current via the first inductor, the second inductor is connected in parallel with the first winding, the first capacitor is connected in parallel with the series branch of the first switch and the third switch, and the second capacitor is connected in parallel with the series branch of the second switch and the fourth switch.

[0016] Beneficial effect: The bridgeless buck power factor correction circuit of the present invention can improve the efficiency within the entire wide input voltage range; at the same time, it can suppress the voltage spikes of the switch and the diode.

[0017] In order to make the above features and advantages of the invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The figure is a circuit diagram of a first specific embodiment of a bridgeless buck power factor correction circuit of the present invention.

[0019] Figure 2 The figure is a circuit diagram of a second specific embodiment of a bridgeless buck power factor correction circuit of the present invention.

[0020] Figure 3 The figure is a circuit diagram of a third specific embodiment of a bridgeless buck power factor correction circuit of the present invention.

[0021] Figure 4 This is a circuit diagram of a fourth specific embodiment of a bridgeless buck power factor correction circuit of the present invention.

[0022] Figure 5 This is a circuit diagram of a fifth specific embodiment of a bridgeless buck power factor correction circuit of the present invention.

[0023] Figure 6 For the positive half cycle of AC Figure 1 Schematic diagram of the switch drive voltage, output current, excitation current, and voltage across the diode in the circuit.

[0024] Figure 7 Negative half cycle of AC Figure 1 Schematic diagram of the switch drive voltage, output current, excitation current, and voltage across the diode in the circuit.

[0025] Figure 8 for Figure 1 Simulation waveform of the circuit in .

[0026] Figure 9(a) shows the voltage u across switch Q1 before reducing the conduction angleQ1 Waveform diagram of .

[0027] Figure 9(b) shows the voltage u across switch Q1 after reducing the conduction angle Q1 Waveform DETAILED DESCRIPTION

[0028] In order to make the purpose and technical solution of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] Figure 1 FIG. 1 is a circuit diagram of a first specific embodiment of a bridgeless buck power factor correction circuit of the present invention. Figure 1 As shown, a bridgeless buck power factor correction circuit of the present invention includes a switch Q1, a switch Q2, a diode D1, a diode D2, a winding N1, a winding N2, an inductor L o With capacitor C o , the first end of the switch Q1 is connected to the AC current u ac The first end of the switch Q1 is connected to the first end of the winding N1, the second end of the winding N1 is connected to the first end of the winding N2, the second end of the winding N2 is connected to the second end of the switch Q2, and the first end of the switch Q2 is connected to the AC voltage u ac The second end of the winding N1 is connected to the inductor L o The first end of the inductor L o The second end of the capacitor C o The first end of the capacitor C o The second end of the capacitor C is connected to the anode of the diode D1, the cathode of the diode D1 is connected to the second end of the switch Q1, and the o The second end of the capacitor C is connected to the anode of the diode D2, and the cathode of the diode D2 is connected to the second end of the switch Q2; o A load R is also connected in parallel at both ends load , capacitor C o The output voltage V o .

[0030] Among them, the diode D1 and the diode D2 play the role of freewheeling.

[0031] Further, the first end of the winding N1 and the first end of the winding N2 are the same-named ends.

[0032] Furthermore, the number of turns of the winding N1 is equal to that of the winding N2.

[0033] Furthermore, the inductor L m Connected in parallel across the two ends of winding N1, it is the magnetizing inductance of winding N1.

[0034] Optionally, the switch Q1 and the switch Q2 are MOSFETs, the first end of the switch Q1 is the drain of the MOSFET, and the second end of the switch Q1 is the source of the MOSFET; the first end of the switch Q2 is the drain of the MOSFET, and the second end of the switch Q2 is the source of the MOSFET.

[0035] Optionally, the switch Q1 and the switch Q2 may be other semiconductor devices.

[0036] Next, continue to combine Figure 1 The working principle of a bridgeless buck power factor correction circuit of the present invention is introduced. ac In the positive half cycle, switch Q1 is a high frequency switch, and switch Q2 can be always on or switch synchronously with switch Q1. The working principles of these two methods are the same. The working principle of the present invention is explained below by taking switch Q2 and switch Q1 switching synchronously as an example.

[0037] In AC u ac In the positive half cycle, when switch Q1 is turned on, diode D1 is reversely cut off, switch Q2 and diode D2 are turned on, at this time, the relationship between voltage and current in the circuit is as follows:

[0038] i in =i m +i1,

[0039] i o =i m +i1+i2,

[0040] V1=V2=0.5V ac ,

[0041] Among them, V ac For alternating current u ac The instantaneous value of in is the input current, i m is the excitation current, i1 is the current flowing through winding N1, i2 is the current flowing through winding N2, i o is the output current, V1 is the voltage across winding N1, and V2 is the voltage across winding N2.

[0042] Figure 6 For the positive half cycle of AC Figure 1 Schematic diagram of the switch drive voltage, output current, excitation current, and voltage across the diode in the circuit, where G Q1 , G Q2 is the driving voltage of switch Q1 and switch Q2, V D1 is the voltage across diode D1, VD2 is the voltage across diode D2. In this process, the output current i o Rising, the rising slope is (0.5V ac -V o ) / L o ; Excitation current i m Rising, the rising slope is 0.5V ac / L m .

[0043] In AC u ac In the positive half cycle, when switch Q1 is turned off, switch Q2 is turned off synchronously, and diode D1 and diode D2 are turned on for freewheeling. The relationship between the currents in the circuit is as follows:

[0044] i D1 =i m +i1,

[0045] i D2 =i2,

[0046] i o =i m +i1+i2,

[0047] Among them, i D1 is the current flowing through diode D1, i D2 is the current flowing through diode D2.

[0048] Please continue to refer to Figure 6 During this process, the output current i o Rapidly decreases, with a slope of V o / L o , when the output current i o Drop to the excitation current i m When , diode D2 is cut off and only diode D1 is still turned on.

[0049] The relationship between the voltages in the circuit is as follows:

[0050] V1=V2=-L m *V o / (L m +L o ),

[0051] At this time, add the inductor L m and inductor L o The output voltage V o The current is reduced until the volt-second balance reaches a steady state. After the switch Q1 and the switch Q2 are turned on again, the next cycle begins.

[0052] In AC u acIn the negative half cycle, switch Q2 is a high frequency switch, and switch Q1 can be always on or switch synchronously with switch Q2. The working principle of the present invention is described below by taking switch Q1 and switch Q2 switch synchronously as an example.

[0053] In AC u ac In the negative half cycle, when switch Q2 is turned on, diode D2 is reversely cut off, switch Q1 and diode D1 are turned on. At this time, the relationship between voltage and current in the circuit is as follows:

[0054] i in = -i2,

[0055] i o =i m +i1+i2,

[0056] V1=V2=0.5V ac .

[0057] Figure 7 Negative half cycle of AC Figure 1 Schematic diagram of the switch drive voltage, output current, excitation current, and voltage across the diode in the circuit, where G Q1 , G Q2 is the driving voltage of switch Q1 and switch Q2, V D1 is the voltage across diode D1, V D2 is the voltage across diode D2. In this process, the output current i o Rising, the rising slope is (-0.5V ac -V o ) / L o ; Excitation current i m Falling, the falling slope is -0.5V ac / L m .

[0058] In AC u ac In the negative half cycle, when switch Q2 is turned off, switch Q1 is turned off synchronously, and diodes D1 and D2 are turned on for freewheeling. The relationship between the currents in the circuit is as follows:

[0059] i D2 =i2,

[0060] i D1 =i m +i1,

[0061] i o =i m +i1+i2,

[0062] Please continue to refer to Figure 7 During this process, the output current i o Rapidly decreases, with a slope of Vo / L o , when the output current i o Drop to -i m When Figure 5 At time t1, diode D1 is cut off and only diode D2 is still turned on.

[0063] The relationship between the voltages in the circuit is as follows:

[0064] V1=V2=L m *V o / (L m +L o ),

[0065] At this time, add the inductor L m and inductor L o The output voltage V o So that the current i o Decrease until the volt-second balance reaches a steady state, that is, Figure 7 At time t2 in the circuit, the next cycle begins after switches Q1 and Q2 are turned on again.

[0066] Figure 8 Shows Figure 1 The simulation waveform of the circuit in the figure includes the AC current u ac 、Input current i in , output voltage V o , excitation current i m With the output current i o ,from Figure 6 It can be seen that the input current i in Very close to a sine wave.

[0067] by Figure 1 The circuit is in AC u ac For example, when the positive half cycle, switch Q1 is turned on, diode D1 is reversely cut off, switch Q2 and diode D2 are turned on, when (0.5V ac -V o ) / L o Less than 0.5V ac / L m When the output current i o The rising slope is less than the excitation current i m The rising slope of the output current i o Less than the excitation current i m , at this time i2=(i o -i m ) / 2 is less than 0.

[0068] When switch Q1 is turned off, switch Q2 is turned off synchronously, diode D1 is turned on, and diode D2 is turned off,

[0069] i1=i2<0,

[0070] i D1 =i m +i1,

[0071] i o =i m +i1+i2,

[0072] i D2 =i o -i D1 =i2<0,

[0073] Among them, the inductor current cannot change suddenly, because the current i flowing through the diode D2 D2 Less than 0, at this time, the current i flowing through the diode D2 D2 The junction capacitance of diode D2 is charged, which increases the voltage V across diode D2. D2 , and the voltage across switch Q1 is equal to V D2 +V ac Therefore, a voltage spike will be generated across the switch Q1 and the diode D2. As the voltage across the switch Q1 and the diode D2 increases sharply, the excitation inductance L m The voltage across the two ends is -0.5V D2 / L m , inductance L o The voltage across the terminals is 0.5V D2 -V o During this process, the output current i o Rapidly increases, the excitation current i m The current i2 flowing through the winding N2 decreases rapidly, and when the current i2 flowing through the winding N2 increases to zero, i o =i m ,i o with i m The downward slope is V o / (L o +L m ).

[0074] In order to solve the above voltage spike problem, the present invention also provides a second specific embodiment of a bridgeless buck power factor correction circuit, as shown in FIG. Figure 2 As shown, in Figure 1 Capacitors C1 and C2 are added to the circuit. The first end of capacitor C1 is connected to the alternating current u ac The first end of the capacitor C1 is connected to the anode of the diode D2, and the first end of the capacitor C2 is connected to the AC voltage u ac The second end of the capacitor C2 is connected to the anode of the diode D2.

[0075] More specifically, after adding capacitors C1 and C2, a freewheeling path is provided for current i2, and current i2 will flow to capacitors C1 and C2 through switch Q2. At this time, capacitors C1 and C2 clamp the voltage across switch Q1 and diode D2.

[0076] When switch Q1 is turned off, switch Q2 is turned off synchronously, diode D1 is turned on, and diode D2 is turned off, the voltage across Q1 is the voltage across capacitor C1, and the voltage across diode D2 is the voltage across capacitor C1 minus V ac , thereby achieving suppression of voltage spikes.

[0077] in, Figure 2 The working state of the switch in the circuit Figure 1 The circuits are the same and will not be described again here.

[0078] Figure 3 FIG. 1 is a circuit diagram of a third specific embodiment of a bridgeless buck power factor correction circuit of the present invention. Figure 3 As shown, a method is proposed in Figure 2 An inductor L1 and a capacitor Cx are added to the middle circuit, the first end of the capacitor Cx is connected between the inductor L1 and the first end of the switch Q1, and the second end of the capacitor Cx is connected between the second end of the alternating current and the first end of the switch Q2; the inductor L1 is located between the switch Q1 and the alternating current, and the first end of the switch Q1 is connected to the first end of the alternating current via the inductor L1.

[0079] Among them, the working principle of capacitor Cx is the same as that of capacitors C1 and C2. Figure 3 I will not go into details here.

[0080] in, Figure 3 The working state of the switch in the circuit Figure 2 The same circuit, Figure 3 I will not go into details here.

[0081] Figure 4 FIG. 5 is a circuit diagram of a fifth specific embodiment of a bridgeless buck power factor correction circuit according to the present invention. Figure 4 As shown, in Figure 2 A clamping circuit module is added on the basis of the middle circuit, and the clamping module includes a winding N3, a diode D3, a diode D4, a diode D5 and a diode D6. The first end of the winding N3 is connected to the anode of the diode D5 and the cathode of the diode D6, the second end of the winding N3 is connected to the anode of the diode D3 and the cathode of the diode D4, the cathode of the diode D3 is connected to the cathode of the diode D5, the anode of the diode D4 is connected to the anode of the diode D6, and the cathode of the diode D5 is also connected to the capacitor C o The first end of the diode D6 is connected to the anode of the capacitor C oThe second end.

[0082] More specifically, the winding N3 is a clamping winding. The diode D3, the diode D4, the diode D5 and the diode D6 are clamping diodes, and the diode D3, the diode D4, the diode D5 and the diode D6 form a rectifier bridge.

[0083] Further, the first end of the winding N3 is a same-name end.

[0084] More specifically, during normal operation, the voltage across winding N3 is lower than the output voltage V o , winding N3 does not work. When the voltage spike occurs, the voltage across winding N3 is higher than the output voltage V o , the excess energy is transferred to the output through the output voltage V o Clamping is performed.

[0085] More specifically, after adding the winding N3 clamp, the voltage across the switch Q1 will be clamped at V o *(N1+N2) / N3+V ac Taking the positive half cycle of AC as an example, in normal operation, switch Q1 is turned on, switch Q2 is turned on, and the voltage across the coupled inductor formed by winding N1 and winding N2 is V ac , then the voltage across winding N3 is V ac *N3 / (N1+N2), select appropriate parameters N3 / (N1+N2) so that V ac *N3 / (N1+N2) <V o , the clamping diode is reverse biased, and the clamping circuit does not work. When switch Q1 is turned off, switch Q2 is turned off, or switch Q2 is turned on, the voltage across the coupled inductor (which is equal to the voltage V across the diode D2) D2 ) is greater than V o *(N1+N2) / N3, the voltage across winding N3 is greater than the output voltage V o , the clamping diode is turned on, and the voltage across the coupled inductor is clamped at V o *(N1+N2) / N3, the voltage across switch Q1 is clamped at V o *(N1+N2) / N3+V ac , thereby achieving suppression of voltage spikes.

[0086] in, Figure 4 The working state of the switch in the circuit Figure 1 The circuits are the same and will not be described again here.

[0087] Figure 5 FIG. 5 is a circuit diagram of a fifth specific embodiment of a bridgeless buck power factor correction circuit according to the present invention. Figure 5 As shown, a method is proposed in Figure 2Based on the circuit in the middle, the inductor L1 is added and the Figure 2 The inductor L0 in the circuit is located between the switch Q1 and the alternating current. The first end of the switch Q1 is connected to the first end of the alternating current via the inductor L1.

[0088] More specifically, the inductance L is obtained by using the leakage magnetic field M generated by the windings N1 and N2 through the non-fully coupled inductor solution. o , without the need to wind an additional inductor L o .

[0089] in, Figure 5 The working state of the switch in the circuit Figure 2 The same circuit, Figure 5 I will not go into details here.

[0090] In another specific embodiment, the conduction angles of switches Q1 and Q2 can also be reduced to avoid areas where voltage spikes are likely to occur, thereby suppressing voltage spikes. FIG9(a) shows the voltage u across switch Q1 before the conduction angle is reduced. Q1 Figure 9(b) shows the voltage u across the switch Q1 after the conduction angle is reduced. Q1 From the waveform diagram, it can be seen that after reducing the conduction angle, the voltage u across the switch Q1 Q1 The peak is suppressed.

[0091] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person having ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A bridgeless buck power factor correction circuit, characterized in that: The invention comprises a first switch, a second switch, a third switch, a fourth switch, a first winding and a second winding, wherein a first end of the first switch is connected to a first end of the alternating current, a second end of the first switch is connected to a first end of the first winding, a second end of the first winding is connected to a first end of the second winding, a second end of the second winding is connected to a second end of the second switch, and a first end of the second switch is connected to a second end of the alternating current; the third switch is connected in parallel to a series branch of the first winding and a load, and the fourth switch is connected in parallel to a series branch of the second winding and the load.

2. A bridgeless buck power factor correction circuit as claimed in claim 1, characterized in that: Also includes: A first inductor and a second inductor; one end of the first inductor is connected between the first winding and the second winding, and the other end is connected to the load; The second inductor is connected in parallel with the first winding.

3. A bridgeless buck power factor correction circuit as claimed in claim 2, characterized in that: It also includes a first capacitor and a second capacitor, wherein the first capacitor is connected in parallel with a series branch of the first switch and the third switch; and the second capacitor is connected in parallel with a series branch of the second switch and the fourth switch.

4. A bridgeless buck power factor correction circuit as claimed in claim 2, characterized in that: Also includes: a third inductor, a first capacitor, a second capacitor and a third capacitor, wherein the third inductor is located between the first switch and the alternating current, the first end of the first switch is connected to the first end of the alternating current via the third inductor, the first capacitor is connected in parallel to a series branch of the first switch and the third switch, the second capacitor is connected in parallel to a series branch of the second switch and the fourth switch, the first end of the third capacitor is connected between the third inductor and the first end of the first switch, and the second end of the third capacitor is connected between the second end of the alternating current and the first end of the second switch.

5. A bridgeless buck power factor correction circuit as claimed in claim 2, characterized in that: It also includes a third winding, a third diode, a fourth diode, a fifth diode and a sixth diode, wherein the first end of the third winding is connected to the anode of the fifth diode and the cathode of the sixth diode, the second end of the third winding is connected to the anode of the third diode and the cathode of the fourth diode, the cathode of the third diode is connected to the cathode of the fifth diode, the anode of the fourth diode is connected to the anode of the sixth diode, the cathode of the fifth diode is connected to the first end of the load, and the anode of the sixth diode is connected to the second end of the load.

6. A bridgeless buck power factor correction circuit as claimed in claim 5, characterized in that: The third switch and the fourth switch are diodes.

7. A bridgeless buck power factor correction circuit as claimed in claim 6, characterized in that: The number of turns of the first winding is equal to that of the second winding, and the first end of the third winding is a same-name end.

8. A bridgeless buck power factor correction circuit as claimed in claim 7, characterized in that: The first end of the first winding and the first end of the second winding are the same end.

9. A bridgeless buck power factor correction circuit as claimed in claim 8, characterized in that: The first switch and the second switch are MOSFETs, the first end of the first switch is the drain of the MOSFET, and the second end of the first switch is the source of the MOSFET; the first end of the second switch is the drain of the MOSFET, and the second end of the second switch is the source of the MOSFET.

10. A bridgeless buck power factor correction circuit as claimed in claim 1, characterized in that: Also includes: A first inductor, a second inductor, a first capacitor and a second capacitor, wherein the first inductor is located between the first switch and the alternating current, the first end of the first switch is connected to the first end of the alternating current via the first inductor, the second inductor is connected in parallel with the first winding, the first capacitor is connected in parallel with a series branch of the first switch and the third switch, and the second capacitor is connected in parallel with a series branch of the second switch and the fourth switch.

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