An integrated oscillator and a preparation method thereof

Abstract

The present application provides an integrated oscillator and a preparation method thereof, relating to the technical field of oscillators. In the present application, a conductive member is arranged in a substrate; a driving circuit structure is formed on the side surface of the substrate; the conductive member is electrically connected to the driving circuit structure; a bottom electrode layer, a piezoelectric layer and a top electrode layer are sequentially stacked on the substrate to form a beam structure; both the bottom electrode layer and the top electrode layer are electrically connected to the conductive member. By integrating the driving circuit structure and the beam structure on two sides of the substrate, it is convenient to reduce the overall size of the oscillator, and the driving circuit structure and the beam structure are electrically connected through the conductive member in the substrate to achieve electrical interconnection, simplify the preparation steps, and the connection is more stable compared with external welding.

Description

Technical Field

[0001] The present application relates to the technical field of oscillators, and in particular, to an integrated oscillator and a manufacturing method thereof. Background Art

[0002] Micro-Electro-Mechanical System (MEMS) is a technology that integrates micro mechanical structures and electronic functions on a single chip, and has a wide range of application fields, such as MEMS sensors and MEMS oscillators. Among them, MEMS oscillators use micro mechanical resonators to generate high-precision time-frequency signals. MEMS oscillators can be divided into electrostatic drive and piezoelectric drive according to different resonance drive methods.

[0003] In the prior art, a piezoelectric-driven MEMS oscillator includes a MEMS resonator and a drive circuit. After the MEMS resonator and the drive circuit are respectively packaged, they are integrated in a form of stacking up and down through packaging technologies, such as Quad Flat No-leads Package (QFN).

[0004] However, the above structure has a large size. Summary of the Invention

[0005] The present application provides an integrated oscillator and a manufacturing method thereof to solve the problem that the existing oscillator structure has a large size.

[0006] To achieve the above object, the technical solution of the present application is as follows:

[0007] On the one hand, the present application provides a manufacturing method of an integrated oscillator, including: arranging a conductive member in a substrate; forming a drive circuit structure on the side surface of the substrate; electrically connecting the conductive member and the drive circuit structure; sequentially laminating a bottom electrode layer, a piezoelectric layer, and a top electrode layer on the substrate to form a beam structure; and electrically connecting both the bottom electrode layer and the top electrode layer to the conductive member.

[0008] In a possible implementation manner, the manufacturing method provided by the embodiments of the present application, sequentially laminating a bottom electrode layer, a piezoelectric layer, and a top electrode layer on the substrate to form a beam structure, includes: arranging two connection holes on the substrate to correspondingly expose one end of the conductive member facing away from the drive circuit structure, wherein two conductive members are arranged; arranging the bottom electrode layer in one connection hole to the substrate; sequentially laminating the piezoelectric layer and the top electrode layer on the bottom electrode layer, both the bottom electrode layer and the top electrode layer are located on one side of the connection hole, and the top electrode layer extends into the other connection hole to be connected to the conductive member.

[0009] In a possible implementation, for the preparation method provided by the embodiments of the present application, two connection holes are provided on the substrate, including: sequentially stacking a top silicon layer, a buried oxide layer, and a substrate silicon to form the substrate; connection holes are provided on the top silicon layer and the buried oxide layer, and a conductive member is located on the substrate silicon.

[0010] In a possible implementation, for the preparation method provided by the embodiments of the present application, sequentially stacking a top silicon layer, a buried oxide layer, and a substrate silicon to form the substrate, including: providing a buried oxide layer with a thickness of 1 um - 5 um on a top silicon layer with a thickness of 2 um - 20 um, and providing a substrate silicon with a thickness of 300 um - 800 um on the buried oxide layer. Among them, a cavity is provided in the substrate silicon, the depth of the cavity is 2 um - 5 um, and the width and length of the cavity are both 400 um - 500 um.

[0011] In a possible implementation, for the preparation method provided by the embodiments of the present application, a conductive member is provided in the substrate, including: providing a through hole in the substrate; providing a passivation layer on the surface of the substrate and the inner wall surface of the through hole, and the conductive member is provided in the through hole.

[0012] In a possible implementation, for the preparation method provided by the embodiments of the present application, providing a through hole in the substrate, including: etching a through hole with a diameter of 10 um - 200 um by using photolithography and DRIE processes.

[0013] In a possible implementation, for the preparation method provided by the embodiments of the present application, two connection holes are provided on the substrate, including: sequentially etching the top silicon layer and the buried oxide layer by using photolithography, DRIE, and RIE processes to form the connection holes; the diameter of the connection holes is larger than that of the through holes.

[0014] In a possible implementation, for the preparation method provided by the embodiments of the present application, a bottom electrode layer, a piezoelectric layer, and a top electrode layer are sequentially stacked on the substrate to form a beam structure, including: depositing a piezoelectric layer with a thickness of 500 nm - 2000 nm on a bottom electrode layer 310 with a thickness of 20 nm - 100 nm by using PVD process, and depositing a top electrode layer with a thickness of 20 nm - 500 nm on the piezoelectric layer; patterning the bottom electrode layer by using photolithography and etching processes, and sequentially patterning the piezoelectric layer and the top electrode layer by using photolithography process, IBE process, and ICP etching process; removing the top silicon layer by using photolithography and DRIE dry etching processes to etch and form the beam structure.

[0015] In a possible implementation, for the preparation method provided by the embodiments of the present application, a drive circuit structure is formed on the side surface of the substrate, including: forming a drive circuit structure on the side surface of the substrate silicon of the substrate by using CMOS process with a process of 40 nm - 180 nm, and performing passivation treatment on the side surface of the substrate silicon.

[0016] On the other hand, the present application also provides an integrated oscillator, which is prepared by the preparation method in any of the above embodiments, and includes: a substrate, a drive circuit structure, and a beam structure; the drive circuit structure and the beam structure are respectively arranged on opposite sides of the substrate, a conductive member is arranged in the substrate, the drive circuit structure and the beam structure are electrically connected through the conductive member, one end of the beam structure is connected to the substrate, and the other end of the beam structure is suspended above the substrate.

[0017] For the integrated oscillator and the preparation method provided by the present application, a conductive member is arranged in the substrate; a drive circuit structure is formed on the side surface of the substrate; the conductive member is electrically connected to the drive circuit structure; a bottom electrode layer, a piezoelectric layer, and a top electrode layer are sequentially stacked on the substrate to form a beam structure; both the bottom electrode layer and the top electrode layer are electrically connected to the conductive member. By integrating the drive circuit structure and the beam structure on two sides of the substrate, it is convenient to reduce the overall size of the oscillator, and the drive circuit structure and the beam structure are electrically connected through the conductive member in the substrate to achieve electrical interconnection, simplify the preparation steps, and the connection is more stable compared with external welding. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0019] Figure 1 is a schematic structural diagram of the integrated oscillator provided by the embodiment of the present application;

[0020] Figure 2 is Figure 1 a schematic structural diagram of another perspective of the integrated oscillator in

[0021] Figure 3 is Figure 1 a schematic structure during the preparation process of the integrated oscillator in Figure 1 ;

[0022] Figure 4 is Figure 1 a schematic structure during the preparation process of the integrated oscillator in Figure 2 ;

[0023] Figure 5 is Figure 1 a schematic structure during the preparation process of the integrated oscillator in Figure 3 ;

[0024] Figure 6 is Figure 1 a schematic structure during the preparation process of the integrated oscillator in Figure 4 ;

[0025] Figure 7 is Figure 1 a schematic structure during the preparation process of the integrated oscillator inFigure 5 ;

[0026] Figure 8 is Figure 1 a structural schematic diagram during the preparation process of the integrated oscillator in Figure 6 ;

[0027] Figure 9 is Figure 1 a structural schematic diagram during the preparation process of the integrated oscillator in Figure 7 ;

[0028] Figure 10 is Figure 1 a structural schematic diagram during the preparation process of the integrated oscillator in Figure 8 ;

[0029] Figure 11 is Figure 1 a structural schematic diagram during the preparation process of the integrated oscillator in Figure 9 ;

[0030] Figure 12 is Figure 1 a structural schematic diagram during the preparation process of the integrated oscillator in Figure 10 ;

[0031] Figure 13 is Figure 1 a structural schematic diagram of the beam structure in ;

[0032] Figure 14 is Figure 1 a structural schematic diagram of the drive circuit structure in ;

[0033] Figure 15 This is a flowchart of the method for preparing an integrated oscillator in an embodiment of the present application.

[0034] Explanation of reference numerals:

[0035] 100 - Substrate;

[0036] 110 - Conductive member;

[0037] 120 - Cavity;

[0038] 130 - Through hole;

[0039] 140 - Top silicon layer;

[0040] 150 - Buried oxide layer;

[0041] 160 - Substrate silicon;

[0042] 170 - Passivation layer;

[0043] 200 - Drive circuit structure;

[0044] 210 - Electrical connection member

[0045] 300 - Beam structure;

[0046] 310 - Bottom electrode layer;

[0047] 320 - Piezoelectric layer;

[0048] 330 - Top electrode layer.

[0049] Through the above - mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed Description of the Embodiments

[0050] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0051] It should be noted that in the description of the embodiments of the present application, the terms indicating orientation or positional relationship such as "upper", "lower", "inner", "outer", etc. are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of description, rather than indicating or implying that the device or component must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the embodiments of the present application.

[0052] In addition, it should also be noted that the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0053] In the present application, unless otherwise clearly defined and limited, the terms such as "installed", "connected", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or a connection that can communicate with each other; it may be a direct connection, or an indirect connection through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above - mentioned terms in the present application can be understood according to specific circumstances.

[0054] The CMOS process is short for Complementary Metal-Oxide-Semiconductor process, which is a semiconductor manufacturing technology used to fabricate integrated circuits.

[0055] PECVD deposition is short for Plasma-Enhanced Chemical Vapor Deposition, which is a process used to deposit thin films on substrates.

[0056] The PVD (Physical Vapor Deposition) process is a thin film deposition technology used to deposit thin films on solid surfaces.

[0057] IBE (Ion Beam Mixing or Ion Beam Doping) is a process that uses ion beam technology to dope or mix semiconductor materials.

[0058] ICP dry etching refers to a dry etching process that uses Inductively Coupled Plasma (abbreviated as ICP) technology.

[0059] The RIE (Reactive Ion Etching) dry etching process is a process that uses reactive gases to react with the material surface in a plasma environment to achieve precise etching.

[0060] Micro-Electro-Mechanical System (MEMS) is a technology that integrates micro mechanical structures and electronic functions on a single chip, and it has a wide range of applications, such as MEMS sensors and MEMS oscillators. Among them, MEMS oscillators use micro mechanical resonators to generate high-precision time-frequency signals. MEMS oscillators can be divided into electrostatic drive and piezoelectric drive according to different resonance drive methods.

[0061] In the prior art, a piezoelectric-driven MEMS oscillator includes a MEMS resonator and a drive circuit. After the MEMS resonator and the drive circuit are respectively packaged, they are integrated through an up-and-down stacking form by packaging technology, such as Quad Flat No-leads Package (QFN). However, the above structure has a large size.

[0062] In view of this, the present application provides an integrated oscillator and a manufacturing method, including: arranging a conductive member in a substrate; forming a driving circuit structure on a side surface of the substrate; electrically connecting the conductive member to the driving circuit structure; sequentially laminating a bottom electrode layer, a piezoelectric layer, and a top electrode layer on the substrate to form a beam structure; and electrically connecting both the bottom electrode layer and the top electrode layer to the conductive member. By integrating the driving circuit structure and the beam structure on two sides of the substrate, it is convenient to reduce the overall size of the oscillator, and the driving circuit structure and the beam structure are electrically connected through the conductive member in the substrate to achieve electrical interconnection, simplify the manufacturing steps, and the connection is more stable compared with external welding.

[0063] Combined with Figures 1 to 15 specific embodiments, the present application will be described. Figure 1 FIG. Figure 2 is Figure 1 a schematic structural diagram of the integrated oscillator provided by an embodiment of the present application; Figure 3 FIG. Figure 1 is a schematic structural diagram of the integrated oscillator in Figure 1 from another perspective; Figure 4 FIG. Figure 1 is a schematic structural diagram during the manufacturing process of the integrated oscillator in Figure 2 ; Figure 5 FIG. Figure 1 is a schematic structural diagram during the manufacturing process of the integrated oscillator in Figure 3 ; Figure 6 FIG. Figure 1 is a schematic structural diagram during the manufacturing process of the integrated oscillator in Figure 4 ; Figure 7 FIG. Figure 1 is a schematic structural diagram during the manufacturing process of the integrated oscillator in Figure 5 ; Figure 8 FIG. Figure 1 is a schematic structural diagram during the manufacturing process of the integrated oscillator in Figure 6 ; Figure 9 FIG. Figure 1 is a schematic structural diagram during the manufacturing process of the integrated oscillator in Figure 7 ; Figure 10 FIG. Figure 1 is a schematic structural diagram during the manufacturing process of the integrated oscillator in Figure 8 ; Figure 11 FIG. Figure 1 is a schematic structural diagram during the manufacturing process of the integrated oscillator in Figure 9 ; Figure 12 FIG. Figure 1 is a schematic structural diagram during the manufacturing process of the integrated oscillator in Figure 10 ; Figure 13 FIG. Figure 1 is a schematic structural diagram of the beam structure in Figure 14 FIG. Figure 1 is a schematic structural diagram of the driving circuit structure in

[0064] On the one hand, the present application provides a method for manufacturing an integrated oscillator, including: S100, disposing a conductive member 110 within a substrate 100; S200, forming a drive circuit structure 200 on a side surface of the substrate 100; S300, electrically connecting the conductive member 110 to the drive circuit structure 200; S400, sequentially laminating a bottom electrode layer 310, a piezoelectric layer 320, and a top electrode layer 330 on the substrate 100 to form a beam structure 300; both the bottom electrode layer 310 and the top electrode layer 330 are electrically connected to the conductive member 110.

[0065] The substrate 100 is a Cavity-Silicon-On-Insulator wafer (C-SOI wafer). The structure of the substrate 100 is as Figure 3 shown. The substrate 100 includes a top silicon layer 140, a buried oxide layer 150, and a substrate silicon 160 that are sequentially laminated. A cavity 120 is provided within the substrate silicon 160. The present application places no restrictions on the size and structure of the substrate 100. Exemplarily, a buried oxide layer 150 with a thickness of 1 um to 5 um is disposed on a top silicon layer 140 with a thickness of 2 um to 20 um, and a substrate silicon 160 with a thickness of 300 um to 800 um is disposed on the buried oxide layer 150. Among them, a cavity 120 is provided within the substrate silicon 160. The depth of the cavity 120 is 2 um to 5 um, and both the width and length of the cavity 120 are 400 um to 500 um. For example, the thickness of the substrate silicon 160 is 500, the thickness of the buried oxide layer 150 is 3 um, the thickness of the top silicon layer 140 is 5 um, the depth of the cavity 120 is 3 um, and both the width and length of the cavity 120 are 500 um.

[0066] When disposing the conductive member 110 within the substrate 100, it is necessary to first form a through hole 130 in the substrate 100. As Figure 4 shown, the through hole 130 is fabricated in the substrate silicon 160 using TSV technology, and the through hole 130 is etched using photolithography and DRIE processes. The diameter of the through hole 130 is 10 um to 200 um, and the etching stops at the buried oxide layer 150. The through hole 130 is fabricated in the substrate silicon 160 of the substrate 100 using TSV technology, and the through hole 130 is etched using photolithography and DRIE processes. The diameter of the through hole 130 is 10 um to 200 um, and when etching reaches the buried oxide layer 150, the etching stops, thereby forming Figure 4 the shown through hole.

[0067] A passivation layer 170 is disposed on the surface of the substrate 100 and the inner wall surface of the through hole 130, that is, a SiO2 passivation layer 170 is formed through a thermal oxidation process, and the thickness is 0.1 um to 2 um. As Figure 5 shown.

[0068] A passivation layer 170 is provided on the surface of the substrate 100 and the inner wall surface of the through-hole 130, and the conductive member 110 is disposed in the through-hole 130. Specifically, an adhesion layer or a barrier layer is grown on the inner wall of the through-hole 130 and the surface of the substrate silicon 160 by magnetron sputtering. The sputtered metal is titanium (Ti), titanium tungsten (TiW) or titanium nitride (TiN), and the thickness is 0.1 um to 1 um, such as Figure 6 shown.

[0069] The conductive member 110 is made of metal copper (Cu). Through the electroplating process, the surface of the through-hole 130 and the substrate silicon 160 is filled with metal copper, such as Figure 7 shown.

[0070] Perform a CMP process on the copper metal on the surface of the substrate silicon 160 to remove the copper on its surface, such as Figure 8 shown. The CMP process refers to the Chemical Mechanical Polishing (CMP) process, which is used to remove materials or smooth the surface.

[0071] A drive circuit structure 200 is provided on one side of the substrate 100 by the CMOS process, that is, an ASIC drive circuit is fabricated on the back surface of the C-SOI wafer, using the CMOS process with a process of 40 to 180 nm. And passivation treatment is performed on the back surface, and silicon oxide or silicon nitride is deposited by PECVD, such as Figure 9 shown.

[0072] Lithography is performed on the area corresponding to the through-hole 130 of the top silicon layer 140. The top silicon layer 140 and the buried oxide layer 150 are etched in sequence by the DRIE process and the RIE process to form a connection hole 180, exposing the copper lead, that is, one end of the conductive member 110 facing away from the drive circuit structure 200. That is, connection holes 180 are provided on the top silicon layer 140 and the buried oxide layer 150, wherein the conductive member 110 is located in the through-hole 130 of the substrate silicon 160, and the connection hole 180 communicates with the through-hole 130, such as Figure 10 shown. It should be noted that the diameter of the connection hole 180 is larger than that of the through-hole 130.

[0073] Two connection holes 180 are provided on the substrate 100 to correspondingly expose one end of the conductive member 110 facing away from the drive circuit structure 200, and two conductive members 110 are provided; a bottom electrode layer 310 is provided in one connection hole 180 to the substrate 100; a piezoelectric layer 320 and a top electrode layer 330 are sequentially stacked on the bottom electrode layer 310. The bottom electrode layer 310 and the top electrode layer 330 are both located on one side of the connection hole 180, and the top electrode layer 330 extends into the other connection hole 180 to be connected to the conductive member 110.

[0074] The bottom electrode of the MEMS part is fabricated by metal deposition. Molybdenum, gold, or platinum is deposited by PVD process with a thickness of 20 - 100 nm. The bottom electrode layer 310 is patterned by photolithography and etching processes, and the input electrodes of the beam structure 300 and the drive circuit structure 200 are interconnected, as Figure 11 shown.

[0075] A piezoelectric film is deposited, using AlN or PZT by PVD process with a deposition thickness of 500 - 2000 nm. The top electrode of molybdenum, gold, or platinum is deposited with a thickness of 20 nm - 500 nm. The top layer metal is removed by photolithography and IBE dry etching process of metal to pattern the top electrode. On the bottom electrode layer 310 with a thickness of 20 nm - 100 nm, a piezoelectric layer 320 with a thickness of 500 nm - 2000 nm is deposited by PVD process, and a top electrode layer 330 with a thickness of 20 nm - 500 nm is deposited on the piezoelectric layer 320; the bottom electrode layer 310 is patterned by photolithography and etching processes, the piezoelectric layer 320 is patterned by photolithography process, IBE process, and ICP etching process, and the top electrode layer 330 is patterned by photolithography process and IBE etching process; combined with Figure 12 and Figure 2 shown.

[0076] The top silicon layer 140 is removed by photolithography and DRIE dry etching process, and the beam structure 300 is etched. Finally, the buried oxide layer 150 is etched by RIE dry etching process to release the beam structure 300, as Figure 1 shown.

[0077] On the other hand, the present application also provides an integrated oscillator, which is fabricated by the preparation method in any of the above embodiments, including: a substrate 100, a drive circuit structure 200, and a beam structure 300; the drive circuit structure 200 and the beam structure 300 are respectively arranged on opposite sides of the substrate 100, a conductive member 110 is arranged in the substrate 100, the drive circuit structure 200 and the beam structure 300 are electrically connected through the conductive member 110, one end of the beam structure 300 is connected to the substrate 100, and the other end of the beam structure 300 is suspended above the substrate 100.

[0078] Specifically, for the substrate 100, the drive circuit structure 200, and the beam structure 300, the drive circuit structure 200 and the beam structure 300 are respectively arranged on opposite sides of the substrate 100. Two conductive members 110 and a cavity 120 are arranged in the substrate 100, the conductive members 110 are arranged on one side of the cavity 120, one end of the beam structure 300 is suspended above the cavity 120, and the other end of the beam structure 300 is connected to the substrate 100. It should be noted that one end of a conductive member 110 is connected to the top electrode of the beam structure 300, one end of the other conductive member 110 is connected to the bottom electrode of the beam structure 300, and the other ends of the two conductive members 110 are both connected to the drive circuit structure 200.

[0079] The beam structure 300 includes a first beam, a second beam, and a connecting beam. The first beam and the second beam are arranged opposite to each other and connected by the connecting beam. One end of each of the first beam and the second beam is connected to the substrate 100.

[0080] The substrate 100 includes a top silicon layer 140, a buried oxide layer 150, and a substrate silicon 160 arranged in sequence from bottom to top. A cavity 120 is provided on one side of the substrate silicon 160 facing the buried oxide layer 150. The through hole 130 sequentially penetrates the top silicon layer 140, the buried oxide layer 150, and the substrate silicon 160. There are two through holes provided on the substrate 100. The conductive members 110 are connected to the through holes in one-to-one correspondence and are embedded in the through holes. Specifically, the inner wall of the through hole 130 is provided with silicon oxide.

[0081] The beam structure 300 includes a bottom electrode layer 310, a piezoelectric layer 320, and a top electrode layer 330. The piezoelectric layer 320 is located between the bottom electrode layer 310 and the top electrode layer 330. The piezoelectric layer 320 is provided with a piezoelectric pattern, the top electrode layer 330 is provided with a top electrode pattern, and the bottom electrode layer 310 is provided with a bottom electrode pattern.

[0082] Specifically, the piezoelectric layer 320 is located between the bottom electrode layer 310 and the top electrode layer 330. The piezoelectric layer 320 is provided with a piezoelectric pattern. For example, the piezoelectric layer is removed through a photolithography and ICP dry etching process to pattern the piezoelectric layer. The top electrode layer 330 is provided with a top electrode pattern. For example, the top layer metal is removed through a photolithography and IBE metal dry etching process to pattern the top electrode layer. The bottom electrode layer 310 is provided with a bottom electrode pattern. In some embodiments, one end of the piezoelectric layer 320 is connected to the top silicon layer 140. In some embodiments, neither end of the piezoelectric layer 320 is connected to the top silicon layer 140.

[0083] In some embodiments, the top electrode layer 330 is arranged in sequence from the direction of the conductive member 110 above the piezoelectric layer 320, and the bottom electrode layer 310 is arranged in sequence from the direction of the conductive member 110 below the piezoelectric layer 320. The piezoelectric layer 320 is sandwiched between the top electrode layer 330 and the bottom electrode layer 310. For example, part of the piezoelectric layer 320 is arranged in parallel, and part of the piezoelectric layer 320 is arranged obliquely.

[0084] At least one side of the drive circuit structure 200 is provided with an electrical connector 210, and the electrical connector 210 is used to connect to a power supply circuit. At least one side of the drive circuit structure 200 is provided with an electrical connector 210, and the electrical connector 210 is used to connect to a power supply circuit. For example, the number of electrical connectors 210 is four, and the electrical connectors 210 are arranged in pairs opposite to each other on both sides of the drive circuit structure 200. The outer frame of the drive circuit structure 200 is square or rectangular, and the embodiments of the present application do not limit this.

[0085] A conductive component 110 is disposed within the substrate 100 through a magnetron sputtering process and an electroplating process; a driving circuit structure 200 is disposed on one side of the substrate 100 through a CMOS process; a bottom electrode layer 310, a piezoelectric layer 320, and a top electrode layer 330 are sequentially deposited on the side of the substrate 100 facing away from the driving circuit structure 200, and a beam structure 300 is formed through photolithography and DRIE dry etching processes; the beam structure 300 is connected to the driving circuit structure 200 electrically through metal deposition such that both the bottom electrode layer 310 and the top electrode layer 330 are electrically connected to the driving circuit structure 200 through the conductive component 110.

[0086] In this application, the position and shape of the through-hole 130 are defined through a photolithography technique, then precise etching is performed using the DRIE process, and finally a conductive material is filled in the etched through-hole 130 to establish an electrical connection.

[0087] The substrate 100 is placed on a workbench; through-holes 130 are etched in the substrate silicon 160 of the substrate 100 through photolithography and DRIE processes; the conductive component 110 is filled in the through-holes 130 and on one side of the substrate silicon 160 through magnetron sputtering and electroplating processes; the driving circuit structure 200 is disposed on the substrate silicon 160 through a CMOS process; photolithography is performed in the area of the through-holes 130 corresponding to the top silicon layer 140, the top silicon layer and the buried oxide layer are etched through DRIE and RIE processes, and the bottom electrode layer 310 is electrically connected to the conductive component 110 through metal deposition; a bottom electrode pattern is formed on the bottom electrode layer 310 through photolithography and etching processes, the piezoelectric layer 320 and the top electrode layer 330 are sequentially deposited on the bottom electrode layer 310, and the bottom electrode pattern and the top electrode pattern are formed through photolithography processes, IBE processes, and ICP etching processes; the top silicon layer is removed through photolithography and DRIE dry etching processes, and the beam structure 300 is etched.

[0088] TSV is the abbreviation of Through-Silicon Via, which is a technology for fabricating tiny through-holes perpendicular to the surface in a semiconductor wafer. These through-holes can establish electrical connections between different layers of the wafer. TSV includes the following steps: Etching: Using an etching technique (such as deep reactive ion etching DRIE) to etch vertical through-holes in the wafer. Filling: Filling the through-holes with metal or other conductive materials to establish electrical connections. Sealing: To protect the through-holes and the filled materials, the through-holes usually need to be sealed.

[0089] Photolithography is a key technology in semiconductor manufacturing, used to transfer circuit patterns onto the surface of a wafer. Before fabricating TSV through-holes, it is usually necessary to use photolithography technology to define the areas to be etched. In this process, a photoresist and a mask are used to define the position and shape of the through-holes, and then the pattern on the mask is irradiated with ultraviolet light or other light sources, causing chemical changes in the photoresist in the corresponding areas.

[0090] The DRIE process is used to etch vias. DRIE is the abbreviation of Deep Reactive Ion Etching, which is an advanced process for etching semiconductor materials such as silicon. The DRIE process can achieve deep and uniform etching, which is very suitable for manufacturing the TSV via 130 because it can precisely etch the required depth and size without damaging the surface layer of the wafer.

[0091] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0092] It should be understood that the present application is not limited to the exact structures already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A method for preparing an integrated oscillator, characterized in that, Including: A conductive member (110) is disposed within a substrate (100), specifically including: forming a through hole (130) in the substrate (100); forming a passivation layer (170) on the surface of the substrate (100) and the inner wall surface of the through hole (130), and the conductive member (110) is disposed within the through hole (130); The conductive member (110) is made of metallic copper, and through an electroplating process, the surface of the through hole (130) and the substrate silicon (160) of the substrate (100) are filled with metallic copper; Performing a CMP process on the copper metal on the surface of the substrate silicon (160) to remove the copper on its surface; Forming a drive circuit structure (200) on the side surface of the substrate (100); the conductive member (110) is electrically connected to the drive circuit structure (200); Stacking a bottom electrode layer (310), a piezoelectric layer (320), and a top electrode layer (330) on the substrate (100) in sequence to form a beam structure (300), specifically including: forming two connection holes (180) on the substrate (100) to correspondingly expose one end of the conductive member (110) facing away from the drive circuit structure (200), and two conductive members (110) are provided; the bottom electrode layer (310) is disposed from within one connection hole (180) to the substrate (100); the piezoelectric layer (320) and the top electrode layer (330) are stacked in sequence on the bottom electrode layer (310), both the bottom electrode layer (310) and the top electrode layer (330) are located on one side of the connection hole (180), and the top electrode layer (330) extends into the other connection hole (180) to be connected to the conductive member (110); The drive circuit structure (200) and the beam structure (300) are located on two sides of the substrate (100); Both the bottom electrode layer (310) and the top electrode layer (330) are electrically connected to the conductive member (110).

2. The manufacturing method of the integrated oscillator according to claim 1, characterized in that, Two connection holes (180) are formed on the substrate (100), including: Stacking a top silicon layer (140), a buried oxide layer (150), and a substrate silicon (160) in sequence to form the substrate (100); The connection holes (180) are formed on the top silicon layer (140) and the buried oxide layer (150), and the conductive member (110) is located on the substrate silicon (160).

3. The manufacturing method of the integrated oscillator according to claim 2, characterized in that, The stacking of the top silicon layer (140), the buried oxide layer (150), and the substrate silicon (160) in sequence to form the substrate (100) includes: Forming the buried oxide layer (150) with a thickness of 1 um - 5um on the top silicon layer (140) with a thickness of 2 um - 20um, and forming the substrate silicon (160) with a thickness of 300 um - 800um on the buried oxide layer (150). Wherein, a cavity (120) is provided within the substrate silicon (160), the depth of the cavity (120) is 2 um - 5um, and the width and length of the cavity (120) are both 400 um - 500um.

4. The manufacturing method of the integrated oscillator according to claim 1, characterized in that Providing a through hole (130) in the substrate (100) includes: Etching the through hole (130) with a diameter of 10um - 200um using photolithography and DRIE processes.

5. The manufacturing method of the integrated oscillator according to any one of claims 2-3, characterized in that, Providing two connection holes (180) in the substrate (100) includes: Successively etching the top silicon layer (140) and the buried oxide layer (150) through photolithography, DRIE, and RIE processes to form the connection holes (180); The diameter of the connection holes (180) is larger than that of the through hole (130).

6. The manufacturing method of the integrated oscillator according to any one of claims 2-3, characterized in that, Successively stacking a bottom electrode layer (310), a piezoelectric layer (320), and a top electrode layer (330) on the substrate (100) to form a beam structure (300) includes: Depositing the piezoelectric layer (320) with a thickness of 500 nm - 2000nm on the bottom electrode layer (310) with a thickness of 20 nm - 100nm by PVD process, and depositing the top electrode layer (330) with a thickness of 20 nm - 500nm on the piezoelectric layer (320); Patterning the bottom electrode layer (310) through photolithography and etching processes, patterning the piezoelectric layer (320) through photolithography and ICP etching processes, and patterning the top electrode layer (330) through photolithography and IBE processes; Removing the top silicon layer (140) through photolithography and DRIE dry etching process to etch and form the beam structure (300).

7. The manufacturing method of the integrated oscillator according to claim 6, characterized in that, Forming a drive circuit structure (200) on the side of the substrate (100) includes: Forming the drive circuit structure (200) on the side of the substrate silicon (160) of the substrate (100) through CMOS process with a process of 40nm - 180nm, and passivating the side of the substrate silicon (160).

8. An integrated oscillator, characterized in that, The integrated oscillator is prepared by the preparation method of any one of claims 1 - 7 above, and includes: A substrate (100), a drive circuit structure (200), and a beam structure (300); The drive circuit structure (200) and the beam structure (300) are respectively arranged on opposite sides of the substrate (100). A conductive member (110) is arranged in the substrate (100). The drive circuit structure (200) and the beam structure (300) are electrically connected through the conductive member (110). One end of the beam structure (300) is connected to the substrate (100), and the other end of the beam structure (300) is suspended above the substrate (100).

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