Digital filter device based on random computation

Abstract

The invention discloses a random computation-based digital filter device, which comprises a preprocessing unit used for preprocessing input data; the input cache unit is used for caching the preprocessed data and sequentially outputting cached data at a preset time interval; the serial shift register group is used for performing serial shift on the input data, caching and outputting the data subjected to serial shift processing; the data conversion unit is used for converting multiple pieces of data input in parallel into multiple paths of random bit sequences and outputting the multiple paths of random bit sequences; the random calculation unit is used for performing logical operation processing on the multi-path random bit sequence and a plurality of pre-configured filter coefficients to obtain and output a random filtering result; the data recovery unit is used for converting the random filtering result into binary data and outputting the binary data; and the output cache unit is used for caching and outputting the binary data. The digital filter device provided by the invention is low in hardware complexity and low in hardware resource overhead, and can ensure the calculation accuracy when bit flipping occurs.

Description

Technical Field

[0001] The invention relates to the technical field of signal processing, and in particular to a digital filter device based on random calculation. Background Art

[0002] Digital filters are the basic functional units for baseband signal processing in various electronic systems such as communication, navigation, detection and perception. They have a wide range of applications and are essentially discrete linear systems with special frequency response characteristics. After the digital signal is sent to the digital filter, it will be convolved with the filter coefficients to suppress the signal components in a certain frequency range. Compared with analog filters, digital filters have the following significant advantages:

[0003] First, the hardware cost is lower and the flexibility is higher. Digital filters can run in FPGA programmable logic devices, and the filter characteristics can be adjusted on demand by changing the digital filter coefficients and orders, without considering the circuit impedance matching problem. Analog filters need to be implemented through complex analog circuit design, and the filter characteristics are basically solidified after the design is completed, the adjustable range is very small, and the filter impedance matching is complex.

[0004] Second, it has better stability and better performance. Digital filters will not have performance fluctuations due to changes in the temperature and humidity working environment, and digital filters have the characteristics of linear phase, passband flatness, stopband attenuation and transition band width are better than analog filters. The performance of analog filters will deviate as the work increases or the working environment changes. Due to the nonlinear response characteristics of the device, it is difficult for analog filters to guarantee linear phase characteristics.

[0005] In terms of the implementation of digital filters, existing digital filters are mainly composed of digital multipliers, adders and delay units. Regardless of whether it is a direct digital filter structure, a transposed digital filter structure, or a lattice digital filter structure, it is necessary to use a multiplier to realize the multiplication of the input digital signal and the filter coefficient, and to complete the accumulation of the multiplication results of different coefficients through an adder. A certain length of input data is cached through a delay unit to meet the requirements of convolution calculation for data memory length.

[0006] However, in FPGA programmable logic devices, the logic resources occupied by a pipeline multiplier are often more than dozens of times the logic resources of an adder with the same bit width, and as the filter data bit width increases, the resource overhead of the multiplier will increase dramatically. Therefore, high-order digital filters can only be implemented on high-end FPGAs with rich logic resources. In some low-cost devices using low-end FPGAs, it is difficult to apply complex digital filters to ensure signal frequency domain selection performance. In addition, in some special scenarios such as satellite applications, due to the single particle effect of the space environment, FPGA programmable logic devices are prone to errors such as bit flips. When errors such as bit flips occur, the calculation accuracy of existing digital filters will drop significantly, thereby affecting the execution of the overall system function. Summary of the invention

[0007] In order to solve part or all of the technical problems existing in the above-mentioned prior art, the present invention provides a digital filter device based on random calculation.

[0008] The technical solution of the present invention is as follows:

[0009] A digital filter device based on random calculation is provided, and the digital filter device comprises:

[0010] A preprocessing unit, used for preprocessing the input data of the digital filter device, obtaining and outputting preprocessed data;

[0011] An input buffer unit, wherein the input end of the input buffer unit is connected to the output end of the preprocessing unit, and the output end of the input buffer unit is respectively connected to the serial shift register group and the data conversion unit, and the input buffer unit is used to buffer the input data and output the buffered data in sequence at a preset time interval;

[0012] The serial shift register group includes L-1 first registers connected in sequence, the input end of the first of the L-1 first registers is connected to the output end of the input buffer unit, and the output ends of the L-1 first registers are respectively connected to the data conversion unit, the serial shift register group is used to perform serial shift on the input data, and cache and output the data after the serial shift processing, and L represents the number of filter tap coefficients;

[0013] The data conversion unit, the output end of the data conversion unit is connected to the input end of the random calculation unit, and the data conversion unit is used to convert multiple data input in parallel into a multi-channel random bit sequence and output it;

[0014] The random calculation unit, the output end of the random calculation unit is connected to the input end of the data recovery unit, and the random calculation unit is used to perform logical operation processing on multiple random bit sequences and multiple pre-configured filter coefficients to obtain and output random filtering results;

[0015] The data recovery unit, the output end of the data recovery unit is connected to the input end of the output buffer unit, and the data recovery unit is used to convert the random filtering result into binary data and output it;

[0016] The output buffer unit is used to buffer and output binary data.

[0017] In some optional implementations, the preprocessing expression is:

[0018]

[0019] Among them, x i represents the obtained preprocessed data, represents the input data of the digital filter device, and n represents the input data The data width of the input data The value range is [-2 n-1 ,2 n-1 -1], preprocessed data x i The value range is [0,2 n -1].

[0020] In some optional implementations, the data conversion unit includes: a first linear feedback shift register, a first weight generation subunit and a first value comparison subunit;

[0021] The number of stages of the first linear feedback shift register is n, and is used to generate a cycle period of 2 n -1 pseudo-random sequence, caching and outputting the pseudo-random sequence, and n represents the data bit width of the input data of the digital filter device;

[0022] The first weight generating subunits include two, the input ends of the two first weight generating subunits are respectively connected to the output end of the first linear feedback shift register, and the two first weight generating subunits respectively perform weight calculation on the data input by the first linear feedback shift register to generate and output n weights;

[0023] The first numerical comparison subunits include L units, and the first input ends of the L first numerical comparison subunits are respectively connected to the output end of the input cache unit and the output ends of L-1 first registers, the second input ends of the first numerical comparison subunits of the odd bits of the L first numerical comparison subunits are connected to the output end of the first first weight generation subunit, and the second input ends of the first numerical comparison subunits of the even bits of the L first numerical comparison subunits are connected to the output end of the second first weight generation subunit, and the first numerical comparison subunits are used to perform AND logic operations on n weights and n data bits of data input by the input cache unit or the first register, and perform OR logic operations on the n AND logic operation results to obtain and output a random bit sequence.

[0024] In some optional implementations, the weight calculation expression corresponding to the first weight generating subunit is:

[0025]

[0026] Where i is a variable, i=2,3...,n-3, w 1,m (k) represents the kth weight generated by the first weight generating subunit in the mth clock cycle, represents the output data of the kth register in the first linear feedback shift register in the mth clock cycle, Express Negate, k=1,2,3...,n, ∧ represents logical AND operation.

[0027] In some optional implementations, the weight calculation expression corresponding to the second first weight generating subunit is:

[0028]

[0029] Where i is a variable, i=2,3...,n-3, w 2,m (k) represents the kth weight generated by the second first weight generating subunit in the mth clock cycle, represents the output data of the kth register in the first linear feedback shift register in the mth clock cycle, Express Negate, k=1,2,3...,n, ∧ represents logical AND operation.

[0030] In some optional implementations, the first value comparison subunit includes: an AND gate and an OR gate;

[0031] The AND gates include n AND gates, the first input ends of the n AND gates are connected to the output end of the input buffer unit or one of the first registers, the second input ends of the n AND gates are connected to the output end of the first first weight generating subunit or the second first weight generating subunit, and the kth AND gate among the n AND gates is used to perform an AND logic operation on the kth weight input by the first weight generating subunit and the kth data bit of the data input by the input buffer unit or the first register and output the AND logic operation result;

[0032] The OR gate includes n-1, the n-1 OR gates are cascaded in sequence, the output end of the AND gate is connected to the input end of the OR gate, and the n-1 OR gates are used to perform OR logic operations on the n AND logic operation results output by the n AND gates to obtain and output a random bit sequence.

[0033] In some optional implementations, the random calculation unit includes: an XNOR gate, a data selector, and a selector control unit;

[0034] The XEN-OR gates include L gates, the first input ends of the L XEN-OR gates are respectively connected to the output ends of the L first value comparison subunits, the second input ends of the L XEN-OR gates are respectively used to input the sign bits of the pre-configured L filter coefficients in the binary complement representation form, and the kth XEN-OR gate among the L XEN-OR gates is used to perform an XEN-OR logic operation on the random bit sequence input by the kth first value comparison subunit and the sign bit of the kth filter coefficient in the binary complement representation form, to obtain and output the XEN-OR logic operation result;

[0035] The data selectors include L-1, the L-1 data selectors are cascaded in sequence, the output end of the XNOR gate is connected to the input end of the data selector, and the L-1 data selectors are used to select one path of data output from L paths of data output by the L XNOR gates according to the control signal of the selector control unit;

[0036] The selector control unit includes multiple data selectors at the same level connected to the same selector control unit, and the selector control unit is used to generate a control signal based on the filter coefficient corresponding to the input data of the XENOR gate associated with the connected data selector and send it to the data selector.

[0037] In some optional implementations, the selector control unit includes: a second linear feedback shift register, a second weight generation subunit, and a second value comparison subunit;

[0038] The number of stages of the second linear feedback shift register is n, and is used to generate a cycle period of 2 n-1 pseudo-random sequence, and cache and output the pseudo-random sequence, where n represents the data bit width of the input data of the digital filter device;

[0039] The input end of the second weight generating subunit is connected to the output end of the second linear feedback shift register, and the second weight generating subunit is used to perform weight calculation on the data input by the second linear feedback shift register to generate and output n weights;

[0040] The second numerical comparison subunit includes s i , s i Indicates the number of the data selectors connected to the selector control unit, s i The first input terminals of the second value comparison subunits are respectively used to input pre-configured s i comparison value, s i The second input terminals of the second value comparison subunits are respectively connected to the output terminals of the second weight generation subunits. i The output terminals of the second value comparison subunits are respectively connected to s i The second numerical comparison subunit is connected to the data selector, the second numerical comparison subunit is used to perform AND logic operations on the n weights and the n data bits of the comparison value, and perform OR logic operations on the n AND logic operation results to obtain and output a control signal, and the comparison value input to the second numerical comparison subunit is determined according to the filter coefficient corresponding to the input data of the XNOR gate associated with the data selector connected to the second numerical comparison subunit.

[0041] In some optional implementations, it is assumed that: the first input terminal of the data selector connected to the rth second value comparison subunit is associated with P said XNOR gates, and the filter coefficients corresponding to the input data of the P said XNOR gates are respectively The second input terminal of the data selector connected to the rth second value comparison subunit is associated with Q XNOR gates, and the filter coefficients corresponding to the input data of the Q XNOR gates are respectively Then the comparison value input to the rth second value comparison subunit is expressed as:

[0042]

[0043] Among them, λ i,r represents the comparison value input to the rth second numerical comparison subunit, and p and q represent intermediate variables.

[0044] In some optional implementations, the data recovery unit includes: an adder, an n-bit register, and a subtractor;

[0045] The first input end of the adder is connected to the output end of the random calculation unit, the second input end of the adder is connected to the output end of the n-bit register, the output end of the adder is connected to the input end of the n-bit register, and the adder is used to accumulate the random filtering result output by the random calculation unit bit by bit and output the accumulated result;

[0046] The output end of the n-bit register is also connected to the first input end of the subtractor, and the n-bit register is used to determine and output 2 according to the accumulated result. n-1 The number of bits "1" in a clock cycle;

[0047] The second input terminal of the subtractor is used to input 2 n-1 The output end of the subtractor is connected to the input end of the output buffer unit, and the subtractor is used to add the data input by the n-bit register to the 2 n-1 Subtract and obtain and output binary data.

[0048] The main advantages of the technical solution of the present invention are as follows:

[0049] The random calculation-based digital filter device of the present invention is mainly implemented by logic gate circuits, does not contain multipliers, and only uses one adder and one subtractor, which can significantly reduce hardware complexity and hardware resource overhead, and can be implemented on various types of FPGAs; by converting binary data into random bit streams, and performing logical operations on the random bit streams to equivalently achieve arithmetic operations such as binary multiplication and addition, when encountering situations such as single particle flips, only a small number of bits in the random bit stream flip, and in the process of bit accumulation performed by the data recovery unit, these bit flips have little effect on the final binary data recovery, which can ensure the calculation accuracy of the digital filter when bit flips occur, and ensure the stable execution of the overall function. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 A schematic diagram of the structure of a random calculation digital filter device provided by an embodiment of the present invention;

[0052] Figure 2 A schematic diagram of the working timing of a random calculation digital filter device provided by an embodiment of the present invention;

[0053] Figure 3 A structural schematic diagram of a data conversion unit provided by an embodiment of the present invention;

[0054] Figure 4 A schematic diagram of the structure of a first linear feedback shift register provided by an embodiment of the present invention;

[0055] Figure 5 A schematic diagram of the structure of a first weight generating subunit provided by an embodiment of the present invention;

[0056] Figure 6 A schematic diagram of the connection relationship between the first linear feedback shift register and the first weight generating subunit in the data conversion unit provided by an embodiment of the present invention;

[0057] Figure 7 A schematic diagram of the structure of a first numerical comparison subunit provided by an embodiment of the present invention;

[0058] Figure 8 A schematic diagram of the structure of a random calculation unit provided by an embodiment of the present invention;

[0059] Fig. 9 A schematic diagram of the structure of a selector control unit provided by an embodiment of the present invention;

[0060] Fig.10 A structural schematic diagram of a data recovery unit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0062] The technical solution provided by the embodiments of the present invention is described in detail below with reference to the accompanying drawings.

[0063] See also Figure 1 , Figure 1 A schematic diagram of a random calculation digital filter device provided by an embodiment of the present invention is provided. Figure 1 In the embodiment of the present invention, D represents a first register. A digital filter device based on random calculation is provided, and the digital filter device comprises:

[0064] A preprocessing unit, used for preprocessing input data of the digital filter device, obtaining and outputting preprocessed data;

[0065] An input buffer unit, wherein the input end of the input buffer unit is connected to the output end of the preprocessing unit, and the output end of the input buffer unit is respectively connected to the serial shift register group and the data conversion unit, and the input buffer unit is used to buffer the input data and output the buffered data in sequence at a preset time interval;

[0066] A serial shift register group, comprising L-1 first registers connected in sequence, wherein an input end of a first first register among the L-1 first registers is connected to an output end of an input buffer unit, and output ends of the L-1 first registers are respectively connected to data conversion units, the serial shift register group is used to perform serial shifting on input data, and cache and output the data after serial shifting processing, wherein L represents the number of filter tap coefficients;

[0067] A data conversion unit, wherein an output end of the data conversion unit is connected to an input end of the random calculation unit, and the data conversion unit is used to convert a plurality of data input in parallel into a multi-channel random bit sequence and output the sequence;

[0068] A random calculation unit, wherein the output end of the random calculation unit is connected to the input end of the data recovery unit, and the random calculation unit is used to perform logic operations on multiple random bit sequences and multiple pre-configured filter coefficients to obtain and output random filtering results;

[0069] A data recovery unit, wherein the output end of the data recovery unit is connected to the input end of the output buffer unit, and the data recovery unit is used to convert the random filtering result into binary data and output the binary data;

[0070] The output buffer unit is used to buffer and output binary data.

[0071] The working principle of the random calculation digital filter device provided by the embodiment of the present invention is described below:

[0072] See also Figure 1-Figure 2 , Figure 2 The following is a schematic diagram of the working sequence of a random calculation digital filter device provided by an embodiment of the present invention. Assumption: The clock frequency corresponding to the input data of the digital filter device is The digital filter device performs random calculations at a clock frequency of The input data, output data and filter coefficients of the digital filter device are all signed fixed-point numbers, and the data bit width is n bits.

[0073] Based on the above assumptions, when the random calculation digital filter device provided by the embodiment of the present invention is working, the preprocessing unit first processes the input data of the digital filter device. Convert the converted data x iThe input buffer unit is sent to the write port (input port) of the input buffer unit according to the clock frequency. Work, read port (output port) according to the clock frequency Work, thereby achieving isolation of different clock domains; the input cache unit sends data x to the cache preprocessing unit i At the same time, The buffered data is outputted in sequence at time intervals to send the buffered data to a serial shift register group and a data conversion unit of length L-1; the serial shift register group performs serial shifting and buffering on the received data, and sends the buffered data in the L-1 registers to the data conversion unit together; the data conversion unit receives L data (x1, x2, ..., x L ) and then starts data conversion, converting the L parallel input data into L paths with a length of 2 n A random bit sequence (p1, p2, ..., p L ) and outputs it to the random calculation unit, and the processing delay of the data conversion unit is 2 clock cycles; after receiving the random bit sequence, the random calculation unit starts to perform logical operation processing on the random bit sequence and the pre-configured filter coefficients to obtain a random bit stream y1 corresponding to the output data of the digital filter device, that is, the random filtering result, and outputs the obtained random bit stream to the data recovery unit, and the processing delay of the random calculation unit is 1 clock cycle; the data recovery unit converts the random bit stream into n-bit data That is, binary signed data, and outputs the binary signed data to the output buffer unit, and the processing delay of the data recovery unit is 1 clock cycle; the write port (input end) of the output buffer unit is based on the clock frequency Work, read port (output port) according to the clock frequency Work, read and output binary signed data when the output buffer is not empty As the output of the digital filter device.

[0074] According to the above working process, it can be seen that in the working clock In the clock domain, the computational delay of the digital filter device is L(2 n -1)+4 clock cycles.

[0075] Further, in one implementation of the embodiment of the present invention, when the preprocessing unit preprocesses the input data, the preprocessing expression is:

[0076]

[0077] Among them, x i represents the obtained preprocessed data, represents the input data of the digital filter device, and n represents the input data The data width of the input data The value range is [-2 n-1 ,2 n-1 -1], preprocessed data x i The value range is [0,2 n -1].

[0078] refer to Figure 3-7 ,Further, in one implementation of the embodiment of the present invention, the data conversion unit includes: a first linear feedback shift register, a first weight generation subunit and a first value comparison subunit;

[0079] The number of stages of the first linear feedback shift register is n, which is used to generate a cycle period of 2 n -1 pseudo-random sequence, caching and outputting the pseudo-random sequence, and n represents the data bit width of the input data of the digital filter device;

[0080] The first weight value generating subunits include two, the input ends of the two first weight value generating subunits are respectively connected to the output end of the first linear feedback shift register, and the two first weight value generating subunits respectively perform weight value calculation on the data input by the first linear feedback shift register to generate and output n weight values;

[0081] The first numerical comparison subunit includes L units, and the first input ends of the L first numerical comparison subunits are respectively connected to the output end of the input cache unit and the output ends of the L-1 first registers. The second input ends of the first numerical comparison subunits of odd bits in the L first numerical comparison subunits are connected to the output end of the first first weight generation subunit, and the second input ends of the first numerical comparison subunits of even bits in the L first numerical comparison subunits are connected to the output end of the second first weight generation subunit. The first numerical comparison subunit is used to perform AND logic operations on n weights and n data bits of data input from the input cache unit or the first register, and perform OR logic operations on the n AND logic operation results to obtain and output a random bit sequence.

[0082] In the embodiment of the present invention, the number of stages of the first linear feedback shift register is n, and the first linear feedback shift register generates a cycle period of 2 by selecting a suitable primitive polynomial. n -1 pseudo-random sequence and rewrite it back to n shift registers R1, R2, ..., R n , during the operation of the first linear feedback shift register, registers R1, R2, ..., R n The values ​​are sent to two first weight generation subunits, and the first weight generation subunit calculates the weights required by the first value comparison subunit according to the input values.

[0083] Further, in one implementation of the embodiment of the present invention, the weight calculation expression corresponding to the first first weight generating subunit is:

[0084]

[0085] The weight calculation expression corresponding to the second first weight generating subunit is:

[0086]

[0087] Where i is a variable, i=2,3...,n-3, w 1,m (k) represents the kth weight generated by the first first weight generation subunit in the mth clock cycle, w 2,m (k) represents the kth weight generated by the second first weight generation subunit in the mth clock cycle, represents the output data of the kth register in the first linear feedback shift register in the mth clock cycle, Express Negate, k=1,2,3...,n, ∧ represents logical AND operation.

[0088] refer to Figure 5 , Further, in one implementation of the embodiment of the present invention, the first weight generating subunit is constructed using an OR gate and a NOT gate.

[0089] refer to Figure 6 In an embodiment of the present invention, the first input port to the nth input port of the first first weight generating subunit are respectively connected to the first register to the nth register of the first linear feedback shift register, and the first input port to the nth input port of the second first weight generating subunit are respectively connected to the nth register to the first register of the first linear feedback shift register, so as to implement the weight calculation method of the first weight generating subunit defined above.

[0090] In the embodiment of the present invention, the first weight value generation subunit is implemented by using an OR gate and a NOT gate, which can reduce hardware resource overhead. At the same time, the two first weight value generation subunits use different orders when using the output bits of the first linear feedback shift register, which can reduce the correlation between the two sets of weight values ​​generated, thereby ensuring the accuracy of random calculation.

[0091] refer to Figure 7 ,Further, in one implementation of the embodiment of the present invention, the first numerical comparison subunit includes: an AND gate and an OR gate;

[0092] The AND gates include n AND gates, the first input ends of the n AND gates are connected to the output end of the input buffer unit or a first register, the second input ends of the n AND gates are connected to the output end of the first first weight generating subunit or the second first weight generating subunit, and the kth AND gate among the n AND gates is used to perform an AND logic operation on the kth weight input by the first weight generating subunit and the kth data bit of the data input by the input buffer unit or the first register, and output the AND logic operation result;

[0093] The OR gates include n-1 gates, which are cascaded in sequence, and the output end of the AND gate is connected to the input end of the OR gate. The n-1 OR gates are used to perform OR logic operations on n AND logic operation results output by the n AND gates to obtain and output a random bit sequence.

[0094] Specifically, the input data received by the first numerical comparison subunit is x i For example, x i The corresponding n data bits x i (1),x i (2),…,x i (n) in 2 n -1 clock cycle, during which the first weight generation subunit outputs w 1,m (k), k=1,2,…,n(or w 2,m (k), k=1,2,…,n) in the mth clock cycle (m=1,2,…,2 n-1 ) and data x i The n data bits are respectively ANDed by n AND gates, and then the n AND operation results are ORed as a whole by n-1 cascaded OR gates to obtain a random sequence p. i The logic value p at the mth clock cycle i (m).

[0095] In the embodiment of the present invention, the first numerical comparison subunit is implemented by using an AND gate and an OR gate, which can reduce hardware resource overhead, and the digital logic circuit formed by the AND gate and the OR gate can generate a random bit sequence corresponding to the input data.

[0096] refer to Figure 8 , Figure 8 A schematic diagram of a random computing unit provided in an embodiment of the present invention is provided. Figure 8 In the embodiment, MUX represents a data selector. Further, in one implementation of the embodiment of the present invention, the random calculation unit includes: an XNOR gate, a data selector and a selector control unit;

[0097] The XOR gates include L gates, the first input ends of the L XOR gates are respectively connected to the output ends of the L first value comparison subunits, the second input ends of the L XOR gates are respectively used to input the sign bits of the pre-configured L filter coefficients in the binary complement representation form, and the kth XOR gate among the L XOR gates is used to perform an XOR logic operation on the random bit sequence input by the kth first value comparison subunit and the sign bit of the kth filter coefficient in the binary complement representation form, to obtain and output the XOR logic operation result;

[0098] The data selector includes L-1 data selectors, which are cascaded in sequence, and the output end of the X-OR gate is connected to the input end of the data selector. The L-1 data selectors are used to select one data path from L data paths output by the L X-OR gates according to the control signal of the selector control unit to output;

[0099] The selector control unit includes multiple data selectors at the same level connected to the same selector control unit. The selector control unit is used to generate a control signal according to the filter coefficient corresponding to the input data of the XENOR gate associated with the connected data selector and send it to the data selector.

[0100] In the embodiment of the present invention, in order to facilitate the design layout and data processing, L-1 data selectors are formed. class, Indicates rounding up, and when the number of output signal paths of the i-th stage is an odd number, the spare one signal will be directly sent to the next stage with spare signals, and the combination of two spare signals will be sent to a data selector of the next stage for selection. Accordingly, based on the above settings, the number of data selectors deployed at the i-th stage is or indivual.

[0101] It should be noted that when L-1 data selectors are formed The selector control unit includes at least The data selectors at the same level are connected to the same selector control unit, and the data selectors at different levels are connected to different selector control units.

[0102] Specifically, the random bit sequence received by the random computing unit is p i ,p i-1 ,…,p i-L-1 , the configured L filter coefficients are c1, c2, …, c L For example, in each clock cycle, under the processing of the random computing unit, the random bit sequence p i ,p i-1 ,…,p i-L-1 The L bit values ​​of are respectively the same as sign(c1),sign(c2),…,sign(cL ) performs an XNOR operation, where sign(c i ) represents the filter coefficient c i In the two's complement representation, the sign bit is ORed. After the level data selector is selected, it is used as the random filtering result y i output during the current clock cycle.

[0103] Furthermore, in the embodiment of the present invention, the data selector of each stage is controlled by generating an independent control signal through the corresponding selector control unit.

[0104] refer to Fig. 9 , in one implementation of the embodiment of the present invention, the selector control unit includes: a second linear feedback shift register, a second weight generation subunit and a second value comparison subunit;

[0105] The number of stages of the second linear feedback shift register is n, which is used to generate a cycle period of 2 n -1 pseudo-random sequence, and cache and output the pseudo-random sequence, where n represents the data bit width of the input data of the digital filter device;

[0106] The input end of the second weight generating subunit is connected to the output end of the second linear feedback shift register, and the second weight generating subunit is used to perform weight calculation on the data input by the second linear feedback shift register to generate and output n weights;

[0107] The second numerical comparison subunit includes s i , s i Indicates the number of data selectors connected to the selector control unit, s i The first input terminals of the second value comparison subunits are respectively used to input the pre-configured s i comparison value, s i The second input terminals of the second value comparison subunits are respectively connected to the output terminals of the second weight generation subunits. i The output terminals of the second value comparison subunits are respectively connected to s i The second numerical comparison subunit is connected to a data selector, and the second numerical comparison subunit is used to perform AND logic operations on the n weights and the n data bits of the comparison value, and perform OR logic operations on the n AND logic operation results to obtain and output a control signal, and the comparison value input to the second numerical comparison subunit is determined according to the filter coefficient corresponding to the input data of the XNOR gate associated with the data selector connected to the second numerical comparison subunit.

[0108] It should be noted that the second linear feedback shift register, the second weight generating subunit and the second value comparing subunit have the same structure as the first linear feedback shift register, the first weight generating subunit and the first value comparing subunit.

[0109] In the embodiment of the present invention, for each stage of selector control unit, different values ​​are selected to initialize the second linear feedback shift register, thereby ensuring the independence of control signals at each stage.

[0110] In the embodiment of the present invention, the comparison value input by the second numerical comparison subunit inside the selector control unit is configured according to the data selector connected to the output end of the second numerical comparison subunit. Specific setting: the first input end of the data selector connected to the rth second numerical comparison subunit of the i-th level selector control unit is associated with P XNOR gates, and the XNOR gate associated with the first input end of the data selector is determined by backtracking the input signal of the first input end. The filter coefficients corresponding to the input data of the P XNOR gates are respectively The second input terminal of the data selector connected to the rth second value comparison subunit is associated with Q XNOR gates. The XNOR gate associated with the second input terminal of the data selector is determined by backtracking the input signal of the second input terminal. The filter coefficients corresponding to the input data of the Q XNOR gates are: Then the comparison value input to the rth second value comparison subunit of the i-th level selector control unit is expressed as:

[0111]

[0112] Among them, λ i,r represents the comparison value input to the rth second numerical comparison subunit of the i-th level selector control unit, and p and q represent intermediate variables.

[0113] In an embodiment of the present invention, based on the structure of the random calculation unit and the selector control unit defined above, when the filter coefficient and the order are determined, the comparison value corresponding to the second numerical comparison subunit can also be determined. Therefore, the comparison value corresponding to the second numerical comparison subunit is calculated offline after the filter coefficient and the order are determined, and stored inside the random calculation unit of the digital filter device, thereby eliminating the need to deploy additional calculation circuits for determining the comparison value, thereby reducing hardware resource overhead.

[0114] Furthermore, in the embodiment of the present invention, the data recovery unit is used to convert the random filtering result into binary data and output it.

[0115] refer to Fig.10 , in one implementation of the embodiment of the present invention, the data recovery unit includes: an adder, an n-bit register and a subtractor;

[0116] A first input end of the adder is connected to an output end of the random calculation unit, a second input end of the adder is connected to an output end of the n-bit register, and an output end of the adder is connected to an input end of the n-bit register. The adder is used to accumulate the random filtering result output by the random calculation unit bit by bit and output the accumulated result.

[0117] The output end of the n-bit register is also connected to the first input end of the subtractor. The n-bit register is used to determine and output 2 according to the accumulated result. n-1 The number of bits "1" in a clock cycle;

[0118] The second input of the subtractor is used to input 2 n-1 The output of the subtractor is connected to the input of the output buffer unit. The subtractor is used to combine the data input by the n-bit register with the 2 n-1 Subtract and obtain and output binary data.

[0119] Specifically, refer to Fig.10 , the random filtering result received by the data recovery unit is y i For example, the random filtering result y i By adding bit by bit, we can determine 2 n -The number of bits "1" in 1 clock cycle is taken as y i ′. Note that y i The value range of ′ is [0,2 n -1], according to the data x input by the input buffer unit i The actual input data of the digital filter device The conversion relationship is calculated by i ′-2 n-1 Get the actual output of the digital filter device And send the result to the output buffer unit, The value range is [-2 n-1 ,2 n-1 -1].

[0120] It can be seen that the random calculation-based digital filter device provided in the embodiment of the present invention is mainly implemented using logic gate circuits, does not contain multipliers, and only uses 1 adder and 1 subtractor, which can significantly reduce hardware complexity and hardware resource overhead, and can be implemented on various types of FPGAs.

[0121] The random calculation-based digital filter device provided by the embodiment of the present invention converts binary data into a random bit stream, and implements equivalent arithmetic operations such as binary multiplication and addition by performing logical operations on the random bit stream. When encountering a single particle flip, only a small number of bits in the random bit stream flip. During the bit accumulation process performed by the data recovery unit, these bit flips have little effect on the final binary data recovery, which can ensure the calculation accuracy of the digital filter when a bit flip occurs, and ensure the stable execution of the overall function.

[0122] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A digital filter device based on random calculation, characterized in that: The digital filter device comprises: A preprocessing unit, used for preprocessing the input data of the digital filter device, obtaining and outputting preprocessed data; An input buffer unit, wherein the input end of the input buffer unit is connected to the output end of the preprocessing unit, and the output end of the input buffer unit is respectively connected to the serial shift register group and the data conversion unit, and the input buffer unit is used to buffer the input data and output the buffered data in sequence at a preset time interval; The serial shift register group includes L-1 first registers connected in sequence, the input end of the first of the L-1 first registers is connected to the output end of the input buffer unit, and the output ends of the L-1 first registers are respectively connected to the data conversion unit, the serial shift register group is used to perform serial shift on the input data, and cache and output the data after the serial shift processing, and L represents the number of filter tap coefficients; The data conversion unit, the output end of the data conversion unit is connected to the input end of the random calculation unit, and the data conversion unit is used to convert multiple data input in parallel into a multi-channel random bit sequence and output it; The random calculation unit, the output end of the random calculation unit is connected to the input end of the data recovery unit, and the random calculation unit is used to perform logical operation processing on multiple random bit sequences and multiple pre-configured filter coefficients to obtain and output random filtering results; The data recovery unit, the output end of the data recovery unit is connected to the input end of the output buffer unit, and the data recovery unit is used to convert the random filtering result into binary data and output it; The output buffer unit is used to buffer and output binary data.

2. The random calculation digital filter device according to claim 1, characterized in that: The preprocessing expression is: Among them, x i represents the obtained preprocessed data, represents the input data of the digital filter device, and n represents the input data The data width of the input data The value range is [-2 n-1 ,2 n-1 -1], preprocessed data x i The value range is [0,2 n -1].

3. The random calculation based digital filter device according to claim 1, characterized in that: The data conversion unit includes: a first linear feedback shift register, a first weight generation subunit and a first value comparison subunit; The number of stages of the first linear feedback shift register is n, and is used to generate a cycle period of 2 n -1 pseudo-random sequence, caching and outputting the pseudo-random sequence, and n represents the data bit width of the input data of the digital filter device; The first weight generating subunits include two, the input ends of the two first weight generating subunits are respectively connected to the output end of the first linear feedback shift register, and the two first weight generating subunits respectively perform weight calculation on the data input by the first linear feedback shift register to generate and output n weights; The first numerical comparison subunits include L units, and the first input ends of the L first numerical comparison subunits are respectively connected to the output end of the input cache unit and the output ends of L-1 first registers, the second input ends of the first numerical comparison subunits of the odd bits of the L first numerical comparison subunits are connected to the output end of the first first weight generation subunit, and the second input ends of the first numerical comparison subunits of the even bits of the L first numerical comparison subunits are connected to the output end of the second first weight generation subunit, and the first numerical comparison subunits are used to perform AND logic operations on n weights and n data bits of data input by the input cache unit or the first register, and perform OR logic operations on the n AND logic operation results to obtain and output a random bit sequence.

4. The random calculation based digital filter device according to claim 3, characterized in that: The weight calculation expression corresponding to the first weight generating subunit is: Where i is a variable, i=2,3...,n-3, w 1,m (k) represents the kth weight generated by the first weight generating subunit in the mth clock cycle, represents the output data of the kth register in the first linear feedback shift register in the mth clock cycle, Express Negate, k=1,2,3...,n, ∧ represents logical AND operation.

5. The random calculation based digital filter device according to claim 4, characterized in that: The weight calculation expression corresponding to the second first weight generating subunit is: Where i is a variable, i=2,3...,n-3, w 2,m (k) represents the kth weight generated by the second first weight generating subunit in the mth clock cycle, represents the output data of the kth register in the first linear feedback shift register in the mth clock cycle, Express Negate, k=1,2,3...,n, ∧ represents logical AND operation.

6. The random calculation based digital filter device according to claim 5, characterized in that: The first numerical comparison subunit includes: an AND gate and an OR gate; The AND gates include n AND gates, the first input ends of the n AND gates are connected to the output end of the input buffer unit or one of the first registers, the second input ends of the n AND gates are connected to the output end of the first first weight generating subunit or the second first weight generating subunit, and the kth AND gate among the n AND gates is used to perform an AND logic operation on the kth weight input by the first weight generating subunit and the kth data bit of the data input by the input buffer unit or the first register and output the AND logic operation result; The OR gate includes n-1, the n-1 OR gates are cascaded in sequence, the output end of the AND gate is connected to the input end of the OR gate, and the n-1 OR gates are used to perform OR logic operations on the n AND logic operation results output by the n AND gates to obtain and output a random bit sequence.

7. The random calculation based digital filter device according to claim 3 or 6, characterized in that: The random calculation unit comprises: an XNOR gate, a data selector and a selector control unit; The XEN-OR gates include L gates, the first input ends of the L XEN-OR gates are respectively connected to the output ends of the L first value comparison subunits, the second input ends of the L XEN-OR gates are respectively used to input the sign bits of the pre-configured L filter coefficients in the binary complement representation form, and the kth XEN-OR gate among the L XEN-OR gates is used to perform an XEN-OR logic operation on the random bit sequence input by the kth first value comparison subunit and the sign bit of the kth filter coefficient in the binary complement representation form, to obtain and output the XEN-OR logic operation result; The data selectors include L-1, the L-1 data selectors are cascaded in sequence, the output end of the XNOR gate is connected to the input end of the data selector, and the L-1 data selectors are used to select one path of data output from L paths of data output by the L XNOR gates according to the control signal of the selector control unit; The selector control unit includes multiple data selectors at the same level connected to the same selector control unit, and the selector control unit is used to generate a control signal based on the filter coefficient corresponding to the input data of the XENOR gate associated with the connected data selector and send it to the data selector.

8. The random calculation based digital filter device according to claim 7, characterized in that: The selector control unit comprises: a second linear feedback shift register, a second weight generating subunit and a second value comparing subunit; The number of stages of the second linear feedback shift register is n, and is used to generate a cycle period of 2 n -1 pseudo-random sequence, and cache and output the pseudo-random sequence, where n represents the data bit width of the input data of the digital filter device; The input end of the second weight generating subunit is connected to the output end of the second linear feedback shift register, and the second weight generating subunit is used to perform weight calculation on the data input by the second linear feedback shift register to generate and output n weights; The second numerical comparison subunit includes s i , s i Indicates the number of the data selectors connected to the selector control unit, s i The first input terminals of the second value comparison subunits are respectively used to input pre-configured s i comparison value, s i The second input terminals of the second value comparison subunits are respectively connected to the output terminals of the second weight generation subunits. i The output terminals of the second value comparison subunits are respectively connected to s i The second numerical comparison subunit is connected to the data selector, the second numerical comparison subunit is used to perform AND logic operations on the n weights and the n data bits of the comparison value, and perform OR logic operations on the n AND logic operation results to obtain and output a control signal, and the comparison value input to the second numerical comparison subunit is determined according to the filter coefficient corresponding to the input data of the XNOR gate associated with the data selector connected to the second numerical comparison subunit.

9. The random calculation based digital filter device according to claim 8, characterized in that: Assume that the first input terminal of the data selector connected to the rth second value comparison subunit is associated with P XNOR gates, and the filter coefficients corresponding to the input data of the P XNOR gates are: The second input terminal of the data selector connected to the rth second value comparison subunit is associated with Q XNOR gates, and the filter coefficients corresponding to the input data of the Q XNOR gates are respectively Then the comparison value input to the rth second value comparison subunit is expressed as: Among them, λ i,r represents the comparison value input to the rth second numerical comparison subunit, and p and q represent intermediate variables.

10. The random calculation based digital filter device according to claim 7, characterized in that: The data recovery unit comprises: an adder, an n-bit register and a subtractor; The first input end of the adder is connected to the output end of the random calculation unit, the second input end of the adder is connected to the output end of the n-bit register, the output end of the adder is connected to the input end of the n-bit register, and the adder is used to accumulate the random filtering result output by the random calculation unit bit by bit and output the accumulated result; The output end of the n-bit register is also connected to the first input end of the subtractor, and the n-bit register is used to determine and output 2 according to the accumulated result. n-1 The number of bits "1" in a clock cycle; The second input terminal of the subtractor is used to input 2 n-1 The output end of the subtractor is connected to the input end of the output buffer unit, and the subtractor is used to add the data input by the n-bit register to the 2 n-1 Subtract and obtain and output binary data.

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