Duty cycle adjustment circuit and memory

Abstract

The present application discloses a duty cycle adjustment circuit and memory. The duty cycle adjustment circuit includes a duty cycle adjustment link, a duty cycle detector and a state machine. The duty cycle adjustment link receives an initial clock signal and adjusts the initial clock signal to generate an output clock signal; the duty cycle detector is coupled to the duty cycle adjustment link to generate a corresponding detection signal based on the detected duty cycle of the output clock signal; the state machine is coupled to the duty cycle detector to generate a corresponding control code based on the detection signal; the duty cycle adjustment link includes a plurality of inverter units connected in series, a first adjustment link and a second adjustment link, and the first adjustment link and the second adjustment link are both coupled to the same intermediate node of the duty cycle adjustment link. In the above manner, the present application couples the first adjustment link and the second adjustment link to the same intermediate node of the duty cycle adjustment link to reduce the delay of the duty cycle adjustment circuit.

Description

Technical Field

[0001] The present application relates to the technical field of duty cycle regulation, and in particular to a duty cycle adjustment circuit and a memory. Background Art

[0002] Double Data Rate (DDR) synchronous random access memory (SDRAM) is the mainstream random access memory and a typical semiconductor memory. DDR-type memory is designed to synchronize data input and output on both the rising and falling edges of the clock signal. Therefore, the clock signal's duty cycle must be precisely maintained at 50%. To this end, chips typically use a duty cycle adjustment circuit to adjust the clock signal's duty cycle. Chip specifications specify delays related to memory chip reads, writes, and on-die termination (ODT). Therefore, the delay of the delay-locked loop (DLL) path cannot be too long. The duty cycle adjustment circuit is part of the DLL path, so reducing its delay is essential. Summary of the Invention

[0003] In order to solve the above problems, the present application provides a duty cycle adjustment circuit and a memory to reduce the delay of the duty cycle adjustment circuit, thereby reducing the delay of the delay-locked loop path.

[0004] To solve the above technical problems, a technical solution adopted in the present application is: providing a duty cycle adjustment circuit, which includes a duty cycle adjustment link, a duty cycle detector and a state machine, wherein the duty cycle adjustment link receives an initial clock signal and adjusts the initial clock signal to generate an output clock signal; the duty cycle detector is coupled to the duty cycle adjustment link to generate a corresponding detection signal based on the detected duty cycle of the output clock signal; the state machine is coupled to the duty cycle detector to generate a corresponding control code based on the detection signal; wherein the duty cycle adjustment link includes a plurality of inverter units connected in series, a first adjustment link and a second adjustment link, the first adjustment link and the second adjustment link are both coupled to the same intermediate node of the duty cycle adjustment link, and adjust the slope of the rising edge or falling edge of the intermediate clock signal generated at the same intermediate node based on the control code and the detection signal, thereby adjusting the duty cycle of the output clock signal, wherein the intermediate node is the connection point between the two inverter units.

[0005] The duty cycle adjustment circuit further includes a bias voltage generation module, which is respectively coupled to the state machine, the first adjustment link and the second adjustment link, and is used to generate a corresponding bias voltage based on the control code and provide it to the first adjustment link and the second adjustment link; wherein the first adjustment link and the second adjustment link adjust the pull-down current or pull-up current of the same intermediate node in the duty cycle adjustment link based on the detection signal and the bias voltage, so as to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node, thereby adjusting the duty cycle of the output clock signal.

[0006] In which, the bias voltage includes a first bias voltage and a second bias voltage, the first regulation link includes a first transmission gate branch and a discharge branch, the first transmission gate branch receives a detection signal and a first bias voltage, and is used to control the conduction or shutoff of the discharge branch based on the detection signal and the first bias voltage; the discharge branch is coupled to the first transmission gate branch and the intermediate node, and in response to the discharge branch being turned on, the discharge branch performs a discharge operation on the intermediate node to adjust the slope of the rising edge of the intermediate clock signal.

[0007] The second regulation link includes a second transmission gate branch and a charging branch. The second transmission gate branch receives a detection signal and a second bias voltage, and is used to control the conduction or shutoff of the charging branch based on the detection signal and the second bias voltage. The charging branch is coupled to the second transmission gate branch and the intermediate node. In response to the charging branch being turned on, the charging branch performs a charging operation on the intermediate node to adjust the slope of the falling edge of the intermediate clock signal.

[0008] The first transmission gate branch includes a first transmission gate and a first transistor. The input terminal of the first transmission gate receives a first bias voltage, the first control terminal of the first transmission gate receives a detection signal, and the second control terminal of the first transmission gate receives an inverted detection signal. The first pass terminal of the first transistor is grounded, and the second pass terminal of the first transistor is coupled to the output terminal of the first transmission gate and the discharge branch. The control terminal of the first transistor receives the inverted detection signal. The discharge branch includes a second transistor and a third transistor. The control terminal of the second transistor is coupled to the output terminal of the first transmission gate and the second pass terminal of the first transistor. The first pass terminal of the second transistor is coupled to the input terminal of the inverter unit in the stage following the intermediate node. The control terminal of the third transistor is coupled to the output terminal of the inverter unit in the stage following the intermediate node. The first pass terminal of the third transistor is coupled to the second pass terminal of the second transistor, and the second pass terminal of the third transistor is grounded. When the detection signal is high, the first transmission gate is turned on and the first transistor is turned off. The control terminal of the second transistor receives the first bias voltage, turning on the second and third transistors. A corresponding pull-down current is generated between the second and third transistors, discharging the intermediate clock signal to adjust the slope of the rising edge of the intermediate clock signal.

[0009] The second transmission gate branch includes a second transmission gate and a fourth transistor, the input end of the second transmission gate receives a second bias voltage, the first control end of the second transmission gate receives an inverted detection signal, and the second control end of the second transmission gate receives the detection signal; the first pass end of the fourth transistor receives a preset voltage, the second pass end of the fourth transistor is coupled to the output end of the second transmission gate and the charging branch; the control end of the fourth transistor receives the inverted detection signal; the charging branch includes a fifth transistor and a sixth transistor, the control end of the fifth transistor is coupled to the output end of the second transmission gate and the second pass end of the fourth transistor, and the first pass end of the fifth transistor is coupled to the output end of the second transmission gate and the second pass end of the fourth transistor. The sixth transistor is coupled to the input terminal of the inverter unit of the subsequent stage of the intermediate node, the control terminal of the sixth transistor is coupled to the output terminal of the inverter unit of the subsequent stage of the intermediate node, the first pass terminal of the sixth transistor is coupled to the second pass terminal of the fifth transistor, and the second pass terminal of the sixth transistor receives a preset voltage; wherein, when the detection signal is at a low level, the second transmission gate is turned on and the fourth transistor is turned off, the control terminal of the fifth transistor receives a second bias voltage, the fifth transistor and the sixth transistor are turned on, and a corresponding pull-up current is generated between the fifth transistor and the sixth transistor, performing a charging operation on the intermediate clock signal to adjust the slope of the falling edge of the intermediate clock signal.

[0010] Among them, in response to the intermediate clock signal and the initial clock signal being in phase, the first adjustment link is used to narrow the duty cycle of the output clock signal based on the first bias voltage and the detection signal; the second adjustment link is used to increase the duty cycle of the output clock signal based on the second bias voltage and the detection signal; in response to the intermediate clock signal and the initial clock signal being out of phase, the first adjustment link is used to increase the duty cycle of the output clock signal based on the first bias voltage and the detection signal; the second adjustment link is used to narrow the duty cycle of the output clock signal based on the second bias voltage and the detection signal.

[0011] The bias voltage generation module includes a bias current generation module and a current mirror module. The bias current generation module includes multiple bias current branches connected in parallel and adjusts the number of bias current branches connected based on a control code to generate a corresponding bias current. The current mirror module is coupled to the bias current generation module to generate a first bias voltage and a second bias voltage based on the bias current. The first bias voltage and the second bias voltage make the pull-down current or pull-up current of the intermediate node the same.

[0012] The current mirror module includes a seventh transistor, an eighth transistor, a ninth transistor, and a first capacitor. The first channel terminal of the seventh transistor is connected to the output terminal of the bias current generating module and coupled to the control terminal of the seventh transistor. The second channel terminal of the seventh transistor is grounded. The control terminal of the seventh transistor is also used to output a first bias voltage. The control terminal of the eighth transistor is connected to the control terminal of the seventh transistor. The first channel terminal of the eighth transistor is connected to the second channel terminal of the ninth transistor. The second channel terminal of the eighth transistor is grounded. The first channel terminal of the ninth transistor receives the first operating voltage. The control terminal of the ninth transistor is coupled to the second channel terminal of the ninth transistor and is used to output a second bias voltage. The first terminal of the first capacitor is grounded. The second terminal of the first capacitor is coupled to the control terminal of the seventh transistor and the control terminal of the eighth transistor, respectively.

[0013] Each bias current branch in the bias current generating module includes a tenth transistor and a switch. The control terminal of the tenth transistor receives a reference voltage, and the first channel terminal of the tenth transistor receives a second operating voltage. The first terminal of the switch is coupled to the second channel terminal of the tenth transistor, and the second terminal of the switch is coupled to the bias current output module. The control terminal of the switch is used to receive a control code to determine whether the corresponding bias current branch is conductive based on the control code.

[0014] Among them, the bias voltage generating module includes a first bias voltage generating module and a second bias voltage generating module, wherein the first bias voltage generating module is used to generate a first bias voltage, and the second bias voltage generating module is used to generate a second bias voltage, and the first bias voltage and the second bias voltage make the pull-down current or the pull-up current of the intermediate node the same.

[0015] In order to solve the above technical problems, another technical solution adopted in the present application is: providing a memory, which includes any one of the duty cycle adjustment circuits mentioned above.

[0016] Different from the prior art, the duty cycle adjustment circuit of the present application includes a duty cycle adjustment link, a duty cycle detector and a state machine. The duty cycle adjustment link receives an initial clock signal and adjusts the initial clock signal to generate an output clock signal; the duty cycle detector is coupled to the duty cycle adjustment link to generate a corresponding detection signal based on the detected duty cycle of the output clock signal; the state machine is coupled to the duty cycle detector to generate a corresponding control code based on the detection signal; wherein, the duty cycle adjustment link includes multiple inverter units connected in series, a first adjustment link and a second adjustment link, the first adjustment link and the second adjustment link are both coupled to the same intermediate node of the duty cycle adjustment link, and adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node based on the control code and the detection signal, thereby adjusting the duty cycle of the output clock signal, and the intermediate node is the connection point between the two inverter units. Through the above method, the first adjustment link and the second adjustment link of the present application can be coupled to the same intermediate node of the duty cycle adjustment link, and there is no need to adjust the duty cycle of the output clock signal separately at the two intermediate nodes of the duty cycle adjustment link, so that the inverter units connected in series in the duty cycle adjustment link can be reduced, thereby saving the delay of the duty cycle adjustment circuit and the delay of the delay-locked loop path. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0018] Figure 1 is a schematic diagram of a first embodiment of a duty cycle adjustment circuit provided by the present application;

[0019] Figure 2 This is a schematic diagram of the second embodiment of the duty cycle adjustment circuit provided by this application

[0020] Figure 3 is a schematic diagram of an embodiment of a duty cycle adjustment link provided by the present application;

[0021] Figure 4 It is a waveform diagram of the intermediate clock signal adjustment process;

[0022] Figure 5 1 is a schematic diagram of the circuit structure of the first embodiment of the bias voltage generating module provided by the present application;

[0023] Figure 6 1 is a circuit structure diagram of a third embodiment of a duty cycle adjustment circuit provided by the present application;

[0024] Figure 7 1 is a structural diagram of an embodiment of a first bias voltage generating module provided by the present application;

[0025] Figure 8 It is a structural diagram of an embodiment of a memory provided by this application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0027] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] Double Data Rate (DDR) synchronous random access memory (SDRAM) is the mainstream random access memory and a typical semiconductor memory. DDR-type memory is designed to synchronize data input and output on both the rising and falling edges of the clock signal. Therefore, the clock signal's duty cycle must be precisely maintained at 50%. To this end, chips typically use a duty cycle adjustment circuit to adjust the clock signal's duty cycle. Chip specifications specify delays related to memory chip reads, writes, and on-die termination (ODT). Therefore, the delay of the delay-locked loop (DLL) path cannot be too long. The duty cycle adjustment circuit is part of the DLL path, so reducing its delay is essential.

[0029] In order to solve the above problems, this application first proposes a duty cycle adjustment circuit. Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the first embodiment of the duty cycle adjustment circuit provided by the present application. Figure 1 As shown, the duty cycle adjustment circuit 100 of this embodiment includes a duty cycle adjustment link 10 , a duty cycle detector 20 and a state machine 30 .

[0030] like Figure 1As shown, the duty cycle adjustment link 10 receives the initial clock signal CLKIN and adjusts the initial clock signal CLKIN to generate the output clock signal CLKOUT; the duty cycle detector 20 is coupled to the duty cycle adjustment link 10 to generate a corresponding detection signal based on the detected duty cycle of the output clock signal CLKOUT; the state machine 30 is coupled to the duty cycle detector 20 to generate a corresponding control code code based on the detection signal <n:1>The duty cycle adjustment link 10 includes a plurality of inverter units 11 connected in series, a first adjustment link 12 and a second adjustment link 13. The first adjustment link 12 and the second adjustment link 13 are both coupled to the same intermediate node of the duty cycle adjustment link 10 and are based on the control code code <n:1>The detection signal adjusts the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT. In this embodiment, the intermediate node of the duty cycle adjustment link 10 is the connection point between the two inverter units 11. It is worth noting that in some embodiments, the duty cycle adjustment link 10 does not directly receive the control code code <n:1>, but based on the control code code <n:1>The detection signal generates other signals to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node.

[0031] In this embodiment, the first regulation link 12 and the second regulation link 13 in the duty cycle regulation link 10 are coupled to the same intermediate node of the duty cycle regulation link 10, that is, coupled to the same connection point between the two inverter units 11, and are used to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT. The specific circuit structures of the first regulation link 12 and the second regulation link 13 are shown below and are not described in detail here.

[0032] The duty cycle detector 20 detects the duty cycle of the output clock signal CLKOUT of the duty cycle adjustment link 10. The duty cycle detector 20 periodically outputs a detection signal during the detection process. In this embodiment, the detection signal is a level signal. If the detection signal outputs a logic level "1", it indicates that the duty cycle is greater than 50%, and if the detection signal outputs a logic level "0", it indicates that the duty cycle is less than 50%. In other embodiments, the detection signal can also be output as a logic level "0" to indicate that the duty cycle is greater than 50%, and as a logic level "1" to indicate that the duty cycle is less than 50%. The relationship between the logic level of the detection signal and the size of the duty cycle is not limited here.

[0033] When the state machine 30 receives the detection signal from the duty cycle detector 20, it will generate the corresponding control code code <n:1>, based on the control code code <n:1>In this embodiment, the first regulation link 12 and the second regulation link 13 are coupled to the same intermediate node of the duty cycle regulation link 10 and can operate separately under the control of the corresponding bias voltage and the detection signal of the duty cycle detector 20, thereby adjusting the duty cycle of the output clock signal CLKOUT of the duty cycle regulation link 10.

[0034] In addition, in this embodiment, the first regulation link 12 and the second regulation link 13 do not operate at the same time. Under the control of the detection signal, only one of the first regulation link 12 and the second regulation link 13 can operate. In this embodiment, the number of inverter units 11 of the duty cycle regulation link 10 is generally set to an even number, so that the initial clock signal CLKIN and the output clock signal CLKOUT are in phase.

[0035] Different from the prior art, the duty cycle adjustment circuit 100 of the present application includes a duty cycle adjustment link 10, a duty cycle detector 20 and a state machine 30. The duty cycle adjustment link 10 receives the initial clock signal CLKIN and adjusts the initial clock signal CLKIN to generate an output clock signal CLKOUT; the duty cycle detector 20 is coupled to the duty cycle adjustment link 10 to generate a corresponding detection signal based on the detected duty cycle of the output clock signal CLKOUT; the state machine 30 is coupled to the duty cycle detector 20 to generate a corresponding control code code based on the detection signal. <n:1>The duty cycle adjustment link 10 includes a plurality of inverter units 11 connected in series, a first adjustment link 12 and a second adjustment link 13. The first adjustment link 12 and the second adjustment link 13 are both coupled to the same intermediate node of the duty cycle adjustment link 10 and are based on the control code code <n:1>The detection signal adjusts the slope of the rising or falling edge of the intermediate clock signal generated by the same intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT, and the intermediate node is the connection point between the two inverter units 11. Through the above method, the first adjustment chain 12 and the second adjustment chain 13 of the present application can be coupled to the same intermediate node of the duty cycle adjustment chain 10, eliminating the need to adjust the duty cycle of the output clock signal CLKOUT separately at the two intermediate nodes of the duty cycle adjustment chain 10. This can reduce the number of inverter units 11 connected in series in the duty cycle adjustment chain 10, thereby reducing the delay of the duty cycle adjustment circuit 100 and the delay of the delay-locked loop path.

[0036] Optionally, based on the above embodiment, please refer to Figure 2 , Figure 2 FIG is a schematic diagram of the second embodiment of the duty cycle adjustment circuit provided by this application. Figure 2 As shown, the duty cycle adjustment circuit 100 further includes a bias voltage generating module 40, which is coupled to the state machine 30, the first adjustment link 12 and the second adjustment link 13 respectively, and is used to adjust the duty cycle based on the control code code <n:1>Generate a corresponding bias voltage and provide it to the first regulation link 12 and the second regulation link 13; wherein the first regulation link 12 and the second regulation link 13 adjust the pull-down current or pull-up current of the same intermediate node in the duty cycle regulation link 10 based on the detection signal and the bias voltage, so as to adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node, thereby adjusting the duty cycle of the output clock signal CLKOUT.

[0037] In this embodiment, the bias voltage generating module 40 can be a voltage generating module, which provides the first bias voltage and the second bias voltage for the first regulation link 12 and the second regulation link 13 respectively; in other embodiments, the bias voltage generating module 40 can also be set as two voltage generating modules, which provide the first bias voltage and the second bias voltage for the first regulation link 12 and the second regulation link 13 respectively, which is not limited here.

[0038] Optionally, based on the above embodiments, in this embodiment, in response to the intermediate clock signal being in phase with the initial clock signal CLKIN, the first adjustment link 12 is used to narrow the duty cycle of the output clock signal CLKOUT based on the first bias voltage and the detection signal; the second adjustment link 13 is used to increase the duty cycle of the output clock signal CLKOUT based on the second bias voltage and the detection signal; in response to the intermediate clock signal being out of phase with the initial clock signal CLKIN, the first adjustment link 12 is used to increase the duty cycle of the output clock signal CLKOUT based on the first bias voltage and the detection signal; the second adjustment link 13 is used to narrow the duty cycle of the output clock signal CLKOUT based on the second bias voltage and the detection signal.

[0039] Optionally, based on the above embodiment, please refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram of an embodiment of a duty cycle adjustment link provided by the present application. In this embodiment, as described above, the bias voltage includes a first bias voltage and a second bias voltage. Figure 3 As shown, the first regulation link 12 of this embodiment includes a first transmission gate branch 121 and a discharge branch 122. The first transmission gate branch 121 receives a detection signal and a first bias voltage, and is used to control the conduction or shutoff of the discharge branch 122 based on the detection signal and the first bias voltage; the discharge branch 122 is coupled to the first transmission gate branch 121 and the intermediate node. In response to the discharge branch 122 being turned on, the discharge branch 122 performs a discharge operation on the intermediate node to adjust the slope of the rising edge of the intermediate clock signal.

[0040] Optionally, based on the above embodiment, as Figure 3 As shown, the first transmission gate branch 121 of this embodiment includes a first transmission gate TG1 and a first transistor M1. The input terminal of the first transmission gate TG1 receives a first bias voltage, the first control terminal of the first transmission gate TG1 receives a detection signal, and the second control terminal of the first transmission gate TG1 receives an inverted detection signal. The first pass terminal of the first transistor M1 is grounded, and the second pass terminal of the first transistor M1 is coupled to the output terminal of the first transmission gate TG1 and the discharge branch 122. The control terminal of the first transistor M1 receives the inverted detection signal. The discharge branch 122 includes a second transistor M2 and a third transistor M3. The control terminal of the second transistor M2 is coupled to the output terminal of the first transmission gate TG1 and the second pass terminal of the first transistor M1. The first pass terminal of the second transistor M2 is coupled to the input terminal of the inverter unit 11 in the stage following the intermediate node. The control terminal of the third transistor M3 is coupled to the output terminal of the inverter unit 11 in the stage following the intermediate node. The first pass terminal of the third transistor M3 is coupled to the second pass terminal of the second transistor M2, and the second pass terminal of the third transistor M3 is grounded.

[0041] When the detection signal is at a high level, the first transmission gate TG1 is turned on and the first transistor M1 is turned off. The control terminal of the second transistor M2 receives the first bias voltage, the second transistor M2 and the third transistor M3 are turned on, and a corresponding pull-down current is generated between the second transistor M2 and the third transistor M3. A discharge operation is performed on the intermediate clock signal to adjust the slope of the rising edge of the intermediate clock signal.

[0042] For example, Figure 3 As shown, the first transistor M1, the second transistor M2, and the third transistor M3 in the first regulation chain 12 are all NMOS transistors. The intermediate clock signal CLK1 at the intermediate node to which the first regulation chain 12 and the second regulation chain 13 are coupled is in phase with the initial clock signal CLKIN. The first control terminal of the first transmission gate TG1 is the gate of the NMOS transistor in the first transmission gate TG1, and the second control terminal of the first transmission gate TG1 is the gate of the PMOS transistor in the first transmission gate TG1. In this case, the first regulation chain 12 is used to narrow the duty cycle of the output clock signal CLKOUT based on the first bias voltage and the detection signal.

[0043] The working principle of the first regulation link 12 for narrowing the duty cycle of the output clock signal CLKOUT is as follows:

[0044] The input terminal of the first transmission gate TG1 receives the first bias voltage, the first control terminal of the first transmission gate TG1 receives the detection signal VSEL, and the second control terminal of the first transmission gate TG1 and the control terminal of the first transistor M1 receive the inverted detection signal VSELB. If the detection signal output by the duty cycle detector 20 is high, indicating that the duty cycle of the output clock signal CLKOUT is greater than 50%, the detection signal VSEL is also high, and the inverted detection signal VSELB is low. At this time, the first transmission gate TG1 is turned on, and the first transistor M1 in the first regulation chain 12 is turned off. The first transmission gate TG1 then transmits the first bias voltage to the control terminal of the second transistor M2. At this time, the discharge branch 122 is operative, and the second transistor M2 is turned on.

[0045] In this embodiment, since the control terminal of the third transistor M3 is coupled to the output terminal of the inverter unit 11 at a stage subsequent to the intermediate node, the control terminal of the third transistor M3 receives the inverted intermediate clock signal CLK1B.

[0046] See also Figure 4 , Figure 4 This is a waveform diagram of the intermediate clock signal adjustment process. Figure 4 As shown, when the intermediate clock signal CLK1 is at a rising edge, the inverted intermediate clock signal CLK1B remains at a high level. At this time, the second transistor M2 and the third transistor M3 are both in the on state. As the voltage at the node corresponding to the intermediate clock signal CLK1 increases, the second transistor M2 and the third transistor M3 generate a pull-down current I1, slowing the rise speed of the node corresponding to the intermediate clock signal CLK1. When the intermediate clock signal CLK1 rises to the flip point of the inverter unit 11 one stage after the intermediate node, the inverted intermediate clock signal CLK1B begins to change from high to low. When the inverted intermediate clock signal CLK1B falls below the control terminal threshold voltage of the third transistor M3, the third transistor M3 turns off, and I1 gradually decreases to 0. After I1 = 0, the intermediate clock signal CLK1 continues to be driven by the inverter unit 11 of the previous stage, and its voltage is quickly pulled up to the power supply voltage. After being shaped by the inverter unit 11 in the subsequent chain, the duty cycle of the output clock signal CLKOUT is narrowed. It can be seen that during the adjustment process, the higher the first bias voltage is, the larger the pull-down current I1 is, the slower the rising speed of the intermediate clock signal CLK1 is, and the more the duty cycle of the output clock signal CLKOUT is narrowed.

[0047] In other embodiments, if the intermediate clock signal CLK1 of the intermediate node coupled to the first regulation chain 12 and the second regulation chain 13 is in anti-phase with the initial clock signal CLKIN, the first regulation chain 12 is used to increase the duty cycle of the output clock signal CLKOUT.

[0048] Optionally, based on the above embodiment, in this embodiment, the bias voltage includes a first bias voltage and a second bias voltage. Figure 3 As shown, the second regulation link 13 includes a second transmission gate branch 131 and a charging branch 132. The second transmission gate branch 131 receives a detection signal and a second bias voltage, and is used to control the conduction or shutoff of the charging branch 132 based on the detection signal and the second bias voltage; the charging branch 132 is coupled to the second transmission gate branch 131 and the intermediate node. In response to the charging branch 132 being turned on, the charging branch 132 performs a charging operation on the intermediate node to adjust the slope of the falling edge of the intermediate clock signal.

[0049] Alternatively, as Figure 3 As shown, the second transmission gate branch 131 of this embodiment includes a second transmission gate TG2 and a fourth transistor M4. The input terminal of the second transmission gate TG2 receives the second bias voltage, the first control terminal of the second transmission gate TG2 receives the inverted detection signal, and the second control terminal of the second transmission gate TG2 receives the detection signal. The first pass terminal of the fourth transistor M4 receives a predetermined voltage, and the second pass terminal of the fourth transistor M4 is coupled to the output terminal of the second transmission gate TG2 and the charging branch 132. The control terminal of the fourth transistor M4 receives the inverted detection signal. The charging branch 132 includes a fifth transistor M5 and a sixth transistor M6. The control terminal of the fifth transistor M5 is coupled to the output terminal of the second transmission gate TG2 and the second pass terminal of the fourth transistor M4. The first pass terminal of the fifth transistor M5 is coupled to the input terminal of the inverter unit 11 in the stage following the intermediate node. The control terminal of the sixth transistor M6 is coupled to the output terminal of the inverter unit 11 in the stage following the intermediate node. The first pass terminal of the sixth transistor M6 is coupled to the second pass terminal of the fifth transistor M5, and the second pass terminal of the sixth transistor M6 receives the predetermined voltage.

[0050] When the detection signal is at a low level, the second transmission gate TG2 is turned on and the fourth transistor M4 is turned off. The control terminal of the fifth transistor M5 receives the second bias voltage, the fifth transistor M5 and the sixth transistor M6 are turned on, and a corresponding pull-up current is generated between the fifth transistor M5 and the sixth transistor M6. The intermediate clock signal is charged to adjust the slope of the falling edge of the intermediate clock signal.

[0051] Based on the above, if Figure 3 As shown, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 in the second regulation chain 13 are all PMOS transistors. The intermediate clock signal CLK1 at the intermediate node to which the first regulation chain 12 and the second regulation chain 13 are coupled is in phase with the initial clock signal CLKIN. The first control terminal of the second transmission gate TG2 is the gate of the NMOS transistor in the second transmission gate TG2, and the second control terminal of the second transmission gate TG2 is the gate of the PMOS transistor in the second transmission gate TG2. In this case, the second regulation chain 13 is used to increase the duty cycle of the output clock signal CLKOUT based on the second bias voltage and the detection signal.

[0052] The working principle of the second regulation link 13 for increasing the duty cycle of the output clock signal CLKOUT is similar to that of the first regulation link 12 , and the specific working principle is as follows:

[0053] The input terminal of the second transmission gate TG2 receives the second bias voltage. The first control terminal of the second transmission gate TG2 and the control terminal of the fourth transistor M4 receive the inverted detection signal VSELB. The second control terminal of the second transmission gate TG2 receives the detection signal VSEL. If the detection signal output by the duty cycle detector 20 is low, indicating that the duty cycle of the output clock signal CLKOUT is less than 50%, the detection signal VSEL is low and the inverted detection signal VSELB is high. In this case, the second transmission gate TG2 is turned on, the fourth transistor M4 is turned off, and the charging branch 132 is operated. At this time, the second transmission gate TG2 transmits the second bias voltage to the control terminal of the fifth transistor M5, which is now in the on state.

[0054] In this embodiment, since the control terminal of the sixth transistor M6 is also coupled to the output terminal of the inverter unit 11 at a stage subsequent to the intermediate node, the control terminal of the sixth transistor M6 also receives the inverted intermediate clock signal CLK1B.

[0055] Similarly, when the intermediate clock signal CLK1 is at a falling edge, the inverted intermediate clock signal CLK1B remains at a low level. At this time, both the fifth transistor M5 and the sixth transistor M6 are in the on state. Since the second channel terminal of the sixth transistor M6 receives a predetermined voltage, as the voltage at the node corresponding to the intermediate clock signal CLK1 decreases, the fifth transistor M5 and the sixth transistor M6 generate a pull-up current I2, slowing the falling speed of the node corresponding to the intermediate clock signal CLK1. When the intermediate clock signal CLK1 falls to the flip point of the inverter unit 11 one stage after the intermediate node, the inverted intermediate clock signal CLK1B begins to rise from low to high. When the inverted intermediate clock signal CLK1B rises above the control terminal threshold voltage of the sixth transistor M6, the sixth transistor M6 turns off, and I2 gradually decreases to 0. When I2 = 0, the intermediate clock signal CLK1 continues to be driven by the inverter unit 11 of the previous stage, and its voltage is quickly pulled down to ground. After being shaped by the inverter units 11 in the subsequent chain, the duty cycle of the output clock signal CLKOUT is increased. It can be seen that during the adjustment process, the lower the second bias voltage is, the larger the pull-up current I2 is, the slower the falling speed of the intermediate clock signal CLK1 is, and the more the duty cycle of the output clock signal CLKOUT is increased.

[0056] In other embodiments, if the intermediate clock signal CLK1 of the intermediate node coupled to the first regulation chain 12 and the second regulation chain 13 is in anti-phase with the initial clock signal CLKIN, the second regulation chain 13 is used to narrow the duty cycle of the output clock signal CLKOUT.

[0057] Optionally, see Figure 5 , Figure 5 FIG. 1 is a schematic diagram of the circuit structure of the first embodiment of the bias voltage generating module provided by this application. Figure 5 As shown, the bias voltage generating module 40 of this embodiment includes a bias current generating module 401 and a current mirror module 402; the bias current generating module 401 includes a plurality of bias current branches connected in parallel, and based on the control code code <n:1>The number of bias current branches connected is adjusted to generate a corresponding bias current. The current mirror module 402 is coupled to the bias current generating module 401 to generate a first bias voltage and a second bias voltage based on the bias current, wherein the first bias voltage and the second bias voltage make the pull-down current or the pull-up current of the intermediate node the same.

[0058] In this embodiment, the first bias voltage and the second bias voltage generated by the current mirror module 402 can ensure that the pull-down current of the discharge branch 122 in the first regulation link 12 and the pull-up current of the charging branch 132 in the second regulation link 13 are the same, thereby ensuring that the first regulation link 12 and the second regulation link 13 have the same range of increase and decrease of the duty cycle of the output clock signal CLKOUT.

[0059] Alternatively, as Figure 5 As shown, the current mirror module 402 of this embodiment includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a first capacitor C1. A first channel terminal of the seventh transistor M7 is connected to the output terminal of the bias current generating module 401 and coupled to the control terminal of the seventh transistor M7. A second channel terminal of the seventh transistor M7 is grounded, and the control terminal of the seventh transistor M7 is also used to output a first bias voltage. A control terminal of the eighth transistor M8 is connected to the control terminal of the seventh transistor M7. A first channel terminal of the eighth transistor M8 is connected to the second channel terminal of the ninth transistor M9. The second channel terminal of the eighth transistor M8 is grounded. A first channel terminal of the ninth transistor M9 receives the first operating voltage VCC1. A control terminal of the ninth transistor M9 is coupled to the second channel terminal of the ninth transistor M9 and is used to output a second bias voltage. A first terminal of the first capacitor C1 is grounded, and a second terminal of the first capacitor C1 is coupled to the control terminal of the seventh transistor M7 and the control terminal of the eighth transistor M8, respectively.

[0060] In this embodiment, the seventh transistor M7 can be configured as an NMOS transistor, and the first bias voltage is the gate voltage of the seventh transistor M7. The ninth transistor M9 can be configured as a PMOS transistor, and the second bias voltage is the gate voltage of the ninth transistor M9. In this embodiment, the generated first bias voltage and the second bias voltage may be different.

[0061] Alternatively, as Figure 5 As shown, each bias current branch in the bias current generating module 401 of this embodiment includes a tenth transistor MPn (n=1, 2, 3, ..., n) and a switch Tn (n=1, 2, 3, ..., n). The control terminal of the tenth transistor MPN receives the reference voltage Vref, and the first channel terminal of the tenth transistor MPn receives the second working voltage VCC2. The first terminal of the switch Tn is coupled to the second channel terminal of the tenth transistor MPn, and the second terminal of the switch Tn is coupled to the bias current output module. The control terminal of the switch Tn is used to receive the control code code. <n:1>, based on the control code code <n:1>The control determines whether the corresponding bias current branch is turned on.

[0062] In this embodiment, the ratio of the sizes of the plurality of tenth transistors MPn included in the bias current branch is 1, 2, 4, 8 ... 2^(N-1) in sequence, where N is the number of bias current branches, so that based on the control code code <n:1>The bias current is adjusted with a precision continuous within the range of 0 to (2^N-1)*I0, where I0 is the bias current provided by the tenth transistor MPn of the unit size. Figure 5 MP1 in.

[0063] For example, Figure 5 As shown, the size of the tenth transistor MP1 is unit size, and the bias current it provides is I0. The size of the tenth transistor MP2 is 2*unit size, and the bias current it provides is 2I0. The size of the tenth transistor MP3 is 4*unit size, and the bias current it provides is 4I0. By analogy, the size of the tenth transistor MP4 is 8*unit size, and the bias current it provides is 8I0. By analogy, the size of the tenth transistor MPn is 2^(N-1)*unit size, and the bias current it provides is 2^(N-1)*I0. If the control code code <n:1>If the control code is all 0, the tenth transistor MPn is all turned off and the bias current provided is 0; <n:1>If all 1s are on, the tenth transistor MPn is fully turned on, and the bias current provided is the sum of N bias currents, that is, (2^N-1)*I0. That is to say, in this embodiment, by controlling the number of conductive bias current branches, the bias current can be accurately and continuously adjusted in the range of 0, I0, 2I0, 3I0...(2^N-1)*I0, that is, the bias voltage can be accurately and continuously adjusted, so that the duty cycle of the clock signal can be accurately adjusted.

[0064] In other embodiments, when the control code code <n:1>When the temperature code format changes, the size of the tenth transistor MPn of each bias current branch in the above embodiment may also be the same, which is not limited here.

[0065] Optionally, see Figure 6 , Figure 6 FIG. 1 is a circuit diagram of the second embodiment of the duty cycle adjustment circuit provided by the present application. Figure 6 As shown, in this embodiment, the bias voltage generating module 40 includes a first bias voltage generating module 41 and a second bias voltage generating module 42, wherein the first bias voltage generating module 41 is used to generate a first bias voltage, and the second bias voltage generating module 42 is used to generate a second bias voltage, wherein the first bias voltage and the second bias voltage make the pull-down current or the pull-up current of the intermediate node the same.

[0066] In this example, see Figure 7 , Figure 7 FIG. 1 is a structural diagram of an embodiment of a first bias voltage generating module provided by the present application. Figure 7 As shown, the first bias voltage generating module 41 of this embodiment includes a bias current generating module 401 and a voltage generating submodule 411 .

[0067] The bias current generating module 401 includes a plurality of bias current branches connected in parallel and is based on the control code code <n:1>The conduction quantity of the bias current branch is adjusted to generate a corresponding bias current. The bias voltage generating module 40 is coupled to the bias current generating module 401 to generate and output a bias voltage based on the bias current.

[0068] Among them, the bias current generating module 401 and Figure 5 The bias current generating module 401 in the embodiments is the same and will not be described again here.

[0069] like Figure 7 As shown, the voltage generating submodule 411 includes an eleventh transistor M11 and a second capacitor C2. The first channel end of the eleventh transistor M11 is coupled to the output end of the bias current generating module 401 and the control end of the eleventh transistor M11, respectively. The second channel end of the eleventh transistor M11 is grounded. The control end of the eleventh transistor M11 serves as the output end of the first bias voltage generating module 41 to output the first bias voltage. The first end of the second capacitor C2 is grounded, and the second end of the second capacitor C2 is coupled to the control end of the eleventh transistor M11. The second capacitor C2 is used to filter out glitches in the first bias voltage generating module 41.

[0070] exist Figure 6 and Figure 7 In the embodiment, the size ratio of the tenth transistor MPm (n=1, 2, ... N) in the bias current branch can be set to conform to the binary weight. When the control terminal of the tenth transistor MPn receives the reference voltage Vref, the tenth transistor MPn is turned on. At this time, if the control code code <n:1>When the switch Tn of a branch is closed, a branch current will be generated on the branch based on the reference voltage Vref. <n:1>The number of bias current branches in the bias current generating module 401 that are turned on is controlled, thereby controlling the bias current generating module 401 to generate a corresponding bias current.

[0071] The structure of the second bias voltage generating module 42 can be the same as Figure 5 The structure of the bias voltage generating module 40 shown is the same, and it is only necessary to use the control end of the ninth transistor M9 in the current mirror module 402 as the output end of the second bias voltage generating module 42 to output the second bias voltage. In other embodiments, the second bias voltage generating module 42 can also be other circuit structures, as long as the generated second bias voltage is the same as the first bias voltage and the pull-down current or pull-up current of the intermediate node is the same, and no limitation is made here.

[0072] Optionally, this application further proposes a memory, see Figure 8 , Figure 8 Schematic diagram of the structure of a memory device according to the present application. Figure 8 As shown, the memory 200 of this embodiment includes the duty cycle adjustment circuit 100 of any one of the above embodiments.

[0073] In this embodiment, the memory 200 may be a random access memory (DRAM), a static random access memory (SRAM), or a pseudo static random access memory (Pseudo SRAM, PSRAM), which is not limited here.

[0074] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made according to the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A duty cycle adjustment circuit, characterized in that: include: A duty cycle adjustment link receives an initial clock signal and adjusts the initial clock signal to generate an output clock signal; a duty cycle detector coupled to the duty cycle adjustment link to generate a corresponding detection signal based on the detected duty cycle of the output clock signal; a state machine coupled to the duty cycle detector to generate a corresponding control code based on the detection signal; The duty cycle adjustment link includes a plurality of inverter units connected in series, a first adjustment link, and a second adjustment link. The first adjustment link and the second adjustment link are both coupled to the same intermediate node of the duty cycle adjustment link, and adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the same intermediate node based on the control code and the detection signal, thereby adjusting the duty cycle of the output clock signal. The intermediate node is a connection point between two inverter units. a bias voltage generating module, coupled to the state machine, the first regulation link, and the second regulation link, respectively, for generating a corresponding bias voltage based on the control code and providing the bias voltage to the first regulation link and the second regulation link; The bias voltage includes a first bias voltage and a second bias voltage; the first regulation link includes a first transmission gate branch and a discharge branch, the first transmission gate branch including a first transmission gate and a first transistor, an input terminal of the first transmission gate receiving the first bias voltage, a first control terminal of the first transmission gate receiving the detection signal, and a second control terminal of the first transmission gate receiving an inverted detection signal; a first pass terminal of the first transistor is grounded, a second pass terminal of the first transistor is coupled to an output terminal of the first transmission gate and the discharge branch; a control terminal of the first transistor receives the inverted detection signal; wherein, when the detection signal is at a high level, the first transmission gate is turned on and the first transistor is turned off, controlling the discharge branch to conduct and generate a corresponding pull-down current, thereby performing a discharge operation on the intermediate clock signal to adjust the slope of the rising edge of the intermediate clock signal; The second regulation link includes a second transmission gate branch and a charging branch. The second transmission gate branch includes a second transmission gate and a fourth transistor. The input end of the second transmission gate receives the second bias voltage, the first control end of the second transmission gate receives the inverted detection signal, and the second control end of the second transmission gate receives the detection signal. The first pass end of the fourth transistor receives a preset voltage, and the second pass end of the fourth transistor is coupled to the output end of the second transmission gate and the charging branch. The control end of the fourth transistor receives the inverted detection signal. When the detection signal is at a low level, the second transmission gate is turned on and the fourth transistor is turned off, controlling the charging branch to conduct and generate a corresponding pull-up current, thereby performing a charging operation on the intermediate clock signal to adjust the slope of the falling edge of the intermediate clock signal.

2. The duty cycle adjustment circuit according to claim 1, wherein: The discharge branch comprises: a second transistor, wherein a control terminal of the second transistor is coupled to the output terminal of the first transmission gate and the second pass terminal of the first transistor, and a first pass terminal of the second transistor is coupled to the input terminal of the inverter unit at a stage subsequent to the intermediate node; a third transistor, wherein a control terminal of the third transistor is coupled to the output terminal of the inverter unit at a stage subsequent to the intermediate node, a first pass terminal of the third transistor is coupled to the second pass terminal of the second transistor, and a second pass terminal of the third transistor is grounded; When the detection signal is at a high level, the first transmission gate is turned on and the first transistor is turned off, the control end of the second transistor receives the first bias voltage, the second transistor and the third transistor are turned on, a corresponding pull-down current is generated between the second transistor and the third transistor, and a discharge operation is performed on the intermediate clock signal to adjust the slope of the rising edge of the intermediate clock signal.

3. The duty cycle adjustment circuit according to claim 1, wherein: The charging branch includes: a fifth transistor, wherein a control terminal of the fifth transistor is coupled to the output terminal of the second transmission gate and the second pass terminal of the fourth transistor, and a first pass terminal of the fifth transistor is coupled to the input terminal of the inverter unit at a stage subsequent to the intermediate node. a sixth transistor, wherein a control terminal of the sixth transistor is coupled to the output terminal of the inverter unit at a stage subsequent to the intermediate node, a first pass terminal of the sixth transistor is coupled to the second pass terminal of the fifth transistor, and a second pass terminal of the sixth transistor receives the preset voltage; When the detection signal is at a low level, the second transmission gate is turned on and the fourth transistor is turned off, the control end of the fifth transistor receives the second bias voltage, the fifth transistor and the sixth transistor are turned on, and a corresponding pull-up current is generated between the fifth transistor and the sixth transistor, performing a charging operation on the intermediate clock signal to adjust the slope of the falling edge of the intermediate clock signal.

4. The duty cycle adjustment circuit according to claim 1, wherein: In response to the intermediate clock signal being in phase with the initial clock signal, the first regulation chain is configured to narrow a duty cycle of the output clock signal based on the first bias voltage and the detection signal; The second regulation link is used to increase the duty cycle of the output clock signal based on the second bias voltage and the detection signal; In response to the intermediate clock signal being in phase opposition with the initial clock signal, the first regulation link is configured to increase a duty cycle of the output clock signal based on the first bias voltage and the detection signal; The second regulation link is used to narrow the duty cycle of the output clock signal based on the second bias voltage and the detection signal.

5. The duty cycle adjustment circuit according to claim 1, wherein: The bias voltage generating module includes a bias current generating module and a current mirror module; The bias current generating module includes a plurality of bias current branches connected in parallel, and adjusts the number of the bias current branches connected based on the control code to generate a corresponding bias current. The current mirror module is coupled to the bias current generating module to generate a first bias voltage and a second bias voltage based on the bias current. The first bias voltage and the second bias voltage make the pull-down current or the pull-up current of the intermediate node the same.

6. The duty cycle adjustment circuit according to claim 5, wherein: The current mirror module includes a seventh transistor, an eighth transistor, a ninth transistor and a first capacitor; wherein the first channel terminal of the seventh transistor is connected to the output terminal of the bias current generating module and coupled to the control terminal of the seventh transistor, the second channel terminal of the seventh transistor is grounded, and the control terminal of the seventh transistor is further used to output the first bias voltage; The control terminal of the eighth transistor is connected to the control terminal of the seventh transistor, the first pass terminal of the eighth transistor is connected to the second pass terminal of the ninth transistor, and the second pass terminal of the eighth transistor is grounded; The first pass terminal of the ninth transistor receives the first operating voltage, the control terminal of the ninth transistor is coupled to the second pass terminal of the ninth transistor, and is used to output the second bias voltage; A first terminal of the first capacitor is grounded, and a second terminal of the first capacitor is coupled to the control terminal of the seventh transistor and the control terminal of the eighth transistor respectively.

7. The duty cycle adjustment circuit according to claim 5, wherein: Each of the bias current branches in the bias current generating module comprises: a tenth transistor, wherein a control terminal of the tenth transistor receives a reference voltage, and a first pass terminal of the tenth transistor receives a second operating voltage; A switch, wherein a first end of the switch is coupled to the second path end of the tenth transistor, a second end of the switch is coupled to the bias current output module, and a control end of the switch is used to receive the control code to determine whether the corresponding bias current branch is turned on based on the control of the control code.

8. The duty cycle adjustment circuit according to claim 1, wherein: The bias voltage generating module includes a first bias voltage generating module and a second bias voltage generating module. The first bias voltage generating module is used to generate a first bias voltage, and the second bias voltage generating module is used to generate a second bias voltage. The first bias voltage and the second bias voltage make the pull-down current or the pull-up current of the intermediate node the same.

9. A memory, characterized in that: The invention comprises the duty cycle adjustment circuit according to any one of claims 1 to 8.

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