Delay locked loop

Abstract

A delay locked loop circuit includes a voltage controlled delay line that applies a time delay to a clock input signal to provide a first output signal and a last output signal, the magnitude of the time delay being based on a control voltage signal and a delay code. The DLL circuit also includes a feedback circuit configured to provide a feedback voltage signal based on a phase difference between the first output signal and the last output signal. When the delay locked loop circuit is in a calibration mode of operation: the fixed voltage source provides a fixed voltage signal as a control voltage signal for the VCDL; the delay code setter applies a delay code setting signal to the VCDL such that the delay code setter applies a series of different candidate delay codes to the VCDL in order to identify a selected delay code as a code that produces a predetermined phase difference between the first output signal and the last output signal. When the delay locked loop circuit is in an active operation mode: the feedback circuit provides a feedback voltage signal as a control voltage signal of the VCDL; the VCDL uses a selected delay code as a delay code.

Description

Technical Field

[0001] The present disclosure relates to delay locked loop circuits. Background Art

[0002] A delay locked loop (DLL) circuit includes a delay chain that applies a time delay to an input clock signal. The DLL circuit also includes a feedback circuit that phase locks a final output signal to the input clock signal so that it is delayed by 2Π radians with respect to the input clock signal. The feedback circuit may include a phase detector and a charge pump. The delay chain may include a VCDL (voltage controlled delay line). The magnitude of the time delay applied by the VCDL is affected by a control voltage signal. The VCDL may have a limited acceptable control voltage range due to limitations associated with the supply voltage and the overdrive voltage of the charge pump. Therefore, if the control voltage (vcntrl) of the DLL exceeds the safe specified range, the DLL will be locked with an incorrect phase alignment. That is, the final output signal of the DLL will not be delayed by 2Π radians with respect to the input reference clock of the DLL. Summary of the invention

[0003] According to a first aspect of the present disclosure, a delay locked loop circuit is provided, comprising:

[0004] A voltage controlled delay line comprising one or more variable components, wherein the voltage controlled delay line is configured to:

[0005] Receive a clock-in signal;

[0006] receiving a control voltage signal; and

[0007] applying a time delay to the clock input signal to provide a first output signal and a final output signal, wherein a magnitude of the time delay is based on the control voltage signal and a delay code, and wherein the delay code defines a value of the one or more variable components in the voltage-controlled delay line;

[0008] a feedback circuit configured to provide a feedback voltage signal based on a phase difference between the first output signal and the last output signal;

[0009] a delay code setter configured to provide a delay code setting signal representing one of a series of different candidate delay codes;

[0010] a fixed voltage source configured to provide a fixed voltage signal; and

[0011] a switch circuit configured to place the delay locked loop circuit into an active operating mode or a calibration operating mode, wherein:

[0012] When the delay locked loop circuit is in the calibration operation mode:

[0013] The fixed voltage source is configured to provide the fixed voltage signal as the control voltage signal of the voltage-controlled delay line; and

[0014] the delay code setter being configured to apply the delay code setting signal to the voltage-controlled delay line, so that the delay code setter applies one or more of the series of different candidate delay codes to the voltage-controlled delay line so as to determine a candidate delay code that produces a predetermined phase difference between the first output signal and the final output signal, and to designate the candidate delay code as a selected delay code;

[0015] When the delay locked loop circuit is in the active operating mode:

[0016] The feedback circuit is configured to provide the feedback voltage signal as the control voltage signal of the voltage-controlled delay line; and

[0017] The voltage-controlled delay line is configured to use the selected delay code as the delay code.

[0018] <Insert exact text of independent claim 1>.

[0019] Advantageously, such a delay locked loop circuit can provide accurate calibration of the control voltage signal by setting the delay code during the calibration mode of operation. During the subsequent active mode of operation, the control voltage signal can be limited within the process, voltage, temperature (PVT) variation range, thereby being more likely to remain within an acceptable value range.

[0020] In one or more embodiments, the voltage-controlled delay line includes a plurality of buffers connected in series.

[0021] In one or more embodiments, at least one of the variable components of the voltage controlled delay line is associated with each of the plurality of buffers.

[0022] In one or more embodiments, the fixed voltage signal has a value in the middle of a range of voltage values ​​that enable the DLL circuit to operate properly.

[0023] In one or more embodiments, the fixed voltage signal has a value equal to half of a supply voltage of the DLL circuit.

[0024] In one or more embodiments, the fixed voltage source includes a potentiometer configured to receive a calibration voltage control signal. The potentiometer can be used to tap a voltage based on the calibration voltage control signal to provide the fixed voltage signal.

[0025] In one or more embodiments, when the delay locked loop circuit is in the active operating mode, the predetermined phase difference corresponds to a phase difference of 2Π radians.

[0026] In one or more embodiments, the switch circuit includes a control voltage connection switch configured to provide the fixed voltage signal or the feedback voltage signal as the control voltage signal of the voltage-controlled delay line.

[0027] In one or more embodiments, the delay locked loop circuit further includes a clock signal generator, wherein the clock signal generator is configured to:

[0028] When the delay locked loop circuit is in the calibration operation mode, providing a calibration clock signal as the clock input signal of the voltage controlled delay line; and

[0029] providing an active clock signal as the clock input signal of the voltage-controlled delay line when the delay-locked loop circuit is in the active operating mode;

[0030] The calibration clock signal and the active clock signal have different frequencies.

[0031] In one or more embodiments, the frequency of the calibration clock signal is half the frequency of the active clock signal.

[0032] In one or more embodiments, when the delay locked loop circuit is in the calibration operation mode:

[0033] The delay code setter is configured as follows:

[0034] applying the delay code setting signal to the voltage-controlled delay line so that the delay code setter applies a plurality of the series of different candidate delay codes to the voltage-controlled delay line to determine the candidate delay code that produces a predetermined phase difference of π radians between the first output signal (PH0) and the final output signal (PHN); and

[0035] The candidate delay code is assigned as the selected delay code.

[0036] In one or more embodiments, the delay locked loop circuit further comprises a phase comparator, and wherein when the delay locked loop circuit is in the calibration operation mode:

[0037] The phase comparator is configured to compare the phase of the first output signal with the phase of the last output signal so as to provide a lock signal indicating whether the phase difference between the first output signal and the last output signal is the predetermined phase difference; and

[0038] The delay code setter is configured to determine the selected delay code based on the lock signal.

[0039] In one or more embodiments, the feedback circuit includes a phase detector and a charge pump.

[0040] In one or more embodiments, when the delay locked loop circuit is in the calibration operation mode, the delay locked loop circuit is configured to operate in an open loop operation mode.

[0041] In one or more embodiments, when the delay locked loop circuit is in the active operating mode, the delay locked loop circuit is configured to operate in a closed loop operating mode.

[0042] Although the details of the present disclosure have been shown in the accompanying drawings by way of example and will be described in detail, the present disclosure is applicable to various modifications and alternative forms. However, it should be understood that, in addition to the specific embodiments described, other embodiments are also possible. All modifications, equivalents and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0043] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future claim sets. The following figures and detailed description also illustrate various example embodiments. Various example embodiments may be more fully understood by considering the following detailed description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0045] Figure 1 An example embodiment of a delay locked loop (DLL) circuit according to the present disclosure is shown;

[0046] Figure 2 Another example of a DLL circuit according to the present disclosure is shown;

[0047] Figure 3 Shown will be used to describe Figure 2 Flowchart of the functions of the delay code setter and the D-type flip-flop;

[0048] Figure 4 Show further instructions Figure 3 A timing diagram of the function of the flowchart;

[0049] Figure 5 a graph showing candidate delayed codes on the horizontal axis versus time delay on the vertical axis;

[0050] Figure 6 Show that it can be Figure 2A flow chart of a calibration sequence performed by a DLL circuit; and

[0051] Figure 7 The following figure will be used to describe the calibrated DLL circuit when it is in the active operating mode. Figure 6 The timing diagram of the function after the last step of the flowchart. DETAILED DESCRIPTION

[0052] Figure 1 An example embodiment of a delay locked loop (DLL) circuit 100 according to the present disclosure is shown. As will be discussed below, the DLL circuit 100 can be in an active operating mode or a calibration operating mode. In the calibration operating mode, the voltage controlled delay line (VCDL) 101 is calibrated so that the control voltage signal 103 applied to the VCDL 101 when the DLL circuit 100 is in the active operating mode is expected to have a value that reduces the likelihood that it exceeds an acceptable value range, which would result in incorrect operation of the DLL circuit 100. For example, the VCDL 101 can be calibrated so that the control voltage signal 103 is expected to have a value that is in the middle of the acceptable value range when the DLL circuit is in the active operating mode. Therefore, if any condition occurs that causes the control voltage signal 103 to increase or decrease (e.g., a change in the temperature of the DLL circuit 100), the control voltage signal 103 has the maximum margin for increase or decrease while still having a value that enables the DLL circuit 100 to apply the correct phase delay.

[0053] Now turn to Figure 1 In more detail, the VCDL 101 receives a clock input signal 102 and a control voltage signal 103. The VCDL 101 applies a time delay to the clock input signal 102 to provide a first output signal (PH <0> )104 and the final output signal (PH <n>) 105. In some examples, the first output signal (PH <0> ) 104 may be the same signal as the clock input signal 102, so that the VCDL 101 provides the first output signal (PH <0> )104. When the DLL circuit 100 is in the active operation mode, the final output signal (PH <n>)105 should be related to the first output signal (PH <0> )104 delay, so that there is a 2H arc phase difference between the signals. In addition, as for Figure 2 As will be described, VCDL 101 may also provide one or more intermediate output signals PH <1> to PH <n-1>(not shown), which are related to the first output signal (PH <0> )104The phase shift is less than 2Π radians.

[0054] The magnitude of the time delay applied by the VCDL 101 is based on the control voltage signal 103 and also on the delay code. The delay code defines the value of one or more variable components in the VCDL 101. In this way, the value of the one or more variable components affects the magnitude of the time delay applied by the VCDL 101. Figure 2 It will be described that, in one example, the variable component may be a variable capacitor, but it will be appreciated that any type of variable component that affects a time delay may be used.

[0055] The DLL circuit 100 further includes a feedback circuit 106 configured to generate a feedback signal based on the first output signal (PH <0> )104 and the final output signal (PH <n>) 105 to provide a feedback voltage signal 107. As is known in the art, and as Figure 2 As shown, the feedback circuit 106 can be implemented as a phase detector and a charge pump. The DLL circuit 100 also includes a fixed voltage source 110 that provides a fixed voltage signal 111. As will be discussed below: when the DLL circuit 100 is in the calibration operation mode, the fixed voltage signal 111 is provided as the control voltage signal 103; and when the DLL circuit 100 is in the active operation mode, the feedback voltage signal 107 is provided as the control voltage signal 103. In this way, the DLL circuit 100 is in an open-loop configuration when it is in the calibration operation mode, and in a closed-loop configuration when it is in the active operation mode.

[0056] The DLL circuit 100 further includes a delay code setter 108 that provides a delay code setting signal 109 to the VCDL 101. At any time when the DLL circuit 100 is in the calibration operation mode, the delay code setting signal 109 indicates one of a series of different candidate delay codes. The delay code setter 108 is used to calibrate the VCDL 101 when the DLL circuit 100 is in the calibration operation mode.

[0057] like Figure 1 As shown, the DLL circuit 100 further includes a switch circuit 112. The switch circuit 112 is used to place the DLL circuit 100 in an active operation mode or a calibration operation mode. Figure 1 In the embodiment, the switch circuit 112 is implemented as a single switch. However, in other examples, including Figure 2 In the example of FIG. 1 , more than one switching component (including a multiplexer) may be used to control the operating mode of the DLL circuit 100 .

[0058] When the DLL circuit 100 is in the calibration operation mode, the switch circuit 112 connects the fixed voltage source 110 to the VCDL 101. The switch circuit 112 also disconnects the feedback circuit 106 from the VCDL 101. In this way, the fixed voltage source 110 provides a fixed voltage signal 111 as the control voltage signal 103 of the VCDL 101. As will be discussed below, in one example, the fixed voltage signal 111 may have a value in the middle of a range of voltage values ​​that enable the DLL circuit 100 to operate correctly. This can be implemented by providing several voltage signals that are close to the middle of the supply voltage, such as Figure 2 The resistor divider is shown in Figure 2.

[0059] In addition, when the DLL circuit 100 is in the calibration operation mode, the delay code setter 108 applies a delay code setting signal 109 to the VCDL 101 so that it applies one or more of the series of different candidate delay codes to the VCDL to determine the delay code between the first output signal (PH <0> )104 and the final output signal (PH <n>) 105. Then, the delay code setter 108 may assign the candidate delay code as the selected delay code. In this example, the DLL circuit 100 further includes comparing the first output signal (PH <0> )104 and the final output signal (PH <n>) 105. The phase comparator 113 provides a lock signal 114 as an output signal. In this example, the phase comparator 113 sets the value of the lock signal 114 to the following value: <0> )104 phase mismatch final output signal (PH <n>)105, is set to a first value; and in the first output signal (PH <0> )104 phase matching final output signal (PH <n>In this way, the delay code setter 108 can sequentially apply multiple candidate delay codes to the VCDL 101 until a delay code that is not equal to the first output signal (PH) is found. <0> )104 and the final output signal (PH <n>)105 until a candidate delay code with a predetermined phase difference is generated between them. When the DLL circuit 100 is in the active operation mode, this predetermined phase difference corresponds to a phase difference of 2Π radians. Figure 2 Description, the predetermined phase difference in the calibration operation mode does not necessarily have to be 2Π radians.

[0060] When the DLL circuit 100 is in the active operation mode, the switch circuit 112 connects the feedback circuit 106 to the VCDL 101. The switch circuit 112 also disconnects the fixed voltage source 110 from the VCDL 101. In this way, the feedback circuit 106 provides the feedback voltage signal 107 as the control voltage signal 103 of the VCDL 101.

[0061] In addition, when the DLL circuit 100 is in the active operation mode, the VCDL 101 uses the selected delay code (i.e., the delay code determined during the calibration operation mode) as the delay code. That is, the variable components in the VCDL 101 are set so that their values ​​correspond to the delay code at the first output signal (PH) identified during the calibration operation mode. <0> )104 and the final output signal (PH <n>) 105. Then, the DLL circuit 100 can be operated in a closed-loop configuration in the active operating mode so that the value of the feedback voltage signal 107 is expected to have the same value as the fixed voltage signal 111 in order to achieve the first output signal (PH <0> )104 and the final output signal (PH <n>) 105. Then, if there are any PVT (process, voltage, temperature) variations during operation of the DLL circuit 100 in the active operating mode, the DLL circuit 100 adapts well to any associated variations in the feedback voltage signal 107 that occur due to the closed loop configuration without saturating the control of the VCDL 101.

[0062] Advantageously, Figure 1 In one example, the control voltage signal 103 may be limited within a PVT (process, voltage, temperature) variation range. In this example, this may be accomplished by calibrating the RC delay (by applying a candidate delay code) to maintain the control voltage signal at a value that is midway between the supply voltages (e.g., VDD / 2) when the feedback circuit 106 is disabled or disconnected. In other examples, the control voltage signal may be maintained at a different value that may or may not be close to VDD / 2. Such a control voltage may be provided by a resistor divider (e.g., Figure 2 ) or any bias generation voltage source. In either case, the DLL circuit 100 can change the RC delay of the VCDL 101 until the final output signal 105 of the DLL is 2π radians apart from the first output signal 104. Once the calibrated RC value is determined, the DLL circuit enters a closed-loop operation mode (referred to as the active operation mode above) using the final calibrated RC value of the VCDL 101 to lock around the fixed value of the control voltage signal used in the calibration mode, which may be VDD / 2.

[0063] Figure 2 Another example of a DLL circuit 200 according to the present disclosure is shown. Figure 1 As shown in Figure 2 Features of the DLL circuit 200 have corresponding reference numerals in the 200 series and will not necessarily be described again here. As will be discussed below, the DLL circuit 200 includes a calibration mode enable signal (Oploop_en) 222, which is set high when the DLL circuit 200 is to be in the calibration mode of operation and is set low when the DLL circuit 200 is to be in the active mode of operation. The DLL circuit 200 also generates and uses an inverted signal (Oploop_enb) 223 of the calibration mode enable signal.

[0064] In this example, VCDL 201 is implemented as a chain of N+2 delay buffers connected in series. The first buffer in the chain receives a clock input signal 202 as an input signal and provides a first output signal (PH <0> ) as its output signal. The penultimate buffer in the chain provides the final output signal (PH <n>) as its output signal. Figure 2 As shown, the variable capacitor is connected between the output terminal of each of the first to the second-to-last buffers and the ground terminal. Figure 1 In the same manner as described above, the value of the variable capacitor is set by the delay code. Thus, a variable component (in this example a variable capacitor, but it may be a variable resistor or any other suitable type of variable component) is associated with each buffer so that it helps define the magnitude of the time delay applied by each buffer in VCDL 201.

[0065] In this example, each of the first to second to last buffers provides an output signal that is a phase-shifted version of the clock input signal 202. Because each buffer applies the same amount of delay in this example, the phase of each output signal is equally shifted relative to the phase of the earlier output signal, and if the DLL circuit 200 is operating correctly, the final output signal 205 is phase-shifted by 2π radians with respect to the first output signal 204.

[0066] In this example, the feedback circuit 206 is implemented as a phase detector 215 and a charge pump 216. The phase detector 215 compares the first output signal (PH <0> )204 and the final output signal (PH <n>) 205, and according to the comparison result, it controls the charge pump 216 so that it increases or decreases the feedback voltage signal 207 provided as the output signal of the charge pump 216. In this way, when the DLL circuit 200 is in the active operation mode, the feedback voltage signal 207 is adjusted so that the first output signal (PH <0> )204 and the final output signal (PH <n>)205 are in phase with each other. Due to the time delay imposed by VCDL 201, this should mean that the final output signal (PH <n>)205 Regarding the first output signal (PH <0> )204 phase shift 2Π radians.

[0067] In this example, the fixed voltage source 210 is configurable so that the voltage level of the fixed voltage signal 211 can be set by the user. Figure 2 , the fixed voltage source 210 includes a potentiometer 227 (also referred to as a resistor divider). It should be understood that in other examples, the fixed voltage source 210 can be implemented in different ways and it can include any bias voltage design. The fixed voltage source 210 receives a calibration voltage control signal 239 that defines the desired level of the voltage of the fixed voltage signal 211. In this example, the DLL circuit 200 converts the calibration voltage control signal 239 into four binary signals 226 for controlling four corresponding switches. Each of the four switches is connected to a different node in the potentiometer 227 so that different voltage levels can be tapped and connected to the input of an operational amplifier (op-amp) 228. The operational amplifier 228 is configured as a unity gain amplifier so that the output signal of the operational amplifier 228 is the fixed voltage signal 211.

[0068] Figure 2 The DLL circuit 200 includes a control voltage connection switch 212, which is a part of a switch circuit for controlling the operation mode of the DLL circuit 200. Figure 1 In the same manner, the control voltage connection switch 212 provides the fixed voltage signal 211 or the feedback voltage signal 207 as the control voltage signal 203 of the VCDL 201 .

[0069] exist Figure 2 In the example of FIG. 1 , the DLL circuit 200 further includes a clock signal generator 217 that provides a calibration clock signal when the DLL circuit 200 is in the calibration operation mode and provides an active clock signal when the DLL circuit 200 is in the active operation mode. The calibration clock signal and the active clock signal have different frequencies. In this example, the frequency of the calibration clock signal is half the frequency of the active clock signal.

[0070] The clock signal generator 217 receives the reference clock signal 218, which is also the active clock signal in this example. When the DLL circuit 200 is in the calibration operation mode, the D-type flip-flop is enabled so that it halves the frequency of the reference clock signal 218 to provide a calibration clock signal (Refclk / 2) 220. The clock signal generator 217 also includes a multiplexer 221 (which can be considered as another component of the switching circuit). The multiplexer 221 has two input terminals: one receives the calibration clock signal (Refclk / 2) 220; and the other receives the active clock signal (Phref_clk) 218. The multiplexer 221 is controlled by an inverted signal (Oploop_enb) 223 of the calibration mode enable signal (but it can equally be controlled by the calibration mode enable signal (Oploop_en) 222) so that: when the DLL circuit 200 is in the active operation mode, the active clock signal (Phref_clk) 218 ​​is provided as the clock input signal 202 to the VCDL 201; and when the DLL circuit 200 is in the calibration operation mode, the calibration clock signal (Refclk / 2) 220 is provided as the clock input signal 202 to the VCDL 201.

[0071] We will now describe the delay code setter 208. Using a calibration clock signal (Refclk / 2) 220 with a frequency different from the frequency of the active clock signal (Phref_clk) 218 ​​can improve the delay code setter 208 to determine the first output signal (Phref_clk) when the DLL circuit is in the active operating mode. <0> )204 and the final output signal (PH <n>)205 has the ability to produce a selected delay code with a phase shift of 2Π radians.

[0072] Figure 2 The delay code setter block 208 is implemented as a resistor transistor logic (RTL) circuit. The delay code setter block 208 provides a delay code setting signal (load_cal<n:0> ) 209. In this example, the delay code setter block 208 starts with the lowest candidate delay code and gradually increases the value of the candidate delay code until it is applied to the first output signal (PH <0> )204 and the final output signal (PH <n>)205 until a code with a predetermined phase difference is generated between them.

[0073] In this example, since the frequency of the calibration clock signal (Refclk / 2) 220 is half the frequency of the active clock signal (Phref_clk) 218, the first output signal (Phref_clk) is <0> )204 and the final output signal (PH <n>) 205 will correspond to 2Π radians in the active operating mode. As will be appreciated from the following description, identifying a Π radian phase difference in the calibration mode can help to require only the D-type flip-flop 213 to compare the first output signal (PH <0> )204 and the final output signal (PH <n>) 205 without encountering any metastability issues. That is, if the DLL circuit 200 does not halve the clock frequency in the calibration mode of operation, then the delay code setter 208 may risk determining the selected delay code as a code that produces a π radian phase shift in the active mode of operation (when it should be 2π radians for correct operation).

[0074] We will now also Figure 3 Flowchart description of Figure 2 The functions of the delay code setter 208 and the D-type flip-flop 213 are as follows. Figure 3 The flowchart of FIG. 2 includes an initial step of checking whether the calibration mode enable signal (Oploop_en) 222 has a logic high value, which indicates that the DLL circuit 200 is in the calibration operation mode. If the calibration mode enable signal (Oploop_en) 222 has a logic high value, the delay code setter 208 sets the delay code setting signal (load_cal<n:0> )209 is set as the first candidate delay code to initialize it ( Figure 3 330 in step 330).

[0075] Next, when VCDL 201 uses the first candidate delay code, D-type flip-flop 213 receives the first output signal (PH) at its clock input terminal. <0> )204, and receives the final output signal (PH) at its data input terminal <n>)205. In this example, the final output signal (PH <n>)205 is provided to the data input terminal of the D-type flip-flop 213 so that it is driven by the first output signal (PH <0> )204 sampling. However, it should be understood that these signals can be swapped and any suitable signal that causes a transition from 1 to 0 or from 0 to 1 at the correct switching time can be used so that the locking signal is used as Figure 3 As will be discussed below, the FSM may check the switching signal cal_lock; that is, the FSM only looks for data transitions from 0 to 1 or from 1 to 0.

[0076] The output signal of the D-type flip-flop 213 will be referred to as the lock signal 214 (in Figure 2 and Figure 3 The first candidate delay code will have a logic 0 value because the first output signal (PH <0> )204 and the final output signal (PH <n>)205 have only a small phase difference. This is because the final output signal (PH <n>)205 in the first output signal (PH <0> ) 204 controls the D-type flip-flop 213 to have a logic 0 value. This check of the state of the lock signal 214 is performed at Figure 3 , which is represented as step 331, wherein a check is made as to whether the lock signal (cal_lock) has transitioned to a logic 1. If it has not, then the delay code setter 208 increases the delay code setting signal so that it represents the next candidate delay code in the sequence. This is done in Figure 3 332. Then at step 333, the D-type flip-flop 213 waits for a period of time, which may be a predetermined period of time, so that the VCDL 201 is stable and the final output signal (PH<N>) 205 is stable. Then, Figure 3 The method is repeated Figure 3 Step 331, and the loop continues until the state of the lock signal 214 becomes logic 1, at which time Figure 3 The flowchart of ends, and the final candidate delay code applied is stored as the selected delay code. As discussed above, it is this selected delay code that will be used by VCDL 201 in the active operation mode.

[0077] Figure 4 Show further instructions Figure 3 The flowchart is a timing diagram of the function.

[0078] Figure 4 The uppermost curve in is the reference clock signal (Phref clk) 418, which, as discussed above, is also the active clock signal (Phref clk).

[0079] The next curve is the clock input signal (Refclk_op) 402, which is the calibration clock signal (Refclk / 2) because the DLL circuit is in the calibration operation mode. Figure 4 It can be seen that the calibration clock signal (Refclk / 2) has half the frequency of the reference clock signal (Phref clk) 418 .

[0080] The next curve is the first output signal (PH <0> )404.

[0081] The next curve is at Figure 4 The final output signal of the first iteration of the loop (PH <n>)405a; that is, the final output signal (PH) when the first candidate delay code is applied <n>)405a. From this curve, it can be seen that the final output signal (PH <n>)405a has not yet been related to the first output signal (PH <0> ) 404 is sufficient phase shift. As discussed above, when the clock frequency is halved, the target phase shift is π radians.

[0082] The next two curves are Figure 4 The final output signal (PH) of the subsequent iteration of the loop <n>)405b, c; that is, the final output signal (PH) when the subsequent candidate delay code in the sequence is applied <n>)405b, c. It can be seen from these curves that the final output signal (PH <n>) 405b, c still have not yet been related to the first output signal (PH <0> )404 is fully phase shifted.

[0083] The lowest curve is at Figure 4 The final output signal (PH) of the subsequent iteration of the loop when the candidate delay code that produces the lock signal (cal lock) state change is applied <n>)405d. Add to Figure 4 The vertical dashed line shows the final output signal (PH <n>)405d is the first output signal (PH <0> )404 has a logic 1 value. Therefore, the last output signal (PH <n>)405d is generated when the candidate delay code is stored as the selected delay code. Figure 4 Indicated as "@load cal = locked value".

[0084] Figure 5 A graph showing candidate delay code indices on the horizontal axis, where each index represents a different candidate delay code in a sequence. In this example, a sequence with 16 candidate delay codes is shown. The time delay in seconds for the entire VCDL is shown on the vertical axis.

[0085] for Figure 5 , the eighth candidate delay code is identified as the selected delay code, which corresponds to a time delay of 1.39 ns.

[0086] Figure 6 Show that it can be Figure 2 Flowchart of the calibration sequence performed by the DLL circuit. Figure 6 The names of the signals included in Figure 2 Shown in.

[0087] At step 660, the DLL circuit is enabled by setting the DLL_EN signal to a logic 1. Figure 2 It can be seen that setting this signal in this way opens the switch, thereby disconnecting the signal of the control voltage signal 203 from the VDD supply. This is before applying a fixed voltage as the control voltage signal 203 in the calibration mode, and the same is true in the active mode, otherwise the control voltage signal 203 will always remain at VDD. Then at step 661, the calibration sequence waits for 100 μs to wait for the initial startup function of the DLL circuit 200.

[0088] At step 662, the calibration mode enable signal (Oploop_en) 222 is set to a logic high value. As discussed in detail above, this places the DLL circuit 200 in a calibration mode of operation. When the calibration mode enable signal (Oploop_en) 222 is set to a high value:

[0089] The fixed voltage signal 211 is provided as the control voltage signal 203 of the VCDL 201;

[0090] The D-type flip-flop 222 of the clock signal generator 217 is enabled;

[0091] The multiplexer 221 of the clock signal generator 217 is controlled so that the calibration clock signal (Refclk / 2) 220 is provided as the clock input signal 202 of the VCDL 201; and

[0092] The D-type flip-flop 213 associated with the delay code setter 208 is enabled.

[0093] At step 663, Figure 6 Flowchart of waiting Figure 3 The calibration sequence ends, and the selected delay code has been determined. Next, at step 664, Figure 6 The flowchart of FIG. 2 sets the calibration mode enable signal (Oploop_en) 222 to a logic low value, so that the DLL circuit 200 enters the active operation mode, such that:

[0094] The feedback voltage signal 207 is provided as the control voltage signal 203 of the VCDL 201;

[0095] The D-type flip-flop 222 of the clock signal generator 217 is disabled;

[0096] The multiplexer 221 of the clock signal generator 217 is controlled so that the active clock signal (Phref_clk) 218 ​​is provided as the clock input signal 202 of the VCDL 201;

[0097] The D-type flip-flop 213 associated with the delay code setter 208 is disabled; and

[0098] VCDL 201 uses the selected delay code.

[0099] At step 665, the DLL circuit is disabled by setting the DLL_EN signal to logic 0 so that the control voltage signal 203 will tend toward the supply voltage VDD. Next, the flow chart waits for the control voltage signal 203 to reach the supply voltage VDD, and at step 666, the DLL circuit is re-enabled by setting the DLL_EN signal to logic 1. The DLL circuit 200 is now calibrated and in an active operating mode.

[0100] Figure 7 The following figure will be used to describe the operation of a calibrated DLL circuit immediately after it is in an active operating mode. Figure 6 The timing diagram of the function after the last step of the flowchart. That is, the timing diagram when the following occurs:

[0101] The control voltage signal has been initialized to the supply voltage (VDD); and

[0102] • The selected delay code has been determined and applied so that the variable components of the VCDL present loads in the active operating mode that correspond to the loads determined in the calibration operating mode to achieve the desired phase shift when the control voltage signal is at a fixed voltage.

[0103] Figure 7 The uppermost curve in FIG. 7 is the reference clock signal (Phref_clk) 718, which, as discussed above, is also the active clock signal (refclk_op) when the DLL circuit is in the active operating mode.

[0104] The next curve is the first output signal (PH <0> )704.

[0105] The third curve is Figure 2 The final output signal of the first iteration of the closed-loop feedback (PH <n>) 705a; that is, the feedback loop including the phase detector 215 and the charge pump 216. Because the control voltage signal has been initialized to the supply voltage (VDD), which is 1V in this example, the phase detector determines the first output signal (PH <0> )704 and the final output signal (PH <n>)705a is too large, so it causes the charge pump 216 to reduce the control voltage signal (Vcntrl).

[0106] The fourth curve is Figure 2 The final output signal (PH) of the second iteration of the feedback loop <n>)705b. For the second iteration, the control voltage signal (Vctrl) has been reduced to 0.8V. However, the phase detector still determines the first output signal (PH <0> )704 and the final output signal (PH <n>)705b is too large, so it causes the charge pump 216 to further reduce the control voltage signal (Vcntrl).

[0107] The fifth curve is Figure 2 The final output signal (PH) of the third iteration of the feedback loop <n>)705c. For the third iteration, the control voltage signal (Vctrl) has been further reduced to 0.6V. However, the phase detector still determines the first output signal (PH <0> )704 and the final output signal (PH <n>)705c is too large, so it causes the charge pump 216 to further reduce the control voltage signal (Vcntrl).

[0108] The sixth and lowest curve is at Figure 2 The final output signal (PH) of the fourth iteration of the feedback loop <n>) 705d. For this iteration, the control voltage signal (Vctrl) has been further reduced to 0.5V. For this iteration, the phase detector 215 determines the first output signal (PH <0> )704 and the final output signal (PH <n>)705d is zero (or close enough to zero), so it causes the charge pump 216 to maintain the control voltage signal (Vcntrl) at its current value of 0.5V. Therefore, in the closed-loop active operating mode, the feedback circuit 206 has determined a control voltage signal of 0.5V, which corresponds to the fixed voltage signal applied during the calibration operating mode. Recall that the fixed voltage signal is set to VDD / 2 in order to provide maximum positive and negative margin for the voltage control signal to drift during the active operating mode without attempting to adopt values ​​outside the achievable range between 0V and the supply voltage (VDD). Therefore, by determining and applying a selected delay code that achieves the desired function during the active operating mode, the DLL circuit has been successfully calibrated during the calibration operating mode.

[0109] The functions described above can be summarized as follows:

[0110] • Perform load calibration by enabling the calibration mode enable signal (Oploop_en) 222 .

[0111] When the calibration mode enable signal (Oploop_en) 222 is enabled, a fixed voltage is selected by the resistor divider circuit 227 for use as the control voltage signal (vcntrl), while the charge pump 216 is disabled and the fixed voltage (vcntrl) is kept close to VDD / 2 to achieve a good vcntrl range within the temperature variation range.

[0112] ●By keeping the fixed voltage (vcntrl) close to VDD / 2, the candidate delay code (l0ad cal<n:0> ) changes from 0 until the lock signal (cal lock) 214 switches.

[0113] ● At the value at which the lock signal (cal lock) 214 will switch, the final output signal PH <n>205 will be relative to the first output signal PH <0> 204 is delayed by half a cycle. It should be noted that when the DLL circuit is in the active operating mode, this half cycle corresponds to the input clock period of the DLL. Therefore, when the DLL circuit 200 is in the active operating mode, the candidate delay code (load_cal<n:0> ) will cause the final output signal PH <n>205 relative to the first output signal PH <0> 204 delays a whole clock cycle (Tclk).

[0114] Thus, when the DLL circuit is in the closed-loop active mode of operation, the DLL circuit 200 will lock to a value close to the control voltage signal (vcntrl) used in the open-loop calibration mode of operation, namely VDD / 2, by maintaining the same candidate delay code (load_cal value) converted by the lock signal (cal_lock) 214.

[0115] Advantageously, the DLL circuit described herein can provide accurate calibration of the control voltage signal by varying the RC delay across the PVT during a calibration mode of operation before entering a lock condition in a closed-loop configuration during an active mode of operation. Since the control voltage signal (Vcntrl) has a limited range, e.g., it cannot fall outside the range defined by ground and the supply voltage (VDD), the value of the control voltage signal applied to the voltage-controlled delay line should remain within these limits over the expected range of PVT variations.

[0116] Examples disclosed herein relate to a calibration circuit for a wide range frequency DLL circuit, which may represent an efficient and novel approach for gain calibration of a delay line.

[0117] The instructions and / or process steps in the above figures may be executed in any order unless a specific order is explicitly stated. Also, those skilled in the art will recognize that although an example instruction set / method has been discussed, the materials in this specification may also be combined in a variety of ways to produce other examples, and should be understood within the context provided by this detailed description.

[0118] In some example embodiments, the instruction / method step sets described above are implemented as functions and software instructions that are implemented as executable instruction sets and implemented on a computer or machine that is programmed with and controlled by the executable instructions. Such instructions are loaded to be executed on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor may refer to a single component or multiple components.

[0119] In other examples, the instruction / method set shown herein and the data and instructions associated therewith are stored in a corresponding storage device implemented as one or more non-transient machine or computer readable or computer usable storage media. Such computer readable or computer usable storage media are considered to be part of an article (or product). An article or product may refer to a single component or multiple components of any manufacture. A non-transient machine or computer usable medium as defined herein does not include a signal, but such a medium is capable of receiving and processing information from a signal and / or other transient medium.

[0120] Example embodiments of the material discussed in this specification may be implemented in whole or in part via a network, computer or data-based device and / or service. These may include the cloud, the Internet, an intranet, a mobile device, a desktop computer, a processor, a lookup table, a microcontroller, a consumer device, an infrastructure or other enabling device and service. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0121] In one example, one or more instructions or steps discussed herein are automatic. The term automatic or automatically (and similar variations thereof) refers to the controlled operation of a device, system, and / or process using computers and / or mechanical / electrical devices without human intervention, observation, effort, and / or decision making.

[0122] It should be understood that any components referred to as being coupled may be coupled or connected directly or indirectly. In the case of an indirect coupling, there may be additional components between the two components referred to as being coupled.

[0123] In this specification, example embodiments have been presented with respect to a selected set of details. However, one of ordinary skill in the art will appreciate that many other example embodiments including different selected sets of these details may be practiced. The appended claims are intended to cover all possible example embodiments.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A delay locked loop circuit, characterized in that: include: A voltage controlled delay line comprising one or more variable components, wherein the voltage controlled delay line is configured to: receiving a clock input signal; receiving a control voltage signal; as well as applying a time delay to the clock input signal to provide a first output signal and a final output signal, wherein a magnitude of the time delay is based on the control voltage signal and a delay code, and wherein the delay code defines a value of the one or more variable components in the voltage-controlled delay line; a feedback circuit configured to provide a feedback voltage signal based on a phase difference between the first output signal and the last output signal; a delay code setter configured to provide a delay code setting signal representing one of a series of different candidate delay codes; a fixed voltage source configured to provide a fixed voltage signal; as well as a switch circuit configured to place the delay locked loop circuit into an active operating mode or a calibration operating mode, wherein: When the delay locked loop circuit is in the calibration operation mode: The fixed voltage source is configured to provide the fixed voltage signal as the control voltage signal of the voltage-controlled delay line; and the delay code setter being configured to apply the delay code setting signal to the voltage-controlled delay line, so that the delay code setter applies one or more of the series of different candidate delay codes to the voltage-controlled delay line so as to determine a candidate delay code that produces a predetermined phase difference between the first output signal and the final output signal, and to designate the candidate delay code as a selected delay code; When the delay locked loop circuit is in the active operating mode: The feedback circuit is configured to provide the feedback voltage signal as the control voltage signal of the voltage-controlled delay line; and The voltage-controlled delay line is configured to use the selected delay code as the delay code.

2. The delay locked loop circuit according to claim 1, characterized in that: The voltage-controlled delay line includes a plurality of buffers connected in series.

3. The delay locked loop circuit according to claim 2, characterized in that: At least one of the variable components of the voltage-controlled delay line is associated with each of the plurality of buffers.

4. A delay locked loop circuit according to any preceding claim, characterised in that The fixed voltage signal has a value in the middle of a range of voltage values ​​that enable the DLL circuit to operate properly.

5. The delay locked loop circuit according to claim 4, characterized in that: The fixed voltage signal has a value equal to half of a supply voltage of the DLL circuit.

6. A delay locked loop circuit according to any preceding claim, characterised in that The fixed voltage source includes a potentiometer configured to receive a calibration voltage control signal, wherein the potentiometer is operable to tap a voltage based on the calibration voltage control signal to provide the fixed voltage signal.

7. A delay locked loop circuit according to any preceding claim, characterised in that Wherein when the delay locked loop circuit is in the active operating mode, the predetermined phase difference corresponds to a phase difference of 2Π radians.

8. A delay locked loop circuit according to any preceding claim, characterised in that The switch circuit includes a control voltage connection switch configured to provide the fixed voltage signal or the feedback voltage signal as the control voltage signal of the voltage-controlled delay line.

9. A delay locked loop circuit according to any preceding claim, characterised in that Also included is a clock signal generator, wherein the clock signal generator is configured to: providing a calibration clock signal as the clock input signal of the voltage-controlled delay line when the delay-locked loop circuit is in the calibration operation mode; and providing an active clock signal as the clock input signal of the voltage-controlled delay line when the delay-locked loop circuit is in the active operating mode; The calibration clock signal and the active clock signal have different frequencies.

10. The delay locked loop circuit according to claim 9, characterized in that: The frequency of the calibration clock signal is half the frequency of the active clock signal.

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