An analog-to-digital converter based on a reset ring oscillator supporting Nyquist bandwidth

Abstract

The present invention discloses an analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator. The analog-to-digital converter includes a sampling and holding circuit, a tail current source tube, an oscillator, a voltage balancing circuit, and a transmission gate. The oscillator includes n delay units connected end to end and delayed in sequence to form a loop, and each delay unit has input terminals,,,, and output terminals,,,. Each is connected to the tube drain, each is connected to the tube drain, each is connected to the tube drain, and each is connected to the tube drain. The gates of, are controlled by a control signal synchronized with the sampling signal and the source is connected to the drain; the gates of, are controlled by and the source is connected to a voltage source. The voltage balancing circuit includes two tubes, and two electrically controlled switches controlled by. The transmission gate is connected in series between the first and last delay units. The present invention can quickly reset the loop.

Description

Technical Field

[0001] The present invention relates to an analog-to-digital converter, and in particular to an analog-to-digital converter / differential analog-to-digital converter supporting Nyquist bandwidth and based on a reset ring oscillator. Background Art

[0002] With the rapid development of sensing and communication technologies, there is an increasing demand for medium-resolution (6–8 bits) and high-speed (>1 GS / s) analog-to-digital converters (ADCs). Flash ADCs and time-interleaved ADCs can usually achieve high sampling rates, but at the cost of high power consumption. With the rapid development of CMOS process technology, time-domain-based converters can achieve faster and faster conversion speeds. Among them, low-power digital ADCs based on voltage-controlled oscillators (VCOs) benefit particularly from this trend. VCO-based ADCs inherently have the first-order noise shaping characteristics of quantization noise, and through oversampling technology, they are widely used in low-speed, high-precision applications. However, with the continuous increase in VCO frequency in new process nodes, VCO-based Nyquist ADCs can achieve high accuracy at higher sampling rates, making them more attractive in high-speed applications. In addition, since VCO-based Nyquist ADCs can obtain additional resolution by halving the sampling rate, this feature makes it easier to adapt to different communication standards and frequency bands, thereby improving its adaptability and versatility.

[0003] But in the traditional ring VCO-based ADC, such as Figure 1 As shown, the input voltage Vin adjusts the oscillation frequency of the ring VCO, and the phase of the VCO is then quantized and differentiated (i.e., 1 – z) by a frequency-to-digital converter (FDC). -1 ). In this process, the VCO and FDC introduce phase noise (PN) and quantization noise (Q) into the system, respectively. First-order noise shaping by the differentiator usually helps reduce noise within the system bandwidth, but this advantage is significantly reduced at low oversampling ratios (OSR) and especially at the Nyquist bandwidth. For VCO phase noise, (1 – z -1 ) noise shaping flattens the original –20 dB / dec slope to a flat spectrum. In contrast, the shaping of the quantization noise appears as 2 × (Δ 2 / 12), which results in a decrease in the signal quantization dynamic range (SQDR) by about 3 dB. Summary of the invention

[0004] In order to solve the problem of SQNR degradation caused by quantization noise shaping in traditional VCO-based Nyquist ADC, resulting in quantization noise doubling, the present invention provides an analog-to-digital converter / differential analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator.

[0005] The present invention is implemented by the following technical scheme: an analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator, which includes a sampling and holding circuit, an NMOS tail current source tube M0, an oscillator VCO The sampling and holding circuit is based on the sampling signal Φ s Sampling analog signals V in And output digital control signal V ctrl The gate of NMOS tail current source tube M0 receives V ctrl , with its source grounded. VCO It includes n delay units, each of which has four input terminals IN1, IN0, , And 4 output terminals O1, O0, , The four output terminals O1, O0, , Connect the four input terminals IN1, IN0, , , so that n delay units are connected end to end and delayed in sequence to form VCO Loop.

[0006] Each input terminal IN1 is connected to an NMOS tube M SW1 The drain connection of each output With a PMOS tube M SW2 The drain connection of each input With a PMOS tube M SW3 Each output terminal O0 is connected to an NMOS tube M SW4 Drain connection; M SW1 、M SW4 The gate is controlled by the control signal Φ rst ;M SW2 、M SW3 The gate is controlled by the control signal , M SW1 、M SW4 The source of M0 is connected to the drain of M1. SW2 、M SW3 The source of the voltage source V DD ; Control signal Φ rst With Φ s The analog-to-digital converter also includes a voltage balancing circuit and a transmission gate unit TG. The voltage balancing circuit includes two MOS tubes M1 and M2 and both are controlled by a control signal Φ rst Two electric switches KM1 , K M2 ; The source of M1 is connected to the voltage source V DD , the drain of M1 passes through K M1 Connect the gate of M1, and the drain of M1 is connected through K M1 , K M2 Connect the drain of M2, and the gate of M1 is also connected to the gate of M2 and M SW1 、M SW4 The source of M2 is grounded. The transmission gate unit TG is connected in series between the first delay unit and the nth delay unit.

[0007] As a further improvement of the above scheme, each delay unit includes 8 inverters N1 to N8; the input ends of N1 and N2 are IN1 and IN0 respectively, and the output ends of N1 and N2 are connected to form ; The input terminals of N3 and N4 are , , the output ends of N3 and N4 are connected to form O0; the output end of N1 is also connected to the input end of N5, the output end of N3 is also connected to the input end of N8, the output ends of N5 and N6 are both O1, and the output ends of N7 and N8 are both ; The input terminals of N6 and N7 are 、IN1.

[0008] As a further improvement of the above solution, the analog-to-digital converter further includes:

[0009] The coarse quantizer samples IN0 of the first delay unit, And perform coarse quantization, and thus obtain the output signal D CQ ;

[0010] The fine quantizer samples IN1, IN0, , And fine quantization is performed, and the output signal D1~D is obtained 2（n+1） ;

[0011] The encoder encodes the coarse quantization signal and the fine quantization signal into a binary code to obtain a digital signal. D out .

[0012] Furthermore, the fine quantizer includes two control signals Φ and Φ. buf 2 (n+1) switch buffers; every 2 switch buffers correspond to 1 delay unit, and the remaining 2 switch buffers correspond to the transmission gate unit TG;

[0013] Among them, IN1, Input to the corresponding switch buffer's in-phase terminal and inverting terminal respectively, IN0, IN2, IN3, IN4, IN5, IN6, IN7, IN8, IN9, IN10, IN11, IN12, IN13, IN14, IN15, IN16, IN17, IN18, IN19, IN20, IN21, IN22, IN23, IN24, IN25, IN26, IN27, IN28, IN29, IN They are respectively input to the non-inverting terminal and the inverting terminal of another corresponding switch buffer, and the four outputs of the delay unit of the last stage are connected to the transmission gate unit. The inputs are respectively sent to the non-inverting terminal and the inverting terminal of a corresponding switch buffer, and the O0 and It is also input to the non-inverting terminal and the inverting terminal of the corresponding other switch buffer; so that the 2 (n + 1) switch buffers correspond to the 4 (n + 1) output signals output by the n delay units and a transmission gate unit, and the 2 (n + 1) switch buffers output D1~D 2（n+1） ; Control signal Φ buf The falling edge of Φ rst The rising edges are aligned and the high level time is X ps.

[0014] Preferably, each switch buffer includes: 4 NMOS transistors M buf1 ~ M buf4 , 2 PMOS tubes M buf5 ~ M buf6 , 6 inverters N9~N 14 ;M buf1 and M buf2 The gates of the or IN0, , M buf1 and M buf2 The source of M is grounded. buf1 and M buf2 The drain of buf3 and M buf4 The source, M buf3 and M buf4 The gate connection, M buf3 and M buf4 The drain of M buf5 and M buf6 The drain, M buf5 and M buf6 The source of both are connected to V DD ;M buf5 The gate connection M buf6 The drain of N9 and the input of M buf6 The gate connection M buf5 The drain and N 10 The output of N9 is connected to N 11 The output terminal and N 12 The input terminal, N 12 The output terminal is connected to N 10 The output terminal, N 11The input terminal, N 13 The input terminal, N 13 The output terminal is connected to N 14 The input terminal, N 14 The corresponding signal D at the output end belongs to D1~D 2（n+1） .

[0015] Preferably, the fine quantizer further comprises a phase folding detector PF and a thermometer code-to-binary converter T2B; 2 (n+1) switch buffers sample 4 (n+1) phases of the ring oscillator to produce 2 (n+1) signals D1~D 2（n+1） , and output to the phase folding detector and the thermometer code to binary converter; the thermometer code to binary converter converts D1~D 2（n+1） Converted into binary output to the phase folding detector, the phase folding detector samples half of the phase information and converts the phase data according to the last flipped edge, i.e., D 2（n+1） Convert to low-order digital output code.

[0016] Furthermore, the coarse quantizer includes a first-stage switch buffer that is always turned on, a buffer, a resettable fast asynchronous counter, a D flip-flop array, and a delay calibrator; IN0 of the first delay unit in the oscillator, The output is sent to the first-stage switch buffer, and then sent to the counter after passing through the buffer; the outputs of the two buffers and the counter are sampled by the D flip-flop array and then sent to the delay calibrator. 2（n+1） The signal is also output to the delay calibrator; the delay calibrator outputs the output signal D of the coarse quantizer CQ ; The sampling clock of the D flip-flop array is Φ cnt , and after a delay, it is used as the reset control signal of the counter. The control signal Φ cnt is the control signal Φ rst Delayed signal.

[0017] Furthermore, the encoder comprises a weighter; an output D of the fine quantizer FQ and the output of the coarse quantizer D CQ The final ADC output code D is output after the weighting device out ; Fine quantizer output D FQ As the low-order codeword, the output D of the coarse quantizer CQ It is a high-order code word.

[0018] As a further improvement of the above solution, the sampling and holding circuit includes a capacitor C s and is controlled by Φ s Sampling switch K s ; V in Through the sampling switch Ks is sampled to capacitor C s Output V ctrl .

[0019] The present invention also provides a differential analog-to-digital converter, which converts a pair of analog differential input signals V in,n , V in,p Converted into a pair of digital differential signals D out,n , D out,p The differential analog-to-digital converter comprises two of the above-mentioned arbitrary analog-to-digital converters supporting Nyquist bandwidth based on reset ring oscillators, respectively V in,n , V in,p Convert to corresponding D out,n , D out,p .

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] (1) The analog-to-digital converter of the present invention is a Nyquist ADC based on a reset ring VCO, and has a single-channel sampling rate of 2GS / s. Compared with the traditional VCO-based Nyquist ADC, the ADC does not shape the quantization noise within the Nyquist bandwidth, thereby achieving a relatively high SQNR.

[0022] (2) Since the buffer of the multi-phase VCO output needs to operate at a frequency of up to several GHz, and the subsequent D flip-flop also consumes a lot of power, the present invention improves the fine quantizer and designs a switch buffer structure (including 2 (n+1) switch buffers), which not only realizes the buffering of phase information, but also can sample it, thereby significantly reducing power consumption. The switch buffer significantly reduces power consumption. At 7 GHz VCO output and 2 GHz sampling rate, the sw-buf with 90 ps turn-on time consumes only 30.3 μW. In comparison, the same size level conversion and TSPC DFF and level conversion and master-slave DFF consume 188.8 μW and 179.7 μW respectively.

[0023] (3) The analog-to-digital converter of the present invention further improves the fine quantizer and proposes a compact fine quantizer with phase folding function. Thanks to the unique characteristics of R-RVCO, the phase node of the first flip edge is known. Therefore, unlike the traditional VCO-based ADC, which needs to sample all phase nodes, the present invention only needs to sample half of the phase information. Compared with the fine quantizer traditionally used in VCO-based ADCs, this structure eliminates a large number of D flip-flops and edge detectors. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the circuit structure of a differential analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator provided in an embodiment of the present invention.

[0025] Figure 2 for Figure 1 Circuit diagram of the delay unit of the analog-to-digital converter.

[0026] Figure 3 for Figure 1 Circuit diagram of the switch buffer structure in .

[0027] Figure 4 for Figure 3 Circuit diagram of the switching buffer.

[0028] Figure 5 for Figure 1 Schematic diagram of the structure of the fine quantizer and coarse quantizer of the analog-to-digital converter.

[0029] Figure 6 For traditional ring VCO-based ADC and Figure 1 The comparison chart of the ADC modules based on reset ring VCO (R-RVCO) with n=8 after being equivalent.

[0030] Figure 7 for Figure 1 Simplified module diagram of ADC where n is 8.

[0031] Figure 8 for Figure 1 In the same f VCO , D CQ , D 18 Below, two D before phase folding (before folding) and phase folding (Folding) FQ .

[0032] Fig. 9 for Figure 1The timing diagram between the sampling signal of the ADC and various control signals when n is 8. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] The present invention is intended to disclose a reset ring oscillator based analog-to-digital converter (R-RVCO type ADC) supporting Nyquist bandwidth, which can process a separate analog signal V in , the analog input signal V in Convert to digital signal D out If the input signal is a pair of analog differential input signals V in,n , V in,p When the two analog-to-digital converters are used, they are processed separately. Figure 1 As shown in FIG. 1 , it is a schematic diagram of a circuit structure of a differential analog-to-digital converter based on a reset ring oscillator and supporting Nyquist bandwidth provided by an embodiment of the present invention. The differential analog-to-digital converter is used to convert a pair of analog differential input signals V in,n , V in,p Converted into a pair of digital differential signals D out,n , D out,p .

[0035] Each analog-to-digital converter includes a sample-and-hold circuit, an NMOS tail current source tube M0, an oscillator VCO , voltage balancing circuit, transmission gate unit TG, each analog-to-digital converter may also include a coarse quantizer (CQ), a fine quantizer (FQ), and an encoder.

[0036] The sample-and-hold circuit is used to sample the signal Φ s Sampling analog signals V in And output digital control signal V ctrl The sample-and-hold circuit may include a capacitor C s and is controlled by the sampling signal Φ sSampling switch K s ; V in Through the sampling switch K s is sampled to capacitor C s Output V ctrl The sampling switch Ks can achieve good linearity and low on-resistance through a gate voltage bootstrap circuit.

[0037] The gate of the NMOS tail current source tube M0 receives V ctrl , with its source connected to ground.

[0038] Oscillator VCO The delay units include n. In this embodiment, in order to give a specific example, n is 8 for example. Figure 2 Each delay unit has four input terminals IN1, IN0, , And 4 output terminals O1, O0, , The four output terminals O1, O0, , Connect the four input terminals IN1, IN0, , , so that n delay units are connected end to end and delayed in sequence to form VCO Each input terminal IN1 is connected to an NMOS tube M SW1 The drain connection of each output With a PMOS tube M SW2 The drain connection of each input With a PMOS tube M SW3 Each output terminal O0 is connected to an NMOS tube M SW4 Drain connection of the M SW1 、M SW4 The gate is controlled by the control signal Φ rst . M SW2 、M SW3 The gate is controlled by the control signal , M SW1 、M SW4 The source of M0 is connected to the drain of M1. SW2 、M SW3 The source of the voltage source V DD . Control signal Φ rst With Φ s Therefore, the oscillator VCODesigned to reset the ring oscillator R-RVCO .

[0039] There are many types of delay unit circuits, as long as they can satisfy the above output relationship. In this embodiment, each delay unit may include 8 inverters N1 to N8. The input terminals of N1 and N2 are IN1 and IN0 respectively, and the output terminals of N1 and N2 are connected to form ; The input terminals of N3 and N4 are , , the output ends of N3 and N4 are connected to form O0; the output end of N1 is also connected to the input end of N5, the output end of N3 is also connected to the input end of N8, the output ends of N5 and N6 are both O1, and the output ends of N7 and N8 are both ; The input terminals of N6 and N7 are 、IN1.

[0040] The voltage balancing circuit includes two MOS tubes M1 and M2 and both are controlled by a control signal Φ rst Two electric switches K M1 , K M2 The source of M1 is connected to a voltage source V DD , the drain of M1 passes through K M1 Connect the gate of M1, and the drain of M1 is connected through K M1 , K M2 Connect the drain of M2, and the gate of M1 is also connected to the gate of M2 and M SW1 、M SW4 The source of M2 is grounded. The transmission gate unit TG is connected in series between the first delay unit and the nth delay unit. The transmission gate unit TG can generally be composed of four transmission gates.

[0041] The analog-to-digital converter uses the above circuit connection relationship. As long as the sampling signal Φ s , Φ rst When synchronization conditions are met (such as Figure 5 As shown in Figure 2, in the proposed R-RVCO ADC, each node of the VCO loop is reset to V outside the conversion cycle. DD or V tail , where V tail As the virtual ground of the VCO. At the same time, the transmission gate unit (TG) module disconnects the VCO loop, thereby accelerating the reset process. After the reset is completed, the output of the TG module ( and ) will be fed back to the first flip phase node. Therefore, the present invention can solve the problem of SQNR reduction caused by quantization noise shaping in the traditional VCO-based Nyquist ADC, which leads to quantization noise doubling. This is the first innovation of the present invention: 1) A ring VCO (i.e. VCO Loop: R-RVCO).

[0042] Please refer again Figure 1 , the coarse quantizer samples IN0 of the first delay unit, And perform coarse quantization, and thus obtain the output signal D CQ The fine quantizer samples IN1, IN0, , And fine quantization is performed, and the output signal D1~D is obtained 2（n+1） The encoder encodes the coarse quantization signal and the fine quantization signal into binary to obtain a digital signal D out .

[0043] The fine quantizer may include a phase folding detector PF and a thermometer code-to-binary converter T2B, and may also include a switch buffer structure, wherein the switch buffer structure includes 2 (n+1) switch buffers (sw-bufs). The 2 (n+1) switch buffers sample the 4 (n+1) phases of the ring oscillator to produce 2 (n+1) signals D1~D 2（n+1） , and output to the phase folding detector and the thermometer code to binary converter, the thermometer code to binary converter converts D1~D 2（n+1） Converted into binary output and given to the phase folding detector.

[0044] Please combine Figure 3 , (2n+1) switch buffers are controlled by the control signal Φ buf , every two switch buffers correspond to one delay unit, and the remaining two switch buffers correspond to the transmission gate unit TG. IN1, Input to the corresponding switch buffer's in-phase terminal and inverting terminal respectively, IN0, IN2, IN3, IN4, IN5, IN6, IN7, IN8, IN9, IN10, IN11, IN12, IN13, IN14, IN15, IN16, IN17, IN18, IN19, IN20, IN21, IN22, IN23, IN24, IN25, IN26, IN27, IN28, IN29, IN30, IN31, IN32, IN33, IN44, IN51, IN62, IN71, IN81, IN9, IN10, IN11, IN12, IN13, IN14, IN15 The four outputs of the delay unit at the last stage are connected to the transmission gate unit. The inputs are respectively sent to the non-inverting terminal and the inverting terminal of a corresponding switch buffer, and the O0 and It is also input to the non-inverting terminal and the inverting terminal of the corresponding switch buffer. The 2 (n+1) switch buffers correspond to the 4 (n+1) output signals output by n delay units and a transmission gate unit, and the 2 (n+1) switch buffers output D1~D in sequence.2（n+1） .

[0045] Since n is 8 for example, 2 (n+1) switch buffers are 18 switch buffers, all of which are controlled by the control signal Φ buf , 18 switch buffers finally output D1~D 18 There are 18 signals in total. Every 2 switch buffers correspond to 1 delay unit (such as Figure 1 The output signal D1~D 16 , a total of 16 output signals), the remaining 2 switch buffers correspond to 1 transmission gate TG (such as Figure 1 Output signal D 17 and D 18 , a total of 2 output signals).

[0046] The analog-to-digital converter increases the number of switch buffers by 2 (n+1) as long as the control signal Φ buf , Φ rst Satisfaction Figure 3 The conditions shown are: the control signal Φ buf The falling edge of Φ rst The rising edges are aligned, and the high level time is X ps. In this embodiment, X is 90, that is, Φ buf The falling edge of Φ rst The rising edge is aligned, and the high level time of 90ps can ensure that the buffer can achieve relatively low power consumption while realizing the functions of buffering and sampling phase information. Therefore, the addition of 2 (n+1) switch buffers in the analog-to-digital converter of the present invention can solve the high power consumption problem caused by the VCO output buffer in the traditional VCO-based Nyquist ADC always working under high-frequency input (because the buffer of the multi-phase VCO output needs to work at a frequency of up to several GHz, and the subsequent D flip-flop will also consume a lot of power). This is the second innovation of the present invention: 2) 2 (n+1) switch buffers (sw-buf) are added to the fine quantizer. This structure not only realizes the buffering of phase information, but also can sample it, thereby significantly reducing power consumption.

[0047] In the specific circuit structure design of the switch buffer, you can choose Figure 4 Each switch buffer (Switched Buffer, sw-buf) includes: 4 NMOS tubes M buf1 ~ M buf4 , 2 PMOS tubes M buf5 ~ M buf6 , 6 inverters N9~N 14 . M buf1 and M buf2 The gates of the or IN0, , M buf1 and M buf2 The source of M is grounded. buf1 and M buf2 The drain of buf3 and M buf4 The source, M buf3 and M buf4 The gate connection, M buf3 and M buf4 The drain of M buf5 and M buf6 The drain, M buf5 and M buf6 The source of both are connected to V DD ;M buf5 The gate connection M buf6 The drain of N9 and the input of M buf6 The gate connection M buf5 The drain and N 10 The output of N9 is connected to N 11 The output terminal and N 12 The input terminal, N 12 The output terminal is connected to N 10 The output terminal, N 11 The input terminal, N 13 The input terminal, N 13 The output terminal is connected to N 14 The input terminal, N 14 The corresponding signal D at the output end belongs to D1~D 2（n+1） .

[0048] In this embodiment, the fine quantizer can be mainly composed of 18 switch buffers (sw-bufs), a phase folding detector PF and a thermometer code-to-binary converter T2B. The switch buffer samples the 36 phases of the ring oscillator to produce 18 signals D1~D 18 , and output to the phase folding detector and the thermometer code-to-binary converter. The thermometer code-to-binary converter converts D1~D 18 Converted into binary output to the phase folding detector. Due to the characteristics of the reset ring oscillator, the output node with the slowest flip in each oscillation cycle is fixed, which is D in this design. 18 When D 18 =0, the output range of the thermometer code to binary converter is 0~17. At this time, the phase folding detector does not operate, and the output of the thermometer code to binary converter is the fine quantizer output D FQ When D 18=1, the output range of the thermometer code-to-binary converter is 18~1. At this time, the phase folding detector performs a folding operation on it and calibrates the codeword in the range of 18~1 to 18~35 (for example, D 18 =1, code word 17 is calibrated to 36-17=19 after phase folding detector, thus obtaining the fine quantizer output D with full range of 0~35 FQ This is the third innovation of the present invention: 3) A compact fine quantizer with phase folding function solves the problem of large area and high power consumption caused by a large number of flip-flops (DFFs) and edge detectors in the fine quantizer of the traditional VCO-based Nyquist ADC.

[0049] Please refer again Figure 1 The coarse quantizer may include a first-stage switch buffer (buf), a buffer, a resettable fast asynchronous counter (Counter), a D flip-flop array (D Flip-Flops), a delay calibrator (Latency correction), and a delay device. The first-stage switch buffer is always turned on. IN0 of the first delay unit in the oscillator, The output is sent to the first-stage switch buffer of the coarse quantizer, and then to a counter after passing through a buffer. The counter is used to count the oscillation period of the buffer output signal. The outputs of the two buffers and the counter are sampled by the D flip-flop array and then output to the delay calibrator. At the same time, the D 18 The signal is also output to the delay calibrator to calibrate the delay between the two calibrators. The delay calibrator outputs the output D of the coarse quantizer. CQ The sampling clock of the D flip-flop array is Φ cnt , and after a short delay of the delay device, it serves as the reset control signal (Reset) of the counter (Counter). The control signal Φ cnt is the control signal Φ rst Delayed signal.

[0050] The encoder may include a weighter. The fine quantizer output D FQ and the output of the coarse quantizer D CQ The final ADC output code D is output after the weighting device out . Fine quantizer output D FQ As the low-order codeword, the output D of the coarse quantizer CQ For high-order codewords, D CQ The weight is 36.

[0051] The design of the present invention aims to significantly improve the signal-to-noise-and-distortion ratio (SNDR) and the figure of merit (FOM), thereby providing better performance under high speed requirements.

[0052] In order to better verify the technical effect of the present invention and also to more clearly demonstrate the technical effect of the present invention, in this embodiment, the circuit of the present invention is equivalent to the corresponding functional modules, and then compared and analyzed with the traditional equivalent functional modules. Figure 6 As shown, Figure 6 For traditional ring VCO-based ADC and Figure 1 The figure shows the comparison of the ADC modules based on reset ring VCO (R-RVCO) after being equivalent.

[0053] Figure 6 The comparison between the conventional Nyquist VCO-Based ADC and the proposed Resettable-Ring VCO-Based ADC under Nyquist bandwidth is shown. In the conventional design, the input voltage Vin adjusts the oscillation frequency of the ring VCO, and the phase of the VCO is then quantized and differentiated by a frequency-to-digital converter (FDC). The frequency-to-digital converter (FDC) includes a quantizer and a differentiator (1 – z -1 ). In this process, the VCO and FDC introduce phase noise (PN) and quantization noise (Q-noise, Q) into the system, respectively. The first-order noise shaping of the differentiator usually helps to reduce the noise within the system bandwidth, but this advantage is significantly reduced at low oversampling ratios (OSR) and especially at the Nyquist bandwidth. For VCO phase noise, (1 – z -1 ) noise shaping flattens the original –20 dB / dec slope to a flat spectrum with good tolerance to VCO noise. In contrast, the quantization noise shaping is 2 × (Δ 2 / 12), which results in a signal quantization dynamic range (SQDR) decrease of about 3 dB (SQNR decreased by 3dB).

[0054] The present invention resets the phase of RVCO after each conversion, thereby directly integrating 1-z -1 function, by resetting the ring VCO (Resettable-Ring VCO) followed by quantization. This method significantly improves SQNR (High SQNR) by performing first-order noise shaping (Good tolerance to VCO noise) on the phase noise while avoiding further increase in quantization noise (Q-noise). Please combine Figure 7 , Figure 7 for Figure 1 The simplified module diagram of the ADC based on the resettable-ring VCO (R-RVCO) in the figure shows that the gray arrow on the left points to the curve in the lower left area, which represents two outputs of the transmission gate unit TG. and The voltage curve changes with time t. There is only 80ps reset time (Reset) between two adjacent oscillations (Oscillation); the middle green arrow indicates that the equivalent module of the switch buffer structure is further simplified to a module schematic diagram of 2 (n+1) switch buffers SW-bufs, without the need for triggers and detectors in the traditional architecture (No need conv.DFFs and detectors); the green arrow on the right indicates that the ADC based on the reset ring VCO (R-RVCO) of the present invention does not need to add an additional 1-z -1 function, no differentiator is required (1 – z -1 )(Noneed additional 1 – z -1 ).

[0055] In addition, since the reset type R-RVCO of the present invention contains 1 – z -1 function, so the subsequent differentiator is no longer needed. In the proposed R-RVCO ADC, each node of the VCO loop is reset to V outside the conversion cycle. DD or V tail , where V tail As the virtual ground of the VCO. At the same time, the transmission gate unit (TG) module disconnects the VCO loop, thereby accelerating the reset process. After the reset is completed, the output of the TG module ( and ) is fed back to the first flip phase node.

[0056] Since the buffer of the multi-phase VCO output needs to operate at a frequency of up to several GHz, and the subsequent D flip-flop will also consume a lot of power, the present invention also improves the fine quantizer and adds a switch buffer structure (including 2 (n+1) switch buffers) that matches the improved VCO loop. The switch buffer structure not only buffers the phase information, but also samples it, thereby significantly reducing power consumption. After being processed by the coarse-fine quantizer, the output signal of the RVCO is encoded into a binary code. Thanks to the unique characteristics of the R-RVCO, the phase node of the first flip edge is known. Therefore, unlike the traditional VCO-based ADC, which requires sampling of all phase nodes, the present invention further improves the fine quantizer and adopts a phase folding detector PF, so that only half of the phase information needs to be sampled. The phase folding (PF) technology is used to sample the phase data according to the last flip edge (D 18 ) is converted into a low-order digital output code. The nonlinearity, offset and gain errors of the RVCO tuning curve are corrected by foreground digital calibration (using a lookup table LUT).

[0057] The phase folding detector PF itself is not an innovation of the present invention, but belongs to the application of the present invention. Based on the VCO loop designed by the present invention, a phase folding idea is designed, and the phase folding idea of ​​the present invention is realized by using the phase folding detector PF.

[0058] See also Figure 8 and Fig. 9 , Figure 8 Shown in the same f VCO , D CQ , D 18 The two Ds before phase folding and phase folding FQ The comparison, Fig. 9 It shows the timing relationship between the sampling signal and each control signal, and expresses the timing of the coarse-fine quantizer (coarse quantizer and fine quantizer). Fig. 9 It is also shown that the switching buffer is controlled by Φ buf (bufs ctrl by Φ buf ) 1~18 , D FQ , D CQ Curves showing the time series and D when the switch buffer is always closed (bufs always on) 1~18 The input signal is sampled to the capacitor C S Upper, C SThe capacity of is 200 fF to accommodate the kick-back noise from R-RVCO. Pseudo-differential implementation is adopted to effectively suppress common-mode interference and even-order harmonic distortion. The phase signal of R-RVCO is provided to the fine quantizer (FQ) and the coarse quantizer (CQ) for parallel quantization. The fine quantizer (FQ) consists of multiple switch buffers, which generate flip edges D1 to D 18 These buffers consist of Φ buf control, with a 90 ps turn-on time before sampling to ensure proper capture of phase information. 18 After passing through the phase folding (PF) and thermometer code to binary (T2B) converter, a 6-bit code is output. 18 It is the last flip edge in the oscillation cycle and can therefore be used as a phase folding sign. 18 When it is low, no additional operation is performed; when D 18 When HIGH, phase folding is performed, resulting in full 36-phase information. The coarse quantizer (CQ) counts these cycles with a fast asynchronous counter that can run up to 10 GHz, covering the entire VCO oscillation frequency. The output signal of the counter is then sampled by a D flip-flop (DFF) and reset after a short delay. Delay correction is used to account for phase deviations between quantizers.

[0059] 16-level differential R-RVCO (see Figure 1 ) is based on a current-starved inverter and integrates a feed-forward path (i.e., a pre-predicted phase signal) to attenuate the common-mode gain, increase the oscillation speed, and extend the tuning range of the VCO, ultimately improving the resolution of the ADC. Each RVCO node consists of a switch (M sw1–4 ) is used to reset the state of RVCO. Since the RVCO signal is not full scale, the pull-down switch M sw1 and M sw4 connected to the tail current transistor (V tail ) instead of ground. Due to the charge accumulation at each phase node, V tail It may rise rapidly during reset, causing the pull-down switch to fail. To solve this problem, V tail Balance circuit to regulate the voltage, ensuring that V tail When the normal level is exceeded, it discharges quickly and tail Minimize its effects while staying within the nominal range.

[0060] The VCO buffer is then bufControlled, turns off when activated to isolate the RVCO output, and performs level shifting, driving, and latching functions. This switching buffer (sw-buf) significantly reduces power consumption. At 7 GHz VCO output and 2 GHz sampling rate, the sw-buf with 90 ps turn-on time consumes only 30.3 μW, compared to 188.8 μW and 179.7 μW for the same size level shift with TSPCDFF and level shift with master-slave DFF, respectively. The robust latching function can maintain phase information before disconnection and pass this pre-disconnection phase data to subsequent stages. The complementary input transistors of the switching buffer do not need to be designed too large, resulting in lower input parasitic capacitance and supporting faster VCOs. This R-RVCO design provides an effective tuning range from 1.4 GHz to 7 GHz with good linearity.

[0061] In summary, the present invention is summarized as follows.

[0062] (1) The analog-to-digital converter of the present invention is a Nyquist ADC based on a reset ring VCO, and has a single-channel sampling rate of 2GS / s. Compared with the traditional VCO-based Nyquist ADC, the ADC does not shape the quantization noise within the Nyquist bandwidth, thereby achieving a relatively high SQNR.

[0063] (2) Since the buffer of the multi-phase VCO output needs to operate at a frequency of up to several GHz, and the subsequent D flip-flop also consumes a lot of power, the present invention improves the fine quantizer and designs a switch buffer structure (including 2 (n+1) switch buffers), which not only realizes the buffering of phase information, but also can sample it, thereby significantly reducing power consumption. The switch buffer significantly reduces power consumption. At 7 GHz VCO output and 2 GHz sampling rate, the sw-buf with 90 ps turn-on time consumes only 30.3 μW. In comparison, the same size level conversion and TSPC DFF and level conversion and master-slave DFF consume 188.8 μW and 179.7 μW respectively.

[0064] (3) The analog-to-digital converter of the present invention further improves the fine quantizer and proposes a compact fine quantizer with phase folding function. Thanks to the unique characteristics of R-RVCO, the phase node of the first flip edge is known. Therefore, unlike the traditional VCO-based ADC, which needs to sample all phase nodes, the present invention only needs to sample half of the phase information. Compared with the fine quantizer traditionally used in VCO-based ADCs, this structure eliminates a large number of triggers and edge detectors.

[0065] Therefore, the analog-to-digital converter based on the reset ring oscillator (i.e., the Nyquist ADC based on VCO) supporting Nyquist bandwidth of the present invention has a single-channel sampling rate of 2 GS / s, and has no shaping of the quantization noise within the Nyquist bandwidth, thereby achieving a relatively high SQNR. The main innovations of the present invention include: 1) a fast reset ring VCO (R-RVCO); 2) a switch buffer (sw-buf); 3) a compact fine quantizer with phase folding function. The design of the present invention aims to significantly improve the signal-to-noise-distortion ratio (SNDR) and the quality factor (FOM), thereby providing better performance under high speed requirements.

[0066] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator, comprising: The sample-and-hold circuit uses the sampling signal Φ s Sampling analog signals V in And output digital control signal V ctrl ; NMOS tail current source tube M0, its gate receives V ctrl , with its source grounded; and Oscillator VCO , which includes n delay units, each delay unit has 4 input terminals IN1, IN0, , And 4 output terminals O1, O0, , ; Any of the four output terminals O1, O0, , Connect the four input terminals IN1, IN0, , , so that n delay units are connected end to end and delayed in sequence to form VCO Loop; It is characterized in that each input terminal IN1 is connected to an NMOS tube M SW1 The drain connection of each output With a PMOS tube M SW2 The drain connection of each input With a PMOS tube M SW3 Each output terminal O0 is connected to an NMOS tube M SW4 Drain connection; M SW1 、M SW4 The gate is controlled by the control signal Φ rst ;M SW2 、M SW3 The gate is controlled by the control signal , M SW1 、M SW4 The source of M0 is connected to the drain of M1. SW2 、M SW3 The source is connected to the voltage source V DD ; Control signal Φ rst With Φ s synchronous; The analog-to-digital converter further comprises: The voltage balancing circuit includes two MOS tubes M1 and M2 and a control signal Φ rst Two electric switches K M1 , K M2 ; The source of M1 is connected to the voltage source V DD , the drain of M1 passes through K M1 Connect the gate of M1, and the drain of M1 is connected through K M1 , K M2 Connect the drain of M2, and the gate of M1 is also connected to the gate of M2 and M SW1 、M SW4 The source of M2 is grounded; and The transmission gate unit TG is connected in series between the first delay unit and the nth delay unit.

2. The analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator according to claim 1, characterized in that: Each delay unit includes 8 inverters N1 to N8; the input terminals of N1 and N2 are IN1 and IN0 respectively, and the output terminals of N1 and N2 are connected to form ; The input terminals of N3 and N4 are , , the output ends of N3 and N4 are connected to form O0; the output end of N1 is also connected to the input end of N5, the output end of N3 is also connected to the input end of N8, the output ends of N5 and N6 are both O1, and the output ends of N7 and N8 are both ; The input terminals of N6 and N7 are 、IN1.

3. The analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator according to claim 1, characterized in that: The analog-to-digital converter further comprises: The coarse quantizer samples IN0 of the first delay unit, And perform coarse quantization, and thus obtain the output signal D CQ ; The fine quantizer samples IN1, IN0, , And fine quantization is performed, and the output signal D1~D is obtained 2（n+1） ; The encoder encodes the coarse quantization signal and the fine quantization signal into a binary code to obtain a digital signal. D out .

4. The analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator according to claim 3, characterized in that: The fine quantizer includes a control signal Φ buf 2 (n+1) switch buffers; every 2 switch buffers correspond to 1 delay unit, and the remaining 2 switch buffers correspond to the transmission gate unit TG; Among them, IN1, Input to the corresponding switch buffer's in-phase terminal and inverting terminal respectively, IN0, IN2, IN3, IN4, IN5, IN6, IN7, IN8, IN9, IN10, IN11, IN12, IN13, IN14, IN15, IN16, IN17, IN18, IN19, IN20, IN21, IN22, IN23, IN24, IN25, IN26, IN27, IN28, IN29, IN They are respectively input to the non-inverting terminal and the inverting terminal of another corresponding switch buffer, and the four outputs of the delay unit of the last stage are connected to the transmission gate unit. The inputs are respectively sent to the non-inverting terminal and the inverting terminal of a corresponding switch buffer, and the O0 and It is also input to the non-inverting terminal and the inverting terminal of the corresponding other switch buffer; so that the 2 (n + 1) switch buffers correspond to the 4 (n + 1) output signals output by the n delay units and a transmission gate unit, and the 2 (n + 1) switch buffers output D1~D 2（n+1） ; Control signal Φ buf The falling edge of Φ rst The rising edges are aligned and the high level time is X ps.

5. The analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator according to claim 4, characterized in that: Each switch buffer includes: 4 NMOS tubes M buf1 ~ M buf4 , 2 PMOS tubes M buf5 ~ M buf6 , 6 inverters N9~N 14 ;M buf1 and M buf2 The gates of the or IN0, , M buf1 and M buf2 The source of M is grounded. buf1 and M buf2 The drain of buf3 and M buf4 The source, M buf3 and M buf4 The gate connection, M buf3 and M buf4 The drain of M buf5 and M buf6 The drain, M buf5 and M buf6 The source of both are connected to V DD ;M buf5 The gate connection M buf6 The drain of N9 and the input of M buf6 The gate connection M buf5 The drain and N 10 The output of N9 is connected to N 11 The output terminal and N 12 The input terminal, N 12 The output terminal is connected to N 10 The output terminal, N 11 The input terminal, N 13 The input terminal, N 13 The output terminal is connected to N 14 The input terminal, N 14 The corresponding signal D at the output end belongs to D1~D 2（n+1） .

6. The analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator according to claim 4, characterized in that: The fine quantizer also includes a phase folding detector PF and a thermometer code-to-binary converter T2B; 2 (n+1) switch buffers sample 4 (n+1) phases of the ring oscillator to produce 2 (n+1) signals D1~D 2（n+1） , and output to the phase folding detector and the thermometer code-to-binary converter; Thermometer code to binary converter converts D1~D 2（n+1） Converted into binary output to the phase folding detector, the phase folding detector samples half of the phase information and converts the phase data according to the last flipped edge, i.e., D 2（n+1） Convert to low-order digital output code.

7. The analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator according to claim 3, characterized in that: The coarse quantizer includes a first-stage switch buffer that is always turned on, a buffer, a resettable fast asynchronous counter, a D flip-flop array, and a delay calibrator; IN0 of the first delay unit in the oscillator, The output is sent to the first-stage switch buffer, and then sent to the counter after passing through the buffer; the outputs of the two buffers and the counter are sampled by the D flip-flop array and then sent to the delay calibrator. 2（n+1） The signal is also output to the delay calibrator; the delay calibrator outputs the output signal D of the coarse quantizer CQ ; The sampling clock of the D flip-flop array is Φ cnt , and after a delay, it is used as the reset control signal of the counter. The control signal Φ cnt is the control signal Φ rst Delayed signal.

8. The analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator according to any one of claims 3 to 7, characterized in that: The encoder comprises a weighter; an output D of a fine quantizer FQ and the output of the coarse quantizer D CQ The final ADC output code D is output after the weighting device out ; Fine quantizer output D FQ As the low-order codeword, the output D of the coarse quantizer CQ It is a high-order code word.

9. The analog-to-digital converter supporting Nyquist bandwidth based on a reset ring oscillator according to claim 1, characterized in that: The sample-and-hold circuit includes a capacitor C s and is controlled by Φ s Sampling switch K s ; V in Through the sampling switch K s is sampled to capacitor C s Output V ctrl .

10. A differential analog-to-digital converter that converts a pair of analog differential input signals V in,n , V in,p Converted into a pair of digital differential signals D out,n , D out,p ; It is characterized in that, The differential analog-to-digital converter comprises two analog-to-digital converters supporting Nyquist bandwidth based on a reset ring oscillator according to any one of claims 1 to 9, respectively V in,n , V in,p Convert to corresponding D out,n , D out,p .

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