A clock mismatch calibration method for time-interleaved ADC

Abstract

The present invention discloses a clock mismatch calibration method for a time-interleaved ADC, and relates to the technical field of clock calibration, including dividing a TI-ADC into M sub-ADCs, selecting a pair of sub-ADCs with an interval of M / 2 for clock mismatch calibration, wherein M is an even number; taking two calibrated sub-ADCs as a reference, selecting a sub-ADC located between the two sub-ADCs for clock mismatch calibration; fixing the three calibrated sub-ADCs, and adjusting the gain of the first sub-ADC in the digital domain; performing clock mismatch calibration on the selected two sub-ADCs again with the gains of the first two sub-ADCs and the first sub-ADC; repeating steps S1 to S4 until all ADCs are calibrated. The method of the present invention effectively solves the problem of large clock mismatch calibration error caused by the coupling effect between gain mismatch and clock deviation, and simultaneously realizes digital domain compensation of gain and high-precision estimation of clock deviation.

Description

Technical Field

[0001] The invention relates to the technical field of clock calibration, in particular to a clock mismatch calibration method for a time-interleaved ADC. Background Art

[0002] With the rapid development of electronic technology and digital signal processing technology, analog-to-digital converters (ADCs) play an increasingly important role in modern communications, measurement, and control systems. In order to improve the sampling rate and resolution of ADCs, time interleaved technology is widely used. Time interleaved ADC (TI-ADC) uses multiple sub-ADCs in parallel, and each sub-ADC samples the input signal in an interleaved manner, thereby achieving a higher total sampling rate.

[0003] However, due to manufacturing process and environmental changes, there are mismatches such as gain, offset and clock mismatch between the sub-ADCs in the time-interleaved ADC system. These mismatches will cause a significant decline in system performance, especially the clock mismatch deviation will cause the inconsistency of the input signal on the time axis, which will cause distortion and noise in the spectrum. Therefore, timing calibration of the time-interleaved ADC to compensate for the clock mismatch deviation is one of the key technologies to ensure its high precision and high performance.

[0004] At present, the timing calibration technology of time-interleaved ADC is mainly divided into two categories: front-end calibration and back-end calibration. Front-end calibration uses hardware circuits to calibrate the signal before it enters the ADC, and adjusts the clock deviation of each sub-ADC in real time; back-end calibration processes the sampled data in the digital domain and compensates for the clock deviation through algorithms. Each method has its advantages and disadvantages. Front-end calibration can achieve real-time calibration, but the hardware complexity is high; back-end calibration hardware implementation is relatively simple, but it requires efficient algorithm support and usually increases calculation delays.

[0005] Due to the coupling effect between gain mismatch and timing deviation, they generate spurs at the same frequency in the frequency domain. When performing timing calibration on a time-interleaved ADC, the residual gain mismatch will cause timing calibration deviation, which in turn affects the performance of the ADC calibration. Therefore, there is an urgent need for a method that can effectively perform timing calibration when gain imbalance exists. Summary of the invention

[0006] In view of the above existing problems, the present invention is proposed.

[0007] Therefore, the present invention provides a clock mismatch calibration method for a time-interleaved ADC.

[0008] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0009] In a first aspect, an embodiment of the present invention provides a clock mismatch calibration method for a time-interleaved ADC, which includes step S1, dividing a TI-ADC into M sub-ADCs, selecting a pair of sub-ADCs with an interval of M / 2 for clock mismatch calibration, where M is an even number;

[0010] Step S2: taking the two calibrated sub-ADCs as a reference, selecting a sub-ADC located between the two sub-ADCs to perform clock mismatch calibration;

[0011] Step S3, fixing the three calibrated sub-ADCs, and adjusting the gain of the first sub-ADC in the digital domain;

[0012] Step S4, performing clock mismatch calibration again on the two selected sub-ADCs using the gains of the first two sub-ADCs and the first sub-ADC;

[0013] Repeat steps S1 to S4 until all ADCs are calibrated.

[0014] As a preferred solution of the clock mismatch calibration method of the time-interleaved ADC of the present invention, the clock mismatch calibration is performed on the sub-ADCs with an interval of M / 2 by the following formula:

[0015] ;

[0016] ;

[0017] Where: represents the gain error, N represents the number of discrete sampling data used for averaging; N0 represents the starting sequence number of the discrete sampling data, and E represents the mathematical period. represents the signal samples received from different sub-ADCs, represents the gain factor of the sub-ADC, represents the delay of sub-ADC 2 relative to sub-ADC 0, represents the delay of sub-ADC 0 relative to sub-ADC 2, is the autocorrelation function of the input signal, represents the total sampling period, , Indicates the absolute clock phase of the sub-ADC.

[0018] As a preferred solution of the clock mismatch calibration method of the time-interleaved ADC of the present invention, the clock mismatch calibration is performed on the sub-ADC located between the two sub-ADCs by the following formula:

[0019] ;

[0020] ;

[0021] In the formula, represents the delay of sub-ADC 1 relative to sub-ADC 0, Represents the phase delay of sub-ADC 2 relative to sub-ADC 1.

[0022] As a preferred solution of the clock mismatch calibration method of the time-interleaved ADC of the present invention, wherein: adjusting the gain of the first sub-ADC in the digital domain comprises the following steps:

[0023] Apply variable gain h0 to the signal in the digital domain;

[0024] Calculate the error signal between two adjacent word ADCs, denoted as E1 and E2, and the formula is expressed as

[0025] ;

[0026] ;

[0027] In the formula, represents the signal samples received by the sub-ADC, Represents the gain coefficient of the sub-ADC;

[0028] Calculate the error signal between error signal E1 and error signal E2, denoted as E 1,2 , the formula is expressed as,

[0029] ;

[0030] Adopt LMS adaptive update algorithm, use error signal E 1,2 Update the variable gain h0.

[0031] As a preferred solution of the clock mismatch calibration method of the time-interleaved ADC of the present invention, wherein: performing clock mismatch calibration on the two selected sub-ADCs again means that the updated digital gain h0 is used to repeatedly perform clock mismatch calibration on the two selected sub-ADCs until the variable gain finally converges. When the variable gain converges, .

[0032] The beneficial effects of the present invention are: effectively solving the problem of large clock mismatch calibration error caused by the coupling effect between gain mismatch and clock deviation, and realizing digital domain compensation of gain and high-precision estimation of clock deviation. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0034] Figure 1 It is a flowchart of the clock mismatch calibration method for the time-interleaved ADC in Embodiment 1. Specific Embodiments

[0035] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings of the specification.

[0036] In the following description, many specific details are set forth to facilitate a thorough understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0037] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that can be included in at least one implementation manner of the present invention. The "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that excludes other embodiments.

[0038] Embodiment 1, referring to Figure 1 , is the first embodiment of the present invention. This embodiment provides a clock mismatch calibration method for a time-interleaved ADC, including the following steps:

[0039] Step S1: Divide the TI-ADC into M sub-ADCs, where the serial number of the sub-ADC is m = 0, 1,..., M - 1, and the ADC sampling period is T s , then the sampling period of each sub-ADC is MT s , select a pair of sub-ADCs with an interval of M / 2 for clock mismatch calibration, where M is an even number, and 0 ≤ m < M. The timing deviation of each sub-ADC is τ m (0 ≤ m < M), and the difference in the timing deviation between two sub-ADCs i and j is Δ i,j = τ i - τ j .

[0040] Step S2: Taking the two calibrated sub-ADCs as a reference, select the sub-ADC located in the middle of the two sub-ADCs for clock mismatch calibration;

[0041] Step S3, fixing the three calibrated sub-ADCs, and adjusting the gain of the first sub-ADC in the digital domain;

[0042] Step S4, performing clock mismatch calibration again on the two selected sub-ADCs using the gains of the first two sub-ADCs and the first sub-ADC;

[0043] Repeat steps S1 to S4 until all ADCs are calibrated.

[0044] It should be noted that in the present invention, the clock mismatch calibration algorithm we use is based on the statistics of the related signals on the adjacent sub-ADCs. Assuming that the continuous signal input to the ADC is r(t), the discrete sampling signal after passing through the ADC can be expressed as:

[0045] .

[0046] Specifically, in step S1, clock mismatch calibration is performed on the sub-ADCs with an interval of M / 2 using the following formula:

[0047] ;

[0048] ;

[0049] Where: represents the gain error, N represents the number of discrete sampling data used for averaging; N0 represents the starting sequence number of the discrete sampling data, and E represents the mathematical period. represents the signal samples received from different sub-ADCs, represents the gain factor of the sub-ADC, represents the delay of sub-ADC 2 relative to sub-ADC 0, represents the delay of sub-ADC 0 relative to sub-ADC 2, is the autocorrelation function of the input signal, represents the total sampling period, , Indicates the absolute clock phase of the sub-ADC.

[0050] Furthermore, the clock mismatch calibration is performed on the sub-ADC located between the two sub-ADCs using the following formula:

[0051] ;

[0052] ;

[0053] In the formula, represents the delay of sub-ADC 1 relative to sub-ADC 0, Represents the phase delay of sub-ADC 2 relative to sub-ADC 1.

[0054] Adjusting the gain of the first sub-ADC in the digital domain includes the following steps:

[0055] Apply variable gain h0 to the signal in the digital domain;

[0056] Calculate the error signal between two adjacent word ADCs, denoted as E1 and E2, and the formula is expressed as

[0057] ;

[0058] ;

[0059] In the formula, represents the signal samples received by the sub-ADC, Represents the gain coefficient of the sub-ADC;

[0060] Calculate the error signal between error signal E1 and error signal E2, denoted as E 1,2 , the formula is expressed as,

[0061] ;

[0062] Adopt LMS adaptive update algorithm, use error signal E 1,2 Update the variable gain h0.

[0063] Preferably, re-calibrating the clock mismatch of the two selected sub-ADCs means that the updated digital gain h0 is used to repeatedly calibrate the clock mismatch of the two selected sub-ADCs until the variable gain finally converges. .

[0064] The method of the present invention effectively solves the problem of large clock mismatch calibration error caused by the coupling effect between gain mismatch and clock deviation, and simultaneously realizes digital domain compensation of gain and high-precision estimation of clock deviation.

[0065] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A clock mismatch calibration method for a time-interleaved ADC, characterized in that: include, Step S1, dividing the TI-ADC into M sub-ADCs, selecting a pair of sub-ADCs with an interval of M / 2 sub-ADCs for clock mismatch calibration, where M is an even number; Step S2: taking the two calibrated sub-ADCs as a reference, selecting a sub-ADC located between the two sub-ADCs to perform clock mismatch calibration; Step S3, fixing the three calibrated sub-ADCs, and adjusting the gain of the first sub-ADC among the three calibrated sub-ADCs in the digital domain; Step S4, performing clock mismatch calibration again on the two selected sub-ADCs using the gains of the first two sub-ADCs and the first sub-ADC; Repeat steps S1 to S4 until all ADCs are calibrated.

2. The clock mismatch calibration method for a time-interleaved ADC as claimed in claim 1, wherein: The clock mismatch calibration of the sub-ADC with an interval of M / 2 is performed by the following formula: ； ； Where: represents the gain error, E represents the mathematical expectation, represents the signal samples received from different sub-ADCs, represents the gain factor of the sub-ADC, represents the delay of sub-ADC 2 relative to sub-ADC 0, represents the delay of sub-ADC 0 relative to sub-ADC 2, is the autocorrelation function of the input signal, represents the total sampling period, , Indicates the absolute clock phase of the sub-ADC.

3. The clock mismatch calibration method for a time-interleaved ADC as claimed in claim 2, wherein: The clock mismatch calibration of the sub-ADC located between the two sub-ADCs is performed using the following formula: ； ； In the formula, represents the delay of sub-ADC 1 relative to sub-ADC 0, Represents the phase delay of sub-ADC 2 relative to sub-ADC 1.

4. The clock mismatch calibration method for a time-interleaved ADC as claimed in claim 3, characterized in that: Adjusting the gain of the first sub-ADC in the digital domain includes the following steps: Apply variable gain h0 to the signal in the digital domain; Calculate the error signal between two adjacent word ADCs, denoted as E1 and E2, and the formula is expressed as ； ； In the formula, represents the signal samples received by the sub-ADC, Represents the gain coefficient of the sub-ADC; Calculate the error signal between error signal E1 and error signal E2, denoted as E 1,2 , the formula is expressed as, ； Adopt LMS adaptive update algorithm, use error signal E 1,2 Update the variable gain h0.

5. The clock mismatch calibration method for a time-interleaved ADC as claimed in claim 4, characterized in that: The clock mismatch calibration of the two selected sub-ADCs is repeated by using the updated digital gain h0 to calibrate the clock mismatch of the two selected sub-ADCs until the variable gain finally converges. .

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