Flash-ADC circuit and module with three-stage comparison

Abstract

The present invention relates to the technical field of analog-to-digital conversion circuit design, and in particular to a Flash-ADC circuit and module with a three-stage comparison stage. The present invention provides a newly designed Flash-ADC circuit that converts 15 reference voltages VREF1 to VREF 15 The comparison is divided into three stages; the comparison result of the first stage controls the selection of the reference voltage of the second stage, and the comparison results of the first and second stages control the selection of the reference voltage of the third stage, thereby avoiding directly comparing all 15 reference voltages with the input voltage, reducing the number of comparators in the circuit and the number of components of the output encoding circuit, and also reducing the number of comparisons performed, thereby greatly reducing the power consumption and area of ​​the Flash-ADC circuit. The present invention solves the problem that the existing Flash ADC has a large area and power consumption due to the number of comparators.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion circuit design, and more specifically to: 1. a Flash-ADC circuit with three-level comparison stages; 2. a Flash-ADC module with three-level comparison stages. Background Art

[0002] Today's software, radio, and digital image acquisition all require high-speed analog-to-digital converter sampling to ensure effectiveness and accuracy. General measurement and control systems also hope to make breakthroughs in accuracy. Analog-to-digital converters have undergone many technological innovations, from Flash, SAR, and integral ADCs to the newly developed ∑-Δ and Pipeline ADCs in recent years. They each have their own advantages and disadvantages and can meet the needs of different applications.

[0003] In the field of in-memory computing, Flash ADC has been widely used due to its fast speed and simple structure. General analog domain in-memory computing requires quantizing the output analog multiplication and accumulation results to obtain digital output. Analog domain in-memory computing is divided into charge domain and current domain. In the charge domain, since the analog output results are stored in capacitors as carriers, there is no need to use circuits to quantize the analog results, and the Flash ADC used for quantizing in-memory computing results can be further simplified.

[0004] However, the power consumption of Flash ADC is mainly generated by the comparator. The number of comparators required by traditional Flash ADC increases exponentially with the increase of the number of quantization bits. At the same time, the increase in the number of comparators will also cause the area of ​​the overall circuit to increase. Therefore, how to reduce the area and power consumption of Flash ADC has become a major problem. Summary of the invention

[0005] Based on this, it is necessary to provide a Flash-ADC circuit and module with three-level comparison stages to address the problem that the existing Flash ADC has a large area and power consumption due to the number of comparators.

[0006] The present invention is implemented by the following technical solutions:

[0007] In a first aspect, the present invention provides a Flash-ADC circuit having a three-stage comparison stage, which is used to combine 15 reference voltages VREF1~VREF 15 To convert the input voltage VIN into a 4-bit digital quantity.

[0008] Among them, VREF n =n*VREF / 16; n∈[1,15]; VREF∈[0,VDD], VREF represents the analog voltage, and VDD represents the power supply voltage.

[0009] The Flash-ADC circuit with three comparison stages comprises: a first-stage comparison circuit, a second-stage comparison circuit, and a third-stage comparison circuit.

[0010] The first stage comparison circuit includes a rail-to-rail comparator C1.

[0011] Wherein, C1 is used to compare VIN and VREF8 under the control of the control signal CLK1 to obtain the highest bit Y3 of the 4-bit digital value.

[0012] The second-stage comparison circuit includes a two-to-one selector M1 and a rail-to-rail comparator C2.

[0013] Among them, M1 is used to select VREF4 or VREF under the control of Y3. 12 As the output voltage VC2, C2 is used to compare VIN and VC2 under the control of the control signal CLK2 to obtain the second highest bit Y2 of the 4-bit digital quantity.

[0014] The third-stage comparison circuit includes three four-to-one selectors M2-M4, three rail-to-rail comparators C3-C5, and one output encoding circuit.

[0015] Among them, M2 is used to select VREF1, VREF5, VREF9, VREF under the common control of Y3 and Y2. 13 One of them is used as the output voltage VC3, C3 is used to compare VIN and VC3 under the control of the control signal CLK3 to obtain the output signal C3O; M3 is used to select VREF2, VREF6, VREF under the common control of Y3 and Y2. 10 、VREF 14 One of them is used as the output voltage VC4. C4 is used to compare VIN and VC4 under the control of CLK3 to obtain the second lowest bit Y1 of the 4-bit digital quantity; M4 is used to select VREF3, VREF7, VREF under the common control of Y3 and Y2. 11 、VREF 15 One of them is used as the output voltage VC5, C5 is used to compare VIN and VC5 under the control of CLK3 to obtain the output signal C5O; the output encoding circuit is used to combine C3O, Y1, and C3O to output the lowest bit Y0 of the 4-bit digital quantity.

[0016] The implementation of the Flash-ADC circuit with three comparison stages is a method or process according to an embodiment of the present disclosure.

[0017] In a second aspect, the present invention discloses a Flash-ADC module with three-stage comparison stages, which adopts the layout of the three-stage comparison stage Flash-ADC circuit disclosed in the first aspect.

[0018] The implementation of the storage-calculation circuit based on the Flash-ADC circuit with three-stage comparison stage is a method or process according to an embodiment of the present disclosure.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. The present invention provides a newly designed Flash-ADC circuit, which converts 15 reference voltages VREF1~VREF 15 The comparison is divided into three stages; the comparison result of the first stage controls the selection of the reference voltage of the second stage, and the comparison results of the first and second stages control the selection of the reference voltage of the third stage, thereby avoiding directly comparing all 15 reference voltages with the input voltage, reducing the number of comparators in the circuit, the number of devices in the output encoding circuit, and the number of comparisons performed, thereby greatly reducing the power consumption and area of ​​the Flash ADC circuit.

[0021] 2. The present invention designs a voltage divider circuit based on the binary method to convert the analog voltage VREF into 15 reference voltages VREF1~VREF 15 , providing enough options for possible comparison situations to cover various situations of 4-bit analog-to-digital conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] Figure 1 A circuit diagram of a first Flash-ADC circuit with three-stage comparison stages provided in Embodiment 1 of the present invention;

[0024] Figure 2 for Figure 1 The circuit diagram of M1 in the figure;

[0025] Figure 3 for Figure 1 The circuit diagram of M2~M4;

[0026] Figure 4 for Figure 1 The timing description diagram of CLK1~CLK3, Y3~Y0;

[0027] Figure 5 for Figure 1 The timing simulation diagram of the Flash-ADC circuit when it is working;

[0028] Figure 6 To generate Figure 1 VREF1~VREF 15 Circuit diagram of the voltage divider circuit;

[0029] Figure 7 A structural diagram of a first Flash-ADC module with three-stage comparison stages provided in Embodiment 2 of the present invention;

[0030] Figure 8 This is a structural diagram of a second Flash-ADC module with three comparison stages provided in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0034] The Flash-ADC circuit with three comparison stages provided by the present invention is intended to combine 15 reference voltages VREF1~VREF 15 The input voltage VIN is converted into a 4-bit digital quantity to realize the analog-to-digital conversion function.

[0035] It should be noted that VREF n =n*VREF / 16; n∈[1,15].

[0036] Wherein, VREF represents the analog voltage, VREF∈[0,VDD], and VDD represents the power supply voltage.

[0037] Example 1

[0038] See also Figure 1 , is a circuit structure diagram of the first Flash-ADC circuit with three-stage comparison provided in this embodiment 1. From the perspective of function / comparison stage, the Flash-ADC circuit includes: a first-stage comparison circuit, a second-stage comparison circuit, and a third-stage comparison circuit.

[0039] The following are introduced separately:

[0040] (i) The first stage comparison circuit includes: 1 rail-to-rail comparator C1.

[0041] Wherein, C1 is used to compare VIN and VREF8 under the control of the control signal CLK1 to obtain the highest bit Y3 of the 4-bit digital value.

[0042] like Figure 1 As shown, the connection relationship of C1 is as follows:

[0043] The positive input terminal of C1 is connected to VIN, the negative input terminal is connected to VREF8, the control terminal is connected to CLK1, and the output terminal is used to output Y3.

[0044] (ii) The second-stage comparison circuit includes: a two-to-one selector M1 and a rail-to-rail comparator C2.

[0045] Among them, M1 is used to select VREF4 or VREF under the control of Y3. 12 As output voltage VC2;

[0046] C2 is used to compare VIN and VC2 under the control of the control signal CLK2 to obtain the second highest bit Y2 of the 4-bit digital quantity.

[0047] like Figure 1 As shown, the connection relationship between M1 and C2 is as follows:

[0048] Input terminal 1 of M1 is connected to VREF4, and input terminal 2 is connected to VREF 12 , the control end is connected to Y3, and the output end is used to output VC2.

[0049] The positive input terminal of C2 is connected to VIN, the negative input terminal is connected to VC2, the control terminal is connected to CLK2, and the output terminal is used to output Y2.

[0050] For details, see Figure 2 , M1 includes: 1 inverter INV2, 2 transmission gates TG1~TG2;

[0051] The input terminal of INV2, the negative control terminal of TG1, and the positive control terminal of TG2 are all connected to Y3;

[0052] The output end of INV2 is connected to the positive control end of TG1 and the negative control end of TG2;

[0053] The input end of TG1 is connected to VREF4, and the output end is connected to VC2;

[0054] The input of TG2 is connected to VREF 12 , the output end is connected to VC2.

[0055] (iii) The third-level comparison circuit includes three four-to-one selectors M2~M4, three rail-to-rail comparators C3~C5, and one output encoding circuit.

[0056] Among them, M2 is used to select VREF1, VREF5, VREF9, VREF under the common control of Y3 and Y2. 13 One of them is used as the output voltage VC3;

[0057] C3 is used to compare VIN and VC3 under the control of control signal CLK3 to obtain output signal C3O;

[0058] M3 is used to select VREF2, VREF6, and VREF under the common control of Y3 and Y2. 10 、VREF 14 One of them is used as the output voltage VC4;

[0059] C4 is used to compare VIN and VC4 under the control of CLK3 to obtain the second lowest bit Y1 of the 4-bit digital quantity;

[0060] M4 is used to select VREF3, VREF7, VREF under the common control of Y3 and Y2. 11 、VREF 15 One of them is used as the output voltage VC5;

[0061] C5 is used to compare VIN and VC5 under the control of CLK3 to obtain the output signal C5O;

[0062] The output encoding circuit is used to combine C3O, Y1, and C3O to output the lowest bit Y0 of the 4-bit digital quantity.

[0063] like Figure 1 As shown, the connection relationship between M2~M4, C3~C5 and output encoding circuit is as follows:

[0064] Input 1 of M2 is connected to VREF1, input 2 is connected to VREF5, input 3 is connected to VREF9, and input 4 is connected to VREF 13 , control terminal 1 is connected to Y3, control terminal 2 is connected to Y2, and the output terminal is used to output VC3;

[0065] The positive input terminal of C3 is connected to VIN, the negative input terminal is connected to VC3, the control terminal is connected to CLK3, and the output terminal is used to output C3O;

[0066] Input 1 of M3 is connected to VREF2, input 2 is connected to VREF6, and input 3 is connected to VREF 10 、Input terminal 4 connects to VREF 14 , control terminal 1 is connected to Y3, control terminal 2 is connected to Y2, and the output terminal is used to output VC4;

[0067] The positive input terminal of C3 is connected to VIN, the negative input terminal is connected to VC4, the control terminal is connected to CLK3, and the output terminal is used to output Y1;

[0068] Input 1 of M4 is connected to VREF3, input 2 is connected to VREF7, and input 3 is connected to VREF 11 、Input terminal 4 connects to VREF 15 , control terminal 1 is connected to Y3, control terminal 2 is connected to Y2, and the output terminal is used to output VC5;

[0069] The positive input terminal of C5 is connected to VIN, the negative input terminal is connected to VC5, the control terminal is connected to CLK3, and the output terminal is used to output C5O;

[0070] The output encoding circuit includes: an inverter INV1, an AND gate AND1, and an OR gate OR1;

[0071] The input end of INV1 is connected to Y1, and the output end is used to output the reverse signal Y1B;

[0072] Input terminal 1 of AND1 is connected to C3O, input terminal 2 is connected to Y1B, and the output terminal is used to output signal VL1;

[0073] Input terminal 1 of OR1 is connected to VL1, input terminal 2 is connected to C5O, and the output terminal is used to output Y0.

[0074] It should be noted that, see Figure 3 , M2~M4 have the same structure, all including: 1 2 to 4 decoding circuit, 4 transmission gates TG3~TG6; the 2 to 4 decoding circuit includes: 6 inverters INV3~INV8, 4 AND2~AND5.

[0075] In any of the four selectors:

[0076] The input end of INV3 is connected to Y2, and the output end is used to output the reverse signal Y2B;

[0077] The input end of INV4 is connected to Y3, and the output end is used to output the reverse signal Y3B;

[0078] The input terminal 1 of AND2 is connected to Y2B, the input terminal 2 is connected to Y3B, and the output terminal is used to output the control signal D0;

[0079] The input end of INV5 is connected to D0, and the output end is used to output the reverse signal D0B;

[0080] The input terminal 1 of AND3 is connected to Y2, the input terminal 2 is connected to Y3B, and the output terminal is used to output the control signal D1;

[0081] The input end of INV6 is connected to D1, and the output end is used to output the reverse signal D1B;

[0082] The input terminal 1 of AND4 is connected to Y2B, the input terminal 2 is connected to Y3, and the output terminal is used to output the control signal D2;

[0083] The input end of INV7 is connected to D2, and the output end is used to output the reverse signal D2B;

[0084] The input terminal 1 of AND4 is connected to Y2, the input terminal 2 is connected to Y3, and the output terminal is used to output the control signal D3;

[0085] The input end of INV8 is connected to D3, and the output end is used to output the reverse signal D3B;

[0086] The positive control terminal of TG3 is connected to D0, the negative control terminal is connected to D0B, and the input terminal is connected to the reference voltage VREF A , the output terminal is used to output a control signal OUT;

[0087] The positive control terminal of TG4 is connected to D1, the negative control terminal is connected to D1B, and the input terminal is connected to the reference voltage VREF B , the output terminal is used to output a control signal OUT;

[0088] The positive control terminal of TG5 is connected to D2, the negative control terminal is connected to D2B, and the input terminal is connected to the reference voltage VREF C , the output terminal is used to output a control signal OUT;

[0089] The positive control terminal of TG6 is connected to D3, the negative control terminal is connected to D3B, and the input terminal is connected to the reference voltage VREF D , the output terminal is used to output the control signal OUT.

[0090] Then, in M2, VREF A VREF1, VREF B VREF5, VREF C VREF9, VREF D VREF 13 , OUT is VC3;

[0091] In M3, VREFA VREF2, VREF B VREF6, VREF C VREF 10 , VREF D VREF 14 , OUT is VC4;

[0092] In M4, VREF A VREF3, VREF B VREF7, VREF C VREF 11 , VREF D VREF 15 , OUT is VC5.

[0093] For the first Flash-ADC circuit mentioned above, VREF1~VREF 15 Independent control can be used, just ensure VREF n =n*VREF / 16.

[0094] In addition, the pre-charge time T of C1~C5 Pre Same, delay time T delay Same, output reading time T out same.

[0095] See also Figure 4 , CLK1, CLK2, CLK3 have the same period, but different duty cycles:

[0096] In one cycle of CLK1, the low level duration is T Pre , high level duration is 3*T delay +T out ;

[0097] In one cycle of CLK2, the low level duration is T Pre +T delay , high level duration is 2*T delay +T out ;

[0098] In one cycle of CLK3, the low level duration is T Pre +2*T delay , high level time is T delay +T out .

[0099] That is:

[0100] When CLK1=“0”, C1 is precharged; after T PreAfter that, CLK1 jumps to the high level. At this time, CLK1 = "1", and C1 makes a comparison; after T delay After that, Y3 is output; after T out After that, Y3 can be read out.

[0101] When CLK2 = "0", C2 is pre-charged; after T Pre After that, CLK2 jumps to the high level. At this time, CLK2 = "1", and C2 makes a comparison; after T delay After that, Y2 is output; after T out After that, Y2 can be read out.

[0102] When CLK3 = "0", C3 - C5 are pre-charged; after T Pre After that, CLK3 jumps to the high level. At this time, CLK3 = "1", and C3 - C5 make a comparison; after T delay After that, Y1 is output. At the same time, the results of C3 - C5 pass through the output encoding circuit, and Y0 is output; after T out After that, Y1 and Y0 can be read out.

[0103] Based on the above first Flash-ADC circuit, there are 16 situations in total for its analog-to-digital conversion:

[0104] Taking VREF = 800mV as an example, then:

[0105] VREF1 = 50mV; VREF2 = 100mV; VREF3 = 150mV; VREF4 = 200mV;

[0106] VREF5 = 250mV; VREF6 = 300mV; VREF7 = 350mV; VREF8 = 400mV;

[0107] VREF9 = 450mV; VREF 10 = 500mV; VREF 11 = 550mV; VREF 12 = 600mV;

[0108] VREF 13 = 650mV; VREF 14 = 700mV; VREF 15 = 750mV.

[0109] (1) If VIN is within the range of 0 to VREF1 (50mV),

[0110] In the first stage, the positive input terminal of C1 is connected to VIN, and the negative terminal is connected to VREF8 (400mV); when CLK1 jumps to the high level, C1 starts to compare. Since VIN < VREF8, Y3 is "0";

[0111] In the second stage, M1 is controlled by Y3(0), and VREF4(200mV) is selected as VC2; the positive input terminal of C2 is connected to VIN, the negative input terminal is connected to VREF4(200mV), CLK2 jumps to the high level, C2 starts to compare, VIN<VREF4, and Y2 is "0";

[0112] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2(00). M2 selects VREF1(50mV) as VC3, M3 selects VREF2(100mV) as VC4, and M4 selects VREF3(150mV) as VC5; the positive input terminal of C3 is connected to VIN, the negative input terminal is connected to VREF1(50mV), the positive input terminal of C4 is connected to VIN, the negative input terminal is connected to VREF2(100mV), and the positive input terminal of C5 is connected to VIN, the negative input terminal is connected to VREF3(150mV); CLK3 jumps to the high level, C3, C4, and C5 start to compare simultaneously, VIN<VREF1<VREF2<VREF3, C3O is "0", Y1 is "0", and C5O is "0"; Y1B is "1", VL1 = C3O⊙Y1B, VL1 is "0", Y0 = VL1⊕C5O, and Y0 is "0"; then the final 4-bit output Y3Y2Y1Y0 = "0000".

[0113] (2) If VIN is within the range of VREF1(50mV) to VREF2(100mV),

[0114] In the first stage, the positive input terminal of C1 is connected to VIN, and the negative terminal is connected to VREF8(400mV); CLK1 jumps to the high level, C1 starts to compare, VIN<VREF8, and Y3 is "0";

[0115] In the second stage, M1 is controlled by Y3(0), and VREF4(200mV) is selected as VC2; the positive input terminal of C2 is connected to VIN, the negative input terminal is connected to VREF4(200mV), CLK2 jumps to the high level, C2 starts to compare, VIN<VREF4, and Y2 is "0";

[0116] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2(00). M2 selects VREF1(50mV) as VC3, M3 selects VREF2(100mV) as VC4, and M4 selects VREF3(150mV) as VC5. The positive input terminal of C3 is connected to VIN, and the negative input terminal is connected to VREF1(50mV). The positive input terminal of C4 is connected to VIN, and the negative input terminal is connected to VREF2(100mV). The positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF3(150mV). When CLK3 jumps to the high level, C3, C4, and C5 start to compare simultaneously. Since VREF1<VIN<VREF2<VREF3, C3O is "1", Y1 is "0", and C5O is "0". Y1B is "1", VL1 = C3O⊙Y1B, so VL1 is "1", and Y0 = VL1⊕C5O, so Y0 is "1". Then the final 4-bit output Y3Y2Y1Y0 = "0001".

[0117] (3) If VIN is in the range of VREF2(100mV) to VREF3(150mV),

[0118] In the first stage, the positive input terminal of C1 is connected to VIN, and the negative terminal is connected to VREF8(400mV). When CLK1 jumps to the high level, C1 starts to compare. Since VIN<VREF8, Y3 is "0".

[0119] In the second stage, M1 is controlled by Y3(0) and selects VREF4(200mV) as VC2. The positive input terminal of C2 is connected to VIN, and the negative input terminal is connected to VREF4(200mV). When CLK2 jumps to the high level, C2 starts to compare. Since VIN<VREF4, Y2 is "0".

[0120] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2(00). M2 selects VREF1(50mV) as VC3, M3 selects VREF2(100mV) as VC4, and M4 selects VREF3(150mV) as VC5. The positive input terminal of C3 is connected to VIN, and the negative input terminal is connected to VREF1(50mV). The positive input terminal of C4 is connected to VIN, and the negative input terminal is connected to VREF2(100mV). The positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF3(150mV). When CLK3 jumps to the high level, C3, C4, and C5 start to compare simultaneously. Since VREF1<VREF2<VIN<VREF3, C3O is "1", Y1 is "1", and C5O is "0". Y1B is "0", VL1 = C3O⊙Y1B, so VL1 is "0", and Y0 = VL1⊕C5O, so Y0 is "0". Then the final 4-bit output Y3Y2Y1Y0 = "0010".

[0121] (4) If VIN is within the range of VREF3 (150 mV) to VREF4 (200 mV),

[0122] In the first stage, the positive input terminal of C1 is connected to VIN, and the negative terminal is connected to VREF8 (400 mV); CLK1 jumps to the high level, C1 starts to compare, VIN < VREF8, and Y3 is "0";

[0123] In the second stage, M1 is controlled by Y3 (0) and selects VREF4 (200 mV) as VC2; the positive input terminal of C2 is connected to VIN, and the negative input terminal is connected to VREF4 (200 mV), CLK2 jumps to the high level, C2 starts to compare, VIN < VREF4, and Y2 is "0";

[0124] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2 (00). M2 selects VREF1 (50 mV) as VC3, M3 selects VREF2 (100 mV) as VC4, and M4 selects VREF3 (150 mV) as VC5; the positive input terminal of C3 is connected to VIN, and the negative input terminal is connected to VREF1 (50 mV), the positive input terminal of C4 is connected to VIN, and the negative input terminal is connected to VREF2 (100 mV), the positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF3 (150 mV); CLK3 jumps to the high level, C3, C4, and C5 start to compare simultaneously, VREF1 < VREF2 < VREF3 < VIN, C3O is "1", Y1 is "1", C5O is "1"; Y1B is "0", VL1 = C3O ⊙ Y1B, VL1 is "0", Y0 = VL1 ⊕ C5O, Y0 is "1"; then the final 4-bit output Y3Y2Y1Y0 = "0011".

[0125] (5) If VIN is within the range of VREF4 (200 mV) to VREF5 (250 mV),

[0126] In the first stage, the positive input terminal of C1 is connected to VIN, and the negative terminal is connected to VREF8 (400 mV); CLK1 jumps to the high level, C1 starts to compare, VIN < VREF8, and Y3 is "0";

[0127] In the second stage, M1 is controlled by Y3 (0) and selects VREF4 (200 mV) as VC2; the positive input terminal of C2 is connected to VIN, and the negative input terminal is connected to VREF4 (200 mV), CLK2 jumps to the high level, C2 starts to compare, VIN > VREF4, and Y2 is "1";

[0128] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2(01). M2 selects VREF5(250 mV) as VC3, M3 selects VREF6(300 mV) as VC4, and M4 selects VREF7(350 mV) as VC5; the positive input terminal of C3 is connected to VIN, and the negative input terminal is connected to VREF5(250 mV). The positive input terminal of C4 is connected to VIN, and the negative input terminal is connected to VREF6(300 mV). The positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF7(350 mV); when CLK3 jumps to the high level, C3, C4, and C5 start to compare simultaneously. Since VIN < VREF5 < VREF6 < VREF7, C3O is "0", Y1 is "0", and C5O is "0"; Y1B is "1", VL1 = C3O ⊙ Y1B, VL1 is "0", Y0 = VL1 ⊕ C5O, and Y0 is "0"; thus, the final 4-bit output Y3Y2Y1Y0 = "0100".

[0129] (6)If VIN is within the range of VREF5(250 mV) to VREF6(300 mV),

[0130] In the first stage, the positive input terminal of C1 is connected to VIN, and the negative terminal is connected to VREF8(400 mV); when CLK1 jumps to the high level, C1 starts to compare. Since VIN < VREF8, Y3 is "0";

[0131] In the second stage, M1 is controlled by Y3(0) and selects VREF4(200 mV) as VC2; the positive input terminal of C2 is connected to VIN, and the negative input terminal is connected to VREF4(200 mV). When CLK2 jumps to the high level, C2 starts to compare. Since VIN > VREF4, Y2 is "1";

[0132] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2(01). M2 selects VREF5(250 mV) as VC3, M3 selects VREF6(300 mV) as VC4, and M4 selects VREF7(350 mV) as VC5; the positive input terminal of C3 is connected to VIN, and the negative input terminal is connected to VREF5(250 mV). The positive input terminal of C4 is connected to VIN, and the negative input terminal is connected to VREF6(300 mV). The positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF7(350 mV); when CLK3 jumps to the high level, C3, C4, and C5 start to compare simultaneously. Since VREF5 < VIN < VREF6 < VREF7, C3O is "1", Y1 is "0", and C5O is "0"; Y1B is "1", VL1 = C3O ⊙ Y1B, VL1 is "1", Y0 = VL1 ⊕ C5O, and Y0 is "1"; thus, the final 4-bit output Y3Y2Y1Y0 = "0101".

[0133] (7) If VIN is within the range of VREF6 (300 mV) to VREF7 (350 mV),

[0134] In the first stage, the positive input terminal of C1 is connected to VIN, and the negative terminal is connected to VREF8 (400 mV); CLK1 jumps to the high level, C1 starts to compare, VIN < VREF8, and Y3 is "0";

[0135] In the second stage, M1 is controlled by Y3 (0) and selects VREF4 (200 mV) as VC2; the positive input terminal of C2 is connected to VIN, and the negative input terminal is connected to VREF4 (200 mV), CLK2 jumps to the high level, C2 starts to compare, VIN > VREF4, and Y2 is "1";

[0136] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2 (01). M2 selects VREF5 (250 mV) as VC3, M3 selects VREF6 (300 mV) as VC4, and M4 selects VREF7 (350 mV) as VC5; the positive input terminal of C3 is connected to VIN, and the negative input terminal is connected to VREF5 (250 mV), the positive input terminal of C4 is connected to VIN, and the negative input terminal is connected to VREF6 (300 mV), the positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF7 (350 mV); CLK3 jumps to the high level, C3, C4, and C5 start to compare simultaneously, VREF5 < VREF6 < VIN < VREF7, C3O is "1", Y1 is "1", and C5O is "0"; Y1B is "0", VL1 = C3O ⊙ Y1B, VL1 is "0", Y0 = VL1 ⊕ C5O, and Y0 is "0"; then the final 4-bit output Y3Y2Y1Y0 = "0110".

[0137] (8) If VIN is within the range of VREF7 (350 mV) to VREF8 (400 mV),

[0138] In the first stage, the positive input terminal of C1 is connected to VIN, and the negative terminal is connected to VREF8 (400 mV); CLK1 jumps to the high level, C1 starts to compare, VIN < VREF8, and Y3 is "0";

[0139] In the second stage, M1 is controlled by Y3 (0) and selects VREF4 (200 mV) as VC2; the positive input terminal of C2 is connected to VIN, and the negative input terminal is connected to VREF4 (200 mV), CLK2 jumps to the high level, C2 starts to compare, VIN > VREF4, and Y2 is "1";

[0140] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2(01). M2 selects VREF5(250mV) as VC3, M3 selects VREF6(300mV) as VC4, and M4 selects VREF7(350mV) as VC5. The positive input terminal of C3 is connected to VIN, and the negative input terminal is connected to VREF5(250mV). The positive input terminal of C4 is connected to VIN, and the negative input terminal is connected to VREF6(300mV). The positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF7(350mV). When CLK3 jumps to the high level, C3, C4, and C5 start to compare simultaneously. Since VREF5 < VREF6 < VREF7 < VIN, C3O is "1", Y1 is "1", and C5O is "1". Y1B is "0", VL1 = C3O ⊙ Y1B, so VL1 is "0", and Y0 = VL1 ⊕ C5O, so Y0 is "1". Then the final 4-bit output Y3Y2Y1Y0 = "0111".

[0141] (9)If VIN is within the range of VREF8(400mV) to VREF9(450mV),

[0142] In the first stage, the positive input terminal of C1 is connected to VIN, and the negative terminal is connected to VREF8(400mV). When CLK1 jumps to the high level, C1 starts to compare. Since VIN > VREF8, Y3 is "1".

[0143] In the second stage, M1 is controlled by Y3(0) and selects VREF 12 (600mV)as VC2. The positive input terminal of C2 is connected to VIN, and the negative input terminal is connected to VREF 12 (600mV). When CLK2 jumps to the high level, C2 starts to compare. Since VIN < VREF 12 , Y2 is "0".

[0144] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2(10). M2 selects VREF9(450mV) as VC3, M3 selects VREF 10 (500mV)as VC4, and M4 selects VREF 11 (550mV)as VC5. The positive input terminal of C3 is connected to VIN, and the negative input terminal is connected to VREF9(450mV). The positive input terminal of C4 is connected to VIN, and the negative input terminal is connected to VREF 10 (500mV). The positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF 11 (550mV). When CLK3 jumps to the high level, C3, C4, and C5 start to compare simultaneously. Since VIN < VREF9 < VREF 10 <VREF 11, C3O is "0", Y1 is "0", C5O is "0"; Y1B is "1", VL1=C3O⊙Y1B, VL1 is "0", Y0=VL1⊕C5O, Y0 is "0"; then the final 4-bit output is Y3Y2Y1Y0="1000".

[0145] (10) If VIN is between VREF9 (450mV) and VREF 10 (500mV) range,

[0146] In the first stage, the positive input terminal of C1 is connected to VIN and the negative terminal is connected to VREF8 (400mV); CLK1 jumps to a high level, C1 starts to compare, VIN>VREF8, and Y3 is "1";

[0147] In the second stage, M1 is controlled by Y3 (0) and VREF is selected. 12 (600mV) as VC2; the positive input of C2 is connected to VIN and the negative input is connected to VREF 12 (600mV), CLK2 jumps to high level, C2 starts to compare, VIN<VREF 12 , Y2 is "0";

[0148] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2 (10). M2 selects VREF9 (450mV) as VC3, and M3 selects VREF 10 (500mV) as VC4, M4 gates VREF 11 (550mV) as VC5; the positive input of C3 is connected to VIN, the negative input is connected to VREF9 (450mV), the positive input of C4 is connected to VIN, the negative input is connected to VREF 10 (500mV), the positive input of C5 is connected to VIN, and the negative input is connected to VREF 11 (550mV); CLK3 jumps to high level, C3, C4, C5 start to compare at the same time, VREF9 <VIN<VREF 10 <VREF 11 , C3O is "1", Y1 is "0", C5O is "0"; Y1B is "1", VL1=C3O⊙Y1B, VL1 is "1", Y0=VL1⊕C5O, Y0 is "1"; then the final 4-bit output is Y3Y2Y1Y0="1001".

[0149] (11) If VIN is within VREF 10 (500mV)~VREF 11 (550mV) range,

[0150] In the first stage, the positive input terminal of C1 is connected to VIN and the negative terminal is connected to VREF8 (400mV); CLK1 jumps to a high level, C1 starts to compare, VIN>VREF8, and Y3 is "1";

[0151] In the second stage, M1 is controlled by Y3 (0) and VREF is selected. 12 (600mV) as VC2; the positive input of C2 is connected to VIN and the negative input is connected to VREF 12 (600mV), CLK2 jumps to high level, C2 starts to compare, VIN<VREF 12 , Y2 is "0";

[0152] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2 (10). M2 selects VREF9 (450mV) as VC3, and M3 selects VREF 10 (500mV) as VC4, M4 gates VREF 11 (550mV) as VC5; the positive input of C3 is connected to VIN, the negative input is connected to VREF9 (450mV), the positive input of C4 is connected to VIN, the negative input is connected to VREF 10 (500mV), the positive input of C5 is connected to VIN, and the negative input is connected to VREF 11 (550mV); CLK3 jumps to high level, C3, C4, C5 start to compare at the same time, VREF9<VREF 10 <VIN<VREF 11 , C3O is "1", Y1 is "1", C5O is "0"; Y1B is "0", VL1=C3O⊙Y1B, VL1 is "0", Y0=VL1⊕C5O, Y0 is "0"; then the final 4-bit output is Y3Y2Y1Y0="1010".

[0153] (12) If VIN is within VREF 11 (550mV)~VREF 12 (600mV) range,

[0154] In the first stage, the positive input terminal of C1 is connected to VIN and the negative terminal is connected to VREF8 (400mV); CLK1 jumps to a high level, C1 starts to compare, VIN>VREF8, and Y3 is "1";

[0155] In the second stage, M1 is controlled by Y3 (0) and VREF is selected. 12 (600mV) as VC2; the positive input of C2 is connected to VIN and the negative input is connected to VREF 12 (600mV), CLK2 jumps to high level, C2 starts to compare, VIN<VREF 12, Y2 is "0";

[0156] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2 (10). M2 selects VREF9 (450 mV) as VC3, M3 selects VREF 10 (500 mV) as VC4, and M4 selects VREF 11 (550 mV) as VC5; The positive input terminal of C3 is connected to VIN, and the negative input terminal is connected to VREF9 (450 mV). The positive input terminal of C4 is connected to VIN, and the negative input terminal is connected to VREF 10 (500 mV), and the positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF 11 (550 mV); CLK3 jumps to the high level, and C3, C4, and C5 start comparing simultaneously. VREF9 < VREF 10 <VREF 11 < VIN, C3O is "1", Y1 is "1", C5O is "1"; Y1B is "0", VL1 = C3O ⊙ Y1B, VL1 is "0", Y0 = VL1 ⊕ C5O, Y0 is "1"; Then the final 4-bit output Y3Y2Y1Y0 = "1011".

[0157] (13) If VIN is within the range of VREF 12 (600 mV) to VREF 13 (650 mV),

[0158] In the first stage, the positive input terminal of C1 is connected to VIN, and the negative terminal is connected to VREF8 (400 mV); CLK1 jumps to the high level, and C1 starts comparing. VIN > VREF8, and Y3 is "1";

[0159] In the second stage, M1 is controlled by Y3 (0) and selects VREF 12 (600 mV) as VC2; The positive input terminal of C2 is connected to VIN, and the negative input terminal is connected to VREF 12 (600 mV), CLK2 jumps to the high level, and C2 starts comparing. VIN > VREF 12 , and Y2 is "1";

[0160] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2 (11). M2 selects VREF 13 (650 mV) as VC3, M3 selects VREF 14 (700 mV) as VC4, and M4 selects VREF 15 (750 mV) as VC5; The positive input terminal of C3 is connected to VIN, and the negative input terminal is connected to VREF 13 (650 mV), the positive input terminal of C4 is connected to VIN, and the negative input terminal is connected to VREF14 (700mV), the positive input of C5 is connected to VIN, and the negative input is connected to VREF 15 (750mV); CLK3 jumps to high level, C3, C4, C5 start to compare at the same time, VIN<VREF 13 <VREF 14 <VREF 15 , C3O is "0", Y1 is "0", C5O is "0"; Y1B is "1", VL1=C3O⊙Y1B, VL1 is "0", Y0=VL1⊕C5O, Y0 is "0"; then the final 4-bit output is Y3Y2Y1Y0="1100".

[0161] (14) If VIN is within VREF 13 (650mV)~VREF 14 (700mV) range,

[0162] In the first stage, the positive input terminal of C1 is connected to VIN and the negative terminal is connected to VREF8 (400mV); CLK1 jumps to a high level, C1 starts to compare, VIN>VREF8, and Y3 is "1";

[0163] In the second stage, M1 is controlled by Y3 (0) and VREF is selected. 12 (600mV) as VC2; the positive input of C2 is connected to VIN and the negative input is connected to VREF 12 (600mV), CLK2 jumps to high level, C2 starts to compare, VIN>VREF 12 , Y2 is "1";

[0164] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2 (11), and M2 selects VREF 13 (650mV) as VC3, M3 gates VREF 14 (700mV) as VC4, M4 gates VREF 15 (750mV) as VC5; the positive input terminal of C3 is connected to VIN and the negative input terminal is connected to VREF 13 (650mV), the positive input of C4 is connected to VIN, and the negative input is connected to VREF 14 (700mV), the positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF 15 (750mV); CLK3 jumps to high level, C3, C4, C5 start to compare at the same time, VREF 13 <VIN<VREF 14 <VREF 15, C3O is "1", Y1 is "0", C5O is "0"; Y1B is "1", VL1=C3O⊙Y1B, VL1 is "1", Y0=VL1⊕C5O, Y0 is "1"; then the final 4-bit output is Y3Y2Y1Y0="1101".

[0165] (15) If VIN is within VREF 14 (700mV)~VREF 14 (750mV) range,

[0166] In the first stage, the positive input terminal of C1 is connected to VIN and the negative terminal is connected to VREF8 (400mV); CLK1 jumps to a high level, C1 starts to compare, VIN>VREF8, and Y3 is "1";

[0167] In the second stage, M1 is controlled by Y3 (0) and VREF is selected. 12 (600mV) as VC2; the positive input of C2 is connected to VIN and the negative input is connected to VREF 12 (600mV), CLK2 jumps to high level, C2 starts to compare, VIN>VREF 12 , Y2 is "1";

[0168] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2 (11), and M2 selects VREF 13 (650mV) as VC3, M3 gates VREF 14 (700mV) as VC4, M4 gates VREF 15 (750mV) as VC5; the positive input terminal of C3 is connected to VIN and the negative input terminal is connected to VREF 13 (650mV), the positive input of C4 is connected to VIN, and the negative input is connected to VREF 14 (700mV), the positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF 15 (750mV); CLK3 jumps to high level, C3, C4, C5 start to compare at the same time, VREF 13 <VREF 14 <VIN<VREF 15 , C3O is "1", Y1 is "1", C5O is "0"; Y1B is "0", VL1=C3O⊙Y1B, VL1 is "0", Y0=VL1⊕C5O, Y0 is "0"; then the final 4-bit output is Y3Y2Y1Y0="1110".

[0169] (16) If VIN is within VREF 15 (750mV) ~ VREF (800mV),

[0170] The positive input terminal of C1 in the first stage is connected to VIN, and the negative terminal is connected to VREF8 (400 mV); when CLK1 jumps to the high level, C1 starts to compare. Since VIN > VREF8, Y3 is "1".

[0171] In the second stage, M1 is controlled by Y3 (0) and selects VREF 12 (600 mV) as VC2; the positive input terminal of C2 is connected to VIN, and the negative input terminal is connected to VREF 12 (600 mV). When CLK2 jumps to the high level, C2 starts to compare. Since VIN > VREF 12 , Y2 is "1".

[0172] In the third stage, M2, M3, and M4 are controlled by Y3 and Y2 (11). M2 selects VREF 13 (650 mV) as VC3, M3 selects VREF 14 (700 mV) as VC4, and M4 selects VREF 15 (750 mV) as VC5; the positive input terminal of C3 is connected to VIN, and the negative input terminal is connected to VREF 13 (650 mV), the positive input terminal of C4 is connected to VIN, and the negative input terminal is connected to VREF 14 (700 mV), and the positive input terminal of C5 is connected to VIN, and the negative input terminal is connected to VREF 15 (750 mV); when CLK3 jumps to the high level, C3, C4, and C5 start to compare simultaneously. Since VREF 13 < VREF 14 < VREF 15 < VIN, C3O is "1", Y1 is "1", and C5O is "1"; Y1B is "0", VL1 = C3O ⊙ Y1B, VL1 is "0", Y0 = VL1 ⊕ C5O, and Y0 is "1"; thus, the final 4-bit output Y3Y2Y1Y0 = "1111".

[0173] The above 16 cases cover all cases of 4-bit analog-to-digital conversion.

[0174] Simulation verification

[0175] To more clearly show the technical solution provided in Embodiment 1 and the resulting technical effects, the simulation verification was carried out for the 12th case above, and the results are as Figure 5 .

[0176] Figure 5 It shows the analog-to-digital conversion result when VIN takes 560 mV:

[0177] Before 0.1ns, CLK1 is "0", C1 is precharged, 0.1ns, CLK1 jumps to "1", starts comparison, and output Y3 is "1";

[0178] Before 0.9ns, CLK2 is "0", C2 is precharged, and at 0.9ns, CLK2 jumps to "1", starts comparison, and output Y2 is "0";

[0179] Before 1.7ns, CLK3 is "0" and C3~C5 are pre-charged. At 1.7ns, CLK3 jumps to "1" and starts comparison. The outputs Y1 and Y0 are "1".

[0180] The time from 1.7ns to 2.5ns is the output read time of the Flash-ADC circuit, and the final result is Y3Y2Y1Y0="1011".

[0181] The above verifies the effectiveness of the Flash-ADC circuit proposed in Example 1 - in one working cycle, the first Flash-ADC circuit proposed in Example 1 only performs 5 comparisons, which is significantly reduced compared to the 15 comparisons of the traditional Flash ADC, greatly optimizing the power consumption (the average power consumption can be reduced by 46.5%), and because the first Flash-ADC circuit proposed in Example 1 has only 5 rail-to-rail comparators, the area is also significantly reduced.

[0182] Example 2

[0183] The second Flash-ADC circuit with three comparison stages provided in this embodiment 2 is different from the first Flash-ADC circuit in embodiment 1 in that a voltage divider circuit is added to realize the comparison between VREF1 and VREF2. 15 , unified control of VREF.

[0184] See also Figure 6 The voltage divider circuit can be designed to include: 16 resistors R1~R 16 .

[0185] Wherein, the first end of R1 is connected to the ground VSS, and the second end is connected to VREF1;

[0186] R m The first terminal R m-1 The second end is connected to VREF m ; m∈[2,15];

[0187] R 16 The first terminal R 15 The second end of the transistor is connected to VREF.

[0188] In this way, VREF is realized through the voltage division effect of the resistor. n =n*VREF / 16.

[0189] Since other circuit structures and working principles are the same as those in Embodiment 1, they are not repeated here.

[0190] Example 3

[0191] 1. See Figure 7 This embodiment 3 discloses a first Flash-ADC module with three-stage comparison stages, which adopts the layout of the Flash-ADC circuit with three-stage comparison stages disclosed in embodiment 1. The mode of packaging into a module makes it easier to promote and apply the above circuit.

[0192] The pins of the first Flash-ADC module include:

[0193] 1 VDD pin, used to connect VDD;

[0194] 3 CLK pins, used to connect CLK1~CLK3 respectively;

[0195] 1 VIN pin, used to connect VIN;

[0196] 15 VREF pins, used to connect VREF1~VREF 15 ;

[0197] 4 Y pins, which are used to connect Y3~Y0 respectively.

[0198] 2. See Figure 8 This embodiment 3 discloses a second Flash-ADC module with three-stage comparison stages, which adopts the layout of the Flash-ADC circuit with three-stage comparison stages disclosed in embodiment 2. The mode of packaging into a module makes it easier to promote and apply the above circuit.

[0199] The pins of the second Flash-ADC module include:

[0200] 1 VDD pin, used to connect VDD;

[0201] 1 VSS pin, used to connect VSS;

[0202] 3 CLK pins, used to connect CLK1~CLK3 respectively;

[0203] 1 VIN pin, used to connect VIN;

[0204] 1 VREF pin, used to connect VREF;

[0205] 4 Y pins, which are used to connect Y3~Y0 respectively.

[0206] That is to say, compared with the first Flash-ADC module, the second Flash-ADC module also encapsulates the voltage divider circuit therein.

[0207] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0208] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A Flash-ADC circuit with three comparison stages, characterized in that: It is used to combine 15 reference voltages VREF1~VREF 15 To convert the input voltage VIN into a 4-bit digital quantity; VREF n =n*VREF / 16; n∈[1,15]; VREF∈[0,VDD], VREF represents an analog voltage, and VDD represents a power supply voltage; the Flash-ADC circuit with three-stage comparison stages includes: The first stage comparison circuit includes a rail-to-rail comparator C1; wherein C1 is used to compare VIN and VREF8 under the control of the control signal CLK1 to obtain the highest bit Y3 of the 4-bit digital quantity; The second stage comparison circuit includes a two-to-one selector M1 and a rail-to-rail comparator C2; wherein M1 is used to select VREF4 or VREF under the control of Y3. 12 As the output voltage VC2, C2 is used to compare VIN and VC2 under the control of the control signal CLK2 to obtain the second highest bit Y2 of the 4-bit digital quantity; as well as The third level comparison circuit includes three four-to-one selectors M2~M4, three rail-to-rail comparators C3~C5, and an output encoding circuit; wherein M2 is used to select VREF1, VREF5, VREF9, VREF under the common control of Y3 and Y2. 13 One of them is used as the output voltage VC3, C3 is used to compare VIN and VC3 under the control of the control signal CLK3 to obtain the output signal C3O; M3 is used to select VREF2, VREF6, VREF under the common control of Y3 and Y2. 10 、VREF 14 One of them is used as the output voltage VC4. C4 is used to compare VIN and VC4 under the control of CLK3 to obtain the second lowest bit Y1 of the 4-bit digital quantity; M4 is used to select VREF3, VREF7, VREF under the common control of Y3 and Y2. 11 、VREF 15 One of them is used as the output voltage VC5, C5 is used to compare VIN and VC5 under the control of CLK3 to obtain the output signal C5O; the output encoding circuit is used to combine C3O, Y1, and C3O to output the lowest bit Y0 of the 4-bit digital quantity.

2. The Flash-ADC circuit with three comparison stages according to claim 1, characterized in that: The positive input terminal of C1 is connected to VIN, the negative input terminal is connected to VREF8, the control terminal is connected to CLK1, and the output terminal is used to output Y3.

3. The Flash-ADC circuit with three comparison stages according to claim 1, characterized in that: Input terminal 1 of M1 is connected to VREF4, and input terminal 2 is connected to VREF 12 , the control end is connected to Y3, and the output end is used to output VC2; The positive input terminal of C2 is connected to VIN, the negative input terminal is connected to VC2, the control terminal is connected to CLK2, and the output terminal is used to output Y2.

4. The Flash-ADC circuit with three comparison stages according to claim 3, characterized in that: M1 includes: 1 inverter INV2, 2 transmission gates TG1~TG2; The input terminal of INV2, the negative control terminal of TG1, and the positive control terminal of TG2 are all connected to Y3; The output end of INV2 is connected to the positive control end of TG1 and the negative control end of TG2; The input end of TG1 is connected to VREF4, and the output end is connected to VC2; The input of TG2 is connected to VREF 12 , the output end is connected to VC2.

5. The Flash-ADC circuit with three comparison stages according to claim 1, characterized in that: Input 1 of M2 is connected to VREF1, input 2 is connected to VREF5, input 3 is connected to VREF9, and input 4 is connected to VREF 13 , control terminal 1 is connected to Y3, control terminal 2 is connected to Y2, and the output terminal is used to output VC3; The positive input terminal of C3 is connected to VIN, the negative input terminal is connected to VC3, the control terminal is connected to CLK3, and the output terminal is used to output C3O; Input 1 of M3 is connected to VREF2, input 2 is connected to VREF6, and input 3 is connected to VREF 10 、Input terminal 4 connects to VREF 14 , control terminal 1 is connected to Y3, control terminal 2 is connected to Y2, and the output terminal is used to output VC4; The positive input terminal of C3 is connected to VIN, the negative input terminal is connected to VC4, the control terminal is connected to CLK3, and the output terminal is used to output Y1; Input 1 of M4 is connected to VREF3, input 2 is connected to VREF7, and input 3 is connected to VREF 11 、Input terminal 4 connects to VREF 15 , control terminal 1 is connected to Y3, control terminal 2 is connected to Y2, and the output terminal is used to output VC5; The positive input terminal of C5 is connected to VIN, the negative input terminal is connected to VC5, the control terminal is connected to CLK3, and the output terminal is used to output C5O.

6. The Flash-ADC circuit with three comparison stages according to claim 5, characterized in that: M2~M4 have the same structure, including: 1 2 to 4 decoding circuit, 4 transmission gates TG3~TG6; 2 to 4 decoding circuit includes: 6 inverters INV3~INV8, 4 AND2~AND5; In any of the four selectors: The input end of INV3 is connected to Y2, and the output end is used to output the reverse signal Y2B; The input end of INV4 is connected to Y3, and the output end is used to output the reverse signal Y3B; The input terminal 1 of AND2 is connected to Y2B, the input terminal 2 is connected to Y3B, and the output terminal is used to output the control signal D0; The input end of INV5 is connected to D0, and the output end is used to output the reverse signal D0B; The input terminal 1 of AND3 is connected to Y2, the input terminal 2 is connected to Y3B, and the output terminal is used to output the control signal D1; The input end of INV6 is connected to D1, and the output end is used to output the reverse signal D1B; The input terminal 1 of AND4 is connected to Y2B, the input terminal 2 is connected to Y3, and the output terminal is used to output the control signal D2; The input end of INV7 is connected to D2, and the output end is used to output the reverse signal D2B; The input terminal 1 of AND4 is connected to Y2, the input terminal 2 is connected to Y3, and the output terminal is used to output the control signal D3; The input end of INV8 is connected to D3, and the output end is used to output the reverse signal D3B; The positive control terminal of TG3 is connected to D0, the negative control terminal is connected to D0B, and the input terminal is connected to the reference voltage VREF A , the output terminal is used to output a control signal OUT; The positive control terminal of TG4 is connected to D1, the negative control terminal is connected to D1B, and the input terminal is connected to the reference voltage VREF B , the output terminal is used to output a control signal OUT; The positive control terminal of TG5 is connected to D2, the negative control terminal is connected to D2B, and the input terminal is connected to the reference voltage VREF C , the output terminal is used to output a control signal OUT; The positive control terminal of TG6 is connected to D3, the negative control terminal is connected to D3B, and the input terminal is connected to the reference voltage VREF D , the output terminal is used to output a control signal OUT; In M2, VREF A VREF1, VREF B VREF5, VREF C VREF9, VREF D VREF 13 , OUT is VC3; In M3, VREF A VREF2, VREF B VREF6, VREF C VREF 10 , VREF D VREF 14 , OUT is VC4; In M4, VREF A VREF3, VREF B VREF7, VREF C VREF 11 , VREF D VREF 15 , OUT is VC5.

7. The Flash-ADC circuit with three comparison stages according to claim 1, characterized in that: The output encoding circuit includes: an inverter INV1, an AND gate AND1, and an OR gate OR1; The input end of INV1 is connected to Y1, and the output end is used to output the reverse signal Y1B; Input terminal 1 of AND1 is connected to C3O, input terminal 2 is connected to Y1B, and the output terminal is used to output signal VL1; Input terminal 1 of OR1 is connected to VL1, input terminal 2 is connected to C5O, and the output terminal is used to output Y0.

8. The Flash-ADC circuit with three comparison stages according to claim 1, characterized in that: It also includes: The voltage divider circuit includes: 16 resistors R1~R 16 ; Wherein, the first end of R1 is connected to the ground VSS, and the second end is connected to VREF1; R m The first terminal R m-1 The second end is connected to VREF m ; m∈[2,15]; R 16 The first terminal R 15 The second end of the transistor is connected to VREF.

9. The Flash-ADC circuit with three comparison stages according to claim 1, characterized in that: Pre-charge time T of C1~C5 Pre Same, delay time T delay Same, output reading time T out same; CLK1, CLK2, and CLK3 have the same period; In one cycle of CLK1, the low level duration is T Pre , high level duration is 3*T delay +T out ; In one cycle of CLK2, the low level duration is T Pre +T delay , high level duration is 2*T delay +T out ; In one cycle of CLK3, the low level duration is T Pre +2*T delay , high level time is T delay +T out .

10. A Flash-ADC module with three comparison stages, characterized in that: It adopts the layout of the Flash-ADC circuit with three comparison stages as described in any one of claims 1 to 9.

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