Asynchronous normal form ADC (Analog to Digital Converter) circuit with dynamic computing power and variable precision quantization

Abstract

The invention discloses an asynchronous normal form ADC (Analog to Digital Converter) circuit with dynamic computing power and variable precision quantization, which comprises three stages, namely a setting stage, a computing stage and an asynchronous handshake stage, and realizes the self-adaptive capability to signal quantization precision so as to realize balance between high-precision data processing and energy efficiency optimization. According to the ADC circuit, the number of the successive approximation SA registers is effectively reduced in design, so that the energy consumption of the whole circuit is remarkably reduced, and meanwhile, the reduction of the use of the SA registers means lower manufacturing cost, so that the ADC circuit is more economical and efficient in material use and production process.

Description

Technical Field

[0001] The present invention relates to the technical field of ADC circuits, and in particular to an asynchronous paradigm ADC circuit with dynamic computing capability and variable precision quantization. Background Art

[0002] In the post-Moore era, with the exponential growth of data volume and the continuous improvement of intelligent processing requirements, traditional computing architectures have been unable to meet the dual challenges of efficiency and energy consumption. Computing-in-one (CIM) technology, as a disruptive solution, integrates storage and computing functions in the same hardware unit, providing an efficient hardware platform for real-time intelligent processing of big data.

[0003] Deep learning neural network is one of the most cutting-edge artificial intelligence technologies today. Its core operation, multiply accumulate (MAC), requires huge computing resources. In the traditional von Neumann architecture, data must be frequently moved between the processor and the memory, resulting in significant delays and energy waste, which is called the "von Neumann bottleneck". In contrast, the storage-computing technology greatly shortens the data movement distance and reduces the data access time by performing calculations directly in the memory unit, thereby significantly improving computing efficiency and reducing energy consumption.

[0004] At the same time as this transformation, the introduction of asynchronous circuit design further optimized this architecture. Traditional synchronous circuit design relies on global clock signals, and the processing efficiency varies for input signals of different sizes and complexities. Asynchronous circuit design is not limited by the global clock and can dynamically adjust the processing speed according to the actual situation of the input signal. It performs well in high-speed data processing and low-power operation. This design can provide higher flexibility and efficiency when processing complex deep learning tasks, while reducing energy waste caused by fixed clock cycles, providing a more efficient and responsive solution for computing needs in the post-Moore era.

[0005] One of the important branches of the current mainstream storage-computing technology is the analog storage-computing integration implemented by using storage media such as SRAM, ReRAM, and Flash. These media can not only store information, but also perform basic arithmetic operations of analog or digital signals, such as addition and multiplication, which is particularly critical for performing a large number of MAC operations. In this way, the storage-computing architecture can complete complex computing tasks directly in the storage unit without the need for data to return to the central processing unit. The external digital input signal needs to be converted into an analog signal value by DAC first as the input of the analog computing array. The analog computing array is composed of a complex number of SRAM, ReRAM or other storage medium computing units. The array implements multiplication and addition calculations and outputs the calculation results of the analog quantity. Finally, the ADC analog-to-digital conversion device converts the analog quantity into a digital signal as the output result;

[0006] In deep learning and other high-performance computing applications, the accuracy of analog computing is crucial, but this accuracy is often limited by the accuracy of analog-to-digital conversion (ADC). Traditional multi-bit precision ADCs, although powerful, have two major problems due to their design complexity: first, they usually require a larger circuit area, which means higher cost and space constraints in chip design; second, they consume higher power, which is a significant disadvantage in modern computing environments that require maximum energy efficiency;

[0007] Traditional synchronous ADC circuits are often limited in efficiency when processing input signals of different amplitudes due to their fixed computing time. This design relies on global clock synchronization, resulting in the same processing time for signals with smaller amplitudes, thus reducing overall processing efficiency.

[0008] In addition, the existing charge-integrating ADC technology has some inherent problems in actual operation. Due to the delay of the operational amplifier (Op-Amp) and the non-ideality of the charge transfer process, the amount of each discharge may be different, resulting in inconsistency in the integration process. This is particularly prominent in high-speed operations, because when processing a large amount of data in a short period of time, even tiny delays and errors will accumulate, and ultimately affect the output accuracy of the entire system. In addition, during the discharge process, if the input signal continues to change, the current technology may not be able to effectively capture these changes, resulting in data loss. These nonlinear errors and synchronization problems are particularly serious in application scenarios with high precision requirements, because the system cannot guarantee the consistency of the amount of each discharge, which affects the final calculation accuracy. Summary of the invention

[0009] The present invention provides an asynchronous paradigm ADC circuit with dynamic computing capability and variable precision quantization, which can effectively solve the problems raised in the above background technology.

[0010] To achieve the above object, the present invention provides the following technical solution: an ADC circuit with dynamic computing capability and variable precision quantization in an asynchronous paradigm, comprising three stages: a setup stage, a calculation stage, and an asynchronous handshake stage;

[0011] Step 1: Setup Phase:

[0012] In the setting stage, by activating the control signal SET, the charge storage capacitor C1 is charged from the charge bit line to the set reference voltage Vref to reserve the charge required for the charging process. In this stage, the NMOS transistor N2 is turned off to isolate C1, and the NMOS transistor N3 is turned on to allow C2 to discharge to the ground, preparing for the next charging operation;

[0013] Step 2: Calculation phase:

[0014] At this stage, the control signal SET is disabled, causing the NMOS transistor N2 to turn on and the PMOS transistor N3 to turn off. The charge stored in the reservoir capacitor C1 flows to the discharge capacitor C2, thereby accumulating charge on C2. While the charge is transferred from C1 to C2, the charge voltage Vc accumulated on C2 is constantly compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, thereby triggering the release circuit. The discharge triggers the NMOS transistor N4 to turn on, so that C2 is fully discharged, and the corresponding pulse is recorded by the counter. The discharge action will also cause the transistor N2 to turn off through the out_pulse signal, interrupting the charge from CBL to C2. If Vc is lower than Vref after discharge, the transistor N4 is turned off and N2 is turned on again, allowing CBL and C1 to recharge C2 and prepare for the next counting cycle. In this way, the charging and discharging process of C2 and the generation of the pulse output sequence constitute a continuous cycle;

[0015] Step 3: Asynchronous handshake phase:

[0016] During this stage, when the voltage of CBL is lower than Vref, the handshake signal ADCK is activated and increases, prompting the SET signal to be activated, causing CBL to be quickly charged to Vref. The rapid decrease of the ADCK signal then causes the SET signal to be disabled, completing an asynchronous handshake operation and providing a stable voltage environment for the accurate start of the next counting cycle.

[0017] According to the above technical solution, during the calculation stage, the mode selector allows the output unit to adjust the capacitance of the discharge capacitor according to the set mode;

[0018] The mode selector is configured with two modes, corresponding to different resolution ranges:

[0019] a. Mode 0 (Mode = 0): In this mode, the capacitance of the discharge capacitor is set to C0. When the charge on CBL is transferred to the discharge capacitor, the voltage change caused by the charge accumulated on the capacitor is larger due to the smaller capacitance. This enables the same amount of charge on CBL to generate more count pulses in the counter, resulting in higher resolution at the output.

[0020] b. Mode 1 (Mode = 1): In this mode, the capacitance of the discharge capacitor is n times that of Mode 0, i.e., nC0, because a larger capacitor can store more charge without significantly changing the voltage. Therefore, in Mode 1, the same charge on CBL will generate fewer pulses in the counter, resulting in a lower resolution of the output, but allowing a wider range of charge accumulation and processing;

[0021] By switching between these two modes, the system can flexibly configure the accuracy. For applications that require high-resolution readings, mode 0 can be selected;

[0022] For applications that need to process a larger dynamic range but not so high resolution, you can choose Mode 1;

[0023] This flexibility allows the ADC of the present invention to switch between different operating precisions, optimizing power consumption and performance.

[0024] According to the above technical solution, in the counting stage, the D flip-flop detects X <1> After the rising edge, it is pulled high. After the PP_checker detects the rise of out_pulse, it generates a pulse discharge with adjustable width to control the switch of N4 to ensure that the charge accumulated in C2 is completely discharged. The principle of NP_checker is similar to that of PP_checker. After recognizing the falling edge of discharge, it sends out a pulse np as small as possible, thereby controlling out_pulse to be pulled low.

[0025] The escapement discharge circuit ensures that C2 is fully discharged while N2 is in the off state, avoiding a brief short circuit in the circuit.

[0026] According to the above technical solution, during the calculation phase, the charge stored in the reservoir capacitor C1 is allowed to flow to the discharge capacitor C2, so that the charge is accumulated on C2. The configurable capacitor array determines the capacitance of C2 through the setting of the mode selector, which directly affects the charging process and counting accuracy.

[0027] While the charge is transferred from C1 to C2, the charge voltage Vc accumulated on C2 is constantly compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, thereby triggering the release circuit. The discharge triggers the NMOS transistor N4 to turn on, causing C2 to be fully discharged, and the corresponding pulse is recorded by the counter.

[0028] The discharge action also causes transistor N2 to turn off through the out_pulse signal, interrupting the flow of charge from CBL to C2;

[0029] If Vc is lower than Vref after discharge, transistor N4 turns off and N2 turns on again, allowing CBL and C1 to recharge C2 in preparation for the next counting cycle;

[0030] In this way, the charging and discharging process of C2 and the generation of the pulse output sequence constitute a continuous cycle, enabling the ADC circuit to achieve accurate analog-to-digital conversion in high-speed operation.

[0031] Compared with the prior art, the invention has the following beneficial effects: the invention has a scientific and reasonable structure, is safe and convenient to use, realizes the adaptive capability of signal quantization accuracy, and achieves a balance between high-precision data processing and energy efficiency optimization. The number of successive approximation SA registers is effectively simplified in design, thereby significantly reducing the energy consumption of the overall circuit. At the same time, reducing the use of SA registers also means lower manufacturing costs, making the ADC circuit more economical and efficient in terms of material use and production process. The handshake signal ADCK is introduced. Since it does not rely on external clock synchronization, the circuit is less sensitive to changes in the external environment, so that it can still maintain stable performance when facing environmental changes such as temperature fluctuations and power supply noise, thereby improving robustness.

[0032] In addition, another notable feature of asynchronous circuits is low power consumption. Since they consume energy only when processing data rather than continuously relying on clock signals, they can significantly reduce overall energy consumption, especially when processing intermittent or sparse data.

[0033] The escapement discharge circuit adopted by the present invention can accurately control the discharge process, can more accurately control the discharge time of the capacitor, reduce the error caused by inaccurate charge transfer, and improve the overall signal conversion accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0035] In the attached picture:

[0036] Figure 1 is the overall circuit diagram of the ADC of the present invention;

[0037] Figure 2 It is a handshake circuit diagram of the present invention;

[0038] Figure 3 It is a timing diagram of asynchronous handshake signals of the present invention;

[0039] Figure 4 is a circuit diagram of a mode selector of the present invention;

[0040] Figure 5 It is a variable precision quantization circuit diagram of the present invention;

[0041] Figure 6 It is a circuit diagram of the escapement unit of the present invention; DETAILED DESCRIPTION

[0042] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0043] Example: Figure 1 As shown, the present invention provides a technical solution, an asynchronous paradigm ADC circuit with dynamic computing capability and variable precision quantization, including three stages: a setting stage, a computing stage, and an asynchronous handshake stage;

[0044] Step 1: Setup Phase:

[0045] In the setting stage, by activating the control signal SET, the charge storage capacitor C1 is charged from the charge bit line to the set reference voltage Vref to reserve the charge required for the charging process. In this stage, the NMOS transistor N2 is turned off to isolate C1, and the NMOS transistor N3 is turned on to allow C2 to discharge to the ground, preparing for the next charging operation;

[0046] Step 2: Calculation phase:

[0047] At this stage, the control signal SET is disabled, causing the NMOS transistor N2 to turn on and the PMOS transistor N3 to turn off. The charge stored in the reservoir capacitor C1 flows to the discharge capacitor C2, thereby accumulating charge on C2. While the charge is transferred from C1 to C2, the charge voltage Vc accumulated on C2 is constantly compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, thereby triggering the release circuit. The discharge triggers the NMOS transistor N4 to turn on, so that C2 is fully discharged, and the corresponding pulse is recorded by the counter. The discharge action will also cause the transistor N2 to turn off through the out_pulse signal, interrupting the charge from CBL to C2. If Vc is lower than Vref after discharge, the transistor N4 is turned off and N2 is turned on again, allowing CBL and C1 to recharge C2 and prepare for the next counting cycle. In this way, the charging and discharging process of C2 and the generation of the pulse output sequence constitute a continuous cycle;

[0048] Step 3: Asynchronous handshake phase:

[0049] like Figure 2-3 As shown: In this stage, when the voltage of CBL is lower than Vref, the handshake signal ADCK is activated and increases, prompting the SET signal to be activated, causing CBL to be quickly charged to Vref, and the rapid decrease of the ADCK signal then causes the SET signal to be disabled, completing an asynchronous handshake operation and providing a stable voltage environment for the accurate start of the next counting cycle.

[0050] According to the above technical solution, if Figure 4 As shown: During the calculation phase, the mode selector allows the output unit to adjust the capacitance of the discharge capacitor according to the set mode, thereby achieving variable precision quantization;

[0051] The mode selector is configured with two modes, corresponding to different resolution ranges:

[0052] a. Mode 0 (Mode = 0): In this mode, the capacitance of the discharge capacitor is set to C0. When the charge on CBL is transferred to the discharge capacitor, the voltage change caused by the charge accumulated on the capacitor is larger due to the smaller capacitance. This enables the same amount of charge on CBL to generate more count pulses in the counter, resulting in higher resolution at the output.

[0053] b. Mode 1 (Mode = 1): In this mode, the capacitance of the discharge capacitor is n times that of Mode 0, i.e. nC0, which means that under the same amount of charge, the voltage change on the capacitor will be smaller than that in Mode 0, because a larger capacitor can store more charge without significantly changing the voltage. Therefore, in Mode 1, the same charge on CBL will generate fewer pulses in the counter, resulting in a lower resolution of the output, but allowing a wider range of charge accumulation and processing;

[0054] like Figure 5 As shown: By switching between these two modes, the system can flexibly configure the accuracy to suit different application requirements. For applications that require high-resolution readings, mode 0 can be selected;

[0055] For applications that need to process a larger dynamic range but not so high resolution, you can choose Mode 1;

[0056] This flexibility allows the ADC of the present invention to switch between different operating precisions, optimizing power consumption and performance.

[0057] According to the above technical solution, if Figure 6 As shown in the figure, a is the escapement circuit, b is the PP_checker circuit, c is the NP_checker circuit, and d is the voltage waveform of out_pulse, discharge and np. In the counting stage, the escapement circuit plays a key role. The D flip-flop detects X <1> After the rising edge, it is pulled high. After the PP_checker detects the rise of out_pulse, it generates a pulse discharge with adjustable width to control the switch of N4 to ensure that the charge accumulated in C2 is completely discharged. The principle of NP_checker is similar to that of PP_checker. After recognizing the falling edge of discharge, it sends out a pulse np as small as possible, thereby controlling out_pulse to be pulled low.

[0058] The escapement discharge circuit ensures that C2 is fully discharged while N2 is in the closed state, avoiding a brief short circuit in the circuit.

[0059] Furthermore, during the calculation phase, the charge stored in the reservoir capacitor C1 is allowed to flow to the discharge capacitor C2, so that the charge is accumulated on C2. The configurable capacitor array determines the capacitance of C2 through the setting of the mode selector, which directly affects the charging process and counting accuracy.

[0060] While the charge is transferred from C1 to C2, the charge voltage Vc accumulated on C2 is constantly compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, thereby triggering the release circuit. The discharge triggers the NMOS transistor N4 to turn on, causing C2 to be fully discharged, and the corresponding pulse is recorded by the counter.

[0061] The discharge action also causes transistor N2 to turn off through the out_pulse signal, interrupting the flow of charge from CBL to C2;

[0062] If Vc is lower than Vref after discharge, transistor N4 turns off and N2 turns on again, allowing CBL and C1 to recharge C2 in preparation for the next counting cycle;

[0063] In this way, the charging and discharging process of C2 and the generated pulse output sequence constitute a continuous cycle, ensuring the synchronization of the counting accuracy and the charge charging and discharging process, so that the ADC circuit can achieve accurate analog-to-digital conversion in high-speed operation.

[0064] Finally, it should be noted that the above description is only a preferred example of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An asynchronous ADC circuit with dynamic computing capability and variable precision quantization, characterized in that: It includes three phases: setup phase, calculation phase and asynchronous handshake phase; Step 1: Setup Phase: In the setting stage, by activating the control signal SET, the charge storage capacitor C1 is charged from the charge bit line to the set reference voltage Vref to reserve the charge required for the charging process. In this stage, the NMOS transistor N2 is turned off to isolate C1, and the NMOS transistor N3 is turned on to allow C2 to discharge to the ground, preparing for the next charging operation; Step 2: Calculation phase: At this stage, the control signal SET is disabled, causing the NMOS transistor N2 to turn on and the PMOS transistor N3 to turn off. The charge stored in the reservoir capacitor C1 flows to the discharge capacitor C2, thereby accumulating charge on C2. While the charge is transferred from C1 to C2, the charge voltage Vc accumulated on C2 is constantly compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, thereby triggering the release circuit. The discharge triggers the NMOS transistor N4 to turn on, so that C2 is fully discharged, and the corresponding pulse is recorded by the counter. The discharge action will also cause the transistor N2 to turn off through the out_pulse signal, interrupting the charge from CBL to C2. If Vc is lower than Vref after discharge, the transistor N4 is turned off and N2 is turned on again, allowing CBL and C1 to recharge C2 and prepare for the next counting cycle. In this way, the charging and discharging process of C2 and the generation of the pulse output sequence constitute a continuous cycle; Step 3: Asynchronous handshake phase: During this stage, when the voltage of CBL is lower than Vref, the handshake signal ADCK is activated and increases, prompting the SET signal to be activated, causing CBL to be quickly charged to Vref. The rapid decrease of the ADCK signal then causes the SET signal to be disabled, completing an asynchronous handshake operation and providing a stable voltage environment for the accurate start of the next counting cycle.

2. The asynchronous paradigm ADC circuit with dynamic computing capability and variable precision quantization according to claim 1, characterized in that: During the calculation phase, the mode selector allows the output unit to adjust the capacitance of the discharge capacitor according to the set mode; The mode selector is configured with two modes, corresponding to different resolution ranges: a. Mode 0 (Mode = 0): In this mode, the capacitance of the discharge capacitor is set to C0. When the charge on CBL is transferred to the discharge capacitor, the voltage change caused by the charge accumulated on the capacitor is larger due to the smaller capacitance. This enables the same amount of charge on CBL to generate more count pulses in the counter, resulting in higher resolution at the output. b. Mode 1 (Mode = 1): In this mode, the capacitance of the discharge capacitor is n times that of Mode 0, i.e., nC0, because a larger capacitor can store more charge without significantly changing the voltage. Therefore, in Mode 1, the same charge on CBL will generate fewer pulses in the counter, resulting in a lower resolution of the output, but allowing a wider range of charge accumulation and processing; By switching between these two modes, the system can flexibly configure the accuracy. For applications that require high-resolution readings, mode 0 can be selected; For applications that need to process a larger dynamic range but not so high resolution, you can choose Mode 1; This flexibility allows the ADC of the present invention to switch between different operating precisions, optimizing power consumption and performance.

3. The asynchronous paradigm ADC circuit with dynamic computing capability and variable precision quantization according to claim 1, characterized in that: In the counting phase, the D flip-flop detects X <1> After the rising edge, it is pulled high. After the PP_checker detects the rise of out_pulse, it generates a pulse discharge with adjustable width to control the switch of N4 to ensure that the charge accumulated in C2 is completely discharged. The principle of NP_checker is similar to that of PP_checker. After recognizing the falling edge of discharge, it sends out a pulse np as small as possible, thereby controlling out_pulse to be pulled low. The escapement discharge circuit ensures that C2 is fully discharged while N2 is in the closed state, avoiding a brief short circuit in the circuit.

4. The asynchronous paradigm ADC circuit with dynamic computing capability and variable precision quantization according to claim 1, characterized in that: In the calculation phase, the charge stored in the reservoir capacitor C1 is allowed to flow to the discharge capacitor C2, so that the charge accumulates on C2. The configurable capacitor array determines the capacitance of C2 through the setting of the mode selector, which directly affects the charging process and counting accuracy. While the charge is transferred from C1 to C2, the charge voltage Vc accumulated on C2 is constantly compared with the reference voltage Vref. Once Vc exceeds Vref, the comparator outputs a high-level signal, thereby triggering the release circuit. The discharge triggers the NMOS transistor N4 to turn on, causing C2 to be fully discharged, and the corresponding pulse is recorded by the counter. The discharge action also causes transistor N2 to turn off through the out_pulse signal, interrupting the flow of charge from CBL to C2; If Vc is lower than Vref after discharge, transistor N4 turns off and N2 turns on again, allowing CBL and C1 to recharge C2 in preparation for the next counting cycle; In this way, the charging and discharging process of C2 and the generation of the pulse output sequence constitute a continuous cycle, enabling the ADC circuit to achieve accurate analog-to-digital conversion in high-speed operation.

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