A high-speed parallel GPU encoder and encoding method for non-sparse LDPC codes

Abstract

The present invention relates to the field of communication technology, and in particular to a non-sparse LDPC code high-speed parallel GPU encoder and encoding method. The method comprises: improving the utilization rate of the entire computing resource, and adopting two levels of parallelism, namely, inter-frame and intra-frame. In order to greatly improve the efficiency of instruction execution, the information bits at the same position of multiple frames allocated to the same thread block are stored in unsigned integer or unsigned long integer registers according to bit packaging, and are updated simultaneously during the check bit update process. In order to improve the memory access efficiency of the generated matrix shared memory, the present invention allocates a storage space of twice the check bit length to the shared memory of the generated matrix, thereby reducing the number of remainder and division operations that the GPU is not good at. The LDPC encoder proposed by the present invention can be developed through a high-level programming language, has strong flexibility and scalability, and can adapt to the development needs of softwareization and virtualization of future satellite ground station systems.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a non-sparse LDPC code high-speed parallel GPU encoder and encoding method. Background Art

[0002] Low-Density Parity-Check Code (LDPC) is a linear error correction code that plays an important role in coding theory. LDPC codes are widely used in modern communication systems, mainly due to their significant advantages. First, the performance of LDPC codes is close to the Shannon limit, which means that it can achieve the maximum data transmission rate at a given signal-to-noise ratio while maintaining an extremely low error rate. Second, LDPC codes use iterative decoding algorithms that are not only efficient but also can be processed in parallel, which is very suitable for modern high-performance computing platforms, thereby improving the decoding speed. In addition, the design of LDPC codes is highly flexible and scalable, allowing them to easily adapt to different code lengths and code rates to meet different communication systems and bandwidth requirements. LDPC codes also have good fault tolerance, enabling them to maintain stable performance in high-noise environments and multipath fading environments. The excellent characteristics of LDPC codes make them suitable not only for applications with high-reliability transmission, but also for a variety of communication standards such as CCSDS, Wi-Fi, LTE, and 5G. In addition, LDPC codes can also be used in combination with other coding techniques to further improve the performance of communication systems. Therefore, LDPC codes have played an important role in modern communication technology due to their excellent performance, flexibility and efficiency. In order to reduce the decoding complexity of LDPC codes, their check matrices are often sparse. However, the generator matrix of the LDPC codes used by low-Earth satellites recommended by the CCSDS standard does not have the characteristics of sparsity, which greatly increases the coding complexity. Summary of the invention

[0003] In order to solve the technical problem that the generator matrix of the LDPC code used by the near-Earth satellite recommended by the CCSDS standard in the prior art does not have the feature of sparseness, which greatly increases the coding complexity, the embodiment of the present invention provides a non-sparse LDPC code high-speed parallel GPU encoder and encoding method. The technical solution is as follows:

[0004] On the one hand, a non-sparse LDPC code high-speed parallel GPU encoding method is provided, characterized in that the method is applicable to a non-sparse LDPC code high-speed parallel GPU encoder for a near-Earth satellite ground station, and the method comprises:

[0005] S1. Obtain a non-sparse LDPC code for a near-Earth satellite ground station, and perform encoding initialization based on the non-sparse LDPC code; allocate memory and video memory space for information to be stored; the encoding initialization includes: preprocessing the cyclic generator matrix parameters of the non-sparse LDPC code;

[0006] S2, pre-processing the information of the allocated memory and video memory space before encoding, and allocating on-chip shared memory and register resources for generating matrix temporary variables and updating check bits;

[0007] S3, the GPU encoder updates the check bit using inter-frame parallelism and intra-frame parallelism, assigns the updated check bit information to the corresponding position of the encoding result display memory space d_output, and transfers the encoding result from the encoding result display memory space d_output to the encoding result memory space h_output in an asynchronous transmission mode;

[0008] S4. After the GPU encoder completes encoding of all codewords, the initialization process data is released or destroyed, and the high-speed parallel GPU encoding of non-sparse LDPC codes for near-Earth satellite ground stations is completed.

[0009] Optionally, in S1, preprocessing the cyclic generator matrix parameters of the non-sparse LDPC code includes:

[0010] Set the information bit length k, code length n, generator matrix sub-block dimension Z, sub-block column number nc, sub-block row number nk and puncturing length of the LDPC code;

[0011] Among them, each sub-block of the LDPC code generator matrix has a cyclic feature, that is, the next row of each sub-block is obtained by shifting one row to the right of the previous row; then storing the first row information of each sub-block of the LDPC code generator matrix can represent the entire generator matrix;

[0012] The bit information of the LDPC code generation matrix sub-block is encapsulated and packaged according to the bit, and the encapsulated and packaged array is stored using an unsigned integer or unsigned long integer data type array to obtain the encapsulated and packaged matrix information h_g.

[0013] Optionally, in S1, memory and video memory space are allocated for information to be stored, including:

[0014] Allocate device memory space for information bits and encoding results; allocate constant memory c_g for the generator matrix of the LDPC code, and use the encapsulated and packaged matrix information h_g to initialize the constant memory c_g of the generator matrix;

[0015] Create an asynchronous stream for the encoding phase, initializing the dimensions and size of the thread blocks.

[0016] Optionally, in S2, the information of the allocated memory and video memory space is preprocessed before encoding, and on-chip shared memory and register resources are allocated for generating matrix temporary variables and updating check bits, including:

[0017] Use the information bits h_input allocated in the host memory to initialize the information bits d_input in the global memory in an asynchronous transmission manner;

[0018] Before encoding, on-chip resources are allocated for temporary variables of the generator matrix and updated check bits respectively; a shared memory space sh_g is allocated for the generator matrix, and the shared memory space sh_g of the generator matrix is ​​initialized using the constant memory c_g of the generator matrix; wherein, in the shared memory space sh_g of the generator matrix, the storage of the generator matrix includes two methods: storage according to the check bits or storage according to the bit packing method in the constant memory c_g of the generator matrix;

[0019] Loop expansion is performed on the check bits belonging to different sub-blocks, and multiple register resources check and g are respectively allocated to the check bits and the sub-block generation matrix before encoding, where check represents the allocated check bit register and g represents the allocated sub-block generation matrix register.

[0020] Optionally, inter-frame parallelism and intra-frame parallelism include:

[0021] The intra-frame parallelism is that the check information belonging to the same generator matrix sub-block dimension Z is updated simultaneously;

[0022] Inter-frame parallelism includes: multi-frame parallel updates assigned to the same thread block and multi-frame parallel updates assigned to different thread blocks.

[0023] Optionally, in S3, the GPU encoder updates the check bit using inter-frame parallelism and intra-frame parallelism, assigns the updated check bit information to the corresponding position of the encoding result display memory space d_output, and transfers the encoding result from the encoding result display memory space d_output to the encoding result memory space h_output in an asynchronous transmission manner, including:

[0024] According to the information bit d_input in the global memory, the information bit position of each frame in the encoding result display memory space d_output is assigned;

[0025] Based on the inter-frame parallelism and intra-frame parallelism, the check bits of the multi-frame codewords assigned to the same thread block are updated by partial parallel update; each check bit is updated by serial update;

[0026] After the check bit is updated for each information bit, the check bit in the check bit register check is used to assign a value to the corresponding check bit in the encoding result display memory space d_output;

[0027] The encoding result stored in the encoding result display memory space d_output is used to update the encoding result memory space h_output in an asynchronous transmission manner.

[0028] Optionally, S3 further includes:

[0029] Before partially parallel updating the check bits, the information bits at the same position of multiple frames allocated to the same thread block need to be packed and stored in the register msg of unsigned integer or unsigned long integer according to the bits;

[0030] Before updating the check bit, the sub-block generator matrix register g needs to be initialized according to the generator matrix information in the shared memory;

[0031] The check bit register check is partially updated in parallel according to the updated register msg and the sub-block generation matrix register g, wherein the partial parallel update is implemented by loop unrolling.

[0032] Optionally, in S4, after the GPU encoder completes encoding of all codewords, the initialization process data is released or destroyed, including:

[0033] When the GPU encoder completes encoding of all codewords, it releases or destroys the memory and video memory allocated during the initialization process and the asynchronous stream created; it releases h_input and h_output in the memory space, releases d_input and d_output in the video memory space, and destroys the asynchronous stream created.

[0034] On the other hand, a non-sparse LDPC code high-speed parallel GPU encoding is provided, and the encoder is applied to the non-sparse LDPC code high-speed parallel GPU encoding method, and the encoder includes:

[0035] A coding initialization module is used to obtain a non-sparse LDPC code for a near-Earth satellite ground station, and perform coding initialization based on the non-sparse LDPC code; allocate memory and video memory space for information to be stored; the coding initialization includes: preprocessing the cyclic generator matrix parameters of the non-sparse LDPC code;

[0036] A parallel encoding module is used to pre-process the information in the allocated memory and video memory space before encoding, and allocate on-chip shared memory and register resources for generating matrix temporary variables and updating check bits;

[0037] The GPU encoder updates the check bit using inter-frame parallelism and intra-frame parallelism, assigns the updated check bit information to the corresponding position of the encoding result display memory space d_output, and transfers the encoding result from the encoding result display memory space d_output to the encoding result memory space h_output in an asynchronous transmission mode;

[0038] The resource release module is used to release or destroy the initialization process data after the GPU encoder completes the encoding of all code words, and completes the high-speed parallel GPU encoding of non-sparse LDPC codes for near-Earth satellite ground stations.

[0039] On the other hand, a non-sparse LDPC code high-speed parallel GPU encoder electronic device is provided, and the non-sparse LDPC code high-speed parallel GPU encoder electronic device comprises: a processor; a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, any one of the above-mentioned non-sparse LDPC code high-speed parallel GPU encoding methods is implemented.

[0040] On the other hand, a computer-readable storage medium is provided, wherein at least one instruction is stored in the storage medium, and the at least one instruction is loaded and executed by a processor to implement any one of the above-mentioned non-sparse LDPC code high-speed parallel GPU encoding methods.

[0041] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0042] In an embodiment of the present invention, a non-sparse LDPC code high-speed parallel GPU encoder for a near-Earth satellite ground station is provided, which adopts a large-scale inter-frame parallelism and intra-frame parallelism, and can make full use of GPU on-chip storage and computing resources. The non-sparse LDPC code high-speed parallel GPU encoder for a near-Earth satellite ground station provided by the present invention adopts a more convenient generation matrix circular shift method, and when the check bit is updated, the information bits at the same position of multiple frames are updated simultaneously, which greatly improves the instruction execution efficiency and memory access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 This is a flow chart of a high-speed parallel GPU encoding method for non-sparse LDPC codes provided by an embodiment of the present invention;

[0045] Figure 2 Schematic diagram of a high-speed parallel GPU encoding architecture for non-sparse LDPC codes provided by an embodiment of the present invention;

[0046] Figure 3 It is a cyclic structure characteristic diagram of a non-sparse LDPC code encoding matrix provided by an embodiment of the present invention;

[0047] Figure 4 Schematic diagram of two inter-frame parallelisms of an encoder provided by an embodiment of the present invention;

[0048] Figure 5 It is a schematic diagram of storing and accessing a generator matrix in a shared memory according to a check bit provided by an embodiment of the present invention;

[0049] Figure 6 1. It is a schematic diagram of the structure of a high-speed parallel GPU encoder for non-sparse LDPC codes provided by an embodiment of the present invention;

[0050] Figure 7 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0052] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.

[0053] In the embodiments of the present invention, sometimes a subscript such as W1 may be written as a non-subscript such as W1. When the difference is not emphasized, the meanings to be expressed are the same.

[0054] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0055] The embodiment of the present invention provides a non-sparse LDPC code high-speed parallel GPU encoding method, which can be implemented by a non-sparse LDPC code high-speed parallel GPU encoder electronic device, which can be a terminal or a server. Figure 1 The flowchart of the non-sparse LDPC code high-speed parallel GPU encoding method shown in the figure, the processing flow of the method may include the following steps:

[0056] S1. Acquire a non-sparse LDPC code for a near-Earth satellite ground station, and perform encoding initialization based on the non-sparse LDPC code; allocate memory and video memory space for information to be stored; the encoding initialization includes: preprocessing the cyclic generator matrix parameters of the non-sparse LDPC code.

[0057] In a feasible implementation, for the convenience of storage, the generator matrix of the LDPC code is generally a block cyclic matrix, but the coding cyclic matrix of the LDPC code is not necessarily sparse (such as the LDPC code used by the CCSDS low-Earth satellite). This non-sparse LDPC code coding matrix will bring greater coding complexity and limit the encoder rate. The coding process of the LDPC code mainly involves bit operations, and the operation is relatively simple. The present invention makes full use of the operation characteristics of the LDPC code coding process and the cyclic characteristics of the low-Earth satellite LDPC code generator matrix to greatly improve the LDPC coding rate.

[0058] In a feasible implementation, in order to improve the decoding rate, the most notable feature of the LDPC code is that the check matrix is ​​sparse, that is, most of the elements in the matrix are zero. This sparsity makes the LDPC code have a lower complexity when decoding. In order to facilitate storage, the generator matrix of the LDPC code is generally a block cyclic matrix. Although the check matrix required for the decoding process is sparse, the coding cyclic matrix of the LDPC code is not necessarily sparse (such as the LDPC code used by the CCSDS low-Earth satellite). This non-sparse LDPC code coding matrix will bring greater coding complexity and limit the encoder rate. The encoding process of the LDPC code mainly involves bit operations, and the operation operations are relatively simple. The present invention involves a non-sparse LDPC code high-speed parallel GPU encoder for low-Earth satellite ground stations, which makes full use of the operational characteristics of the LDPC code encoding process and the cyclic characteristics of the low-Earth satellite LDPC code generator matrix. Its overall coding architecture is as follows Figure 2 shown.

[0059] In a feasible implementation manner, in S1, preprocessing the cyclic generator matrix parameters of the non-sparse LDPC code includes:

[0060] Set the information bit length k, code length n, generator matrix sub-block dimension Z, sub-block column number nc, sub-block row number nk and puncturing length of the LDPC code;

[0061] Each sub-block of the generator matrix of the LDPC code has a cyclic feature, that is, the next row of each sub-block is obtained by shifting one row to the right of the previous row; Figure 3 The first row of the first block information bits of each generator matrix sub-block (given in hexadecimal form) is given, where nc=8, Z=32, nk=32. Then the first row of information of each sub-block of the LDPC code generator matrix can represent the entire generator matrix;

[0062] The bit information of the LDPC code generation matrix sub-block is encapsulated and packaged according to the bit, and the encapsulated and packaged array is stored using an unsigned integer or unsigned long integer data type array to obtain the encapsulated and packaged matrix information h_g.

[0063] In a feasible implementation, in S1, allocating memory and video memory space for information to be stored includes:

[0064] Allocate device memory space for information bits and encoding results; allocate constant memory c_g for the generator matrix of the LDPC code, and initialize it with the packaged matrix information h_g;

[0065] Create an asynchronous stream for the encoding phase, initializing the dimensions and size of the thread blocks.

[0066] In a feasible implementation manner, the information bits before encoding and the encoding results are generally stored in the host memory, and the host memory space is allocated for the information bits and the encoding results in the initialization phase, such as Figure 2 The h_input and h_output in the table represent the memory space allocated for the information bits before encoding and the encoding result, respectively; accordingly, the device memory space needs to be allocated for the information bits and the encoding result, such as Figure 2 The d_input and d_output in the above table represent the memory space allocated for the information bits before encoding and the encoding result, respectively. The generator matrix of the LDPC code is a constant. The constant memory space c_g allocated for the generator matrix is ​​initialized using the encapsulated generator matrix information h_g. [8] represents the number of elements in the array. For example, g[8] means that 8 registers g are allocated.

[0067] S2, pre-processing the information of the allocated memory and video memory space before encoding, and allocating on-chip shared memory and register resources for the required information;

[0068] In a feasible implementation, in S2, the information of the allocated memory and video memory space is pre-processed before encoding, and on-chip shared memory and register resources are allocated for the required information, including:

[0069] Use the information bits h_input allocated in the host memory to initialize the information bits d_input in the global memory in an asynchronous transmission manner;

[0070] Before encoding, on-chip resources are allocated for the temporary variables of the generated matrix and the updated check bits respectively; a shared memory space sh_g is allocated for the generated matrix and initialized with c_g in the constant memory;

[0071] There are two ways to store the generated matrix in the shared memory sh_g: storage based on the check bit or storage based on the bit packing method in c_g;

[0072] In a feasible implementation, because the values ​​of the elements of the generator matrix are 0 or 1, they can be stored in bits. For example, an unsigned integer can store 32 bits of information of the generator matrix. This is what bit packing means. Figure 4 A similar method for packing information bits is provided, such as a method for packing and storing information bits using a temporary variable register msg.

[0073] The check bits belonging to different sub-blocks are loop-unrolled, and multiple registers are allocated for the check bits and sub-block generation matrices before encoding, e.g. Figure 2 As shown, check and g represent the allocated check bit register and the sub-block generation matrix register, respectively, which facilitates the use of loop unrolling technology to improve instruction execution efficiency.

[0074] In a feasible implementation, the inter-frame parallelism and the intra-frame parallelism are as follows: Figure 4 As shown, including:

[0075] The intra-frame parallelism is the dimension Z of the sub-block, that is, the check information belonging to the same sub-block is updated simultaneously;

[0076] There are two types of inter-frame parallelism: multi-frame parallelism assigned to the same thread block and multi-frame parallelism assigned to different thread blocks.

[0077] In a feasible implementation, the shared memory sh_g can store the generated matrix in two ways: bit-by-bit storage or storage in a bit-packed manner in c_g. For the bit-by-bit storage method, the present invention allocates a storage space of twice the length of the check bit to the shared memory sh_g of the generated matrix, and the data type is an unsigned character type. Figure 5 As shown. In this way, the loop of the generator matrix in the sub-block can be achieved by adjusting the offset, reducing the number of remainder operations. For the storage method based on the bit packing in c_g, the access efficiency of the shared memory is relatively high, but more shift, remainder and division operations are required to complete the access to the bit information of the generator matrix at the corresponding position.

[0078] S3. Through the GPU encoder, the check bit is updated by using the inter-frame parallelism and the intra-frame parallelism, and the updated check bit information is assigned to the corresponding position of d_output, and the encoding result is transmitted to h_output in an asynchronous transmission manner.

[0079] In a feasible implementation, general-purpose processors have developed into multi-core processors with numerous parallel resources. In order to meet the needs of future communication systems for flexibility and scalability, the present invention selects general-purpose processors as development platforms to study parallel decoding technology. There are two main types of general-purpose processors: central processing units (CPUs) and graphics processing units (GPUs). The present invention selects GPUs with good design flexibility and relatively stable performance as programming development platforms, and designs high-performance non-sparse LDPC code GPU parallel encoders to meet the development needs of software and virtualization of future satellite ground station systems.

[0080] In a feasible implementation, in S3, the check bit is updated by using the inter-frame parallelism and the intra-frame parallelism, the updated check bit information is assigned to the corresponding position of d_output, and the encoding result is transmitted from d_output to h_output in an asynchronous transmission manner, including:

[0081] According to the information bit d_input, assign a value to the information bit position of each frame in d_output;

[0082] Based on the inter-frame parallelism and intra-frame parallelism, the check bits of the multi-frame codewords assigned to the same thread block are updated in a partially parallel update manner; for each check bit, a serial update manner is adopted;

[0083] After the check bit is updated for each information bit, the check bit in register check is used to assign a value to the corresponding check bit of d_output according to the puncturing rule;

[0084] The encoding result stored in d_output is updated in the memory space h_output by asynchronous transmission.

[0085] In a feasible implementation, the LDPC encoding process mainly involves the operation of bit data. Considering that the bit information from different frames but at the same position is operated with the generator matrix information at the same position, the present invention converts adjacent multiple frames (such as Figure 4 The bit information at the same position of the 32 frames in the matrix is ​​encapsulated and stored as bits, and then multiplied with the bit information at the corresponding position of the generator matrix to maximize the instruction efficiency. To achieve this purpose, the present invention assigns adjacent multi-frame codewords to the same thread block for processing. In order to improve the utilization rate of the entire computing resource, the present invention further improves the inter-frame parallelism by allocating multiple thread blocks.

[0086] In a feasible implementation manner, S3 further includes:

[0087] Before partially updating the check bits in parallel, the information bits at the same position in multiple frames allocated to the same thread block need to be packed and stored in the unsigned integer or unsigned long integer register msg according to the bits, such as Figure 4 msg in the code to improve memory access efficiency in the subsequent encoding process;

[0088] Before updating the check bit, the sub-block generator matrix register g needs to be initialized according to the generator matrix information in the shared memory; when initializing g, different processing needs to be performed according to the storage method of the generator matrix in the shared memory sh_g.

[0089] The check bit check is partially updated in parallel according to the updated information bit register msg and the sub-block generation matrix register g, and the partial parallel update is implemented by loop unrolling.

[0090] S4. After the GPU encoder completes encoding of all codewords, the initialization process data is released or destroyed, and the high-speed parallel GPU encoding of non-sparse LDPC codes for near-Earth satellite ground stations is completed.

[0091] In a feasible implementation, in S4, after the GPU encoder completes encoding of all codewords, the initialization process data is released or destroyed, including:

[0092] When the GPU encoder completes encoding of all codewords, it releases or destroys the memory and video memory allocated during the initialization process and the asynchronous stream created; it releases the memory space h_input and h_output, releases the video memory space d_input and d_output, and destroys the asynchronous stream created.

[0093] In an embodiment of the present invention, a non-sparse LDPC code high-speed parallel GPU encoder for a near-Earth satellite ground station is provided, which adopts a large-scale inter-frame parallelism and intra-frame parallelism, and can fully utilize the GPU on-chip storage and computing resources.

[0094] The non-sparse LDPC code high-speed parallel GPU encoder for near-Earth satellite ground stations provided by the present invention adopts a more convenient generation matrix cyclic shift method, and simultaneously updates the information bits at the same position of multiple frames when the check bits are updated, thereby greatly improving the instruction execution efficiency and memory access efficiency.

[0095] Figure 6 1 is a block diagram of a non-sparse LDPC code high-speed parallel GPU encoder 300 according to an exemplary embodiment. The encoder 300 is used in a non-sparse LDPC code high-speed parallel GPU encoding method. Figure 6 The encoder includes an encoding initialization module 310, a parallel encoding module 320 and a resource release module 330. Among them:

[0096] The coding initialization module 310 is used to obtain a non-sparse LDPC code for a near-Earth satellite ground station, and perform coding initialization based on the non-sparse LDPC code; allocate memory and video memory space for information to be stored; the coding initialization includes: preprocessing the cyclic generator matrix parameters of the non-sparse LDPC code;

[0097] A parallel encoding module 320 is used to pre-process the information allocated with memory and video memory space before encoding, and allocate on-chip shared memory and register resources for the required information;

[0098] Through the GPU encoder, the check bit is updated using inter-frame parallelism and intra-frame parallelism, the updated check bit information is assigned to the corresponding position of d_output, and the encoding result is transmitted to h_output in an asynchronous transmission mode.

[0099] The resource release module 330 is used to release or destroy the initialization process data after the GPU encoder completes the encoding of all code words, and complete the high-speed parallel GPU encoding of non-sparse LDPC codes for near-Earth satellite ground stations.

[0100] Optionally, the coding initialization module 310 is used to set the information bit length k, the code length n, the generator matrix sub-block dimension Z, the number of sub-block columns nc, the number of sub-block rows nk and the puncturing length of the LDPC code;

[0101] Among them, each sub-block of the LDPC code generator matrix has a cyclic feature, that is, the next row of each sub-block is obtained by shifting one row to the right of the previous row; then storing the first row information of each sub-block of the LDPC code generator matrix can represent the entire generator matrix;

[0102] The bit information of the LDPC code generation matrix sub-block is encapsulated and packaged according to the bit, and the encapsulated and packaged array is stored using an unsigned integer or unsigned long integer data type array to obtain the encapsulated and packaged matrix information h_g.

[0103] Optionally, the encoding initialization module 310 is used to allocate device memory space for information bits and encoding results; allocate constant memory c_g for the generator matrix of the LDPC code, and initialize the constant memory c_g of the generator matrix using the encapsulated and packaged matrix information h_g;

[0104] Create an asynchronous stream for the encoding phase, initializing the dimensions and size of the thread blocks.

[0105] Optionally, the parallel encoding module 320 is used to use the information bits h_input allocated in the host memory to initialize the information bits d_input in the global memory in an asynchronous transmission manner;

[0106] Before encoding, on-chip resources are allocated for temporary variables of the generator matrix and updated check bits respectively; a shared memory space sh_g is allocated for the generator matrix, and the shared memory space sh_g of the generator matrix is ​​initialized using the constant memory c_g of the generator matrix; wherein, in the shared memory space sh_g of the generator matrix, the storage of the generator matrix includes two methods: storage according to the check bits or storage according to the bit packing method in the constant memory c_g of the generator matrix;

[0107] Loop expansion is performed on the check bits belonging to different sub-blocks, and multiple register resources check and g are respectively allocated to the check bits and the sub-block generation matrix before encoding, where check represents the allocated check bit register and g represents the allocated sub-block generation matrix register.

[0108] Optionally, inter-frame parallelism and intra-frame parallelism include:

[0109] The intra-frame parallelism is that the check information belonging to the same generator matrix sub-block dimension Z is updated simultaneously;

[0110] Inter-frame parallelism includes: multi-frame parallel updates assigned to the same thread block and multi-frame parallel updates assigned to different thread blocks.

[0111] Optionally, the parallel encoding module 320 is used to assign a value to the information bit position of each frame in the encoding result display memory space d_output according to the information bit d_input in the global memory;

[0112] Based on the inter-frame parallelism and intra-frame parallelism, the check bits of the multi-frame codewords assigned to the same thread block are updated by partial parallel update; each check bit is updated by serial update;

[0113] After the check bit is updated for each information bit, the check bit in the check bit register check is used to assign a value to the corresponding check bit in the encoding result display memory space d_output;

[0114] The encoding result stored in the encoding result display memory space d_output is used to update the encoding result memory space h_output in an asynchronous transmission manner.

[0115] Optionally, the parallel encoding module 320 is used to pack and store information bits at the same position of multiple frames allocated to the same thread block in an unsigned integer or unsigned long integer register msg according to bits before adopting partial parallel update on the check bits;

[0116] Before updating the check bit, the sub-block generator matrix register g needs to be initialized according to the generator matrix information in the shared memory;

[0117] The check bit register check is partially updated in parallel according to the updated register msg and the sub-block generation matrix register g, wherein the partial parallel update is implemented by loop unrolling.

[0118] Optionally, the resource release module 330 is used to release or destroy the memory and video memory allocated in the initialization process and the created asynchronous stream after the GPU encoder completes the encoding of all codewords; release h_input and h_output in the memory space, release d_input and d_output in the video memory space, and destroy the created asynchronous stream.

[0119] In an embodiment of the present invention, a non-sparse LDPC code high-speed parallel GPU encoder for a near-Earth satellite ground station is provided, which adopts a large-scale inter-frame parallelism and intra-frame parallelism, and can fully utilize the GPU on-chip storage and computing resources.

[0120] The non-sparse LDPC code high-speed parallel GPU encoder for near-Earth satellite ground stations provided by the present invention adopts a more convenient generation matrix cyclic shift method, and simultaneously updates the information bits at the same position of multiple frames when the check bits are updated, thereby greatly improving the instruction execution efficiency and memory access efficiency.

[0121] Figure 7 is a structural diagram of a non-sparse LDPC code high-speed parallel GPU encoder electronic device provided by an embodiment of the present invention, such as Figure 7 As shown, the non-sparse LDPC code high-speed parallel GPU encoder electronic device may include the above Figure 6 The non-sparse LDPC code high-speed parallel GPU encoder shown. Optionally, the non-sparse LDPC code high-speed parallel GPU encoder electronic device 410 may include a first processor 2001 .

[0122] Optionally, the non-sparse LDPC code high-speed parallel GPU encoder electronic device 410 may further include a memory 2002 and a transceiver 2003 .

[0123] The first processor 2001, the memory 2002 and the transceiver 2003 may be connected via a communication bus.

[0124] Combine the following Figure 7 The components of the non-sparse LDPC code high-speed parallel GPU encoder electronic device 410 are specifically introduced:

[0125] The first processor 2001 is the control center of the non-sparse LDPC code high-speed parallel GPU encoder electronic device 410, which can be a processor or a general term for multiple processing elements. For example, the first processor 2001 is one or more central processing units (CPUs), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiment of the present invention, such as one or more microprocessors (digital signal processors, DSPs), or one or more field programmable gate arrays (field programmable gate arrays, FPGAs).

[0126] Optionally, the first processor 2001 can perform various functions of the non-sparse LDPC code high-speed parallel GPU encoder electronic device 410 by running or executing a software program stored in the memory 2002 and calling data stored in the memory 2002.

[0127] In a specific implementation, as an embodiment, the first processor 2001 may include one or more CPUs, such as Figure 7 CPU0 and CPU1 are shown in FIG.

[0128] In a specific implementation, as an embodiment, the non-sparse LDPC code high-speed parallel GPU encoder electronic device 410 may also include multiple processors, such as Figure 7 The first processor 2001 and the second processor 2004 are shown in FIG. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0129] The memory 2002 is used to store the software program for executing the solution of the present invention, and is controlled to be executed by the first processor 2001. The specific implementation method can refer to the above method embodiment, which will not be repeated here.

[0130] Optionally, the memory 2002 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 2002 may be integrated with the first processor 2001, or may exist independently, and may be accessed through the interface circuit ( Figure 7 (not shown) is coupled to the first processor 2001, which is not specifically limited in this embodiment of the present invention.

[0131] The transceiver 2003 is used to communicate with a network device or a terminal device.

[0132] Optionally, the transceiver 2003 may include a receiver and a transmitter ( Figure 7 The receiver is used to implement a receiving function, and the transmitter is used to implement a sending function.

[0133] Optionally, the transceiver 2003 may be integrated with the first processor 2001, or may exist independently, and may be connected to the first processor 2001 through the interface circuit ( Figure 7 (not shown) is coupled to the first processor 2001, which is not specifically limited in this embodiment of the present invention.

[0134] It should be noted that Figure 7 The structure of the non-sparse LDPC code high-speed parallel GPU encoder electronic device 410 shown in the figure does not constitute a limitation on the router, and the actual knowledge structure recognition device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0135] In addition, the technical effects of the non-sparse LDPC code high-speed parallel GPU encoder electronic device 410 can refer to the technical effects of the non-sparse LDPC code high-speed parallel GPU encoding method described in the above method embodiment, and will not be repeated here.

[0136] It should be understood that the first processor 2001 in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0137] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0138] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable sensors. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0139] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0140] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0141] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0142] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0143] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0144] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.

[0145] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A high-speed parallel GPU encoding method for non-sparse LDPC codes, characterized in that: The method is applicable to a non-sparse LDPC code high-speed parallel GPU encoder for a near-Earth satellite ground station, and the method comprises: S1, obtaining a non-sparse LDPC code for a near-Earth satellite ground station, and performing encoding initialization based on the non-sparse LDPC code; allocating memory space and video memory space for information to be stored; the encoding initialization includes: preprocessing the cyclic generator matrix parameters of the non-sparse LDPC code; S2, pre-processing the information of the allocated memory space and video memory space before encoding; allocating on-chip shared memory and register resources for generating matrix temporary variables and updating check bits; S3, updating the check bit by using the GPU encoder in the manner of inter-frame parallelism and intra-frame parallelism, assigning the updated check bit to the corresponding position of the encoding result display memory space d_output, and obtaining the encoding result; transferring the encoding result from the encoding result display memory space d_output to the encoding result memory space h_output in the manner of asynchronous transmission; The inter-frame parallelism and intra-frame parallelism include: The intra-frame parallelism is that the check information belonging to the same generator matrix sub-block dimension Z is updated simultaneously; Inter-frame parallelism includes: multi-frame parallel updates assigned to the same thread block and multi-frame parallel updates assigned to different thread blocks; In S3, the check bit is updated by the GPU encoder using inter-frame parallelism and intra-frame parallelism, and the updated check bit is assigned to the corresponding position of the encoding result display memory space d_output to obtain the encoding result; the encoding result is transferred from the encoding result display memory space d_output to the encoding result memory space h_output in an asynchronous transmission manner, including: According to the information bit d_input in the global memory, the information bit position of each frame in the encoding result display memory space d_output is assigned; Based on the inter-frame parallelism and intra-frame parallelism, the check bits of the multi-frame codewords assigned to the same thread block are updated by partial parallel update; each check bit is updated by serial update; After the check bit is updated for each information bit, the check bit in the check bit register check is used to assign a value to the corresponding check bit in the encoding result display memory space d_output; Use the encoding result stored in the encoding result display memory space d_output to update the encoding result memory space h_output in an asynchronous transmission manner; S4. After the GPU encoder completes the encoding of all codewords, it releases or destroys the initialization process data, completing the high-speed parallel GPU encoding of non-sparse LDPC codes for near-Earth satellite ground stations.

2. The non-sparse LDPC code high-speed parallel GPU encoding method according to claim 1, characterized in that: In S1, preprocessing the cyclic generator matrix parameters of the non-sparse LDPC code includes: Set the information bit length k, code length n, generator matrix sub-block dimension Z, sub-block column number nc, sub-block row number nk and puncturing length of the non-sparse LDPC code; Among them, each sub-block of the generator matrix of the non-sparse LDPC code has a cyclic feature, that is, the next row of each sub-block is obtained by shifting one row to the right of the previous row; then the first row information of each sub-block of the stored non-sparse LDPC code generator matrix can represent the entire generator matrix; The bit information of the non-sparse LDPC code generation matrix sub-block is encapsulated and packaged according to the bit, and the encapsulated and packaged array is stored using an unsigned integer or unsigned long integer data type array to obtain the encapsulated and packaged matrix information h_g.

3. The non-sparse LDPC code high-speed parallel GPU encoding method according to claim 1, characterized in that: In S1, memory and video memory space are allocated for information to be stored, including: Allocate device memory space for information bits and encoding results; allocate constant memory c_g for the generator matrix of non-sparse LDPC code, and initialize the constant memory c_g of the generator matrix using the packaged matrix information h_g; Create an asynchronous stream for the encoding phase, initializing the dimensions and size of the thread blocks.

4. The non-sparse LDPC code high-speed parallel GPU encoding method according to claim 3, characterized in that: In S2, the information of the allocated memory and video memory space is pre-processed before encoding, and on-chip shared memory and register resources are allocated for generating matrix temporary variables and updating check bits, including: Use the information bits h_input allocated in the host memory to initialize the information bits d_input in the global memory in an asynchronous transmission manner; Before encoding, on-chip resources are allocated for temporary variables of the generator matrix and updated check bits respectively; a shared memory space sh_g is allocated for the generator matrix, and the shared memory space sh_g of the generator matrix is ​​initialized using the constant memory c_g of the generator matrix; wherein, in the shared memory space sh_g of the generator matrix, the storage of the generator matrix includes two methods: storage according to the check bits or storage according to the bit packing method in the constant memory c_g of the generator matrix; Loop expansion is performed on the check bits belonging to different sub-blocks, and multiple register resources check and g are respectively allocated to the check bits and the sub-block generation matrix before encoding, where check represents the allocated check bit register and g represents the allocated sub-block generation matrix register.

5. The non-sparse LDPC code high-speed parallel GPU encoding method according to claim 4, characterized in that: The S3 further includes: Before updating the check bit part in parallel, the information bits at the same position of multiple frames allocated to the same thread block are packed and stored in the register msg of unsigned integer or unsigned long integer according to the bits; Before updating the check bit, the sub-block generator matrix register g needs to be initialized according to the generator matrix information in the shared memory; The check bit register check is partially updated in parallel according to the updated register msg and the sub-block generation matrix register g, wherein the partial parallel update is implemented by loop unrolling.

6. The non-sparse LDPC code high-speed parallel GPU encoding method according to claim 5, characterized in that: In S4, after the GPU encoder completes encoding of all codewords, the initialization process data is released or destroyed, including: When the GPU encoder completes encoding of all codewords, the memory and video memory allocated during the initialization process and the created asynchronous stream are released or destroyed; the information bits h_input of the memory space and the encoding result memory space h_output are released, the information bits d_input of the video memory space and the encoding result video memory space d_output are released, and the created asynchronous stream is destroyed.

7. A non-sparse LDPC code high-speed parallel GPU encoder, wherein the non-sparse LDPC code high-speed parallel GPU encoder is used to implement the non-sparse LDPC code high-speed parallel GPU encoding method according to any one of claims 1 to 6, characterized in that: The encoder comprises: A coding initialization module is used to obtain a non-sparse LDPC code for a near-Earth satellite ground station, and perform coding initialization based on the non-sparse LDPC code; allocate memory space and video memory space for information to be stored; the coding initialization includes: preprocessing the cyclic generator matrix parameters of the non-sparse LDPC code; A parallel encoding module is used to pre-process the information in the allocated memory space and video memory space before encoding; allocate on-chip shared memory and register resources for generating matrix temporary variables and updating check bits; The check bit is updated by the GPU encoder using the inter-frame parallelism and intra-frame parallelism, and the updated check bit is assigned to the corresponding position of the encoding result display memory space d_output to obtain the encoding result; the encoding result is transferred from the encoding result display memory space d_output to the encoding result memory space h_output in an asynchronous transmission manner; The resource release module is used to release or destroy the initialization process data after the GPU encoder completes the encoding of all codewords, and completes the high-speed parallel GPU encoding of non-sparse LDPC codes for near-Earth satellite ground stations.

8. A non-sparse LDPC code high-speed parallel GPU encoder electronic device, characterized in that: The non-sparse LDPC code high-speed parallel GPU encoder control device comprises: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the method according to any one of claims 1 to 6 is implemented.

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