Semiconductor device

Abstract

The present disclosure relates to a semiconductor device, including a semiconductor device having a backside power delivery network (BSPDN). An example semiconductor device includes a substrate including a first surface and a second surface opposite to each other; a first active pattern on the first surface; a first gate structure crossing the first active pattern; and a first rear wiring pattern and a second rear wiring pattern disposed on the second surface at the same height from the substrate. The first rear wiring pattern includes a first extension portion and a second extension portion each extending in a first direction, and a connection portion extending in a second direction crossing the first direction to connect the first extension portion to the second extension portion. The second rear wiring pattern is spaced apart from the first extension portion in the second direction and spaced apart from the connection portion in the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits obtained from Korean Patent Application No. 10-2023-0094667 filed in the Korean Intellectual Property Office on July 20, 2023, the entire contents of which are incorporated herein by reference. Background Art

[0003] Semiconductor devices have attracted attention as important elements in the electronics industry due to characteristics such as miniaturization, multi-functions, and / or low manufacturing costs. Semiconductor devices can be divided into semiconductor memory devices for storing logic data, semiconductor logic devices for processing calculations of logic data, hybrid semiconductor devices including storage elements and logic elements, and the like.

[0004] As the electronics industry advances, the requirements for the characteristics of semiconductor devices continue to increase. For example, the requirements for high reliability, high speed and / or multifunctionality of semiconductor devices are increasing. In order to meet these required characteristics, the structure of semiconductor devices has become more and more complex and highly integrated. Summary of the invention

[0005] The present disclosure relates to semiconductor devices, including semiconductor devices with improved design freedom and integration density, and is not limited to the examples set forth herein. Other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0006] Generally, according to some aspects, a semiconductor device includes: a substrate including a first surface and a second surface opposite to each other; a first active pattern on the first surface of the substrate; a first gate structure intersecting the first active pattern; and a first rear wiring pattern and a second rear wiring pattern arranged at the same height on the second surface of the substrate, wherein the first rear wiring pattern includes a first extension portion and a second extension portion both extending along a first direction, and a connecting portion extending along a second direction intersecting the first direction to connect the first extension portion to the second extension portion, and the second rear wiring pattern is spaced apart from the first extension portion in the second direction and spaced apart from the connecting portion in the first direction.

[0007] In general, according to some aspects, a semiconductor device includes: a substrate including a first surface and a second surface opposite to each other; a first active pattern and a second active pattern extending side by side on the first surface of the substrate; a first gate structure intersecting the first active pattern and the second active pattern; a first rear wiring pattern to a third rear wiring pattern arranged at the same height on the second surface of the substrate and spaced apart from each other; a first rear source / drain contact connecting a first source / drain region of the first active pattern to the first rear wiring pattern; a second rear source / drain contact connecting a second source / drain region of the second active pattern to the second rear wiring pattern; a fourth rear wiring pattern farther from the substrate on the second surface of the substrate than the first rear wiring pattern to the third rear wiring pattern; and a first rear via pattern connecting the second rear wiring pattern to the fourth rear wiring pattern, wherein the first rear wiring pattern includes a first extension portion and a second extension portion both extending along a first direction, and a connecting portion extending along a second direction intersecting the first direction to connect the first extension portion to the second extension portion, and the connecting portion is between the second rear wiring pattern and the third rear wiring pattern in the first direction.

[0008] In general, according to some aspects, a semiconductor device includes: a substrate including a first surface and a second surface opposite to each other; a first active pattern on the first surface of the substrate; a first gate structure and a second gate structure extending parallel to each other and both crossing the first active pattern; a first source / drain contact connected to the first active pattern and between the first gate structure and the second gate structure; a first rear wiring pattern to a third rear wiring pattern disposed at the same height on the second surface of the substrate and spaced apart from each other; a first rear source / drain contact connecting the first active pattern to the first rear wiring pattern, the first gate structure being disposed between the first rear source / drain contact and the first source / drain contact; a second rear source / drain contact connecting the first active pattern to the first rear wiring pattern, the first gate structure being disposed between the first rear source / drain contact and the first source / drain contact; A drain contact connects the first active pattern to a second rear wiring pattern, the second gate structure being disposed between the second rear source / drain contact and the first source / drain contact; a fourth rear wiring pattern being farther from the substrate on the second surface of the substrate than the first rear wiring pattern to the third rear wiring pattern; a first rear via pattern connecting the second rear wiring pattern to the fourth rear wiring pattern, wherein the first rear wiring pattern includes a first extension portion and a second extension portion both extending along a first direction, and a connecting portion extending along a second direction intersecting the first direction to connect the first extension portion to the second extension portion, and the connecting portion is between the second rear wiring pattern and the third rear wiring pattern in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0010] Figure 1is a circuit diagram showing an example of a semiconductor device.

[0011] Figure 2 is a layout diagram showing an example of a semiconductor device.

[0012] Figure 3 is along Figure 2 A schematic cross-sectional view taken along line AA.

[0013] Figure 4 is along Figure 2 A schematic cross-sectional view taken along line BB of FIG.

[0014] Figure 5 is along Figure 2 Schematic cross-sectional view taken along line CC.

[0015] Figures 6 to 11 is a layout diagram for explaining an example of a semiconductor device.

[0016] Fig.12 is a layout diagram showing an example of a semiconductor device.

[0017] Fig.13 is along Fig.12 Schematic cross-sectional view taken along line DD.

[0018] Fig.14 is along Fig.12 A schematic cross-sectional view taken along line EE of FIG.

[0019] Fig.15 is along Fig.12 Schematic cross-sectional view taken along line FF.

[0020] Fig.16 and Fig.17 is a layout diagram for explaining an example of a semiconductor device.

[0021] Fig.18 is a circuit diagram showing an example of a semiconductor device.

[0022] Fig.19 and Fig. 20 is a layout diagram for explaining an example of a semiconductor device.

[0023] Fig.21 is a circuit diagram showing an example of a semiconductor device.

[0024] Fig. 22 and Fig.23 is a layout diagram for explaining an example of a semiconductor device. DETAILED DESCRIPTION

[0025] Although the terms "first", "second", etc. may be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are used to distinguish one element or component from another element or component. Therefore, without departing from the teachings of the present disclosure, the first element or component discussed below may also be referred to as the second element or component.

[0026] In the following, reference will be made to Figures 1 to 23 A semiconductor device according to an exemplary embodiment is described. Hereinafter, the embodiments disclosed below mainly describe a static random access memory (SRAM) element as a semiconductor device, but this is only exemplary. Those skilled in the art will understand that the technical spirit of the present disclosure can be applied not only to SRAM elements, but also to various other semiconductor devices such as logic elements.

[0027] Figure 1 is a circuit diagram showing an example of a semiconductor device.

[0028] Reference Figure 1 , the semiconductor device includes a parallel connection at the power supply node V DD and ground node V SS A pair of inverters INV1 and INV2 therebetween, and first and second pass transistors PS1 and PS2 connected to output nodes of the respective inverters INV1 and INV2.

[0029] The first pass transistor PS1 may be connected to a bit line BL, and the second pass transistor PS2 may be connected to a complementary bit line / BL. Gates of the first pass transistor PS1 and the second pass transistor PS2 may be connected to a word line WL.

[0030] In order to configure a latch circuit, an input node of the first inverter INV1 may be connected to an output node of the second inverter INV2, and an input node of the second inverter INV2 may be connected to an output node of the first inverter INV1.

[0031] The first inverter INV1 may include a first pull-up transistor PU1 and a first pull-down transistor PD1 connected in series, and the second inverter INV2 may include a second pull-up transistor PU2 and a second pull-down transistor PD2 connected in series. The first pull-up transistor PU1 and the second pull-up transistor PU2 may be PFETs, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NFETs.

[0032] Figure 2 is a layout diagram showing an example of a semiconductor device. Figure 3 is along Figure 2 A schematic cross-sectional view taken along line AA. Figure 4is along Figure 2 A schematic cross-sectional view taken along line BB of FIG. Figure 5 is along Figure 2 Schematic cross-sectional view taken along line CC.

[0033] Reference Figures 1 to 5 , the semiconductor device includes a device region DR, a front region FR and a back region BR.

[0034] The element region DR may include a substrate 100 , a field insulating layer 105 , first to fourth active patterns AP1 to AP4 , first to fourth gate structures GS1 to GS4 , source / drain contacts 171 to 178 , a first shared contact NC1 , a second shared contact NC2 , first and second interlayer insulating layers ID1 and ID2 .

[0035] The substrate 100 may be a bulk silicon or silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may be a silicon substrate, or may include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 may have an epitaxial layer formed on a base substrate.

[0036] In some embodiments, the substrate 100 may be an insulating substrate including an insulating material. For example, the substrate 100 may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbonitride, or a combination thereof, but is not limited thereto. For example, the substrate 100 may include a silicon oxide layer.

[0037] The substrate 100 may include a first surface 100 a and a second surface 100 b opposite to each other. In the following embodiments, the first surface 100 a may also be referred to as a front surface of the substrate 100 , and the second surface 100 b may also be referred to as a back surface of the substrate 100 .

[0038] The first to fourth active patterns AP1 to AP4 may be formed on the first surface 100a of the substrate 100. The first to fourth active patterns AP1 to AP4 may be spaced apart from each other and extend side by side in the first direction Y. For example, the first to fourth active patterns AP1 to AP4 may each be elongated in the first direction Y and may be sequentially arranged along a second direction X intersecting the first direction Y.

[0039] Each of the first to fourth active patterns AP1 to AP4 may include an elemental semiconductor material such as silicon (Si) or germanium (Ge). Alternatively, each of the first to fourth active patterns AP1 to AP4 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be a binary compound or a ternary compound including at least two elements selected from the group consisting of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or the above-mentioned compound doped with a group IV element. The group III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as group III elements with at least one of phosphorus (P), arsenic (As), and antimony (Sb) as group V elements.

[0040] In some embodiments, the first and fourth active patterns AP1 and AP4 may function as channel regions of an NFET, and the second and third active patterns AP2 and AP3 may function as channel regions of a PFET.

[0041] In some embodiments, each of the first to fourth active patterns AP1 to AP4 may be sequentially stacked on the substrate 100 and may include a plurality of bridge patterns (e.g., first to third bridge patterns 111 to 113) spaced apart from each other. These first to fourth active patterns AP1 to AP4 may be used as a plurality of bridge channels including a plurality of bridge channels. The number of bridge patterns included in each of the first to fourth active patterns AP1 to AP4 is merely exemplary and is not limited thereto.

[0042] In some embodiments, the fin pattern 110F may be formed between the substrate 100 and the first bridge pattern 111. The fin pattern 110F may protrude from the first surface 100a of the substrate 100 and extend in the first direction Y. In some embodiments, the fin pattern 110F may be an insulating pattern including an insulating material.

[0043] A field insulating layer 105 may be formed on the substrate 100. In some embodiments, the field insulating layer 105 may cover at least a portion of a side surface of the fin pattern 110F. The field insulating layer 105 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto.

[0044] The first to fourth gate structures GS1 to GS4 may be formed on the substrate 100 and the field insulating layer 105. The first to fourth gate structures GS1 to GS4 may be spaced apart from each other, and each gate structure may be elongated in the second direction X.

[0045] The first gate structure GS1 may intersect the first active pattern AP1 and the second active pattern AP2. For example, the bridge patterns 111 to 113 of the first active pattern AP1 and the second active pattern AP2 may extend along the first direction Y and penetrate the first gate structure GS1. The first gate structure GS1 may be set as the gate of the first inverter INV1. For example, the first active pattern AP1 intersecting the first gate structure GS1 may be set as the channel region of the first pull-down transistor PD1, and the second active pattern AP2 intersecting the first gate structure GS1 may be set as the channel region of the first pull-up transistor PU1.

[0046] The second gate structure GS2 may be spaced apart from the first gate structure GS1 in the first direction Y. The second gate structure GS2 may extend in parallel with the first gate structure GS1 and may intersect the first active pattern AP1. For example, the bridge patterns 111 to 113 of the first active pattern AP1 may extend along the first direction Y and penetrate the second gate structure GS2. The second gate structure GS2 may be set as the gate of the first transfer transistor PS1. For example, the first active pattern AP1 intersecting the second gate structure GS2 may be set as the channel region of the first transfer transistor PS1.

[0047] The third gate structure GS3 may be spaced apart from the first gate structure GS1 in the second direction X. The third gate structure GS3 may intersect with the fourth active pattern AP4. For example, the bridge patterns 111 to 113 of the fourth active pattern AP4 may extend along the first direction Y and penetrate the third gate structure GS3. The third gate structure GS3 may be set as the gate of the second transfer transistor PS2. For example, the fourth active pattern AP4 intersecting with the third gate structure GS3 may be set as the channel region of the second transfer transistor PS2.

[0048] The fourth gate structure GS4 may be spaced apart from the second gate structure GS2 in the second direction X. The fourth gate structure GS4 may extend in parallel to the third gate structure GS3 and may intersect the third active pattern AP3 and the fourth active pattern AP4. For example, the bridge patterns 111 to 113 of the third active pattern AP3 and the fourth active pattern AP4 may extend along the first direction Y and penetrate the fourth gate structure GS4. The fourth gate structure GS4 may be set as the gate of the second inverter INV2. For example, the fourth active pattern AP4 intersecting the fourth gate structure GS4 may be set as the channel region of the second pull-down transistor PD2, and the third active pattern AP3 intersecting the fourth gate structure GS4 may be set as the channel region of the second pull-up transistor PU2.

[0049] In some embodiments, each of the first to fourth gate structures GS1 to GS4 may be isolated by an isolation pattern GC. For example, the isolation pattern GC may extend along the second direction X between the third active pattern AP3 and the fourth active pattern AP4, and may isolate the first gate structure GS1 from the third gate structure GS3. In addition, for example, the isolation pattern GC may extend along the second direction X between the first active pattern AP1 and the second active pattern AP2, and may isolate the second gate structure GS2 from the fourth gate structure GS4.

[0050] The isolation pattern GC may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxynitride, or a combination thereof, but is not limited thereto.

[0051] Each of the first to fourth gate structures GS1 to GS4 may include a gate dielectric layer 120 , a gate electrode 130 , a gate spacer 140 , and a gate capping layer 150 .

[0052] The gate dielectric layer 120 may be interposed between each of the first to fourth active patterns AP1 to AP4 and the gate electrode 130. The gate dielectric layer 120 may include a dielectric material, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include, for example, at least one selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, but is not limited thereto.

[0053] The gate electrode 130 may be elongated in the second direction X and intersect the first to fourth active patterns AP1 to AP4. Each of the bridge patterns 111 to 113 of the first to fourth active patterns AP1 to AP4 may extend along the first direction Y and penetrate the gate electrode 130. The gate electrode 130 may include a conductive material, such as at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, or a combination thereof, but is not limited thereto. The gate electrode 130 may be formed, for example, by a replacement process, but is not limited thereto.

[0054] Although the gate electrode 130 is shown as a single layer, this is only exemplary, and the gate electrode 130 may be a multilayer formed by stacking a plurality of conductive layers. For example, the gate electrode 130 may include a work function adjustment layer for adjusting the work function and a filling conductive layer for filling the space formed by the work function adjustment layer. For example, the work function adjustment layer may include at least one of TiN, TaN, TiC, TaC, TiAlC, or a combination thereof. The filling conductive layer may include, for example, W or Al.

[0055] The gate spacer 140 may extend along a side surface of the gate electrode 130. Each of the bridge patterns 111 to 113 of the first to fourth active patterns AP1 to AP4 may extend in the first direction Y and penetrate the gate spacer 140. The gate spacer 140 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxynitride, or a combination thereof, but is not limited thereto.

[0056] In some embodiments, the gate dielectric layer 120 may include an interface layer 122 and a high dielectric layer 124 sequentially stacked on the first to fourth active patterns AP1 to AP4 .

[0057] The interface layer 122 may surround the periphery of each of the bridge patterns 111 to 113. For example, the interface layer 122 may conformally extend along the periphery of each of the bridge patterns 111 to 113. In some embodiments, the interface layer 122 may include an oxide layer formed by oxidizing a surface of each of the bridge patterns 111 to 113. For example, when each of the bridge patterns 111 to 113 includes silicon (Si), the interface layer 122 may include a silicon oxide layer.

[0058] The high dielectric layer 124 may surround the periphery of the interface layer 122. In addition, a portion of the high dielectric layer 124 may be interposed between the gate electrode 130 and the gate spacer 140. For example, the high dielectric layer 124 may conformally extend along the periphery of the interface layer 122 and the contour of the inner surface of the gate spacer 140. In addition, the high dielectric layer 124 may also extend along the top surface of the field insulation layer 105.

[0059] In some embodiments, the high dielectric layer 124 may include a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, hafnium oxide (HfO 2 )、ZrO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Strontium Titanium Oxide (SrTiO 3), lanthanum aluminum oxide (LaAlO 3 ), yttrium oxide (Y 2 O 3 ), Hafnium Oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (La 2 O x N y ), aluminum oxynitride (Al 2 O x N y ), titanium oxynitride (TiO x N y ), Strontium Titanium Oxynitride (SrTiO x N y ), lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (Y 2 O x N y ) or at least one of their combinations, but not limited thereto.

[0060] The gate capping layer 150 may extend along the top surface of the gate electrode 130. The gate capping layer 150 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxynitride, or a combination thereof, but is not limited thereto.

[0061] The first to fourth active patterns AP1 to AP4 may include first to fourth source / drain regions 161 to 164. The first to fourth source / drain regions 161 to 164 may be formed in the first to fourth active patterns AP1 to AP4 on the side surfaces of the first to fourth gate structures GS1 to GS4. The bridge patterns 111 to 113 of the first to fourth active patterns AP1 to AP4 may penetrate the gate electrode 130 and the gate spacer 140 to be connected to the first to fourth source / drain regions 161 to 164. The first to fourth source / drain regions 161 to 164 may be electrically isolated from the gate electrode 130 by the gate spacer 140. In the embodiments shown herein, the phrase source / drain region may be understood to mean a source terminal region or a drain terminal region of a transistor.

[0062] In some embodiments, each of the first to fourth source / drain regions 161 to 164 may include an epitaxial layer doped with impurities. For example, the first to fourth source / drain regions 161 to 164 may include an epitaxial pattern grown from the first to fourth active patterns AP1 to AP4 by an epitaxial growth method.

[0063] The source / drain contacts 171 to 178 may be connected to the first to fourth active patterns AP1 to AP4. For example, the source / drain contacts 171 to 178 may be connected to the first to fourth source / drain regions 161 to 164. The shapes, arrangements, etc. of the source / drain contacts 171 to 178 are merely exemplary and are not limited to the shapes, arrangements, etc. shown.

[0064] For example, first to third source / drain contacts 171 to 173 respectively connected to the first source / drain region 161 of the first active pattern AP1 may be formed. The first to third source / drain contacts 171 to 173 may be sequentially arranged along the first direction Y. The second source / drain contact 172 may be between the first gate structure GS1 and the second gate structure GS2. The first gate structure GS1 may be between the first source / drain contact 171 and the second source / drain contact 172. The second gate structure GS2 may be between the second source / drain contact 172 and the third source / drain contact 173.

[0065] For example, a second source / drain contact 172 and a fourth source / drain contact 174 respectively connected to the second source / drain region 162 of the second active pattern AP2 may be formed. The second source / drain contact 172 may extend along the second direction X and connect the first source / drain region 161 of the first active pattern AP1 to the second source / drain region 162 of the second active pattern AP2. The first gate structure GS1 may be interposed between the second source / drain contact 172 and the fourth source / drain contact 174.

[0066] For example, sixth to eighth source / drain contacts 176 to 178 respectively connected to the fourth source / drain region 164 of the fourth active pattern AP4 may be formed. The sixth to eighth source / drain contacts 176 to 178 may be sequentially arranged along the first direction Y. The seventh source / drain contact 177 may be between the third gate structure GS3 and the fourth gate structure GS4. The third gate structure GS3 may be between the sixth source / drain contact 176 and the seventh source / drain contact 177. The fourth gate structure GS4 may be between the seventh source / drain contact 177 and the eighth source / drain contact 178.

[0067] For example, a fifth source / drain contact 175 and a seventh source / drain contact 177 respectively connected to the third source / drain region 163 of the third active pattern AP3 may be formed. The seventh source / drain contact 177 may extend along the second direction X and connect the third source / drain region 163 of the third active pattern AP3 to the fourth source / drain region 164 of the fourth active pattern AP4. The fourth gate structure GS4 may be interposed between the fifth source / drain contact 175 and the seventh source / drain contact 177.

[0068] The first shared contact NC1 may electrically connect the first gate structure GS1 to the seventh source / drain contact 177. For example, the first shared contact NC1 may extend along the first direction Y, and may connect the gate electrode 130 of the first gate structure GS1 to the seventh source / drain contact 177. Through the first shared contact NC1, the input node of the first inverter INV1 (i.e., the first gate structure GS1) may be connected to the output node of the second inverter INV2 (i.e., the seventh source / drain contact 177).

[0069] The second shared contact NC2 may electrically connect the fourth gate structure GS4 to the second source / drain contact 172. For example, the second shared contact NC2 may extend along the first direction Y, and may connect the gate electrode 130 of the fourth gate structure GS4 to the second source / drain contact 172. Through the second shared contact NC2, the input node of the second inverter INV2 (i.e., the fourth gate structure GS4) may be connected to the output node of the first inverter INV1 (i.e., the second source / drain contact 172).

[0070] The first interlayer insulating layer ID1 may fill the space on the side surface of the first to fourth gate structures GS1 to GS4. For example, the first interlayer insulating layer ID1 may cover the first to fourth source / drain regions 161 to 164. The second interlayer insulating layer ID2 may cover the first to fourth gate structures GS1 to GS4 and the first interlayer insulating layer ID1.

[0071] Each of the first and second interlayer insulating layers ID1 and ID2 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbon nitride, silicon carbon nitride oxynitride, or a low-k material having a dielectric constant smaller than silicon oxide, but is not limited thereto.

[0072] The front region FR may be formed on the first surface 100a of the substrate 100. The front region FR may include first-level front wiring patterns 211 to 214 and second-level front wiring patterns 220. For example, the front inter-wiring insulating layer 200 may be formed on the second interlayer insulating layer ID2. The first-level front wiring patterns 211 to 214 and the second-level front wiring patterns 220 may be formed in the front inter-wiring insulating layer 200 and insulated from each other.

[0073] The first-level front wiring patterns 211 to 214 may be arranged at the same height and may be spaced apart from each other. The second-level front wiring patterns 220 may be arranged at the same height and may be spaced apart from each other. In this specification, being arranged "at the same height" means being arranged at the same height in the third direction Z relative to the substrate 100. The second-level front wiring patterns 220 may be arranged at a higher height than the first-level front wiring patterns 211 to 214. For example, the second-level front wiring patterns 220 may be farther from the substrate 100 in the third direction Z than the first-level front wiring patterns 211 to 214.

[0074] In some embodiments, the first level front wiring patterns 211 to 214 may include a first front wiring pattern 211 , a second front wiring pattern 212 , a third front wiring pattern 213 , and a fourth front wiring pattern 214 . In some embodiments, the second level front wiring pattern 220 may include a fifth front wiring pattern 220 .

[0075] The first front wiring pattern 211 may be connected to the third source / drain contact 173. For example, a first contact via 183F may be formed that penetrates the second interlayer insulating layer ID2 to connect the third source / drain contact 173 to the first front wiring pattern 211. The first front wiring pattern 211 may be provided as a bit line BL, and may be connected to the first transfer transistor PS1 through the third source / drain contact 173. In some embodiments, the first front wiring pattern 211 may be elongated in the first direction Y.

[0076] The second front wiring pattern 212 may be connected to the sixth source / drain contact 176. For example, a second contact via 186F may be formed that penetrates the second interlayer insulating layer ID2 to connect the sixth source / drain contact 176 to the second front wiring pattern 212. The second front wiring pattern 212 may be provided as a complementary bit line / BL and may be connected to the second transfer transistor PS2 through the sixth source / drain contact 176. In some embodiments, the second front wiring pattern 212 may be elongated in the first direction Y.

[0077] The third front wiring pattern 213 may be connected to the second gate structure GS2 . For example, a first gate contact 192 may be formed penetrating the second interlayer insulating layer ID2 and the gate capping layer 150 to connect the gate electrode 130 of the second gate structure GS2 to the third front wiring pattern 213 .

[0078] The fourth front wiring pattern 214 may be connected to the third gate structure GS3. For example, a second gate contact 193 may be formed penetrating the second interlayer insulating layer ID2 and the gate capping layer 150 to connect the gate electrode 130 of the third gate structure GS3 to the fourth front wiring pattern 214.

[0079] In some embodiments, the lengths of the third and fourth front wiring patterns 213 and 214 extending along the first direction Y may be smaller than the lengths of the first and second front wiring patterns 211 and 212 extending along the first direction Y.

[0080] The fifth front wiring pattern 220 may be connected to the third front wiring pattern 213 and the fourth front wiring pattern 214. For example, a first front via pattern 233 may be formed, which extends along the third direction Z in the front inter-wiring insulating layer 200 and connects the third front wiring pattern 213 to the fifth front wiring pattern 220. In addition, for example, a second front via pattern 234 may be formed, which extends along the third direction Z in the front inter-wiring insulating layer 200 and connects the fourth front wiring pattern 214 to the fifth front wiring pattern 220. The fifth front wiring pattern 220 may be provided as a word line WL, and may be connected to the gate of the first transfer transistor PS1 through the third front wiring pattern 213, and may be connected to the gate of the second transfer transistor PS2 through the fourth front wiring pattern 214. In some embodiments, the fifth front wiring pattern 220 may be elongated in the second direction X.

[0081] The rear region BR may be formed on the second surface 100b of the substrate 100. The rear region BR may include first-level rear wiring patterns 311 to 313 and second-level rear wiring patterns 321 and 322. For example, a rear inter-wiring insulating layer 300 may be formed on the second surface 100b of the substrate 100. The first-level rear wiring patterns 311 to 313 and the second-level rear wiring patterns 321 and 322 may be formed in the rear inter-wiring insulating layer 300 and insulated from each other.

[0082] The first-level rear wiring patterns 311 to 313 may be arranged at the same height and may be spaced apart from each other. The second-level rear wiring patterns 321 and 322 may be arranged at the same height and may be spaced apart from each other. The second-level rear wiring patterns 321 and 322 may be arranged at a higher height than the first-level rear wiring patterns 311 to 313. For example, the second-level rear wiring patterns 321 and 322 may be farther from the substrate 100 in the third direction Z than the first-level rear wiring patterns 311 to 313.

[0083] In some embodiments, the first level rear wiring patterns 311 to 313 may include a first rear wiring pattern 311, a second rear wiring pattern 312, and a third rear wiring pattern 313. In some embodiments, the second level rear wiring patterns 321 and 322 may include a fourth rear wiring pattern 321 and a fifth rear wiring pattern 322.

[0084] The first rear wiring pattern 311 may include a first extension portion 311a, a second extension portion 311b, and a connection portion 311c. Each of the first extension portion 311a and the second extension portion 311b may extend in the first direction Y. The connection portion 311c may extend in the second direction X to connect the first extension portion 311a to the second extension portion 311b.

[0085] The second rear wiring pattern 312 may be spaced apart from the first extension portion 311a in the second direction X, and may be spaced apart from the connection portion 311c in the first direction Y. The third rear wiring pattern 313 may be spaced apart from the second extension portion 311b in the second direction X, and may be spaced apart from the connection portion 311c in the first direction Y. The connection portion 311c may be interposed between the second rear wiring pattern 312 and the third rear wiring pattern 313.

[0086] In some embodiments, each of the first extension portion 311a and the second extension portion 311b may be elongated in the first direction Y. For example, as shown in the figure, the second rear wiring pattern 312 may be between the first extension portion 311a and the second extension portion 311b in the second direction X, and the third rear wiring pattern 313 may be between the first extension portion 311a and the second extension portion 311b in the second direction X. The first extension portion 311a, the second extension portion 311b, and the connecting portion 311c may be integrally formed to provide the first rear wiring pattern 311 having an approximately "H" shape. Each of the second rear wiring pattern 312 and the third rear wiring pattern 313 may be an island pattern disposed in an empty region of the first rear wiring pattern 311 having an approximately "H" shape.

[0087] The first rear wiring pattern 311 may be connected to the first source / drain region 161 of the first active pattern AP1, wherein the first gate structure GS1 is disposed between the first source / drain region 161 and the second source / drain contact 172. For example, a first rear source / drain contact 181B may be formed, wherein the first gate structure GS1 is disposed between the first rear source / drain contact 181B and the second source / drain contact 172. The first rear source / drain contact 181B may penetrate the substrate 100 and may connect the first source / drain region 161 of the first active pattern AP1 to the first extension portion 311a. The first rear wiring pattern 311 may be disposed to the ground node V SS , used to apply a first power supply voltage to the first pull-down transistor PD1.

[0088] In addition, the first rear wiring pattern 311 may be connected to the fourth source / drain region 164 of the fourth active pattern AP4, wherein the fourth gate structure GS4 is disposed between the fourth source / drain region 164 and the seventh source / drain contact 177. For example, a second rear source / drain contact 188B may be formed, wherein the fourth gate structure GS4 is disposed between the second rear source / drain contact 188B and the seventh source / drain contact 177. The second rear source / drain contact 188B may penetrate the substrate 100 and may connect the fourth source / drain region 164 of the fourth active pattern AP4 to the second extension portion 311b. The first rear wiring pattern 311 may be disposed to the ground node V SS , used to apply a first power supply voltage to the second pull-down transistor PD2.

[0089] The second rear wiring pattern 312 may be connected to the second source / drain region 162 of the second active pattern AP2, wherein the first gate structure GS1 is disposed between the second source / drain region 162 and the second source / drain contact 172. For example, a third rear source / drain contact 184B may be formed, wherein the first gate structure GS1 is disposed between the third rear source / drain contact 184B and the second source / drain contact 172. The third rear source / drain contact 184B may penetrate the substrate 100 and may connect the second source / drain region 162 of the second active pattern AP2 to the second rear wiring pattern 312.

[0090] The third rear wiring pattern 313 may be connected to the third source / drain region 163 of the third active pattern AP3, and the fourth gate structure GS4 is disposed between the third source / drain region 163 and the seventh source / drain contact 177. For example, a fourth rear source / drain contact 185B may be formed, wherein the fourth gate structure GS4 is disposed between the fourth rear source / drain contact 185B and the seventh source / drain contact 177. The fourth rear source / drain contact 185B may penetrate the substrate 100, and may connect the third source / drain region 163 of the third active pattern AP3 to the third rear wiring pattern 313.

[0091] The fourth rear wiring pattern 321 may be connected to the second rear wiring pattern 312. For example, a first rear via pattern 332 may be formed that extends in the third direction Z within the rear inter-wiring insulating layer 300 and connects the second rear wiring pattern 312 to the fourth rear wiring pattern 321. The fourth rear wiring pattern 321 may be set to the power node V DD , for applying a second power voltage different from the first power voltage to the first pull-up transistor PU1 through the second rear wiring pattern 312. In some embodiments, the fourth rear wiring pattern 321 may be elongated in the second direction X.

[0092] The fifth rear wiring pattern 322 may be connected to the third rear wiring pattern 313. For example, a second rear via pattern 333 may be formed that extends in the third direction Z within the rear inter-wiring insulating layer 300 and connects the third rear wiring pattern 313 to the fifth rear wiring pattern 322. The fifth rear wiring pattern 322 may be set to the power node V DD , for applying the second power supply voltage to the second pull-up transistor PU2 through the third rear wiring pattern 313. In some embodiments, the fifth rear wiring pattern 322 may be elongated in the second direction X.

[0093] Figures 6 to 11 is a layout diagram for illustrating an example of a semiconductor device. Figures 1 to 5 Redundant parts of the description.

[0094] Reference Figure 1 and Figure 6 , in the semiconductor device, the first active pattern AP1 and the fourth active pattern AP4 are used as the channel region of the PFET, and the second active pattern AP2 and the third active pattern AP3 are used as the channel region of the NFET.

[0095] The first active pattern AP1 crossing the first gate structure GS1 may be provided as a channel region of the first pull-up transistor PU1 , and the second active pattern AP2 crossing the first gate structure GS1 may be provided as a channel region of the first pull-down transistor PD1 .

[0096] The fourth active pattern AP4 crossing the fourth gate structure GS4 may be provided as a channel region of the second pull-up transistor PU2 , and the third active pattern AP3 crossing the fourth gate structure GS4 may be provided as a channel region of the second pull-down transistor PD2 .

[0097] The first rear wiring pattern 311 may be set to a power supply node V DD , for applying the second power supply voltage to the first pull-up transistor PU1 and the second pull-up transistor PU2.

[0098] The fourth rear wiring pattern 321 may be set to a ground node V SS , for applying the first power supply voltage to the first pull-down transistor PD1 through the second rear wiring pattern 312.

[0099] The fifth rear wiring pattern 322 may be set to a ground node V SS , for applying the first power supply voltage to the second pull-down transistor PD2 through the third rear wiring pattern 313.

[0100] Reference Figure 1 and Figure 7, the semiconductor device includes source / drain contacts 172 , 173 , 176 and 177 .

[0101] The source / drain contacts 172, 173, 176, and 177 may not overlap with the rear source / drain contacts 181B, 184B, 185B, and 188B in the third direction Z. For example, Figure 2 The first source / drain contact 171 , the fourth source / drain contact 174 , the fifth source / drain contact 175 , and the eighth source / drain contact 178 may be omitted as dummy source / drain contacts.

[0102] Reference Figure 1 and Figure 8 The semiconductor device includes a second-level rear wiring pattern 323 , and the second-level rear wiring pattern 323 includes a sixth rear wiring pattern 323 .

[0103] The sixth rear wiring pattern 323 may be connected to the second rear wiring pattern 312 and the third rear wiring pattern 313. For example, the first rear via pattern 332 may connect the second rear wiring pattern 312 to the sixth rear wiring pattern 323, and the second rear via pattern 333 may connect the third rear wiring pattern 313 to the sixth rear wiring pattern 323. The sixth rear wiring pattern 323 may be set to the power node V DD , for applying the second power supply voltage to the first pull-up transistor PU1 and the second pull-up transistor PU2 through the second rear wiring pattern 312 and the third rear wiring pattern 313. In some embodiments, the sixth rear wiring pattern 323 may be elongated in the first direction Y.

[0104] Reference Figure 1 and Fig. 9 , the semiconductor device includes first-level front wiring patterns 211 to 215 , which include a sixth front wiring pattern 215 .

[0105] The sixth front wiring pattern 215 may be connected to the fourth source / drain contact 174 and the fifth source / drain contact 175. For example, a third contact via 184F may be formed to connect the fourth source / drain contact 174 to the sixth front wiring pattern 215. In addition, for example, a fourth contact via 185F may be formed to connect the fifth source / drain contact 175 to the sixth front wiring pattern 215. The sixth front wiring pattern 215 may be set to the power supply node V DD , for applying the second power supply voltage to the first pull-up transistor PU1 and the second pull-up transistor PU2 through the fourth source / drain contact 174 and the fifth source / drain contact 175. In some embodiments, the sixth front wiring pattern 215 may be elongated in the first direction Y.

[0106] Reference Figure 1 and Fig.10In the semiconductor device, the first extending portion 311 a and the second extending portion 311 b extend in opposite directions with respect to the connecting portion 311 c.

[0107] For example, as shown in the figure, the second rear wiring pattern 312 may not overlap with the second extension portion 311b in the second direction X, and the third rear wiring pattern 313 may not overlap with the first extension portion 311a in the second direction X. The first extension portion 311a, the second extension portion 311b, and the connection portion 311c may be integrally formed to provide the first rear wiring pattern 311 having an approximately "right-angle Z" shape. The second rear wiring pattern 312 and the third rear wiring pattern 313 may each be an island pattern disposed in an empty region of the first rear wiring pattern 311 having an approximately "right-angle Z" shape.

[0108] In some embodiments, a portion of the second rear wiring pattern 312 may overlap the second extension portion 311 b in the first direction Y. In some embodiments, a portion of the third rear wiring pattern 313 may overlap the first extension portion 311 a in the first direction Y.

[0109] Reference Figure 1 and Fig.11 The semiconductor device includes: first-level rear wiring patterns 311 to 313, which include a first rear wiring pattern 311; and second-level rear wiring patterns 323, which include a sixth rear wiring pattern 323. The first rear wiring pattern 311 is similar to the above-mentioned Fig.10 The sixth rear wiring pattern 323 is similar to the above referenced Figure 8 The descriptions are similar, so their detailed descriptions are omitted below.

[0110] Fig.12 is a layout diagram showing an example of a semiconductor device. Fig.13 is along Fig.12 An example schematic cross-sectional view taken along line DD. Fig.14 is along Fig.12 An example schematic cross-sectional view taken along line EE. Fig.15 is along Fig.12 In order to simplify the description, the following may be summarized or omitted. Figures 1 to 11 Redundant parts of the description.

[0111] Reference Figure 1 and Figures 12 to 15 The semiconductor device includes first-level front wiring patterns 213 to 215 , a second-level front wiring pattern 220 , first-level rear wiring patterns 311 to 313 , and second-level rear wiring patterns 324 and 325 .

[0112] The first-level front wiring patterns 213 to 215 may include a third front wiring pattern 213, a fourth front wiring pattern 214, and a sixth front wiring pattern 215. For example, Figure 2 Since the first front wiring pattern 211 and the second front wiring pattern 212 are omitted, the third front wiring pattern 213 and the fourth front wiring pattern 214 can be formed to be relatively large in the second direction X. The sixth front wiring pattern 215 is similar to the sixth front wiring pattern 215 in the above reference. Fig. 9 The descriptions are similar, so their detailed description is omitted.

[0113] The first-level rear wiring patterns 311 to 313 may include a first rear wiring pattern 311, a second rear wiring pattern 312, and a third rear wiring pattern 313. The second-level rear wiring patterns 324 and 325 may include a seventh rear wiring pattern 324 and an eighth rear wiring pattern 325. The first rear wiring pattern 311 is similar to the above-mentioned rear wiring pattern 311. Fig.10 The descriptions are similar, so their detailed description is omitted.

[0114] The second rear wiring pattern 312 may be connected to the fourth source / drain region 164 of the fourth active pattern AP4, wherein the third gate structure GS3 is disposed between the fourth source / drain region 164 and the seventh source / drain contact 177. For example, a fifth rear source / drain contact 186B may be formed, wherein the third gate structure GS3 is disposed between the fifth rear source / drain contact 186B and the seventh source / drain contact 177. The fifth rear source / drain contact 186B may penetrate the substrate 100 and connect the fourth source / drain region 164 of the fourth active pattern AP4 to the second rear wiring pattern 312.

[0115] The third rear wiring pattern 313 may be connected to the first source / drain region 161 of the first active pattern AP1, wherein the second gate structure GS2 is disposed between the first source / drain region 161 and the second source / drain contact 172. For example, a sixth rear source / drain contact 183B may be formed, wherein the second gate structure GS2 is disposed between the sixth rear source / drain contact 183B and the second source / drain contact 172. The sixth rear source / drain contact 183B may penetrate the substrate 100 and connect the first source / drain region 161 of the first active pattern AP1 to the third rear wiring pattern 313.

[0116] The seventh rear wiring pattern 324 may be connected to the third rear wiring pattern 313. For example, the second rear via pattern 333 may connect the third rear wiring pattern 313 to the seventh rear wiring pattern 324. The seventh rear wiring pattern 324 may be provided as a bit line BL and may be connected to the first pass transistor PS1 through the third rear wiring pattern 313. In some embodiments, the seventh rear wiring pattern 324 may be elongated in the first direction Y.

[0117] The eighth rear wiring pattern 325 may be connected to the second rear wiring pattern 312. For example, the first rear via pattern 332 may connect the second rear wiring pattern 312 to the eighth rear wiring pattern 325. The eighth rear wiring pattern 325 may be provided as a complementary bit line / BL and may be connected to the second transfer transistor PS2 through the second rear wiring pattern 312. In some embodiments, the eighth rear wiring pattern 325 may be elongated in the first direction Y.

[0118] Fig.16 and Fig.17 is a layout diagram for explaining an example of a semiconductor device. Figures 1 to 15 Redundant parts of the description.

[0119] Reference Figure 1 and Fig.16 , in the semiconductor device, the first active pattern AP1 and the fourth active pattern AP4 are used as the channel region of the PFET, and the second active pattern AP2 and the third active pattern AP3 are used as the channel region of the NFET.

[0120] The first active pattern AP1 crossing the first gate structure GS1 may be provided as a channel region of the first pull-up transistor PU1 , and the second active pattern AP2 crossing the first gate structure GS1 may be provided as a channel region of the first pull-down transistor PD1 .

[0121] The fourth active pattern AP4 crossing the fourth gate structure GS4 may be provided as a channel region of the second pull-up transistor PU2 , and the third active pattern AP3 crossing the fourth gate structure GS4 may be provided as a channel region of the second pull-down transistor PD2 .

[0122] The sixth front wiring pattern 215 may be set to a ground node V SS , for applying the first power supply voltage to the first pull-down transistor PD1 and the second pull-down transistor PD2 through the fourth source / drain contact 174 and the fifth source / drain contact 175 .

[0123] The first rear wiring pattern 311 may be set to a power supply node V DD , for applying the second power supply voltage to the first pull-up transistor PU1 and the second pull-up transistor PU2.

[0124] Reference Figure 1 and Fig.17 , the semiconductor device includes source / drain contacts 172 , 174 , 175 and 177 .

[0125] The source / drain contacts 172, 174, 175, and 177 may not overlap with the rear source / drain contacts 181B, 183B, 186B, and 188B in the third direction Z. For example, Fig.12 The first source / drain contact 171 , the third source / drain contact 173 , the sixth source / drain contact 176 , and the eighth source / drain contact 178 may be omitted as dummy source / drain contacts.

[0126] Fig.18 is a circuit diagram showing an example of a semiconductor device. Figure 1 Redundant parts of the description.

[0127] Reference Fig.18 The semiconductor device further includes a circuit connected in series between the read bit line RBL and the ground node V SS between the first readout transistor PR1 and the second readout transistor PR2.

[0128] The first readout transistor PR1 may be connected to a readout bit line RBL. A gate of the first readout transistor PR1 may be connected to a readout word line RWL. A gate of the second readout transistor PR2 may be connected to an output node of the second inverter INV2.

[0129] Fig.19 and Fig. 20 is a layout diagram for explaining an example of a semiconductor device. Figures 1 to 18 Redundant parts of the description.

[0130] Reference Figures 18 to 20 The semiconductor device further includes a fifth active pattern AP5, a fifth gate structure GS5, and ninth to eleventh source / drain contacts 571 to 573.

[0131] The fifth active pattern AP5 may extend parallel to the first active pattern AP1 to the fourth active pattern AP4. The first gate structure GS1 may intersect the first active pattern AP1, the second active pattern AP2, and the fifth active pattern AP5. The first gate structure GS1 may be set as a gate of the second readout transistor PR2. For example, the fifth active pattern AP5 intersecting the first gate structure GS1 may be set as a channel region of the second readout transistor PR2.

[0132] The fifth gate structure GS5 may be spaced apart from the first gate structure GS1 in the first direction Y. In addition, the fifth gate structure GS5 may be spaced apart from the second gate structure GS2 in the second direction X. The fifth gate structure GS5 may extend parallel to the first gate structure GS1 and intersect with the fifth active pattern AP5. The fifth gate structure GS5 may be set as the gate of the first readout transistor PR1. For example, the fifth active pattern AP5 intersecting with the fifth gate structure GS5 may be set as the channel region of the first readout transistor PR1.

[0133] The ninth source / drain contact 571 to the eleventh source / drain contact 573 may be connected to the fifth active pattern AP5. The ninth source / drain contact 571 to the eleventh source / drain contact 573 may be sequentially arranged along the first direction Y. The tenth source / drain contact 572 may be between the first gate structure GS1 and the fifth gate structure GS5. The first gate structure GS1 may be between the ninth source / drain contact 571 and the tenth source / drain contact 572. The fifth gate structure GS5 may be between the tenth source / drain contact 572 and the eleventh source / drain contact 573.

[0134] Reference Fig.18 and Fig.19 In the semiconductor device, the first-level front wiring patterns 211 to 214, 218, and 219 of the front region FR further include a seventh front wiring pattern 218 and an eighth front wiring pattern 219, and the first-level rear wiring patterns 311 to 313, 317, and 318 of the rear region BR further include a ninth rear wiring pattern 317 and a tenth rear wiring pattern 318. In order to simplify the description, reference will be summarized or omitted. Figure 2 Redundant parts of the description.

[0135] The seventh front wiring pattern 218 may be connected to the eleventh source / drain contact 573. For example, a fifth contact via 583F may be formed to connect the eleventh source / drain contact 573 to the seventh front wiring pattern 218. The seventh front wiring pattern 218 may be provided as a readout bit line RBL and may be connected to the first readout transistor PR1 through the eleventh source / drain contact 573. In some embodiments, the seventh front wiring pattern 218 may be elongated in the first direction Y.

[0136] The eighth front wiring pattern 219 may be connected to the fifth gate structure GS5. For example, a third gate contact 590 may be formed to connect the gate electrode 130 of the third gate structure GS3 to the eighth front wiring pattern 219. The eighth front wiring pattern 219 may be provided as a read word line RWL to be connected to the gate of the first read transistor PR1.

[0137] The ninth rear wiring pattern 317 may be connected to the source / drain region of the fifth active pattern AP5, wherein the first gate structure GS1 is disposed between the source / drain region and the tenth source / drain contact 572. For example, a seventh rear source / drain contact 581B may be formed, wherein the first gate structure GS1 is disposed between the seventh rear source / drain contact 581B and the tenth source / drain contact 572. The seventh rear source / drain contact 581B may connect the fifth active pattern AP5 to the ninth rear wiring pattern 317. The ninth rear wiring pattern 317 may be disposed to the ground node V SS , for applying the first power supply voltage to the second readout transistor PR2. In some embodiments, the ninth rear wiring pattern 317 may be elongated in the first direction Y.

[0138] The tenth rear wiring pattern 318 may extend along the second direction X to connect the ninth rear wiring pattern 317 to the first rear wiring pattern 311. In some embodiments, unlike the illustrated example, the tenth rear wiring pattern 318 may be omitted. That is, the ninth rear wiring pattern 317 may be spaced apart from the first rear wiring pattern 311 in the second direction X.

[0139] Reference Fig.18 and Fig. 20 In the semiconductor device, the first-level front wiring patterns 213 to 215 and 219 of the front region FR further include an eighth front wiring pattern 219, the first-level rear wiring patterns 311 to 313 and 317 to 319 of the rear region BR further include a ninth rear wiring pattern 317 to an eleventh rear wiring pattern 319, and the second-level rear wiring patterns 324, 325 and 329 of the rear region BR further include a twelfth rear wiring pattern 329. In order to simplify the description, reference will be summarized or omitted. Fig.12 Redundant parts of the description.

[0140] The eighth front wiring pattern 219, the ninth rear wiring pattern 317 and the tenth rear wiring pattern 318 are similar to those mentioned above. Fig.19 The descriptions are similar, so their detailed description is omitted.

[0141] The eleventh rear wiring pattern 319 may be connected to the source / drain region of the fifth active pattern AP5, wherein the fifth gate structure GS5 is disposed between the source / drain region and the tenth source / drain contact 572. For example, an eighth rear source / drain contact 583B may be formed, wherein the fifth gate structure GS5 is disposed between the eighth rear source / drain contact 583B and the tenth source / drain contact 572. The eighth rear source / drain contact 583B may connect the fifth active pattern AP5 to the eleventh rear wiring pattern 319.

[0142] The twelfth rear wiring pattern 329 may be connected to the eleventh rear wiring pattern 319. For example, the third rear via pattern 339 may be formed to extend in the third direction Z and connect the eleventh rear wiring pattern 319 to the twelfth rear wiring pattern 329. The twelfth rear wiring pattern 329 may be provided as a readout bit line RBL and may be connected to the first readout transistor PR1 through the eleventh rear wiring pattern 319. In some embodiments, the twelfth rear wiring pattern 329 may be elongated in the first direction Y.

[0143] Fig.21 is a circuit diagram showing an example of a semiconductor device. Figure 1 Redundant parts of the description.

[0144] Reference Fig.21 , the semiconductor device includes first to fourth unit elements D1 to D4 that are adjacent to each other.

[0145] Each of the first to fourth unit elements D1 to D4 may include a plurality of cells connected in parallel at a power supply node V DD and ground node V SS A pair of inverters INV1 and INV2 therebetween, and first and second pass transistors PS1 and PS2 connected to output nodes of the inverters INV1 and INV2, respectively.

[0146] In some embodiments, the first to fourth unit elements D1 to D4 may share a complementary bit line / BL. For example, two bit lines BL extending parallel to each other may be formed on both sides of a complementary bit line / BL. The first unit element D1 and the third unit element D3 may be defined between one of the two bit lines BL and the complementary bit line / BL, and the second unit element D2 and the fourth unit element D4 may be defined between the other of the two bit lines BL and the complementary bit line / BL.

[0147] In some embodiments, the first cell element D1 and the second cell element D2 may share one word line WL, and the third cell element D3 and the fourth cell element D4 may share another word line WL.

[0148] Fig. 22 and Fig.23 is a layout diagram for illustrating an example of a semiconductor device. Figures 1 to 21 Redundant parts of the description.

[0149] Reference Figure 21 to Figure 23 , in the semiconductor device, each of the first to fourth unit elements D1 to D4 includes an element region DR, a front region FR, and a rear region BR. Fig. 22Each of the first to fourth unit elements D1 to D4 is similar to the above-mentioned Figure 2 The same as described above, so the detailed description is omitted. Fig.23 Each of the first to fourth unit elements D1 to D4 is similar to the above-mentioned Fig.12 The descriptions are the same, so their detailed descriptions are omitted.

[0150] The first unit element D1 and the second unit element D2 may be arranged in a plane-symmetrical relationship with respect to a plane intersecting the second direction X (i.e., the YZ plane). The third unit element D3 and the fourth unit element D4 may be arranged in a plane-symmetrical relationship with respect to a plane intersecting the second direction X (i.e., the YZ plane). The first unit element D1 and the third unit element D3 may be arranged in a plane-symmetrical relationship with respect to a plane intersecting the first direction Y (i.e., the XZ plane). The second unit element D2 and the fourth unit element D4 may be arranged in a plane-symmetrical relationship with respect to a plane intersecting the first direction Y (i.e., the XZ plane).

[0151] The first extension portion 311a and the second extension portion 311b of the first rear wiring pattern 311 may be alternately and repeatedly arranged along the second direction X. In addition, the connection portion 311c of the first rear wiring pattern 311 may be repeatedly arranged between the first extension portion 311a and the second extension portion 311b along the first direction Y. The first rear wiring pattern 311 may provide a wiring pattern having a substantially mesh shape. For example, Fig. 22 As shown, the first rear wiring pattern 311 may provide a wiring pattern in a lattice mesh shape. Fig.23 As shown, the first rear wiring pattern 311 may provide a wiring pattern in a zigzag mesh shape.

[0152] The second rear wiring patterns 312 and the third rear wiring patterns 313 may be alternately and repeatedly arranged in the first direction Y. The connection portion 311c of the first rear wiring pattern 311 may be disposed between the repeatedly arranged second rear wiring patterns 312 and the third rear wiring patterns 313. The second rear wiring patterns 312 and the third rear wiring patterns 313 may be disposed in openings of the first rear wiring pattern 311 having a substantially mesh shape.

[0153] As semiconductor devices become more highly integrated, individual circuit patterns become more miniaturized to implement more semiconductor devices within the same area. To this end, a back side power delivery network (BSPDN) that places a power delivery network on the back side of a substrate has been studied.

[0154] According to some embodiments of the semiconductor device, the design freedom and integration density of the semiconductor device can be improved by effectively using the back power delivery network. Specifically, as described above, the first rear wiring pattern 311 of the rear area BR can be set to a substantially mesh shape across multiple elements. Compared with the wiring pattern formed separately for each element, the first rear wiring pattern 311 can reduce the resistance. In addition, the second rear wiring pattern 312 and the third rear wiring pattern 313 of the rear area BR can be arranged in the opening of the first rear wiring pattern 311 having a substantially mesh shape. The second rear wiring pattern 312 and the third rear wiring pattern 313 can provide a connection path between the element and other rear wiring patterns (e.g., the second-level rear wiring pattern) arranged at different heights, thereby allowing the rear area BR to be effectively utilized. Therefore, a semiconductor device with improved design freedom and integration density can be provided.

[0155] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of the claimed scope or any invention, but as descriptions of features of specific embodiments that can be dedicated to specific inventions. In a single embodiment, certain features described in this specification in the context of separate embodiments can also be implemented in combination. On the contrary, different features described in the context of a single embodiment can also be implemented in multiple embodiments, or in any appropriate sub-combination. In addition, although features can be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination can be deleted from the combination in some cases, and the claimed combination can be directed to a sub-combination or a variant of the sub-combination.

[0156] Although the present scope of the technology has been specifically shown and described with reference to the example implementations of the technology described herein, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the technology as defined by the appended claims. It is therefore desired that the present embodiments be considered in all respects as illustrative and not restrictive, with reference to the appended claims rather than the foregoing description indicating the scope of the technology.

Claims

1. A semiconductor device, comprising: A substrate comprising a first surface and a second surface opposite to the first surface; a first active pattern on the first surface of the substrate; a first gate structure intersecting the first active pattern; as well as A first rear wiring pattern and a second rear wiring pattern are disposed on the second surface of the substrate and at the same height relative to the substrate, wherein the first rear wiring pattern comprises: a first extending portion and a second extending portion, each of the first extending portion and the second extending portion extending along a first direction; a connecting portion extending along a second direction crossing the first direction, and the connecting portion is configured to connect the first extending portion with the second extending portion, and wherein the second rear wiring pattern is spaced apart from the first extending portion in the second direction, and the second rear wiring pattern is spaced apart from the connecting portion in the first direction.

2. The semiconductor device of claim 1 , comprising a first rear source / drain contact extending through the substrate, wherein: The first rear source / drain contact is configured to connect a first source / drain region of the first active pattern with the first extension portion.

3. The semiconductor device according to claim 2, comprising: a second active pattern, on the first surface of the substrate, the second active pattern being parallel to the first active pattern and crossing the first gate structure; as well as A second rear source / drain contact extends through the substrate and is configured to connect a second source / drain region of the second active pattern with the second rear wiring pattern.

4. The semiconductor device according to claim 2, comprising: a second active pattern, parallel to the first active pattern, on the first surface of the substrate; a second gate structure intersecting the second active pattern; as well as A second rear source / drain contact extends through the substrate and is configured to connect a second source / drain region of the second active pattern with the second extension portion.

5. The semiconductor device according to claim 1, comprising a first front wiring pattern and a second front wiring pattern, the first front wiring pattern and the second front wiring pattern being arranged on the first surface of the substrate and at the same height relative to the substrate, in, The first front wiring pattern extends along the first direction, and The second front wiring pattern is spaced apart from the first front wiring pattern in the second direction.

6. The semiconductor device according to claim 5, comprising: a second gate structure, parallel to the first gate structure and intersecting the first active pattern; a first source / drain contact connected to the first active pattern and located between the first gate structure and the second gate structure; as well as a second source / drain contact connected to the first active pattern, the second gate structure being disposed between the second source / drain contact and the first source / drain contact, wherein the second gate structure is connected to the second front wiring pattern, and Wherein, the second source / drain contact is connected to the first front wiring pattern.

7. The semiconductor device according to claim 1, wherein The second rear wiring pattern is interposed between the first extending portion and the second extending portion in the second direction.

8. The semiconductor device according to claim 1, wherein The second extending portion does not overlap the second rear wiring pattern in the second direction.

9. The semiconductor device according to claim 1, comprising a third rear wiring pattern provided on the second surface of the substrate and at the same height as the first rear wiring pattern and the second rear wiring pattern relative to the substrate, in, The third rear wiring pattern is spaced apart from the second extending portion in the second direction, and the third rear wiring pattern is spaced apart from the connecting portion in the first direction, and Wherein, the connection portion is interposed between the second rear wiring pattern and the third rear wiring pattern.

10. The semiconductor device according to claim 1, comprising: a third rear wiring pattern on the second surface of the substrate and higher than the first rear wiring pattern and the second rear wiring pattern relative to the substrate; as well as The rear via pattern is configured to connect the second rear wiring pattern with the third rear wiring pattern.

11. A semiconductor device comprising: A substrate comprising a first surface and a second surface opposite to the first surface; a first active pattern and a second active pattern, on the first surface of the substrate, the second active pattern being parallel to the first active pattern; a first gate structure intersecting the first active pattern and the second active pattern; a first rear wiring pattern, a second rear wiring pattern, and a third rear wiring pattern, disposed on the second surface of the substrate, at the same height relative to the substrate and spaced apart from each other; a first rear source / drain contact configured to connect a first source / drain region of the first active pattern to the first rear wiring pattern; a second rear source / drain contact configured to connect a second source / drain region of the second active pattern to the second rear wiring pattern; a fourth rear wiring pattern on the second surface of the substrate and higher than the first rear wiring pattern, the second rear wiring pattern and the third rear wiring pattern relative to the substrate; as well as a first rear via pattern configured to connect the second rear wiring pattern with the fourth rear wiring pattern, wherein the first rear wiring pattern comprises: a first extending portion and a second extending portion, each of the first extending portion and the second extending portion extending along a first direction; a connecting portion extending along a second direction crossing the first direction, and the connecting portion is configured to connect the first extending portion with the second extending portion, and The connection portion is located between the second rear wiring pattern and the third rear wiring pattern in the first direction.

12. The semiconductor device according to claim 11, wherein Each of the second rear wiring pattern and the third rear wiring pattern is interposed between the first extending portion and the second extending portion.

13. The semiconductor device according to claim 11, wherein the second rear wiring pattern does not overlap the second extending portion in the second direction, and Wherein, the third rear wiring pattern does not overlap with the first extending portion in the second direction.

14. The semiconductor device according to claim 11, wherein applying a first power supply voltage to the first rear wiring pattern, and Wherein, a second power supply voltage different from the first power supply voltage is applied to the fourth rear wiring pattern.

15. The semiconductor device according to claim 11, wherein The second rear wiring patterns and the third rear wiring patterns are alternately and repeatedly arranged along the first direction.

16. A semiconductor device comprising: A substrate comprising a first surface and a second surface opposite to the first surface; a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, parallel to each other, on the first surface of the substrate; a first gate structure intersecting the first active pattern and the second active pattern; a second gate structure, parallel to the first gate structure and intersecting the first active pattern; a third gate structure, spaced apart from the first gate structure and intersecting the fourth active pattern; a fourth gate structure, parallel to the third gate structure and intersecting the third active pattern and the fourth active pattern; a first source / drain contact configured to connect the first active pattern with the second active pattern, the first source / drain contact being located between the first gate structure and the second gate structure; a second source / drain contact configured to connect the third active pattern with the fourth active pattern, the second source / drain contact being located between the third gate structure and the fourth gate structure; a first shared contact configured to connect the first gate structure to the second source / drain contact; a second shared contact configured to connect the fourth gate structure to the first source / drain contact; a first rear source / drain contact extending through the substrate to be connected to the first active pattern, the first gate structure being disposed between the first rear source / drain contact and the first source / drain contact; a second rear source / drain contact extending through the substrate to be connected to the fourth active pattern, the fourth gate structure being disposed between the second rear source / drain contact and the second source / drain contact; as well as a first rear wiring pattern, a second rear wiring pattern, and a third rear wiring pattern, which are disposed on the second surface of the substrate, are at the same height relative to the substrate and are spaced apart from each other, The first rear wiring pattern includes: a first extending portion and a second extending portion, each of the first extending portion and the second extending portion extending along a first direction; a connecting portion extending along a second direction crossing the first direction, and the connecting portion is configured to connect the first extending portion with the second extending portion, wherein the connection portion is interposed between the second rear wiring pattern and the third rear wiring pattern in the first direction, and Wherein, the first rear source / drain contact and the second rear source / drain contact are connected to the first rear wiring pattern.

17. The semiconductor device according to claim 16, comprising: a third rear source / drain contact extending through the substrate to be connected to the second active pattern, the first gate structure being disposed between the third rear source / drain contact and the first source / drain contact; as well as a fourth rear source / drain contact extending through the substrate to be connected to the third active pattern, the fourth gate structure being disposed between the fourth rear source / drain contact and the second source / drain contact, wherein the third rear source / drain contact is connected to the second rear wiring pattern, and Wherein, the fourth rear source / drain contact is connected to the third rear wiring pattern.

18. The semiconductor device according to claim 16, wherein: A portion of the second rear wiring pattern overlaps the second extending portion in the first direction, and wherein a portion of the third rear wiring pattern overlaps the first extending portion in the first direction.

19. The semiconductor device according to claim 18, comprising: a third rear source / drain contact extending through the substrate to be connected to the first active pattern, the second gate structure being disposed between the third rear source / drain contact and the first source / drain contact; as well as a fourth rear source / drain contact extending through the substrate to be connected to the fourth active pattern, the third gate structure being disposed between the fourth rear source / drain contact and the second source / drain contact, wherein the third rear source / drain contact is connected to the third rear wiring pattern, and Wherein, the fourth rear source / drain contact is connected to the second rear wiring pattern.

20. The semiconductor device according to claim 16, wherein Each of the first active pattern, the second active pattern, the third active pattern, and the fourth active pattern extends along the first direction, and Wherein, each of the first gate structure, the second gate structure, the third gate structure and the fourth gate structure extends along the second direction.

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