Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. According to an embodiment of the present disclosure, a semiconductor device includes a memory cell including: a stack structure including a plurality of alternating dielectric layers and conductive layers in a first direction; a plurality of vertical transistors arranged in the stacked structure along the first direction, wherein each vertical transistor comprises a semiconductor column extending along the first direction, and a source electrode and a drain electrode located at two ends of the semiconductor column; and a plurality of contact structures extending in the first direction and connected to respective conductive layers of the stacked structure, where the conductive layers include a first conductive layer, a second conductive layer, and a plurality of third conductive layers, gates of the plurality of vertical transistors are connected to the first conductive layer, and gates of the plurality of vertical transistors are connected to the second conductive layer. The drains of the plurality of vertical transistors are connected to a second conductive layer, and the source of each of the vertical transistors is connected to a different third conductive layer via the contact structure.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor technology, and more particularly to a semiconductor device for a three-dimensional (3D) dynamic random access memory (DRAM) and a method for forming the same. Background Art

[0002] Currently, the most common dynamic random access memory (DRAM) memory array is an array composed of a memory cell including a transistor and a capacitor (i.e., a 1T1C memory cell). In such a 1T1C memory cell, Figure 1 As shown in FIG. 1 , the gate of transistor 10 is connected to word line 11, the drain is connected to bit line 12, and the source is connected to capacitor 13. When word line 11 is turned on, transistor 10 is turned on so that information stored in capacitor 13 can be read through bit line 12.

[0003] As the size of dynamic random access memory continues to shrink and the size of transistors continues to shrink, how to achieve dynamic random access memory with larger storage capacity and lower cost has become an urgent problem to be solved. Summary of the invention

[0004] According to an embodiment of the present disclosure, a semiconductor device is provided, which includes a memory cell, and the memory cell includes: a stacking structure including a plurality of alternating dielectric layers and conductive layers along a first direction; a plurality of vertical transistors arranged in the stacking structure along the first direction, each of the vertical transistors including a semiconductor column extending along the first direction and a source and a drain located at both ends of the semiconductor column; and a plurality of contact structures extending along the first direction and connected to corresponding conductive layers of the stacking structure, wherein the conductive layer includes a first conductive layer, a second conductive layer and a plurality of third conductive layers, the gates of the plurality of vertical transistors are connected to the first conductive layer, the drains of the plurality of vertical transistors are connected to the second conductive layer, and the source of each of the vertical transistors is connected to a different third conductive layer via the contact structure.

[0005] In some embodiments, the conductive layer further includes a plurality of fourth conductive layers, the third conductive layers and the fourth conductive layers are alternately stacked in the first direction, and each of the third conductive layers forms a capacitor with an adjacent fourth conductive layer.

[0006] In some embodiments, the plurality of fourth conductive layers are connected to a common potential via the contact structure.

[0007] In some embodiments, the stacked structure includes a core region and a step region, and the plurality of vertical transistors are located in the core region.

[0008] In some embodiments, the memory cell further includes a first isolation structure extending through the first conductive layer and separating the plurality of vertical transistors from each other.

[0009] In some embodiments, the semiconductor device further includes a second isolation structure extending through the stack structure and used to separate the memory cells.

[0010] In some embodiments, the first isolation structure and the second isolation structure include any one of oxide, nitride, and oxynitride.

[0011] In some embodiments, the dielectric layer includes any one of silicon oxide, silicon nitride, and silicon oxynitride.

[0012] In some embodiments, the conductive layer includes polysilicon or metal.

[0013] In some embodiments, the metal includes any one of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al).

[0014] In some embodiments, the contact structure includes any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), and tantalum (Ta).

[0015] According to an embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a stacking structure including a plurality of alternating dielectric layers and conductive layers along a first direction; forming a plurality of vertical transistors arranged along the first direction in the stacking structure, each of the vertical transistors including a semiconductor column extending along the first direction and a source and a drain located at both ends of the semiconductor column; and forming a plurality of contact structures extending along the first direction and connected to corresponding conductive layers of the stacking structure, wherein the conductive layer includes a first conductive layer, a second conductive layer and a plurality of third conductive layers, the gates of the plurality of vertical transistors are connected to the first conductive layer, the drains of the plurality of vertical transistors are connected to the second conductive layer, and the source of each of the vertical transistors is connected to a different third conductive layer via the contact structure.

[0016] In some embodiments, the stacked structure includes a core region and a step region, and wherein, before forming the plurality of vertical transistors, the method further includes: forming a step structure in the step region.

[0017] In some embodiments, forming the multiple vertical transistors includes: forming multiple openings in the core area that pass through the first conductive layer of the stacked structure and extend into the second conductive layer of the stacked structure; forming a first doped region serving as a drain of the vertical transistor at the bottom of each of the openings; forming a gate oxide layer on the first conductive layer exposed by each of the openings; filling the openings with single crystal silicon; and forming a second doped region serving as a source of the vertical transistor at the top of each of the openings.

[0018] In some embodiments, the conductive layer also includes multiple fourth conductive layers, the third conductive layers and the fourth conductive layers are alternately stacked in the first direction, and wherein the method also includes: connecting the multiple fourth conductive layers to a common potential via the contact structure to form multiple capacitors arranged along the first direction in the third conductive layer and the fourth conductive layer.

[0019] In some embodiments, the method further includes forming a first isolation structure extending through the first conductive layer and separating the plurality of vertical transistors from each other.

[0020] In some embodiments, forming the multiple contact structures includes: forming a plurality of contact holes in the stacked structure along the first direction, the bottom of each contact hole exposing the corresponding conductive layer in the stacked structure; and filling the contact holes with a conductive material to form the multiple contact structures connected to the corresponding conductive layers of the stacked structure.

[0021] According to an embodiment of the present disclosure, a storage system is provided, comprising: a storage device, the storage device comprising a plurality of semiconductor devices arranged in an array and configured to store data, the semiconductor device comprising a storage unit, the storage unit comprising: a stack structure comprising a plurality of alternating dielectric layers and conductive layers along a first direction; a plurality of vertical transistors arranged in the stack structure along the first direction, each of the vertical transistors comprising a semiconductor column extending along the first direction and a source and a drain located at both ends of the semiconductor column; and a plurality of contact structures extending along the first direction and connected to corresponding conductive layers of the stack structure, wherein the conductive layer comprises a first conductive layer, a second conductive layer and a plurality of third conductive layers, the gates of the plurality of vertical transistors are connected to the first conductive layer, the drains of the plurality of vertical transistors are connected to the second conductive layer, and the source of each of the vertical transistors is connected to a different third conductive layer via the contact structure; and a memory controller, the memory controller being coupled to the storage device and configured to control the storage device.

[0022] In some embodiments, the memory system further includes a host coupled to the memory controller and configured to send or receive the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For those skilled in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0024] Figure 1 A connection diagram of a 1T1C storage unit in a DRAM is shown;

[0025] FIG. 2( a ) shows a schematic diagram of a DRAM memory array formed by a plurality of 1T1C memory cells according to an embodiment of the present disclosure;

[0026] FIG. 2( b ) shows a schematic diagram of the structure of any 1T1C storage unit in FIG. 2( a );

[0027] FIG3( a ) shows a schematic diagram of a DRAM memory array formed by a plurality of nTnC memory cells according to an embodiment of the present disclosure;

[0028] FIG3( b ) shows a top view of a semiconductor device including memory cells MC1 - MC9 according to an embodiment of the present disclosure;

[0029] FIG3(c) shows a cross-sectional view of the memory cell MC5 along the line AA' of FIG3(b);

[0030] Figure 4(a)-4(d) A cross-sectional view showing various steps of a manufacturing method for forming a semiconductor device including a 2T2C memory cell according to an embodiment of the present disclosure;

[0031] Figure 5 A flowchart showing a manufacturing method for forming a semiconductor device including a 2T2C memory cell according to an embodiment of the present disclosure; and

[0032] Figure 6 A block diagram of an exemplary system having a 3D dynamic random access memory (DRAM) according to an embodiment of the present disclosure is shown.

[0033] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0034] The subject matter described herein will now be discussed with reference to example embodiments. It should be understood that the discussion of these embodiments is only to enable those skilled in the art to better understand and implement the subject matter described herein, and is not a limitation of the scope of protection, applicability or examples set forth in the claims. The function and arrangement of the elements discussed can be changed without departing from the scope of protection of the present disclosure. Various examples can omit, replace or add various processes or components as needed. For example, the described method can be performed in an order different from the described order, and various steps can be added, omitted or combined. In addition, the features described relative to some examples can also be combined in other examples.

[0035] It should be noted that the references to "one embodiment", "embodiment", "some embodiments" and the like in the specification indicate that the embodiments described may include specific features, structures or characteristics, but not every embodiment may include the specific features, structures or characteristics. In addition, such expressions do not necessarily refer to the same embodiment. In addition, when specific features, structures or characteristics are described in conjunction with an embodiment, it should be within the knowledge of technicians in the relevant field to implement such features, structures or characteristics in conjunction with other embodiments that are explicitly or not explicitly described.

[0036] In general, terms may be understood, at least in part, by the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, at least in part depending on the context. Similarly, terms such as "one," "an," or "the" may also be understood to convey singular usage or to convey plural usage, which may depend, at least in part, on the context. In addition, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but may allow for the presence of other factors that may not be explicitly stated, which again may depend, at least in part, on the context.

[0037] It should be easily understood that the terms “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only being directly on something, but also includes being on something with intervening features or layers therebetween, and such that “on” or “over” includes not only the meaning of being on or over something, but also includes the meaning of being on or over something with no intervening features or layers therebetween (i.e., directly on something).

[0038] In addition, spatially relative terms, such as "below," "below," "beneath," "above," "above," etc., may be used herein for ease of description to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0039] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned, or it can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, for example, silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0040] Embodiments of a semiconductor device for a three-dimensional (3D) dynamic random access memory (DRAM) and a method of forming the same according to the present disclosure will now be described with reference to the accompanying drawings.

[0041] FIG. 2( a ) shows a schematic diagram of a DRAM memory array 200 formed by a plurality of (eg, 12) 1T1C memory cells according to an embodiment of the present disclosure. As shown in FIG. 2( a), in a DRAM memory array 200 including, for example, 12 transistors and 12 capacitors, the gates of transistors T11-T14 are connected to word line WL1, the gates of transistors T21-T24 are connected to word line WL2, and the gates of transistors T31-T34 are connected to word line WL3; the drains of transistors T11-T31, T12-T32, T13-T33, T14-T34 are connected to bit lines BL1, BL2, BL3, BL4, respectively; the sources of transistors T11-T14 are connected to first electrodes of capacitors C11-C14, respectively, the sources of transistors T21-T24 are connected to first electrodes of capacitors C21-C24, respectively, and the sources of transistors T31-T34 are connected to first electrodes of capacitors C31-C34, respectively; and the second electrodes of capacitors C11~C14, C21~C24 and C31~C34 are grounded.

[0042] FIG2(b) shows a schematic diagram of the structure of any 1T1C memory cell in FIG2(a). As shown in FIG2(b), the well region 24 may be an n-type well region or a p-type well region (e.g., a p-well 24) formed by injecting a suitable dopant into the semiconductor substrate 20. For example, the dopant used to form the n-type well region may include phosphorus (P), arsenic (As) or other suitable n-type dopants, and the dopant used to form the p-type well region may include boron (B), gallium (Ga) or other suitable p-type dopants. The source region 22 / drain region 23 may be disposed in the well region 24 and disposed on two opposite sides of the gate electrode 21 and the gate dielectric layer 25, respectively. Each of the source region 22 / drain region 23 may be formed by injecting a suitable dopant into the well region 24. When the well region 24 is a p-type well region, each of the source region 22 / drain region 23 may include an n-type doping region, but is not limited thereto. Contact structures 26 , 27 are coupled to the drain and gate of transistor T, respectively, contact structure 28 is coupled to the source of transistor T and the first electrode of capacitor C, respectively, and contact structure 29 is coupled to the second electrode of capacitor C.

[0043] 2( b ), the semiconductor channel of the MOS transistor T is parallel to the substrate 20 and thus the transistor T is a planar transistor. When the 1T1C memory cell of a DRAM includes such a planar transistor, the increase in the DRAM storage capacity is limited by the size of the DRAM.

[0044] FIG3(a) shows a schematic diagram of a DRAM memory array 300 formed by a plurality of (e.g., 9) nTnC memory cells according to an embodiment of the present disclosure. Different from the DRAM memory array 200 shown in FIG2(a), each memory cell MC in the DRAM memory array 300 is not formed by a semiconductor device including a 1T1C structure, but is formed by a semiconductor device including an nTnC structure.

[0045] As shown in FIG. 3( a), in a DRAM memory array 300 including, for example, 9 memory cells, each memory cell includes nTnC. For simplicity, FIG. 3( a) only schematically shows 3 transistors and 3 capacitors in each memory cell. Taking the upper left memory cell MC31 as an example, the gates of its three transistors T1, T2 and T3 are connected to the word line WL3, the drains of the three transistors T1, T2 and T3 are connected to the bit line BL1, and the sources of the three transistors T1, T2 and T3 are respectively connected to the first electrodes of the three capacitors C1, C2 and C3. In addition, the second electrodes of the three capacitors C1, C2 and C3 are grounded.

[0046] It should be noted that the number of transistors and capacitors in each memory cell MC in FIG. 3( a ) is exemplary, and each memory cell MC according to an embodiment of the present disclosure may include other numbers of transistors and capacitors, such as 4, 5, 6, ... and so on.

[0047] FIG3( b) shows a top view of a semiconductor device including memory cells MC1-MC9 according to an embodiment of the present disclosure. For simplicity, memory cells MC1-MC9 are all 2T2C memory cells. Taking memory cell MC5 as an example, it includes an isolation structure 303 for separating two transistors 301 and 302, and also includes contact structures 304, 305, 306, 307, 308, 309, 310. In addition, between each memory cell MC of the semiconductor device, an isolation structure 311 for separating them from each other is also included. It should be noted that FIG3( b) only schematically shows the complete isolation structure 311 surrounding the memory cell MC5.

[0048] FIG3(c) shows a cross-sectional view of the memory cell MC5 along the line AA' of FIG3(b). As shown in FIG3(c), the memory cell MC5 includes a stacked structure 321 disposed on a substrate 320, and the stacked structure 321 includes conductive layers 322 and dielectric layers 323 alternately stacked along the Z direction. In other words, except for the top and bottom layers of the stacked structure 321, each of the other conductive layers 322 may be sandwiched between two adjacent dielectric layers 323, and each of the other dielectric layers 323 may be sandwiched between two adjacent conductive layers 322. In one embodiment, the conductive layer 322 may include a conductive material, the conductive material including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), tantalum (Ta), polysilicon, doped silicon, silicide, or any combination thereof. In one embodiment, the dielectric layer 323 may include any one of silicon oxide, silicon nitride, and silicon oxynitride.

[0049] As shown in FIG3(c), the conductive layer 322 includes a first conductive layer 322-1, a second conductive layer 322-2, a plurality of third conductive layers 322-3, and a plurality of fourth conductive layers 322-4. Contact structures 304, 305, 306, 307, 308, 309, 310 are respectively coupled to the corresponding conductive layers 322. For example, the contact structures 304 and 305 are respectively coupled to the corresponding third conductive layers 322-3, the contact structures 306 and 307 are coupled to the first conductive layer 322-1, the contact structure 308 is coupled to the second conductive layer 322-2, and the contact structures 309 and 310 are respectively coupled to the corresponding fourth conductive layers 322-4.

[0050] As shown in FIG3(c), the memory cell MC5 includes two MOS transistors T1 and T2, and the transistors T1 and T2 include a semiconductor column extending along the Z direction and a source S and a drain D located at both ends of the semiconductor column. As shown in FIG3(c), the drains D1 and D2 of the transistors T1 and T2 are coupled to the second conductive layer 322-2, the gates G1 and G2 of the transistors T1 and T2 are coupled to the first conductive layer 322-1, and the sources S1 and S2 of the transistors T1 and T2 can be coupled to the contact structures 305 and 304, respectively, for example, via the wire 324.

[0051] As shown in FIG. 3( c ), the stacked structure 321 includes a core region C in the middle and two step regions S adjacent to the core region C on both sides, and the transistors T1 and T2 are located in the core region C.

[0052] As shown in FIG3(c), the two fourth conductive layers 322-4 may be connected, for example, via a conductive line 324, that is, the two fourth conductive layers 322-4 may be coupled to a common potential (e.g., ground). In addition, the contact structures 306, 307 may be further coupled to a word line WL (not shown) and the contact structure 308 may be further coupled to a bit line BL (not shown).

[0053] As shown in FIG3( c ), each third conductive layer 322 - 3 may form a capacitor C with one of the fourth conductive layers 322 - 4 adjacent thereto. For example, two capacitors C1 and C2 are formed in FIG3( c ).

[0054] Unlike the planar transistor in FIG. 2( b ), the semiconductor pillars of the transistors T1 and T2 shown in FIG. 3( c ) are perpendicular to the substrate 320 and thus the transistors T1 and T2 are vertical transistors. Figure 3(b)-3(c) It is shown in the figure that each memory cell MC includes two transistors T1, T2 and two capacitors C1, C2, but it is obvious to those skilled in the art that the memory cell MC includes n transistors T1, T2, ... Tn and n capacitors C1, C2, ... Cn.

[0055] according to Figure 3(b)-3(c) In the semiconductor device shown in FIG. 1 , the transistor is formed as a vertical transistor. In addition, by forming a stacked capacitor structure, multiple capacitors can be implemented per unit area, thereby increasing the storage capacity of the dynamic random access memory.

[0056] Figure 4(a)-4(d) A cross-sectional view showing various steps of a manufacturing method for forming a semiconductor device including a 2T2C memory cell according to an embodiment of the present disclosure is shown. Figure 5A flowchart of a method 500 for forming a semiconductor device including a 2T2C memory cell according to an embodiment of the present disclosure is shown. Figure 4(a)-4(d) as well as Figure 5 It should be understood that the operations shown in method 500 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Figure 5 Executed in the order shown in .

[0057] refer to Figure 5 The method 500 begins at operation 510 in which a stack structure including a plurality of alternating dielectric layers and conductive layers along a first direction is formed.

[0058] As shown in FIG4(a), the substrate 420 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. In some embodiments, the substrate 420 is a thinned substrate (e.g., a semiconductor layer) that is thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof.

[0059] A stacked structure 421 may be formed on a substrate 420, as shown in FIG4(a). A stacked structure 421 including a plurality of alternating conductive layers 422 and dielectric layers 423 may be formed on a substrate 420. According to some embodiments, the stacked structure 421 may include a plurality of alternating conductive layers 422 and dielectric layers 423. In other words, except for the top and bottom layers of the stacked structure 421, each of the other conductive layers 422 may be sandwiched between two adjacent dielectric layers 423, and each of the other dielectric layers 423 may be sandwiched between two adjacent conductive layers 422. The stacked structure 421 may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In one embodiment, the dielectric layer 423 may include any one of silicon oxide, silicon nitride, and silicon oxynitride. In one embodiment, the conductive layer 422 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), tantalum (Ta), polysilicon, doped silicon, silicide, or any combination thereof.

[0060] In one embodiment, an initial stack structure including a plurality of alternating sacrificial layers and dielectric layers 423 may first be formed on a substrate 420 , and the sacrificial layers are subsequently replaced by conductive layers 422 , thereby forming a stack structure 421 including a plurality of alternating conductive layers 422 and dielectric layers 423 .

[0061] As shown in FIG. 4( a ), the conductive layer includes a first conductive layer 422 - 1 , a second conductive layer 422 - 2 , two third conductive layers 422 - 3 , and two fourth conductive layers 422 - 4 .

[0062] The method then proceeds to operation 520 in which a step structure is formed in the step region of the stack structure and a first isolation structure extending through the first conductive layer is formed in the core region of the stack structure.

[0063] As shown in FIG. 4( b), the stacked structure 421 includes a core region C in the middle and two step regions S adjacent to the core region C on both sides. According to an embodiment of the present disclosure, a step structure is formed in the step region S of the stacked structure 421. The step structure may be formed by performing a plurality of so-called “trim-etch” cycles on the conductive layer 422 and the dielectric layer 423 of the stacked structure 421 toward the substrate 420. Due to the repeated trim-etch cycles applied to the conductive layer 422 and the dielectric layer 423 of the stacked structure 421, the stacked structure 421 may have one or more inclined edges and a top conductive layer / dielectric layer pair that is shorter than a bottom conductive layer / dielectric layer pair.

[0064] As shown in FIG4(b), after forming the stepped structure in the stepped region S, a dielectric cover layer 424 is formed on the stacked structure 421. In some embodiments, the dielectric cover layer 424 may cover at least the stepped region S. In some embodiments, the dielectric cover layer 424 may cover both the stepped region S and the core region C.

[0065] As shown in FIG. 4( b), after the dielectric cover layer 424 is formed, a first isolation structure 425 extending through the first conductive layer 422-1 is formed in the core region C of the stacked structure 421. To form the first isolation structure 425, an opening is first formed through the dielectric cover layer 424 and the first conductive layer 422-1 and extending to the dielectric layer 423 adjacent to the first conductive layer 422-1, and then the opening is filled with an insulating material to form the first isolation structure 425. In some embodiments, the insulating material includes any one of oxide, nitride, and oxynitride. After the first isolation structure 425 is formed, chemical mechanical polishing (CMP) may be performed on the dielectric cover layer 424 and the first isolation structure 425.

[0066] As shown in FIG. 4( b ), after forming the first isolation structure 425 , the core region C is divided into a first portion C1 and a second portion C2 .

[0067] Then, the method 500 proceeds to operation 530 , in which a plurality of vertical transistors arranged along the first direction are formed in the stacked structure, each of the vertical transistors including a semiconductor column extending along the first direction and a source and a drain located at two ends of the semiconductor column.

[0068] As shown in FIG4(c), in order to form vertical transistors T1 and T2 in the core regions C1 and C2, respectively, openings are first formed in the core regions C1 and C2, respectively, through the dielectric cover layer 424, the first conductive layer 422-1 of the stacked structure 421, and extending to the second conductive layer 422-2 of the stacked structure 421. In some embodiments, the manufacturing process for forming the openings includes wet etching and / or dry etching.

[0069] After the openings are formed in the core regions C1 and C2, respectively, first doped regions D1 and D2 serving as drains of the vertical transistors T1 and T2 are formed at the bottom of each of the openings. Next, a gate oxide layer 426 is formed on the first conductive layer 422-1 exposed by each of the openings; the openings are filled with single crystal silicon; and second doped regions S1 and S2 serving as sources of the vertical transistors T1 and T2 are formed at the top of each of the openings.

[0070] At this point, the first conductive layer 422-1 can be used as the gate of the vertical transistors T1 and T2, that is, the gates G1 and G2 of the vertical transistors T1 and T2 formed according to the method disclosed in the present invention are connected to the first conductive layer 422-1, and the drains D1 and D2 of the vertical transistors T1 and T2 are connected to the second conductive layer 422-2.

[0071] The method 500 then proceeds to operation 540, in which a plurality of contact structures are formed that extend along the first direction and are connected to corresponding conductive layers of the stacked structure, wherein the conductive layers include a first conductive layer, a second conductive layer, and a plurality of third conductive layers, the gates of the plurality of vertical transistors are connected to the first conductive layer, the drains of the plurality of vertical transistors are connected to the second conductive layer, and the source of each of the vertical transistors is connected to a different third conductive layer via the contact structures.

[0072] As shown in FIG4(d), contact structures 404, 405, 406, 407, 408, 409 and 410 are formed and are respectively coupled to the corresponding conductive layers 422. Among them, the contact structures 404 and 405 are respectively coupled to the corresponding third conductive layer 422-3, the contact structures 406 and 407 are coupled to the first conductive layer 422-1, the contact structure 408 is coupled to the second conductive layer 422-2, and the contact structures 409 and 410 are respectively coupled to the corresponding fourth conductive layer 422-4.

[0073] According to an embodiment of the present disclosure, in order to form the contact structures 404-410, a plurality of contact holes are first formed in the stack structure 421 along the Z direction, wherein the bottom of each contact hole exposes the corresponding conductive layer 422 in the stack structure 421. Next, the contact holes are filled with a conductive material to form the contact structures 404-410 connected to the corresponding conductive layers 422 of the stack structure 421. In some embodiments, the conductive material may include any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), and tantalum (Ta).

[0074] Although not shown in FIG. 4( d ), according to the embodiment of the present disclosure, two capacitors C1 and C2 arranged along the Z direction can be formed in the third conductive layer 422-3 and the fourth conductive layer 422-4 adjacent thereto by connecting the two fourth conductive layers 422-4 to a common potential (e.g., ground) via contact structures 409-410. It should be noted that, Figure 4(a)-4(d) The steps of the manufacturing method for forming a semiconductor device including a 2T2C memory cell are exemplary. According to the embodiments of the present disclosure, the manufacturing method for forming a semiconductor device including an nTnC memory cell is obvious to those skilled in the art.

[0075] According to the method for forming a semiconductor device according to the embodiment of the present disclosure, the combination of DRAM and 3D NAND process is realized. In addition, the unit area is changed from 1T1C to nTnC, thereby saving costs.

[0076] Figure 6 A block diagram of an exemplary system 600 having a 3D dynamic random access memory (DRAM) according to an embodiment of the present disclosure is shown. The system 600 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Figure 6 As shown in , system 600 may include a host 608 and a storage system 602, the storage system 602 having one or more 3D storage devices 604 and a memory controller 606. The host 608 may be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host 608 may be configured to send or receive data to or from the storage device 604. In addition to sending or receiving data to or from the storage device 604, the host 608 may also send instructions to the storage system 602.

[0077] The 3D memory device 604 may be / include any 3D memory device / semiconductor device disclosed herein. According to an embodiment of the present disclosure, the transistors in the 3D dynamic random access memory (DRAM) storage unit are formed as vertical transistors. By forming a stacked capacitor structure, multiple capacitors can be implemented per unit area, thereby increasing the storage capacity of the dynamic random access memory. In addition, according to the method for forming a semiconductor device disclosed in the present disclosure, the combination of DRAM and 3D NAND processes is realized, and the unit area of ​​1T1C is changed to nTnC, thereby saving costs.

[0078] According to some embodiments, the memory controller 606 is coupled to the 3D memory device 604 and the host 608, and is configured to control the 3D memory device 604. The memory controller 606 may manage data stored in the 3D memory device 604 and communicate with the host 608. In some embodiments, the memory controller 606 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 606 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc. and an enterprise storage array. The memory controller 606 may be configured to control operations of the 3D memory device 604, such as read, erase, and program operations. The memory controller 606 may also be configured to manage various functions related to data stored or to be stored in the 3D storage device 604, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction code (ECC) related to data read from or written to the 3D storage device 604. Any other suitable functions may also be performed by the memory controller 606, such as formatting the 3D storage device 604. The memory controller 606 may communicate with an external device (e.g., a host 608) according to a specific communication protocol. For example, the memory controller 606 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0079] The above description of specific embodiments will fully demonstrate the general nature of the present disclosure, so that others can easily modify and / or adjust various applications of such specific embodiments by applying knowledge within the technical scope of the art without excessive experimentation and without departing from the general concept of the present disclosure. Therefore, according to the disclosure and guidance given herein, such adjustments and modifications are intended to be within the meaning and scope of the equivalents of the embodiments disclosed herein. It should be understood that the wording or terminology herein is for illustrative purposes, not for limitation, so the terms or wording of this specification will be interpreted by the technician in accordance with the disclosure and guidance.

[0080] The Summary and Abstract sections may set forth one or more, but not necessarily all exemplary embodiments of the present disclosure contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0081] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device, comprising a storage unit, wherein the storage unit comprises: A stack structure including a plurality of alternating dielectric layers and conductive layers along a first direction; a plurality of vertical transistors arranged in the stacked structure along the first direction, each of the vertical transistors comprising a semiconductor column extending along the first direction and a source and a drain located at two ends of the semiconductor column; as well as a plurality of contact structures extending along the first direction and connected to corresponding conductive layers of the stacked structure, The conductive layer includes a first conductive layer, a second conductive layer and multiple third conductive layers, the gates of the multiple vertical transistors are connected to the first conductive layer, the drains of the multiple vertical transistors are connected to the second conductive layer, and the source of each of the vertical transistors is connected to a different third conductive layer via the contact structure.

2. The semiconductor device according to claim 1, wherein The conductive layer further includes a plurality of fourth conductive layers, the third conductive layers and the fourth conductive layers are alternately stacked in the first direction, and each of the third conductive layers forms a capacitor with one of the fourth conductive layers adjacent thereto.

3. The semiconductor device according to claim 2, wherein: The plurality of fourth conductive layers are connected to a common potential via the contact structure.

4. The semiconductor device according to claim 1, wherein: The stacked structure includes a core region and a step region, and the plurality of vertical transistors are located in the core region.

5. The semiconductor device according to claim 1, wherein The memory cell also includes a first isolation structure extending through the first conductive layer and separating the plurality of vertical transistors from each other.

6. The semiconductor device according to claim 1, wherein The semiconductor device further includes a second isolation structure extending through the stack structure and used to separate the memory cells.

7. The semiconductor device according to claim 5 or 6, wherein: The first isolation structure and / or the second isolation structure includes any one of oxide, nitride and oxynitride.

8. The semiconductor device according to claim 1, wherein The dielectric layer includes any one of silicon oxide, silicon nitride and silicon oxynitride.

9. The semiconductor device according to claim 1, wherein: The conductive layer includes polysilicon or metal.

10. The semiconductor device according to claim 9, wherein The metal includes any one of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al).

11. The semiconductor device according to claim 1, wherein The contact structure includes any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), and tantalum (Ta).

12. A method for forming a semiconductor device, comprising: forming a stack structure including a plurality of alternating dielectric layers and conductive layers along a first direction; forming a plurality of vertical transistors arranged along the first direction in the stacked structure, each of the vertical transistors comprising a semiconductor column extending along the first direction and a source and a drain located at two ends of the semiconductor column; as well as A plurality of contact structures are formed extending along the first direction and connected to corresponding conductive layers of the stacked structure, wherein the conductive layers include a first conductive layer, a second conductive layer and a plurality of third conductive layers, the gates of the plurality of vertical transistors are connected to the first conductive layer, the drains of the plurality of vertical transistors are connected to the second conductive layer, and the source of each of the vertical transistors is connected to a different third conductive layer via the contact structure.

13. The method according to claim 12, wherein: The stacked structure includes a core region and a step region, and wherein, before forming the plurality of vertical transistors, the method further includes: A step structure is formed in the step region.

14. The method according to claim 13, wherein: Forming the plurality of vertical transistors includes: forming a plurality of openings in the core region through the first conductive layer of the stacked structure and extending into the second conductive layer of the stacked structure; forming a first doped region serving as a drain of the vertical transistor at a bottom of each of the openings; forming a gate oxide layer on the first conductive layer exposed through each of the openings; filling the opening with single crystal silicon; and A second doped region serving as a source of the vertical transistor is formed at the top of each of the openings.

15. The method according to claim 12, wherein: The conductive layer further includes a plurality of fourth conductive layers, the third conductive layers and the fourth conductive layers are alternately stacked in the first direction, and wherein the method further includes: A plurality of capacitors arranged along the first direction are formed in the third conductive layer and the fourth conductive layer by connecting the plurality of fourth conductive layers to a common potential via the contact structure.

16. The method according to claim 12, further comprising: A first isolation structure is formed that extends through the first conductive layer and separates the plurality of vertical transistors from each other.

17. The method according to claim 12, wherein: Forming the plurality of contact structures comprises: forming a plurality of contact holes in the stacked structure along the first direction, wherein the bottom of each contact hole exposes a corresponding conductive layer in the stacked structure; and The contact holes are filled with a conductive material to form the plurality of contact structures connected to corresponding conductive layers of the stacked structure.

18. A storage system comprising: A memory device, the memory device comprising a plurality of semiconductor devices arranged in an array and configured to store data, the semiconductor device comprising a memory cell, the memory cell comprising: A stack structure including a plurality of alternating dielectric layers and conductive layers along a first direction; a plurality of vertical transistors arranged in the stacked structure along the first direction, each of the vertical transistors comprising a semiconductor column extending along the first direction and a source and a drain located at two ends of the semiconductor column; and a plurality of contact structures extending along the first direction and connected to corresponding conductive layers of the stacked structure, wherein the conductive layers include a first conductive layer, a second conductive layer and a plurality of third conductive layers, the gates of the plurality of vertical transistors are connected to the first conductive layer, the drains of the plurality of vertical transistors are connected to the second conductive layer, and the source of each of the vertical transistors is connected to a different third conductive layer via the contact structure; and A memory controller is coupled to the memory device and is configured to control the memory device.

19. The memory system of claim 18, further comprising a host coupled to the memory controller and configured to send or receive the data.

Images