Semiconductor device and method of forming the same

Abstract

Disclosed are a semiconductor device and a method of forming the same. According to embodiments of the present disclosure, a semiconductor device includes a memory cell including a stack structure including a plurality of alternating dielectric layers and conductive layers in a first direction, a plurality of vertical transistors arranged in the stack structure in the first direction, each of the vertical transistors including a semiconductor pillar extending in the first direction and a source and a drain located at both ends of the semiconductor pillar, and a plurality of contact structures extending in the first direction and connected to respective conductive layers of the stack structure, wherein the conductive layers include a first conductive layer, a second conductive layer, and a plurality of third conductive layers, gates of the plurality of vertical transistors are connected to the first conductive layer, drains of the plurality of vertical transistors are connected to the second conductive layer, and a source of each of the vertical transistors is connected to a different third conductive layer via the contact structure.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and more specifically to a semiconductor device for three-dimensional (3D) dynamic random access memory (DRAM) and a method of forming the same. Background Technology

[0002] Currently, the most common type of Dynamic Random Access Memory (DRAM) array consists of an array of memory cells (i.e., 1T1C memory cells) that include one transistor and one capacitor. In such a 1T1C memory cell, as... Figure 1 As shown, the gate of transistor 10 is connected to word line 11, the drain is connected to bit line 12, and the source is connected to capacitor 13. When word line 11 is enabled, transistor 10 is turned on, allowing information stored in capacitor 13 to be read via bit line 12.

[0003] As the size of dynamic random access memory (DRAM) and transistors continue to shrink, the question of how to achieve DRAM with larger storage capacity and lower cost has become an urgent problem to be solved. Summary of the Invention

[0004] According to embodiments of this disclosure, a semiconductor device is provided, the semiconductor device including a memory cell, the memory cell including: a stacked structure comprising a plurality of alternating dielectric layers and conductive layers along a first direction; a plurality of vertical transistors disposed in the stacked structure along the first direction, each vertical transistor including a semiconductor pillar extending along the first direction and a source and a drain located at both ends of the semiconductor pillar; and a plurality of contact structures extending along the first direction and connected to corresponding conductive layers of the stacked structure, wherein the conductive layers include a first conductive layer, a second conductive layer and a plurality of third conductive layers, the gates of the plurality of vertical transistors are connected to the first conductive layer, the drains of the plurality of vertical transistors are connected to the second conductive layer, and the sources of each vertical transistor are connected to different third conductive layers via the contact structures.

[0005] In some embodiments, the conductive layer further includes a plurality of fourth conductive layers, wherein the third conductive layer and the fourth conductive layers are stacked alternately in the first direction and each of the third conductive layer and its adjacent fourth conductive layer form a capacitor.

[0006] In some embodiments, the plurality of fourth conductive layers are connected to a common potential via the contact structure.

[0007] In some embodiments, the stacked structure includes a core region and a stepped region, and the plurality of vertical transistors are located in the core region.

[0008] In some embodiments, the memory cell further includes a first isolation structure that extends through the first conductive layer and separates the plurality of vertical transistors from one another.

[0009] In some embodiments, the semiconductor device further includes a second isolation structure extending through the stacked structure and used to separate the memory cells.

[0010] In some embodiments, the first isolation structure and the second isolation structure include any one of oxides, nitrides, and oxynitrides.

[0011] In some embodiments, the dielectric layer comprises any one of silicon oxide, silicon nitride, and silicon oxynitride.

[0012] In some embodiments, the conductive layer comprises polycrystalline silicon or metal.

[0013] In some embodiments, the metal includes any one of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al).

[0014] In some embodiments, the contact structure comprises any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), and tantalum (Ta).

[0015] According to embodiments of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a stacked structure comprising a plurality of alternating dielectric layers and conductive layers along a first direction; forming a plurality of vertical transistors arranged along the first direction in the stacked structure, each vertical transistor comprising a semiconductor pillar extending along the first direction and a source and a drain located at both ends of the semiconductor pillar; and forming a plurality of contact structures extending along the first direction and connected to corresponding conductive layers of the stacked structure, wherein the conductive layers comprise a first conductive layer, a second conductive layer and a plurality of third conductive layers, the gates of the plurality of vertical transistors are connected to the first conductive layer, the drains of the plurality of vertical transistors are connected to the second conductive layer, and the sources of each vertical transistor are connected to different third conductive layers via the contact structures.

[0016] In some embodiments, the stacked structure includes a core region and a stepped region, and wherein, prior to forming the plurality of vertical transistors, the method further includes forming a stepped structure in the stepped region.

[0017] In some embodiments, forming the plurality of vertical transistors includes: forming a plurality of openings in the core region that pass through a first conductive layer of the stacked structure and extend into a second conductive layer of the stacked structure; forming a first doped region at the bottom of each opening that serves as the drain of the vertical transistor; forming a gate oxide layer on the first conductive layer exposed through each opening; filling the openings with single-crystal silicon; and forming a second doped region at the top of each opening that serves as the source of the vertical transistor.

[0018] In some embodiments, the conductive layer further includes a plurality of fourth conductive layers, the third conductive layer and the fourth conductive layers being stacked alternately in the first direction, and wherein the method further includes: forming a plurality of capacitors arranged in the third conductive layer and the fourth conductive layer in the first direction by connecting the plurality of fourth conductive layers to a common potential via the contact structure.

[0019] In some embodiments, the method further includes forming a first isolation structure that extends through the first conductive layer and separates the plurality of vertical transistors from each other.

[0020] In some embodiments, forming the plurality of contact structures includes: forming a plurality of contact holes in the stacked structure along the first direction, the bottom of each contact hole exposing a corresponding conductive layer in the stacked structure; and filling the contact holes with a conductive material to form the plurality of contact structures connected to the corresponding conductive layers of the stacked structure.

[0021] According to embodiments of this disclosure, a storage system is provided, comprising: a storage device including a plurality of semiconductor devices arranged in an array and configured to store data, the semiconductor devices including storage cells, the storage cells including: a stacked structure including a plurality of alternating dielectric and conductive layers along a first direction; a plurality of vertical transistors arranged in the stacked structure along the first direction, each vertical transistor including a semiconductor pillar extending along the first direction and a source and a drain located at both ends of the semiconductor pillar; and a plurality of contact structures extending along the first direction and connected to corresponding conductive layers of the stacked structure, wherein the conductive layers include a first conductive layer, a second conductive layer and a plurality of third conductive layers, the gates of the plurality of vertical transistors are connected to the first conductive layer, the drains of the plurality of vertical transistors are connected to the second conductive layer, and the sources of each vertical transistor are connected to different third conductive layers via the contact structures; and a memory controller coupled to the storage device and configured to control the storage device.

[0022] In some embodiments, the storage system further includes a host coupled to the memory controller and configured to send or receive the data. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1 A schematic diagram of the connection of a 1T1C memory cell in DRAM is shown;

[0025] Figure 2(a) shows a schematic diagram of a DRAM memory array formed by a plurality of 1T1C memory cells according to an embodiment of the present disclosure;

[0026] Figure 2(b) shows a schematic diagram of the structure of any 1T1C memory cell in Figure 2(a);

[0027] Figure 3(a) shows a schematic diagram of a DRAM memory array formed by a plurality of nTnC memory cells according to an embodiment of the present disclosure;

[0028] Figure 3(b) shows a top view of a semiconductor device including memory cells MC1-MC9 according to an embodiment of the present disclosure;

[0029] Figure 3(c) shows a cross-sectional view of memory cell MC5 along line A-A' in Figure 3(b);

[0030] Figures 4(a)-4(d) Cross-sectional views are shown of each step in a manufacturing method for forming a semiconductor device including 2T2C memory cells according to an embodiment of the present disclosure;

[0031] Figure 5 A flowchart illustrating a manufacturing method for forming a semiconductor device including 2T2C memory cells according to an embodiment of the present disclosure is shown; and

[0032] Figure 6 A block diagram of an exemplary system having 3D dynamic random access memory (DRAM) according to an embodiment of the present disclosure is shown.

[0033] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0034] The subject matter described herein will now be discussed with reference to exemplary embodiments. It should be understood that these embodiments are discussed only to enable those skilled in the art to better understand and implement the subject matter described herein, and are not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various processes or components may be omitted, substituted, or added as needed in the various examples. For example, the described methods may be performed in a different order than described, and steps may be added, omitted, or combined. Furthermore, features described in some examples may be combined in other examples.

[0035] It should be noted that the use of terms such as "one embodiment," "embodiment," or "some embodiments" in the specification indicates that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such wording does not necessarily refer to the same embodiment. Additionally, when describing specific features, structures, or characteristics in conjunction with embodiments, implementing such features, structures, or characteristics in conjunction with other embodiments, whether explicitly described or not, should be within the knowledge scope of those skilled in the art.

[0036] Generally, terms can be understood at least partly by the context in which they are used. For example, the word "one or more" can be used, at least partly according to context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, words such as "a," "one," or "the" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the word "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the existence of other factors that are not necessarily explicitly stated, again at least partly depending on the context.

[0037] It should be readily understood that “on,” “above,” and “above” in this disclosure should be interpreted in the broadest manner, such that “on” means not only directly on something, but also contained on something with an intermediate feature or layer therebetween, and that “above” or “above” means not only contained on or above something, but also contained on or above something without an intermediate feature or layer therebetween (i.e., directly on something).

[0038] In addition, for ease of explanation, spatial relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used in the text shall be interpreted accordingly.

[0039] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned, or it can remain unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0040] Embodiments of a semiconductor device for a three-dimensional (3D) dynamic random access memory (DRAM) and a method of forming the same, according to the present disclosure, will now be described with reference to the accompanying drawings.

[0041] Figure 2(a) shows a schematic diagram of a DRAM memory array 200 formed by a plurality of (e.g., 12) 1T1C memory cells according to an embodiment of the present disclosure. As shown in Figure 2(a), in a DRAM memory array 200 including, for example, 12 transistors and 12 capacitors, the gates of transistors T11-T14 are connected to word line WL1, the gates of transistors T21-T24 are connected to word line WL2, and the gates of transistors T31-T34 are connected to word line WL3; the drains of transistors T11-T31, T12-T32, T13-T33, and T14-T34 are connected to bit lines BL1, BL2, BL3, and BL4, respectively; the sources of transistors T11-T14 are connected to the first electrodes of capacitors C11-C14, the sources of transistors T21-T24 are connected to the first electrodes of capacitors C21-C24, and the sources of transistors T31-T34 are connected to the first electrodes of capacitors C31-C34; and the second electrodes of capacitors C11~C14, C21~C24, and C31~C34 are grounded.

[0042] Figure 2(b) shows a schematic diagram of the structure of any 1T1C memory cell in Figure 2(a). As shown in Figure 2(b), the well region 24 can be an n-type well region or a p-type well region (e.g., p-well 24) formed by implanting appropriate dopants into the semiconductor substrate 20. For example, the dopants used to form the n-type well region can include phosphorus (P), arsenic (As), or other suitable n-type dopants, and the dopants used to form the p-type well region can include boron (B), gallium (Ga), or other suitable p-type dopants. The source region 22 / drain region 23 can be disposed in the well region 24 and respectively disposed on two opposite sides of the gate electrode 21 and the gate dielectric layer 25. Each of the source region 22 / drain region 23 can be formed by implanting appropriate dopants into the well region 24. When the well region 24 is a p-type well region, each of the source region 22 / drain region 23 can include an n-type doped region, but is not limited thereto. Contact structures 26 and 27 are coupled to the drain and gate of transistor T, respectively; contact structure 28 is coupled to the source of transistor T and the first electrode of capacitor C, respectively; and contact structure 29 is coupled to the second electrode of capacitor C.

[0043] In the 1T1C memory cell shown in Figure 2(b), the semiconductor channel of the MOS transistor T is parallel to the substrate 20, and therefore the transistor T is a planar transistor. When the 1T1C memory cell of the DRAM includes such a planar transistor, the increase in DRAM storage capacity is limited by the size of the DRAM.

[0044] Figure 3(a) shows a schematic diagram of a DRAM memory array 300 formed by a plurality of (e.g., nine) nTnC memory cells according to an embodiment of the present disclosure. Unlike the DRAM memory array 200 shown in Figure 2(a), each memory cell MC in the DRAM memory array 300 is formed by a semiconductor device including an nTnC structure, rather than by a semiconductor device including an nTnC structure.

[0045] As shown in Figure 3(a), in a DRAM memory array 300, for example, comprising nine memory cells, each memory cell includes nTnC. For simplicity, Figure 3(a) only schematically shows three transistors and three capacitors in each memory cell. Taking the memory cell MC31 in the upper left corner as an example, the gates of its three transistors T1, T2, and T3 are connected to word line WL3, the drains of the three transistors T1, T2, and T3 are connected to bit line BL1, and the sources of the three transistors T1, T2, and T3 are connected to the first electrodes of the three capacitors C1, C2, and C3, respectively. Furthermore, the second electrodes of the three capacitors C1, C2, and C3 are grounded.

[0046] It should be noted that the number of transistors and capacitors in each memory cell MC in FIG3(a) is exemplary. Each memory cell MC according to the embodiments of the present disclosure may include other numbers of transistors and capacitors, such as 4, 5, 6, ... etc.

[0047] Figure 3(b) shows a top view of a semiconductor device including memory cells MC1-MC9 according to an embodiment of the present disclosure. For simplicity, memory cells MC1-MC9 are all 2T2C memory cells. Taking memory cell MC5 as an example, it includes an isolation structure 303 for separating two transistors 301, 302, and also includes contact structures 304, 305, 306, 307, 308, 309, 310. In addition, an isolation structure 311 for separating the memory cells MC of the semiconductor device from each other is also included. It should be noted that Figure 3(b) only schematically shows the complete isolation structure 311 surrounding memory cell MC5.

[0048] Figure 3(c) shows a cross-sectional view of the memory cell MC5 along line A-A' of Figure 3(b). As shown in Figure 3(c), the memory cell MC5 includes a stacked structure 321 disposed on a substrate 320, the stacked structure 321 including conductive layers 322 and dielectric layers 323 alternately stacked along the Z direction. In other words, each of the other conductive layers 322, except for the top and bottom layers of the stacked structure 321, can be sandwiched between two adjacent dielectric layers 323, and each of the other dielectric layers 323 can be sandwiched between two adjacent conductive layers 322. In one embodiment, the conductive layer 322 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), tantalum (Ta), polycrystalline silicon, doped silicon, silicide, or any combination thereof. In one embodiment, the dielectric layer 323 may include any one of silicon oxide, silicon nitride, and silicon oxynitride.

[0049] As shown in Figure 3(c), the conductive layer 322 includes a first conductive layer 322-1, a second conductive layer 322-2, multiple third conductive layers 322-3, and multiple fourth conductive layers 322-4. Contact structures 304, 305, 306, 307, 308, 309, and 310 are coupled to their respective conductive layers 322. For example, contact structures 304 and 305 are coupled to their respective third conductive layers 322-3, contact structures 306 and 307 are coupled to their respective first conductive layers 322-1, contact structure 308 is coupled to their respective second conductive layers 322-2, and contact structures 309 and 310 are coupled to their respective fourth conductive layers 322-4.

[0050] As shown in Figure 3(c), the memory cell MC5 includes two MOS transistors T1 and T2. Transistors T1 and T2 include semiconductor pillars extending along the Z direction and source S and drain D located at both ends of the semiconductor pillars. As shown in Figure 3(c), the drains D1 and D2 of transistors T1 and T2 are coupled to the second conductive layer 322-2, and the gates G1 and G2 of transistors T1 and T2 are coupled to the first conductive layer 322-1. The sources S1 and S2 of transistors T1 and T2 can be coupled to contact structures 305 and 304, respectively, for example, via wires 324.

[0051] As shown in Figure 3(c), the stacked structure 321 includes a core region C in the middle and two stepped regions S on both sides adjacent to the core region C. Transistors T1 and T2 are located in the core region C.

[0052] As shown in Figure 3(c), the two fourth conductive layers 322-4 can be connected, for example, via wire 324, meaning that the two fourth conductive layers 322-4 can be coupled to a common potential (e.g., ground). Furthermore, contact structures 306 and 307 can be further coupled to word line WL (not shown), and contact structure 308 can be further coupled to bit line BL (not shown).

[0053] As shown in Figure 3(c), each third conductive layer 322-3 can form a capacitor C with an adjacent fourth conductive layer 322-4. For example, two capacitors C1 and C2 are formed in Figure 3(c).

[0054] Unlike the planar transistors in Figure 2(b), the semiconductor pillars of transistors T1 and T2 shown in Figure 3(c) are perpendicular to the substrate 320, and therefore transistors T1 and T2 are vertical transistors. Furthermore, Figures 3(b)-3(c) The diagram shows that each memory cell MC includes two transistors T1, T2 and two capacitors C1, C2, but it is obvious to those skilled in the art that the memory cell MC includes n transistors T1, T2, ... Tn and n capacitors C1, C2, ... Cn.

[0055] according to Figures 3(b)-3(c) The semiconductor device shown has transistors formed as vertical transistors. Furthermore, by forming a stacked capacitor structure, multiple capacitors can be implemented per unit area, thereby increasing the storage capacity of the dynamic random access memory.

[0056] Figures 4(a)-4(d) Cross-sectional views are shown of the steps in a manufacturing method for forming a semiconductor device including 2T2C memory cells according to an embodiment of the present disclosure. Figure 5A flowchart of a manufacturing method 500 for forming a semiconductor device including 2T2C memory cells according to an embodiment of the present disclosure is shown, which will be described together. Figures 4(a)-4(d) as well as Figure 5 It should be understood that the operations shown in method 500 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a sequence different from the operations shown. Figure 5 The sequence shown is executed.

[0057] refer to Figure 5 Method 500 begins with operation 510, in which a stacked structure comprising a plurality of alternating dielectric and conductive layers is formed along a first direction.

[0058] As shown in FIG4(a), substrate 420 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some embodiments, substrate 420 is a thinned substrate (e.g., a semiconductor layer) that has been thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof.

[0059] A stacked structure 421 can be formed on the substrate 420, as shown in FIG. 4(a). The stacked structure 421, comprising a plurality of alternating conductive layers 422 and dielectric layers 423, can be formed on the substrate 420. According to some embodiments, the stacked structure 421 may include a plurality of alternating conductive layers 422 and dielectric layers 423. In other words, each of the other conductive layers 422, except for the top and bottom layers of the stacked structure 421, may be sandwiched between two adjacent dielectric layers 423, and each of the other dielectric layers 423 may be sandwiched between two adjacent conductive layers 422. The stacked structure 421 may be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In one embodiment, the dielectric layer 423 may include any one of silicon oxide, silicon nitride, and silicon oxynitride. In one embodiment, the conductive layer 422 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), tantalum (Ta), polycrystalline silicon, doped silicon, silicide, or any combination thereof.

[0060] In one embodiment, an initial stacked structure comprising a plurality of alternating sacrificial layers and dielectric layers 423 may first be formed on a substrate 420, and the sacrificial layers may then be replaced by conductive layers 422, thereby forming a stacked structure 421 comprising a plurality of alternating conductive layers 422 and dielectric layers 423.

[0061] As shown in Figure 4(a), the conductive layer includes a first conductive layer 422-1, a second conductive layer 422-2, two third conductive layers 422-3, and two fourth conductive layers 422-4.

[0062] The method then proceeds to operation 520, in which a stepped structure is formed in the stepped region of the stacked structure and a first isolation structure extending through the first conductive layer is formed in the core region of the stacked structure.

[0063] As shown in FIG. 4(b), the stacked structure 421 includes a central core region C and two stepped regions S adjacent to the core region C on both sides. According to an embodiment of the present disclosure, a stepped structure is formed in the stepped regions S of the stacked structure 421. The stepped structure may be formed by performing multiple so-called “trimming-etching” cycles on the conductive layer 422 and dielectric layer 423 of the stacked structure 421 facing the substrate 420. Due to the repeated trimming-etching cycles applied to the conductive layer 422 and dielectric layer 423 of the stacked structure 421, the stacked structure 421 may have one or more sloping edges and a top conductive layer / dielectric layer pair that is shorter than the bottom conductive layer / dielectric layer pair.

[0064] As shown in Figure 4(b), after forming a stepped structure in the stepped region S, a dielectric overlay layer 424 is formed on the stacked structure 421. In some embodiments, the dielectric overlay layer 424 may at least cover the stepped region S. In some embodiments, the dielectric overlay layer 424 may completely cover both the stepped region S and the core region C.

[0065] As shown in Figure 4(b), after forming the dielectric capping layer 424, a first isolation structure 425 extending through the first conductive layer 422-1 is formed in the core region C of the stacked structure 421. To form the first isolation structure 425, an opening is first formed through the dielectric capping layer 424 and the first conductive layer 422-1 and extending into the dielectric layer 423 adjacent to the first conductive layer 422-1. The opening is then filled with an insulating material to form the first isolation structure 425. In some embodiments, the insulating material includes any one of oxides, nitrides, and oxynitrides. After forming the first isolation structure 425, chemical mechanical polishing (CMP) can be performed on the dielectric capping layer 424 and the first isolation structure 425.

[0066] As shown in Figure 4(b), after the first isolation structure 425 is formed, the core region C is divided into a first part C1 and a second part C2.

[0067] The method then proceeds to operation 530, in which a plurality of vertical transistors arranged along the first direction are formed in the stacked structure, each of the vertical transistors including a semiconductor pillar extending along the first direction and a source and a drain located at both ends of the semiconductor pillar.

[0068] As shown in Figure 4(c), in order to form vertical transistors T1 and T2 in the core regions C1 and C2 respectively, openings are first formed in the core regions C1 and C2, respectively, through the dielectric capping layer 424, the first conductive layer 422-1 of the stacked structure 421, and extending into the second conductive layer 422-2 of the stacked structure 421. In some embodiments, the fabrication process for forming the openings includes wet etching and / or dry etching.

[0069] After forming the openings in the core regions C1 and C2, a first doped region D1, D2 serving as the drain of the vertical transistors T1 and T2 is formed at the bottom of each opening. Next, a gate oxide layer 426 is formed on the first conductive layer 422-1 exposed through each opening; the openings are filled with single-crystal silicon; and a second doped region S1, S2 serving as the source of the vertical transistors T1 and T2 is formed at the top of each opening.

[0070] Thus, the first conductive layer 422-1 can be used as the gate of the vertical transistors T1 and T2. That is, the gates G1 and G2 of the vertical transistors T1 and T2 formed according to the method of this disclosure are connected to the first conductive layer 422-1, and the drains D1 and D2 of the vertical transistors T1 and T2 are connected to the second conductive layer 422-2.

[0071] Then method 500 proceeds to operation 540, in which a plurality of contact structures are formed extending along the first direction and connected to the respective conductive layers of the stacked structure, wherein the conductive layers include a first conductive layer, a second conductive layer and a plurality of third conductive layers, the gates of the plurality of vertical transistors are connected to the first conductive layer, the drains of the plurality of vertical transistors are connected to the second conductive layer, and the source of each of the vertical transistors is connected to a different third conductive layer via the contact structures.

[0072] As shown in Figure 4(d), contact structures 404, 405, 406, 407, 408, 409, and 410 are formed and respectively coupled to the corresponding conductive layers 422. Among them, contact structures 404 and 405 are coupled to the corresponding third conductive layer 422-3, contact structures 406 and 407 are coupled to the first conductive layer 422-1, contact structure 408 is coupled to the second conductive layer 422-2, and contact structures 409 and 410 are coupled to the corresponding fourth conductive layer 422-4.

[0073] According to an embodiment of this disclosure, in order to form contact structures 404-410, a plurality of contact holes are first formed in the stacked structure 421 along the Z direction, wherein the bottom of each contact hole exposes a corresponding conductive layer 422 in the stacked structure 421. Next, the contact holes are filled with a conductive material to form contact structures 404-410 connected to the corresponding conductive layers 422 of the stacked structure 421. In some embodiments, the conductive material may include any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), and tantalum (Ta).

[0074] Although not shown in Figure 4(d), according to an embodiment of this disclosure, two capacitors C1 and C2 arranged along the Z direction can be formed in the third conductive layer 422-3 and the adjacent fourth conductive layer 422-4 by connecting the two fourth conductive layers 422-4 to a common potential (e.g., ground) via contact structures 409-410. It should be noted that... Figures 4(a)-4(d) The steps of the manufacturing method shown for forming a semiconductor device including 2T2C memory cells are exemplary. According to embodiments of this disclosure, the manufacturing method for forming a semiconductor device including nTnC memory cells will be apparent to those skilled in the art.

[0075] The method for forming a semiconductor device according to embodiments of this disclosure combines DRAM and 3D NAND processes. Furthermore, it reduces costs by changing the unit area from 1T1C to nTnC.

[0076] Figure 6 A block diagram of an exemplary system 600 having 3D dynamic random access memory (DRAM) according to an embodiment of this disclosure is shown. System 600 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 6 As shown, system 600 may include a host 608 and a storage system 602, the storage system 602 having one or more 3D storage devices 604 and a memory controller 606. The host 608 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). The host 608 may be configured to send or receive data to or from the storage device 604. In addition to sending or receiving data to or from the storage device 604, the host 608 may also send instructions to the storage system 602.

[0077] 3D memory device 604 can be / includes any 3D memory device / semiconductor device disclosed herein. According to embodiments of this disclosure, transistors in the 3D dynamic random access memory (DRAM) memory cell are formed as vertical transistors. By forming a stacked capacitor structure, multiple capacitors can be implemented per unit area, thereby increasing the storage capacity of the dynamic random access memory. Furthermore, the method for forming a semiconductor device according to this disclosure achieves a combination of DRAM and 3D NAND processes, and changes from 1T1C per unit area to nTnC, thereby saving costs.

[0078] According to some embodiments, a memory controller 606 is coupled to a 3D storage device 604 and a host 608, and is configured to control the 3D storage device 604. The memory controller 606 can manage data stored in the 3D storage device 604 and communicate with the host 608. In some embodiments, the memory controller 606 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 606 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., and for enterprise storage arrays. The memory controller 606 can be configured to control the operation of the 3D storage device 604, such as read, erase, and program operations. The memory controller 606 may also be configured to manage various functions related to data stored or to be stored in the 3D storage device 604, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction codes (ECC) related to data read from or written to the 3D storage device 604. The memory controller 606 may also perform any other suitable functions, such as formatting the 3D storage device 604. The memory controller 606 may communicate with external devices (e.g., host 608) according to specific communication protocols. For example, the memory controller 606 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0079] The above description of specific embodiments will fully demonstrate the general nature of this disclosure, enabling others to easily modify and / or adapt various applications of such specific embodiments by applying knowledge within the scope of the art without requiring excessive experimentation and without departing from the general concept of this disclosure. Therefore, such modifications and adaptations are intended to fall within the meaning and scope of equivalents of the embodiments disclosed herein, based on the disclosure and guidance provided herein. It should be understood that the wording or terminology used herein is for illustrative purposes and not for limitation, and therefore the terminology or terminology of this specification will be interpreted by those skilled in the art in accordance with the disclosure and guidance provided.

[0080] The summary and abstract may describe one or more of the present disclosure conceived by the inventors, but not necessarily all exemplary embodiments. Therefore, the summary and abstract are not intended to limit the present disclosure and the appended claims in any way.

[0081] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but only by the appended claims and their equivalents.

Claims

1. A semiconductor device, the semiconductor device comprising a memory cell, the memory cell comprising: A stacked structure comprising multiple alternating dielectric and conductive layers along a first direction; A plurality of vertical transistors are arranged in the stacked structure along the first direction, each of the vertical transistors including a semiconductor pillar extending along the first direction and a source and a drain located at both ends of the semiconductor pillar; as well as Multiple contact structures extending along the first direction and connected to the respective conductive layers of the stacked structure. The conductive layer includes a first conductive layer, a second conductive layer, and a plurality of third conductive layers. The gates of the plurality of vertical transistors are connected to the first conductive layer, the drains of the plurality of vertical transistors are connected to the second conductive layer, and the source of each vertical transistor is connected to a different third conductive layer via the contact structure.

2. The semiconductor device according to claim 1, wherein, The conductive layer further includes a plurality of fourth conductive layers, wherein the third conductive layer and the fourth conductive layers are stacked alternately in the first direction and each third conductive layer forms a capacitor with an adjacent fourth conductive layer.

3. The semiconductor device according to claim 2, wherein, The plurality of fourth conductive layers are connected to a common potential via the contact structure.

4. The semiconductor device according to claim 1, wherein, The stacked structure includes a core region and a stepped region, and the plurality of vertical transistors are located in the core region.

5. The semiconductor device according to claim 1, wherein, The memory cell also includes a first isolation structure that extends through the first conductive layer and separates the plurality of vertical transistors from each other.

6. The semiconductor device according to claim 5, wherein, The semiconductor device also includes a second isolation structure extending through the stacked structure and used to separate the memory cells.

7. The semiconductor device according to claim 6, wherein, The first isolation structure and / or the second isolation structure includes any one of oxides, nitrides, and oxynitrides.

8. The semiconductor device according to claim 1, wherein, The dielectric layer includes any one of silicon oxide, silicon nitride, and silicon oxynitride.

9. The semiconductor device according to claim 1, wherein, The conductive layer comprises polycrystalline silicon or metal.

10. The semiconductor device according to claim 9, wherein, The metal includes any one of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al).

11. The semiconductor device according to claim 1, wherein, The contact structure includes any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), and tantalum (Ta).

12. A method for forming a semiconductor device, comprising: A stacked structure comprising multiple alternating dielectric and conductive layers is formed along a first direction; In the stacked structure, a plurality of vertical transistors are formed along the first direction, each of the vertical transistors including a semiconductor pillar extending along the first direction and a source and a drain located at both ends of the semiconductor pillar; as well as Multiple contact structures are formed that extend along the first direction and are connected to the respective conductive layers of the stacked structure, wherein the conductive layers include a first conductive layer, a second conductive layer and multiple third conductive layers, the gates of the multiple vertical transistors are connected to the first conductive layer, the drains of the multiple vertical transistors are connected to the second conductive layer, and the sources of each vertical transistor are connected to different third conductive layers via the contact structures.

13. The method according to claim 12, wherein, The stacked structure includes a core region and a stepped region, and wherein, prior to forming the plurality of vertical transistors, the method further includes: A stepped structure is formed in the stepped region.

14. The method according to claim 13, wherein, Forming the plurality of vertical transistors includes: Multiple openings are formed in the core region, passing through a first conductive layer of the stacked structure and extending into a second conductive layer of the stacked structure; A first doped region is formed at the bottom of each opening to serve as the drain of the vertical transistor; A gate oxide layer is formed on the first conductive layer exposed through each of the openings; The opening is filled with monocrystalline silicon; and A second doped region is formed at the top of each opening to serve as the source of the vertical transistor.

15. The method according to claim 12, wherein, The conductive layer further includes a plurality of fourth conductive layers, wherein the third conductive layer and the fourth conductive layers are alternately stacked in the first direction, and wherein the method further includes: By connecting the plurality of fourth conductive layers to a common potential via the contact structure, a plurality of capacitors arranged along the first direction are formed in the third conductive layer and the fourth conductive layer.

16. The method of claim 12, further comprising: A first isolation structure is formed that extends through the first conductive layer and separates the plurality of vertical transistors from each other.

17. The method according to claim 12, wherein, Forming the plurality of contact structures includes: A plurality of contact holes are formed in the stacked structure along the first direction, the bottom of each contact hole exposing a corresponding conductive layer in the stacked structure; and The contact holes are filled with a conductive material to form the plurality of contact structures connected to the respective conductive layers of the stacked structure.

18. A storage system, comprising: A storage device comprising a plurality of semiconductor devices arranged in an array and configured to store data, the semiconductor devices including storage cells, the storage cells comprising: A stacked structure comprising multiple alternating dielectric and conductive layers along a first direction; A plurality of vertical transistors are arranged in the stacked structure along the first direction, each vertical transistor including a semiconductor pillar extending along the first direction and a source and a drain located at both ends of the semiconductor pillar; and A plurality of contact structures extending along the first direction and connected to corresponding conductive layers of the stacked structure, wherein the conductive layers include a first conductive layer, a second conductive layer, and a plurality of third conductive layers; the gates of the plurality of vertical transistors are connected to the first conductive layer; the drains of the plurality of vertical transistors are connected to the second conductive layer; and the sources of each of the vertical transistors are connected to a different third conductive layer via the contact structures; and A memory controller, which is coupled to the memory device and configured to control the memory device.

19. The storage system of claim 18, further comprising a host coupled to the memory controller and configured to transmit or receive the data.

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