Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device comprises a stacking structure, the stacking structure comprises a first stacking part and a second stacking part arranged on the first stacking part, and the second stacking part comprises a first sub-part overlapped with the first stacking part and a second sub-part connected to the first sub-part and protruding out of the side face of the first stacking part; wherein one end of the second sub-part is connected to the first sub-part, and the other end of the second sub-part is bent towards the direction close to the first stacking part. According to the invention, the bending structure of the second sub-part can form an avoidance space in space, so that the bending resistance of the semiconductor device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered by planar flash memory and pursue lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D non-or) flash memory and 3D NAND (3D non-and) flash memory.

[0003] Among them, 3D NAND memory takes its small size and large capacity as its starting point, and uses a highly integrated design concept of stacking storage units in a three-dimensional mode to produce memory with high storage density per unit area and efficient storage unit performance. It has become the mainstream process for the design and production of emerging memories.

[0004] Currently, after the memory is manufactured, it is often necessary to perform tests, such as bending tests, to verify its performance. However, the existing memory structure still has defects and is difficult to meet the testing requirements. Summary of the invention

[0005] The embodiments of the present application provide a semiconductor device and a method for manufacturing the same, and an electronic device, which can improve the bending resistance of the semiconductor device.

[0006] An embodiment of the present application provides a semiconductor device, comprising:

[0007] A stacking structure, comprising a first stacking portion, and a second stacking portion arranged on the first stacking portion, wherein the second stacking portion comprises a first sub-portion arranged overlapping with the first stacking portion, and a second sub-portion connected to the first sub-portion and protruding from a side surface of the first stacking portion;

[0008] One end of the second sub-section is connected to the first sub-section, and the other end is bent toward a direction close to the first stacking section.

[0009] In some embodiments of the present application, the semiconductor device includes a first region and a second region surrounding the first region, and the first stacking portion is disposed in the second region, and the second sub-portion is located on a side of the first sub-portion close to the first region.

[0010] In some embodiments of the present application, the first area is a bending test area for performing a bending test.

[0011] In some embodiments of the present application, the second sub-portion extends into the first area.

[0012] In some embodiments of the present application, the stacking structure is located outside the first area.

[0013] In some embodiments of the present application, the thickness of the second stacking portion is greater than or equal to 40 micrometers and less than or equal to 70 micrometers.

[0014] In some embodiments of the present application, the thickness of the second stacking portion is less than the thickness of the first stacking portion;

[0015] Wherein, the second stacking part includes a storage array and / or a peripheral circuit.

[0016] In some embodiments of the present application, the semiconductor device further includes a substrate, the stacking structure is disposed on the substrate, and the second stacking portion is electrically connected to the substrate.

[0017] In some embodiments of the present application, the stacking structure includes a plurality of the second stacking parts stacked on the first stacking part, and the plurality of the second stacking parts includes a top second stacking part;

[0018] Wherein, in the top second stacking portion, one end of the second sub-portion away from the first sub-portion is bent toward a direction close to the substrate and contacts the substrate.

[0019] In some embodiments of the present application, the semiconductor device further includes a control chip disposed on the substrate, wherein the control chip is coupled to the stack structure and is used to control the stack structure to store data.

[0020] The second sub-portion of the second stacking portion is located at a side of the first sub-portion close to the control chip.

[0021] In some embodiments of the present application, the semiconductor device further includes a packaging layer, which is disposed on the substrate and covers the stacking structure and the control chip.

[0022] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0023] forming a first stacking portion;

[0024] forming a second stacking portion on the first stacking portion, wherein the second stacking portion includes a first sub-portion overlapping with the first stacking portion, and a second sub-portion connected to the first sub-portion and protruding from a side surface of the first stacking portion;

[0025] An end of the second sub-portion away from the first sub-portion is bent toward a direction close to the first stacking portion to form a stacking structure.

[0026] In some embodiments of the present application, the step of bending the end of the second sub-portion away from the first sub-portion toward the direction close to the first stacking portion includes:

[0027] forming a packaging material covering the first stacking part and the second stacking part;

[0028] The packaging material is pressed and formed so that an end of the second sub-portion away from the first sub-portion is bent toward a direction close to the first stacking portion.

[0029] In some embodiments of the present application, after the step of bending the end of the second sub-portion away from the first sub-portion toward the direction close to the first stacking portion, the step further includes:

[0030] A bending test area is formed in the semiconductor device, the second sub-portion is formed on a side of the first sub-portion close to the bending test area, and a bending test is performed on the semiconductor device in the bending test area.

[0031] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides an electronic device, which includes the semiconductor device.

[0032] The embodiments of the present application provide a semiconductor device and a method for manufacturing the same, and an electronic device. By setting the second sub-portion of the second stacking portion to be curved, the curved structure of the second sub-portion can form an avoidance in space, thereby improving the bending resistance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0034] Figure 1 A schematic diagram of a structure of a semiconductor device provided for some embodiments of the present application;

[0035] Figure 2 Another structural schematic diagram of a semiconductor device provided for some embodiments of the present application;

[0036] Figure 3 Another structural schematic diagram of a semiconductor device provided for some embodiments of the present application;

[0037] Figure 4 Another structural schematic diagram of a semiconductor device provided for some embodiments of the present application;

[0038] Figure 5 A flow chart of a method for manufacturing a semiconductor device provided for some embodiments of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0040] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0041] The present application embodiment provides a semiconductor device, please refer to Figure 1 The semiconductor device includes a stacking structure 10, wherein the stacking structure 10 includes a first stacking portion 11 and a second stacking portion 12 arranged on the first stacking portion 11, the second stacking portion 12 includes a first sub-portion 101 overlapping the first stacking portion 11, and a second sub-portion 102 connected to the first sub-portion 101 and protruding from the side of the first stacking portion 11.

[0042] Furthermore, one end of the second sub-portion 102 is connected to the first sub-portion 101 , and the other end is bent toward a direction close to the first stacking portion 11 .

[0043] In the embodiment of the present application, the second sub-portion 102 of the second stacking portion 12 is configured to be curved, so that the curved structure of the second sub-portion 102 can be avoided in space, thereby improving the bending resistance of the semiconductor device.

[0044] For details, please refer to Figure 1 The semiconductor device includes a substrate 20, a stacking structure 10, a control chip 30 and a packaging layer 40, wherein the stacking structure 10 and the control chip 30 are both arranged on the substrate 20, and the packaging layer 40 covers the stacking structure 10 and the control chip 30.

[0045] In some embodiments, the stack structure 10 can be a storage chip, and the control chip 30 is coupled to the stack structure 10 for controlling the stack structure 10 to store data. An electrical contact structure can be set on the substrate 20, and the stack structure 10 can be connected to the electrical contact structure on the substrate 20.

[0046] In some embodiments, the material of the encapsulation layer 40 may include an epoxy resin material.

[0047] Among them, the stacking structure 10 includes a plurality of stacking parts arranged in a stacked manner, specifically, may include a first stacking part 11 arranged on a substrate 20 and a second stacking part 12 arranged on the first stacking part 11; it can be understood that the number of the second stacking parts 12 is multiple, and the multiple second stacking parts 12 are stacked in sequence on the side of the first stacking part 11 away from the substrate 20.

[0048] Further, in some embodiments, the first stacking part 11 includes a first chip layer 111 and a first adhesive layer 112, and the first adhesive layer 112 is located between the first chip layer 111 and the substrate 20, and the first chip layer 111 is disposed on the substrate 20 through the first adhesive layer 112. The second stacking part 12 includes a second chip layer 121 and a second adhesive layer 122, and the second adhesive layer 122 is located between the second chip layer 121 and the first stacking part 11.

[0049] It can be understood that when there are multiple second stacking parts 12, in a second stacking part 12 closest to the first stacking part 11, the second chip layer 121 is arranged on the first stacking part 11 through the second adhesive layer 122, and in two adjacent second stacking parts 12, the second chip layer 121 in one of the second stacking parts 12 is connected to the second chip layer 121 in the other second stacking part 12 through the second adhesive layer 122.

[0050] In some embodiments, the first chip layer 111 and the second chip layer 121 may both include a memory array and / or a peripheral circuit, and the first adhesive layer 112 and the second adhesive layer 122 may both be a die attach film (DAF).

[0051] In some embodiments, the thickness of the first stacking portion 11 and the thickness of the second stacking portion 12 may both be greater than or equal to 40 micrometers and less than or equal to 70 micrometers, for example, 40 micrometers, 50 micrometers, 60 micrometers, or 70 micrometers.

[0052] Furthermore, in the stacking structure 10, the second stacking portion 12 is partially overlapped with the first stacking portion 11 along a first direction M, and the first direction M is a direction perpendicular to the substrate 20; the portion of the second stacking portion 12 that does not overlap with the first stacking portion 11 protrudes from the side of the first stacking portion 11 and is suspended.

[0053] Specifically, the second stacking portion 12 includes a first sub-portion 101 overlapping the first stacking portion 11, and a second sub-portion 102 connected to the first sub-portion 101 and protruding from the side of the first stacking portion 11; wherein, one end of the second sub-portion 102 is connected to the first sub-portion 101 along a second direction N, and the second direction N is parallel to the substrate 20, and the other end of the second sub-portion 102 is bent toward a direction close to the first stacking portion 11.

[0054] It should be noted that the semiconductor device provided in the embodiment of the present application includes a first area 201 and a second area 202 arranged around the first area 201, wherein the first area 201 is a bending test area, which can be used to perform a bending test on the semiconductor device, for example, using a bending test fixture to squeeze the part of the semiconductor device located in the first area 201 along the first direction M, so that the semiconductor device is bent under force to test the bending ability of the semiconductor device; and the embodiment of the present application sets the second sub-portion 102 of the second stacking portion 12 into a curved shape, so that the second stacking portion 12 can form a space avoidance in the first direction M to buffer stress, thereby improving the bending resistance of the semiconductor device and reducing the probability of damage to the semiconductor device due to bending during the bending test and subsequent use.

[0055] In some embodiments, the number of the second stacking parts 12 is multiple. And the multiple second stacking parts 12 include the top second stacking part 123, and the distance from the first sub-part 101 in the top second stacking part 123 to the substrate 20 along the first direction M is greater than the distance from the first sub-part 101 in the remaining second stacking parts 12 to the substrate 20 along the first direction M. It can be understood that, among the multiple second stacking parts 12, the top second stacking part 123 is located at the topmost layer of the stacking structure 10, and along the direction of the substrate 20 pointing to the stacking structure 10, the distances of the second sub-parts 102 of the multiple second stacking parts 12 protruding from the side of the first stacking part 11 increase successively, then the distance of the second sub-part 102 in the top second stacking part 123 protruding from the first stacking part 11 is the largest, and the distance from the substrate 20 after bending is the smallest; in the top second stacking part 123, the end of the second sub-part 102 away from the first sub-part 101 is bent toward the direction close to the substrate 20, and is in contact with the substrate 20 or spaced from the substrate 20.

[0056] In some embodiments, the second subsection 102 is located on a side of the first subsection 101 close to the first region 201 . The first region 201 may be located between the stacked structure 10 and the control chip 30 , and the second subsection 102 is located on a side of the first subsection 101 close to the control chip 30 .

[0057] In one embodiment of the present application, please refer to Figure 1The stacking structure 10 is disposed in the second region 202 and partially extends into the first region 201 , that is, the stacking structure 10 partially overlaps with the first region 201 .

[0058] Specifically, the first stacking portion 11 is located in the second region 202 , the second stacking portion 12 is located in the second region 202 and partially extends into the first region 201 , and both the first stacking portion 11 and the second stacking portion 12 can be electrically connected to the substrate 20 through wires.

[0059] Among them, the first sub-section 101 is located in the second area 202, one end of the second sub-section 102 is connected to the first sub-section 101, and the other end extends in a direction close to the first area 201; among the multiple second stacking sections 12, the second sub-sections 102 of some second stacking sections 12 extend into the first area 201, and the second sub-sections 102 of some second stacking sections 12 extend through the first area 201.

[0060] In this embodiment, the second stacking portion 12 is arranged to be curved so that the second stacking portion 12 can form a space avoidance in the first direction M, thereby improving the bending resistance of the semiconductor device and reducing the probability of damage to the semiconductor device due to bending during bending testing and subsequent use.

[0061] In another embodiment of the present application, please refer to Figure 2 , this embodiment and Figure 1 The difference between the illustrated embodiment is that the stacking structure 10 is located outside the first region 201 and inside the second region 202 , that is, the stacking structure 10 has no overlapping portion with the first region 201 .

[0062] Relative to Figure 1 In the embodiment shown, in addition to forming a curved second stacking portion 12 in the stacking structure 10, the stacking structure 10 is also arranged outside the first area 201. Therefore, in this embodiment, the second stacking portion 12 can form a space avoidance in the first direction M, and the stacking structure 10 can form a space avoidance in the second direction N, which can further improve the bending resistance of the semiconductor device and reduce the probability of damage to the semiconductor device due to bending during bending testing and subsequent use.

[0063] In another embodiment of the present application, please refer to Figure 3 , this embodiment and Figure 1 The difference of the illustrated embodiment is that the thickness of the first stack portion 11 and the thickness of the second stack portion 12 are reduced.

[0064] For example, Figure 1In the illustrated embodiment, the thickness of the first stacking portion 11 and the thickness of the second stacking portion 12 may both be 70 micrometers, while in this embodiment, the thickness of the first stacking portion 11 and the thickness of the second stacking portion 12 may both be 40 micrometers.

[0065] Relative to Figure 1 In the embodiment shown, the first stacking part 11 and the second stacking part 12 are thinned, so that the thickness of the stacking structure 10 is reduced, thereby increasing the avoidance space of the stacking structure 10 in the first direction M, which can further improve the bending resistance of the semiconductor device and reduce the probability of damage to the semiconductor device due to bending during bending testing and subsequent use.

[0066] In another embodiment of the present application, please refer to Figure 4 , this embodiment and Figure 3 The difference between the illustrated embodiments is that the stacking structure 10 is located outside the first area 201 , and the first stacking portion 11 is a Dummy structure for supporting the second stacking portion 12 thereon.

[0067] The first stacking part 11 does not participate in signal transmission in the semiconductor device, is not electrically connected to other devices such as the second stacking part 12 , the substrate 20 and the control chip 30 , and is only used to support the second stacking part 12 .

[0068] In some embodiments, the thickness of the first stacking portion 11 is greater than the thickness of the second stacking portion 12 , and the first stacking portion 11 may be made of insulating material.

[0069] Relative to Figure 3 In the embodiment shown, in addition to forming a curved second stacking portion 12 in the stacking structure 10, the stacking structure 10 is also arranged outside the first area 201, so that the second stacking portion 12 can form a space avoidance in the first direction M, and the stacking structure 10 can form a space avoidance in the second direction N, which can further improve the bending resistance of the semiconductor device, so as to reduce the probability of damage to the semiconductor device due to bending during the bending test and subsequent use; in addition, the first stacking portion 11 is arranged below the second stacking portion 12 to play a role of padding and supporting the second stacking portion 12, and relative to Figure 3 The illustrated embodiment increases the thickness of the stacking structure 10 , thereby avoiding the stacking structure 10 having insufficient pressure resistance and stability due to the stacking structure 10 being too thin, and improving the pressure resistance and stability of the stacking structure 10 .

[0070] In addition, the present invention also provides a method for manufacturing a semiconductor device. Figure 1 , the method for manufacturing the semiconductor device comprises the following steps:

[0071] The first stacked portion 11 is formed.

[0072] The second stacking portion 12 is formed on the first stacking portion 11 , wherein the second stacking portion 12 includes a first sub-portion 101 overlapping the first stacking portion 11 and a second sub-portion 102 connected to the first sub-portion 101 and protruding from a side surface of the first stacking portion 11 .

[0073] An end of the second sub-portion 102 away from the first sub-portion 101 is bent toward a direction close to the first stacking portion 11 to form a stacking structure 10 .

[0074] Please combine Figure 1 and Figure 5 The method for manufacturing a semiconductor device provided in the embodiment of the present application comprises the following steps:

[0075] Step S10 : forming a first stacking portion 11 .

[0076] Step S20: forming a second stacking portion 12 on the first stacking portion 11 , wherein the second stacking portion 12 includes a first sub-portion 101 overlapping the first stacking portion 11 , and a second sub-portion 102 connected to the first sub-portion 101 and protruding from a side surface of the first stacking portion 11 .

[0077] Step S30 : bending one end of the second sub-portion 102 away from the first sub-portion 101 toward a direction close to the first stacking portion 11 to form a stacking structure 10 .

[0078] In step S10 , a first stacking part 11 is formed on the substrate 20 , which may specifically include sequentially forming a first adhesive layer 112 and a first chip layer 111 on the substrate 20 , and the first chip layer 111 is connected to the substrate 20 via the first adhesive layer 112 .

[0079] In step S20, at least one second stacking part 12 is formed on the first stacking part 11. Specifically, a second adhesive layer 122 and a second chip layer 121 are sequentially formed on a side of the first stacking part 11 away from the substrate 20, and the second chip layer 121 is connected to the first stacking part 11 through the second adhesive layer 122.

[0080] Among them, the second stacking part 12 is formed with a first sub-part 101 overlapping with the first stacking part 11, and a second sub-part 102 connected to the first sub-part 101 and protruding from the side of the first stacking part 11. The semiconductor device includes a first area 201 for bending test and a second area 202 surrounding the first area 201, that is, the first area 201 is a bending test area, wherein the second sub-part 102 is located on the side of the first sub-part 101 close to the first area 201.

[0081] In some embodiments, the first chip layer 111 and the second chip layer 121 may both include a memory array and / or a peripheral circuit, and the first adhesive layer 112 and the second adhesive layer 122 may both be a die attach film (DAF).

[0082] It should be noted that, before step S30 , a control chip 30 may be disposed on the substrate 20 .

[0083] In step S30 , a packaging material is formed on the substrate 20 to cover the first stacking part 11 , the second stacking part 12 and the control chip 30 .

[0084] In some embodiments, the encapsulation material may include an epoxy material.

[0085] The packaging material can be pressed and formed using a mold or other jig to form a packaging layer 40 covering the first stacking portion 11 and the second stacking portion 12; wherein, during the pressing process of the packaging material, the pressing force in different areas can be controlled to be different, so that the end of the second sub-portion 102 away from the first sub-portion 101 is bent toward the direction close to the first stacking portion 11, so that the protruding portion of the second stacking portion 12 relative to the side of the first stacking portion 11 is curved to form a stacking structure 10.

[0086] Next, a bending test fixture can be used to perform a bending test on the semiconductor device in the bending test area; for example, a pressure head can be used to squeeze the side of the substrate 20 away from the stacking structure 10 in the bending test area, so that the semiconductor device is bent under force to test the bending ability of the semiconductor device.

[0087] It should be noted that, during the process of pressing the packaging material, the pressure applied to bend the second sub-section 102 is much smaller than the pressure generated by the bending test fixture during the bending test.

[0088] As described above, in the embodiment of the present application, the second sub-portion 102 of the second stacking portion 12 is configured to be curved, so that the curved structure of the second sub-portion 102 can form an avoidance in space, thereby improving the bending resistance of the semiconductor device.

[0089] In addition, an embodiment of the present application also provides an electronic device, which includes the semiconductor device described in the above embodiment. Specifically, the electronic device can be a mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted device, wearable device, mobile power supply, and any other device that can store data.

[0090] Some embodiments of the present application provide an electronic device, which has the same beneficial effects as the above-mentioned semiconductor device due to the provision of the semiconductor device provided by some embodiments of the present application.

[0091] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0092] The semiconductor device and its manufacturing method, and the electronic device provided by the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: A stacking structure, comprising a first stacking portion, and a second stacking portion arranged on the first stacking portion, wherein the second stacking portion comprises a first sub-portion arranged overlapping with the first stacking portion, and a second sub-portion connected to the first sub-portion and protruding from a side surface of the first stacking portion; One end of the second sub-section is connected to the first sub-section, and the other end is bent toward a direction close to the first stacking section.

2. The semiconductor device according to claim 1, wherein: The semiconductor device includes a first region and a second region surrounding the first region, the first stacking portion is disposed in the second region, and the second sub-portion is located at a side of the first sub-portion close to the first region.

3. The semiconductor device according to claim 2, characterized in that The first area is a bending test area, which is used for performing a bending test.

4. The semiconductor device according to claim 2, characterized in that The second subsection extends into the first region.

5. The semiconductor device according to claim 2, wherein: The stacked structure is located outside the first area.

6. The semiconductor device according to claim 1, wherein: The thickness of the second stack portion is greater than or equal to 40 micrometers and less than or equal to 70 micrometers.

7. The semiconductor device according to claim 1, wherein: The thickness of the second stacking portion is smaller than the thickness of the first stacking portion; Wherein, the second stacking part includes a storage array and / or a peripheral circuit.

8. The semiconductor device according to claim 7, characterized in that The semiconductor device further includes a substrate, the stacking structure is disposed on the substrate, and the second stacking portion is electrically connected to the substrate.

9. The semiconductor device according to claim 8, characterized in that The stacking structure includes a plurality of second stacking parts stacked on the first stacking part, and the plurality of second stacking parts includes a top second stacking part; Wherein, in the top second stacking portion, one end of the second sub-portion away from the first sub-portion is bent toward a direction close to the substrate and contacts the substrate.

10. The semiconductor device according to claim 8, characterized in that The semiconductor device further comprises a control chip disposed on the substrate, the control chip being coupled to the stack structure and used for controlling the stack structure to store data; The second sub-portion of the second stacking portion is located at a side of the first sub-portion close to the control chip.

11. The semiconductor device according to claim 10, characterized in that The semiconductor device further comprises a packaging layer, which is arranged on the substrate and covers the stacking structure and the control chip.

12. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: forming a first stacking portion; forming a second stacking portion on the first stacking portion, wherein the second stacking portion includes a first sub-portion overlapping with the first stacking portion, and a second sub-portion connected to the first sub-portion and protruding from a side surface of the first stacking portion; An end of the second sub-portion away from the first sub-portion is bent toward a direction close to the first stacking portion to form a stacking structure.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that: The step of bending the end of the second sub-section away from the first sub-section toward the direction close to the first stacking section comprises: forming a packaging material covering the first stacking part and the second stacking part; The packaging material is pressed and formed so that an end of the second sub-portion away from the first sub-portion is bent toward a direction close to the first stacking portion.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: After the step of bending the end of the second sub-section away from the first sub-section toward the direction close to the first stacking section, the step further includes: A bending test area is formed in the semiconductor device, the second sub-portion is formed on a side of the first sub-portion close to the bending test area, and a bending test is performed on the semiconductor device in the bending test area.

15. An electronic device, characterized in that: The electronic device includes the semiconductor device according to any one of claims 1 to 11.

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