Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include: a first gate structure including first gate lines, each of the first gate lines being exposed by a first step structure extending in a first direction; second gate structures disposed on the first gate structures to expose the first step structures, and including second gate lines, each of the second gate lines being exposed by a second step structure extending in the first direction; a channel structure extending through the first gate structure and the second gate structure, the channel structure having a first width; a first support extending through the first stepped structure, the first support having a second width greater than the first width; and a second support extending through the second step structure and the first gate structure, the second support having a third width greater than the first width.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a semiconductor device in which a memory cell is formed as a single layer on a substrate has reached a limit, a three-dimensional semiconductor device in which memory cells are stacked on a substrate is being proposed. In addition, various structures and manufacturing methods are being developed in order to improve the operational reliability of the semiconductor device. Summary of the invention

[0003] According to an embodiment of the present disclosure, a semiconductor device may include: a first gate structure, which includes a first gate line, each of which is exposed through a first step structure extending in a first direction; a second gate structure, which is arranged on the first gate structure to expose the first step structure, and includes a second gate line, each of which is exposed through the second step structure extending in the first direction; a channel structure, which extends through the first gate structure and the second gate structure, and the channel structure has a first width; a first support, which extends through the first step structure, and the first support has a second width greater than the first width; and a second support, which extends through the second step structure and the first gate structure, and the second support has a third width greater than the first width.

[0004] According to an embodiment of the present disclosure, a semiconductor device may include: a first gate structure, which includes a first gate line, each of which is exposed through a first step structure extending in a first direction; a second gate structure, which is arranged on the first gate structure to expose the first step structure, and which includes a second gate line, each of which is exposed through the second step structure extending in the first direction; an etch stop layer, which is located between the first gate structure and the second gate structure to expose the first step structure; a channel structure, which extends through the first gate structure, the etch stop layer and the second gate structure, and includes a stepped sidewall; a first support, which extends through the first step structure and includes a non-stepped sidewall; and a second support, which extends through the second step structure, the etch stop layer and the first gate structure.

[0005] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a first stack including a first unit region and a first contact region; forming an etch stop layer on the first stack; forming a second stack including a second unit region and a second contact region on the etch stop layer; forming a groove extending through the second stack and the etch stop layer and partially exposing the first contact region; and forming a first step structure located in the first stack and a second step structure located in the second stack by composing the first contact region and the second contact region in a step shape.

[0006] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a first stack including a first material layer; forming an etch stop layer on the first stack; forming a second stack including a second material layer on the etch stop layer; exposing the etch stop layer by etching the second stack; exposing the first stack by etching the etch stop layer; forming a first step structure exposing each first material layer and a second step structure exposing each second material layer and the etch stop layer by composing the first stack and the second stack in a step shape; replacing the first material layer, the etch stop layer and the second material layer with a third material layer; and forming contact plugs respectively connected to the third material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1C is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] FIG. 2A to FIG. 2C is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] FIG. 3A to FIG. 3C is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] FIG. 4A to FIG. 10A , FIG. 4B to FIG. 10B and FIG. 6C to FIG. 10C 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0011] FIG. 11A to FIG. 16A , FIG. 11B to FIG. 16B and FIG. 11C to FIG. 16C 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0013] The integration degree of a semiconductor device can be improved by three-dimensionally stacking memory cells. In addition, a semiconductor device having a stable structure and improved reliability can be provided.

[0014] Hereinafter, embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings.

[0015] Figures 1A to 1C is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 1A It is a floor plan. Figure 1B It is along Figure 1A A cross-sectional view taken along line A-A', Figure 1C It is along Figure 1A A cross-sectional view taken along line BB'.

[0016] Reference Figures 1A to 1C The semiconductor device may include a first gate structure GST1, a second gate structure GST2, a channel structure CH, a first supporter SP1, and a second supporter SP2. The semiconductor device may also include at least one of an insulating layer 18, a first contact plug CT1, and a second contact plug CT2.

[0017] The first gate structure GST1 may include a first gate line 11. The first gate structure GST1 may include the first gate lines 11 and the first insulating layer 13 which are alternately stacked. The first gate line 11 may be a selection line or a word line, and may include a conductive material such as polysilicon or a metal. The first insulating layer 13 may insulate the stacked first gate lines 11 from each other, and may include an insulating material such as an oxide, a nitride, an air gap, or a void.

[0018] The first gate structure GST1 may include a first cell region CR1 and a first contact region CTR1. The first cell region CR1 and the first contact region CTR1 may be adjacent to each other in the first direction I. The first gate structure GST1 may include a first step structure SS1 located in the first contact region CTR1. The first step structure SS1 may have a step shape extending in the first direction I, and each of the first gate lines 11 may be exposed through the first step structure SS1.

[0019] The second gate structure GST2 may be located on the first gate structure GST1 and may expose the first step structure SS1. The second gate structure GST may include a second gate line 12. The second gate structure GST2 may include the second gate lines 12 and a second insulating layer 14 alternately stacked. The second gate lines 12 may be selection lines or word lines and may include a conductive material such as polysilicon or metal. The second insulating layer 14 may insulate the stacked second gate lines 12 from each other and may include an insulating material such as oxide, nitride, air gap, or void.

[0020] The second gate structure GST2 may include a second cell region CR2 and a second contact region CTR2. The second cell region CR2 and the second contact region CTR2 may be adjacent to each other in the first direction I. The first cell region CR1 and the second cell region CR2 may overlap in a stacking direction, and the first contact region CTR1 and the second contact region CTR2 may overlap in the stacking direction.

[0021] The second gate structure GST2 may include a second step structure SS2 located in the second contact region CTR2. The second step structure SS2 may have a step shape extending in the first direction I, and each second gate line 12 may be exposed through the second step structure SS2. The first step structure SS1 and the second step structure SS2 may be adjacent to each other in the second direction II, and may be aligned with each other in the second direction II. Here, the second direction II may be a direction intersecting the first direction I. The insulating layer 18 may be located on the second gate structure GST2. The insulating layer 18 may cover the first step structure SS1 and the second step structure SS2.

[0022] The channel structure CH may extend through the first gate structure GST1 and the second gate structure GST2. The channel structure CH may extend through the first cell region CR1 of the first gate structure GST1 and the second cell region CR2 of the second gate structure GST2. The channel structure CH may include a channel layer 15, a memory layer 16, and an insulating core 17, or may include a combination thereof. The memory layer 16 may include at least one of a tunneling layer, a data storage layer, and a barrier layer, and the data storage layer may include a floating gate, polysilicon, a charge trapping material, a nitride, a variable resistance material, etc.

[0023] The first supporter SP1 may extend through the first stepped structure SS1. The first supporter SP1 may pass through the insulating layer 18 and extend into the first stepped structure SS1. The second supporter SP2 may extend through the second stepped structure SS2 and the first gate structure GST1. The second supporter SP2 may pass through the insulating layer 18 and extend into the second stepped structure SS2.

[0024] The first supporter SP1 and the second supporter SP2 may have a shape similar to that of the channel structure CH. In an embodiment, the first supporter SP1 may include a first dummy channel layer 15A, a first dummy memory layer 16A, and a first dummy insulating core 17A, or may include a combination thereof. The second supporter SP2 may include a second dummy channel layer 15B, a second dummy memory layer 16B, and a second dummy insulating core 17B, or may include a combination thereof.

[0025] The sidewall shapes of the first support SP1, the second support SP2, and the channel structure CH may be similar or different from each other. In an embodiment, the channel structure CH may be formed in an opening formed by a plurality of etching processes and may include a stepped sidewall. The stepped sidewall may include a step difference S between the first gate structure GST1 and the second gate structure GST2. The first support SP1 and the second support SP2 may be formed in an opening formed by one etching process and may include a non-stepped sidewall.

[0026] The first supporter SP1, the second supporter SP2 and the channel structure CH may have substantially the same width or different widths. The channel structure CH may have a first width W11, the first supporter SP1 may have a second width W12 greater than the first width W11, and the second supporter SP2 may have a third width W13 greater than the first width W11. In an embodiment, the second width W12 and the third width W13 may be greater than the first width W11, and the second width W12 and the third width W13 may be substantially the same. The width may be the width of the upper surface, the width of the lower surface, or the average width of the corresponding structure. The upper surface may be the top surface. The lower surface may be the bottom surface. In an embodiment, the width of the upper surface of the first supporter SP1 may be greater than the width of the upper surface of the channel structure CH, and the width of the upper surface of the second supporter SP2 may be greater than the width of the upper surface of the channel structure CH. In the illustrated embodiment, the cross-sections of the channel structure CH, the first supporter SP1, and the second supporter SP2 may have a circular shape, and the width refers to the diameter of the cross-section. In other embodiments (not shown), the cross-sections of the channel structure CH, the first supporter SP1, and the second supporter SP2 may have a square shape, and the width may refer to a diagonal line of the square.

[0027] The first contact plugs CT1 may be located between the first supporters SP1 and may be respectively connected to the first gate lines 11. The second contact plugs CT2 may be located between the second supporters SP2 and may be respectively connected to the second gate lines 12. Each of the first contact plugs CT1 may be centered between four adjacent first supporters SP1 located at the vertices of the square. Each of the second contact plugs CT2 may be centered between four adjacent second supporters SP2 located at the vertices of the square.

[0028] According to the above structure, the first step structure SS1 and the second step structure SS2 of the first gate structure GST1 may be adjacent to each other in the second direction II. The first step structure SS1 and the second step structure SS2 of the first gate structure GST1 may contact each other. The first step structure SS1 and the second step structure SS2 may be formed by the same patterning process. The first step included in the first step structure SS1 and the second step included in the second step structure SS2 may be aligned in the second direction II. Therefore, the first step structure SS1 and the second step structure SS2 may be effectively set, and the manufacturing process of the semiconductor device may be improved.

[0029] FIG. 2A to FIG. 2C is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2A It is a floor plan. Figure 2B It is along Figure 2A A cross-sectional view taken along line A-A', Figure 2C It is along Figure 2A The following is a cross-sectional view taken along the line BB' of FIG.

[0030] Reference FIG. 2A to FIG. 2C The semiconductor device may include a first gate structure GST1, a second gate structure GST2, a channel structure CH, a first supporter SP1, and a second supporter SP2. The semiconductor device may also include at least one of an insulating layer 28, a third supporter SP3, a first contact plug CT1, and a second contact plug CT2.

[0031] The first gate structure GST1 may include alternately stacked first gate lines 21 and first insulating layers 23. The first gate structure GST1 may include a first stepped structure SS1. The second gate structure GST2 may include alternately stacked second gate lines 22 and second insulating layers 24. The second gate structure GST2 may include a second stepped structure SS2.

[0032] The channel structure CH may extend through the first gate structure GST1 and the second gate structure GST2. The channel structure CH may include a channel layer 25, a memory layer 26, and an insulating core 27, or may include a combination thereof. The first support SP1 may extend through the first step structure SS1. The first support SP1 may include a first dummy channel layer 25A, a first dummy memory layer 26A, and a first dummy insulating core 27A, or may include a combination thereof. The second support SP2 may extend through the second step structure SS2 and the first gate structure GST1. The second support SP2 may include a second dummy channel layer 25B, a second dummy memory layer 26B, and a second dummy insulating core 27B, or may include a combination thereof.

[0033] The third supporter SP3 may be located in the cell region CR1 / CR2 or in the contact region CTR1 / CTR2. The third supporter SP3 may be located between the channel structure CH and the first supporter SP1, or may be located between the channel structure CH and the second supporter SP2. The third supporter SP3 may extend through the second gate structure GST2 and the first gate structure GST1. The third supporter SP3 may have a shape similar to that of the channel structure CH. In an embodiment, the third supporter SP3 may include a third dummy channel layer 25C, a third dummy memory layer 26C, and a third dummy insulating core 27C, or may include a combination thereof.

[0034] The sidewall shapes of the first supporter SP1, the second supporter SP2, and the third supporter SP3 may be similar or different from each other. At least one of the first supporter SP1, the second supporter SP2, and the third supporter SP3 may include a stepped sidewall. In an embodiment, the second supporter SP2 and the third supporter SP3 may include a stepped sidewall, and the first supporter SP1 may include a non-stepped sidewall.

[0035] The first supporter SP1, the second supporter SP2, and the third supporter SP3 may have substantially the same width or different widths. The channel structure CH may have a first width W21. The second supporter SP2 may have a third width W23 greater than the first width W21. The first supporter SP1 may have a second width W22 greater than the first width W21 and the third width W23. The third supporter SP3 may have a fourth width W24 greater than the first width W21 and less than the second width W22. The fourth width W24 may be substantially the same as the third width W23.

[0036] The first contact plug CT1 may be located between the first supporters SP1 or between the first supporter SP1 and the third supporter SP3. The second contact plug CT2 may be located between the second supporters SP2 or between the second supporter SP2 and the third supporter SP3.

[0037] According to the structure as described above, the first stepped structure SS1 and the second stepped structure SS2 may be effectively provided, and the manufacturing process of the semiconductor device may be improved.

[0038] FIG. 3A to FIG. 3C is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 3A It is a floor plan. Figure 3B It is along Figure 3A A cross-sectional view taken along line A-A', Figure 3C It is along Figure 3A The following is a cross-sectional view taken along the line BB' of FIG.

[0039] Reference FIG. 3A to FIG. 3C The semiconductor device may include a first gate structure GST1, a second gate structure GST2, a channel structure CH, a first supporter SP1 and a second supporter SP2. The semiconductor device may also include at least one of an insulating layer 38, a first contact plug CT1, a second contact plug CT2 and an etching stop layer 39.

[0040] The first gate structure GST1 may include alternately stacked first gate lines 31 and first insulating layers 33. The first gate structure GST1 may include a first stepped structure SS1. The second gate structure GST2 may include alternately stacked second gate lines 32 and second insulating layers 34. The second gate structure GST2 may include a second stepped structure SS2.

[0041] The etch stop layer 39 may be located between the first gate structure GST1 and the second gate structure GST2. When etching the stack in the manufacturing process, the etch stop layer 39 may be used as an etching barrier. The etch stop layer 39 may include a material having an etching selectivity relative to the stack. In an embodiment, the etch stop layer 39 may include aluminum oxide (Al2O3), polysilicon, etc.

[0042] The channel structure CH may extend through the first gate structure GST1, the etch stop layer 39, and the second gate structure GST2. The channel structure CH may include a channel layer 35, a memory layer 36, and an insulating core 37, or may include a combination thereof. The first support SP1 may extend through the first step structure SS1. The second support SP2 may extend through the second step structure SS2, the etch stop layer 39, and the first gate structure GST1. The first support SP1, the second support SP2, and the channel structure CH may have substantially the same width or different widths.

[0043] For reference, during the manufacturing process, the etching stop layer 39 may be replaced with the third gate line 39A, and the third gate line 39A may be included in the first gate structure GST1. The third gate line 39A may include the same material as the first gate line 31 and the second gate line 32, or may include a material different from the materials of the first gate line 31 and the second gate line 32. In an embodiment, the first gate line 31, the second gate line 32, and the third gate line 39A may include a metal such as tungsten (W) or molybdenum (Mo). In an embodiment, the first gate line 31 and the second gate line 32 may include polysilicon, and the third gate line 39A may include a metal such as tungsten (W) or molybdenum (Mo). At least one of the second contact plugs CT2 may be electrically connected to the third gate line 39A.

[0044] As mentioned above Figures 1A to 1C and FIG. 2A to FIG. 2CAs described, the semiconductor device may further include a third supporter SP3. The sidewall shapes of the first supporter SP1, the second supporter SP2, and the third supporter SP3 may be similar to or different from each other. The first supporter SP1, the second supporter SP2, and the third supporter SP3 may have substantially the same width or different widths.

[0045] The first contact plug CT1 may be located between the first supporters SP1 or between the first supporter SP1 and the third supporter SP3. The second contact plug CT2 may be located between the second supporters SP2 or between the second supporter SP2 and the third supporter SP3.

[0046] According to the structure as described above, the first stepped structure SS1 and the second stepped structure SS2 may be effectively provided, and the manufacturing process of the semiconductor device may be improved.

[0047] FIG. 4A to FIG. 10A , FIG. 4B to FIG. 10B and FIG. 6C to FIG. 10C 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 4A to FIG. 10A The graphs in are planar graphs. FIG. 4B to FIG. 10B The figures in FIG. 4A to FIG. 10A The C-C' cross-sectional view of the corresponding figure in, FIG. 6C to FIG. 10C The figures in FIG. 6A to FIG. 10A The D-D' cross-sectional view of the corresponding figure in FIG. The following content that is repeated with the above content is omitted.

[0048] Reference Figure 4A and Figure 4B , a first stack ST1 including a first cell region CR1 and a first contact region CTR1 may be formed. The first cell region CR1 may be a region where stacked memory cells are formed. The first contact region CTR1 may be a region where an interconnection structure for applying a bias to each stacked gate line is formed. The interconnection structure may include a contact plug, a line, etc.

[0049] The first stack ST1 may include a first material layer 41. In an embodiment, the first stack ST1 may include first material layers 41 and first insulating layers 42 that are alternately stacked. The first material layer 41 may be used to form a gate line such as a selection line or a word line. The first material layer 41 may include a sacrificial material such as a nitride, or may include a conductive material such as polysilicon or tungsten. The first insulating layer 42 may insulate the stacked gate lines from each other. The first insulating layer 42 may include an insulating material such as an oxide, a nitride, an air gap, or a void.

[0050] Subsequently, an etch stop layer 43 may be formed on the first stack ST1. The etch stop layer 43 may control the etching depth when etching the second stack in a subsequent process. The etch stop layer 43 may include a material having a large etching selectivity relative to the second stack. In an embodiment, the etch stop layer 43 may include at least one of aluminum oxide (Al2O3) and polysilicon. Subsequently, an insulating layer 44 may be formed on the etch stop layer 43. For reference, the etch stop layer 43 and the insulating layer 44 may be alternately stacked.

[0051] Reference Figure 5A and Figure 5B , a first mask pattern 45 may be formed on the etch stop layer 43. The first mask pattern 45 may include an opening located in the first cell region CR1. Subsequently, the insulating layer 44, the etch stop layer 43, and the first stack ST1 may be etched using the first mask pattern 45 as an etching barrier to form a first sub-channel hole SCH1. The first sub-channel hole SCH1 may be located in the first cell region CR1.

[0052] Reference FIG. 6A to FIG. 6C , a sacrificial layer 46 may be formed in the first sub-channel hole SCH1 . The sacrificial layer 46 may include a material having a large etching selectivity with respect to the first material layer 41 and the first insulating layer 42 .

[0053] Subsequently, a second stack ST2 including a second cell region CR2 and a second contact region CTR2 may be formed on the etch stop layer 43 and the insulating layer 44. The second stack ST2 may include a second material layer 47. In an embodiment, the second stack ST2 may include second material layers 47 and second insulating layers 48 that are alternately stacked. The second material layer 47 may be used to form gate lines such as selection lines and word lines. The second material layer 47 may include a sacrificial material such as a nitride, or may include a conductive material such as polysilicon or tungsten. The second insulating layer 48 may insulate the stacked gate lines from each other. The second insulating layer 48 may include an insulating material such as an oxide, a nitride, an air gap, or a void.

[0054] Subsequently, a second mask pattern 49 may be formed on the second stack ST2. The second mask pattern 49 may be formed to partially expose the first contact region CTR1. The second mask pattern 49 may have a shape that covers the second cell region CR2 and partially exposes the second contact region CTR2. The second mask pattern 49 may expose a region of the first contact region CTR1 where a first step structure is to be formed, and may cover a region of the second contact region CTR2 where a second step structure is to be formed. The second mask pattern 49 may include a photoresist.

[0055] Subsequently, the second stack ST2 may be etched using the second mask pattern 49 as an etching barrier. At this time, the second stack ST2 may be etched to expose the etching stop layer 43. Since the etching depth is controlled using the etching stop layer 43, the first material layer 41 and the first insulating layer 42 may be alternately etched using the same etching recipe. Since the second stack ST2 is etched without changing the etching recipe, the occurrence of tilting of the etching surfaces of the first material layer 41 and the first insulating layer 42 may be improved.

[0056] Subsequently, the exposed etch stop layer 43 may be etched. In an embodiment, the etch stop layer 43 may be etched using the second mask pattern 49 as an etching barrier. In an embodiment, after removing the second mask pattern 49, the etch stop layer 43 may be etched by a wet etching method using phosphoric acid or the like. Thus, a trench T extending through the second stack ST2 and the etch stop layer 43 and partially exposing the first contact region CTR1 may be formed. The sidewall of the trench T may have a vertical profile, and may expose a region of the first contact region CTR1 where a first step structure is to be formed.

[0057] Reference 7A to 7C The first step structure SS1 in the first stack ST1 and the second step structure SS2 in the second stack ST2 may be formed by patterning the first contact region CTR1 and the second contact region CTR2 in a step shape, respectively.

[0058] Each of the first material layers 41 may be exposed through the first step structure SS1. Each of the second material layers 47 and the etching stop layer 43 may be exposed through the second step structure SS2. The first step structure SS1 and the second step structure SS2 may extend in the first direction I and may be adjacent to each other in the second direction II. The first step structure SS1 and the second step structure SS2 may contact each other. The first step S1 included in the first step structure SS1 and the second step S2 included in the second step structure SS2 may be aligned in the second direction II.

[0059] The first step structure SS1 and the second step structure SS2 may be formed using the same mask pattern. In an embodiment, a third mask pattern 51 may be formed on the second stack ST2. The third mask pattern 51 may cover the second cell region CR2 and expose a portion of the second contact region CTR2 and a portion of the first contact region CTR1. Subsequently, the first contact region CTR1 and the second contact region CTR2 may be etched using the third mask pattern 51 as an etching barrier. Subsequently, the third mask pattern 51 may be reduced in the first direction I, and the first contact region CTR1 and the second contact region CTR2 may be etched using the reduced third mask pattern 51 as an etching barrier. The first contact region CTR1 and the second contact region CTR2 may be patterned in a step shape extending in the first direction I by repeatedly performing the reduction and etching process of the third mask pattern 51. Thus, the first step structure SS1 and the second step structure SS2 having the same shape may be formed in the first contact region CTR1 and the second contact region CTR2, respectively.

[0060] Reference FIG. 8A to FIG. 8C , an insulating layer 52 may be formed on the second stack. The insulating layer 52 may cover the first stepped structure SS1 and the second stepped structure SS2. Subsequently, a fourth mask pattern 53 may be formed on the second stack ST2 and the insulating layer 52. Subsequently, the insulating layer 52 and the second stack ST2 may be etched using the fourth mask pattern 53 as an etching barrier to form a second sub-channel hole SCH2 connected to the corresponding first sub-channel hole SCH1.

[0061] The second sub-channel hole SCH2 may be located in the second cell region CR2 of the second stack ST2. The second sub-channel hole SCH2 may extend through the second stack ST2 and expose the sacrificial layer 46. The second sub-channel hole SCH2 may have a first depth D1 and a first width W41. Thus, channel holes CHH each including a first sub-channel hole SCH1 and a corresponding second sub-channel hole SCH2 may be formed. The bottom width of the first sub-channel hole SCH1 and the top width of the second sub-channel hole SCH2 may be different from each other, and therefore, due to the width difference, the sidewall of the channel hole CHH may include a step difference S. The step difference S may be located between the first stack ST1 and the second stack ST2.

[0062] The insulating layer 52 and the second stack ST2 may be etched using the fourth mask pattern 53 as an etching barrier to form a first opening OP1 extending through the first stepped structure SS1. The first opening OP1 may pass through the insulating layer 52 and extend into the first stepped structure SS1. The first opening OP1 may have a second depth D2 and a second width W42. The second depth D2 may be greater than the first depth D1, and the second width W42 may be greater than the first width W41.

[0063] The second stack ST2 may be etched using the fourth mask pattern 53 as an etching barrier to form a second opening OP2 extending through the second step structure SS2. The second opening OP2 may pass through the insulating layer 52, the second step structure SS2, and the etching stop layer 43 and extend into the first stack ST1. The second opening OP2 may be adjacent to the first opening OP1 in the second direction II. The second opening OP2 may have a third depth D3 and a third width W43. The third depth D3 may be greater than the first depth D1, and the third width W43 may be greater than the first width W41. The second depth D2 and the third depth D3 may be substantially the same. The second width W42 and the third width S43 may be substantially the same.

[0064] The first opening OP1 may be formed when the second sub-channel hole SCH2 is formed, or may be formed in a separate process. The second opening OP2 may be formed when the second sub-channel hole SCH2 is formed, or may be formed in a separate process. In an embodiment, the second sub-channel hole SCH2, the first opening OP1, and the second opening OP2 may be formed using a fourth mask pattern 53. When the second sub-channel hole SCH2 is formed, the first opening OP1 and the second opening OP2 may be formed.

[0065] The first opening OP1 and the second opening OP2 may be formed to have a width greater than that of the second sub-channel hole SCH2. In this case, the etching amount of the first opening OP1 and the second opening OP2 may be greater than that of the second sub-channel hole SCH2 by a loading effect. Therefore, the first opening OP1 and the second opening OP2 may be formed to have a depth greater than that of the second sub-channel hole SCH2. The first opening OP1 and the second opening OP2 may be formed in a single etching process and may not include a step difference on the sidewall.

[0066] Reference 9A to 9C , the first sub-channel hole SCH1 may be reopened by removing the sacrificial layer 46. Subsequently, a channel structure CH may be formed in the channel hole CHH. According to the illustrated embodiment, the channel structure CH may include a channel layer 55, a memory layer 56, and an insulating core 57. However, in other embodiments (not shown), the channel structure CH may include at least one of the channel layer 55, the memory layer 56, and the insulating core 57. The sidewall of the channel structure CH may include a step difference S transferred from the channel hole CHH.

[0067] A first support SP1 may be formed in the first opening OP1. In the illustrated embodiment, the first support SP1 may include a first dummy channel layer 55A, a first dummy memory layer 56A, and a first dummy insulating core 57A. However, in other embodiments (not shown), the first support SP1 may include at least one of the first dummy channel layer 55A, the first dummy memory layer 56A, and the first dummy insulating core 57A. The sidewall of the first support SP1 may have a shape transferred from the first opening OP1. The sidewall of the first support SP1 may not include a step change in its width and may be referred to as a non-step sidewall. The width of the first support SP1 may be greater than the width of the channel structure CH.

[0068] A second supporter SP2 may be included in the second opening OP2. The second supporter SP2 may include at least one of a second dummy channel layer 55B, a second dummy memory layer 56B, and a second dummy insulating core 57B. The sidewall of the second supporter SP2 may have a shape transferred from the second opening OP2. The sidewall of the second supporter SP2 may not have a step change in its width and may be referred to as a non-step sidewall. The width of the second supporter SP2 may be greater than the width of the channel structure CH.

[0069] The first supporter SP1 may be formed when the channel structure CH is formed, or may be formed in a separate process. The second supporter SP2 may be formed when the channel structure CH is formed, or may be formed in a separate process. In an embodiment, when the channel structure CH is formed, the first supporter SP1 and the second supporter SP2 may be formed. At least one of the first supporter SP1 and the second supporter SP2 may include a dummy channel layer.

[0070] Subsequently, an insulating layer 58 may be formed to cover the channel structure CH, the first supporter SP1, and the second supporter SP2. Subsequently, the first material layer 41 and the second material layer 47 may be replaced with a conductive layer. In an embodiment, a slit SL extending through the insulating layers 58 and 52, the second stack ST2, the etch stop layer 43, and the first stack ST1 may be formed. Subsequently, the first material layer 41 and the second material layer 47 may be replaced with a conductive layer through the slit SL. An opening may be formed by selectively etching the first material layer 41 and the second material layer 47 through the slit SL, and a conductive layer may be formed in the opening.

[0071] Thus, a first gate structure GST1 including alternately stacked first gate lines 41A and first insulating layers 42 may be formed. A second gate structure GST2 including alternately stacked second gate lines 47A and second insulating layers 48 may be formed. When the first material layer 41 and the second material layer 47 are replaced with a conductive layer, the etch stop layer 43 may remain or may be replaced by a gate line 43A. The gate line 43A may be included in the first gate structure GST1.

[0072] In a variation of the embodiment, when the first material layer 41 and the second material layer 47 include a conductive material, the above replacement process may be omitted. In this case, the first stack ST1 may be the first gate structure GST1, the second stack ST2 may be the second gate structure GST2, and the etch stop layer 43 may remain.

[0073] At least one of the first material layer 41, the second material layer 47, and the etch stop layer 43 may be replaced with a conductive layer. When the first material layer 41 and the second material layer 47 are replaced with a conductive layer, the etch stop layer 43 may be retained, or may be replaced by a gate line 43A. The gate line 43A may be included in the first gate structure GST1. In an embodiment, an opening may be formed by selectively etching the first material layer 41, the second material layer 47, and the etch stop layer 43, and a conductive layer may be formed in the opening. When the first material layer 41, the second material layer 47, and the etch stop layer 43 include nitride, the first material layer 41, the second material layer 47, and the etch stop layer 43 may be selectively etched in a leaching process using phosphoric acid. In an embodiment, when the etch stop layer 43 includes polysilicon, the etch stop layer 43 may be selectively etched using nitric acid or a dry cleaning process.

[0074] Subsequently, a slit structure SLS may be formed in the slit SL. The slit structure SLS may include at least one of an insulating material, a conductive material, and a semiconductor material. In an implementation, the slit structure SLS may include a source contact plug and an insulating spacer surrounding a sidewall of the source contact plug.

[0075] Reference FIG. 10A to FIG. 10C , a first contact plug CT1 and a second contact plug CT2 may be formed. The first contact plug CT1 may be located between the first supports SP1. The first contact plug CT1 may be centered between adjacent first supports SP1. In the illustrated embodiment, one first contact plug CT1 may be centered between four adjacent first supports SP1. Forming the first contact plug CT1 may include first forming an opening that exposes each first gate line 41A through the insulating layers 52 and 58, then a first barrier layer 61B may be formed in the opening, and after forming the first barrier layer 61B, a first metal layer 61A may be formed to fill the remaining gap formed by the first barrier layer 61B. The first contact plug CT1 may extend through the insulating layers 52 and 58, and may be electrically connected to a corresponding one of the first gate lines 41A.

[0076] The second contact plug CT2 may be located between the second supports SP2. The second contact plug CT2 may be centered between the second supports SP2. In the illustrated embodiment, one second contact plug CT2 may be centered between four adjacent second supports SP2. Forming the second contact plug CT2 may include first forming an opening that exposes each second gate line 47A through the insulating layers 52 and 58, then forming a second barrier layer 62B in the opening, and forming a second metal layer 62A after forming the second barrier layer 62B to fill the remaining gap formed by the second barrier layer 62B. The second contact plug CT2 may extend through the insulating layers 52 and 58 and may be electrically connected to the second gate line 47A. The first metal layer 61A and the second metal layer 62A may include a metal such as tungsten or molybdenum. The first barrier layer 61B and the second barrier layer 62B may include a metal nitride such as tungsten nitride, molybdenum nitride, titanium nitride, or tantalum nitride.

[0077] According to the manufacturing method as described above, after the first contact region CTR1 is exposed by forming the trench T, the first contact region CTR1 and the second contact region CTR2 may be patterned in a step shape. Therefore, when the second step structure SS2 is formed in the second contact region CTR2, the first step structure SS1 may be formed in the first contact region CTR1. The process cost may be reduced by simultaneously patterning the first stack ST1 and the second stack ST2 to simultaneously form the first step structure SS1 and the second step structure SS2 located at different heights.

[0078] Since the trench T is formed using the etch stop layer 43, the same recipe can be used to etch the second material layer 47 and the second insulating layer 48. Therefore, compared with the case where the second material layer 47 and the second insulating layer 48 are alternately etched while changing the recipe, the trench T can have a vertical profile, and the increase in the area of ​​the step structure caused by the inclination of the trench T can be improved.

[0079] FIG. 11A to FIG. 16A , FIG. 11B to FIG. 16B and FIG. 11C to FIG. 16C 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 11A to FIG. 16A The graphs in are planar graphs. FIG. 11B to FIG. 16B The figures in FIG. 11A to FIG. 16A The E-E' cross-sectional view of the corresponding figure in, FIG. 11C to FIG. 16C The figures in FIG. 11A to FIG. 16A The F-F' cross-sectional view of the corresponding figure in FIG. The following content that is repeated with the above content is omitted.

[0080] Reference Figure 1A and Fig. 11B, a first stack ST1 including the first cell region CR1 and the first contact region CTR1 may be formed. The first stack ST1 may include first material layers 71 and first insulating layers 72 that are alternately stacked. Subsequently, an etch stop layer 73 and an insulating layer 74 may be formed on the first stack ST1.

[0081] Subsequently, a first mask pattern 75 may be formed on the etch stop layer 73. Subsequently, the etch stop layer 73 and the first stack ST1 may be etched using the first mask pattern 75 as an etching barrier to form a first sub-channel hole SCH1 and a first sub-opening OP2A. The first sub-channel hole SCH1 may be located in the first cell region CR1, and the first sub-opening OP2A may be located in the first contact region CTR1. The first contact region CTR1 may include a region where a first stepped structure is to be formed and a remaining region, and the first sub-opening OP2A may be located in the remaining region.

[0082] The first sub-channel hole SCH1 and the first sub-opening OP2A may have substantially the same width or may have different widths. The first sub-channel hole SCH1 may have a first width W51, and the first sub-opening OP2A may have a third width W53 greater than the first width W51.

[0083] Reference FIG. 12A to FIG. 12C , a first sacrificial layer 76A may be formed in the first sub-channel hole SCH1. A second sacrificial layer 76B may be formed in the first sub-opening OP2A. When the first sacrificial layer 76A is formed, the second sacrificial layer 76B may be formed. The first sacrificial layer 76A and the second sacrificial layer 76B may include a material having a large etching selectivity with respect to the first material layer 71 and the first insulating layer 72.

[0084] Subsequently, a second stack ST2 including the second cell region CR2 and the second contact region CTR2 may be formed on the etch stop layer 73. The second stack ST2 may include second material layers 77 and second insulating layers 78 that are alternately stacked.

[0085] Subsequently, a second mask pattern 79 may be formed on the second stack ST2. The second mask pattern 79 may cover the second cell region CR2 and partially expose the second contact region CTR2. The second mask pattern 79 may expose a region of the first contact region CTR1 where a first stepped structure is to be formed, and may cover a region of the second contact region CTR2 where a second stepped structure is to be formed.

[0086] Subsequently, the second stack ST2 is etched using the second mask pattern 79 as an etching barrier to expose the etch stop layer 73, and the exposed etch stop layer 73 may be etched. Thus, a trench T extending through the second stack ST2 and the etch stop layer 73 and exposing a region of the first contact region CTR1 where the first stepped structure is to be formed may be formed.

[0087] Reference FIG. 13A to FIG. 13C , a third mask pattern 81 may be formed on the second stack ST2. The first step structure SS1 and the second step structure SS2 may be formed by repeatedly performing the reduction and etching process of the third mask pattern 81. Since the first sub-opening OP2A and the second sacrificial layer 76B are not formed in the region where the first step structure SS1 is to be formed, the first material layer 71 and the first insulating layer 72 may be etched to form the first step structure SS1. The second step structure SS2 may be formed on the first sub-opening OP2A and the second sacrificial layer 76B. The first step structure SS1 and the second step structure SS2 may extend in the first direction I and may be adjacent to each other in the second direction II. The first step structure SS1 and the second step structure SS2 may contact each other. The first step S1 included in the first step structure SS1 and the second step S2 included in the second step structure SS2 may be aligned in the second direction II.

[0088] Reference FIG. 14A to FIG. 14C , a fourth mask pattern 83 may be formed on the second stack ST2. The insulating layer 82 and the second stack ST2 may be etched using the fourth mask pattern 83 as an etching barrier to form a second sub-channel hole SCH2 connected to the first sub-channel hole SCH1. The second sub-channel hole SCH2 may be located in the second cell region CR2 of the second stack ST2. The second sub-channel hole SCH2 may have a first depth D1 and a first width W51. Thus, a channel hole CHH including the first sub-channel hole SCH1 and the second sub-channel hole SCH2 may be formed.

[0089] The fourth mask pattern 83 may be used as an etching barrier to etch the insulating layer 82 and the second stack ST2 to form a second sub-opening OP2B. The second sub-opening OP2B may extend through the second step structure SS2 and may be connected to the first sub-opening OP2A. The second sacrificial layer 76B may be exposed through the second sub-opening OP2B. The second opening OP2 may have a third depth D3 and a third width W53. The third depth D3 may be substantially the same as the first depth D1, and the third width W53 may be greater than the first width W51. Thus, a second opening OP2 including the first sub-opening OP2A and the second sub-opening OP2B may be formed.

[0090] The insulating layer 82 and the second stack ST2 may be etched using the fourth mask pattern 83 as an etching barrier to form a first opening OP1 extending through the first stepped structure SS1. The first opening OP1 may pass through the insulating layer 82 and extend into the first stepped structure SS1. The first opening OP1 may have a second depth D2 and a second width W52. The second depth D2 may be greater than the first depth D1 and the third depth D3, and the second width W52 may be greater than the first width W51 and the third width W53.

[0091] The second sub-channel hole SCH2, the first opening OP1, and the second sub-opening OP2B may be formed using the fourth mask pattern 83 as an etching barrier. When the second sub-opening OP2B and the second sub-channel hole SCH2 are formed, the first opening OP1 may be formed. The first opening OP1 may be formed to have a width greater than the widths of the second sub-channel hole SCH2 and the second sub-opening OP2B, and by a loading effect, the etching amount of the first opening OP1 may be greater than the etching amount of the second sub-channel hole SCH2 and the second sub-opening OP2B. Therefore, the first opening OP1 may be formed to have a depth greater than the depths of the second sub-channel hole SCH2 and the second sub-opening OP2B. Therefore, the first opening OP1 may be formed in a single etching process, and may not include a step difference on the sidewall.

[0092] Reference FIG. 15A to FIG. 15C , the first sub-channel hole SCH1 may be reopened by removing the first sacrificial layer 76A. Subsequently, a channel structure CH may be formed in the channel hole CHH. In the illustrated embodiment, the channel structure CH may include a channel layer 85, a memory layer 86, and an insulating core 87. However, in other embodiments, the channel structure CH may include at least one of the channel layer 85, the memory layer 86, and the insulating core 87. The sidewall of the channel structure CH may include a step difference S transferred from the channel hole CHH.

[0093] A first supporter SP1 may be formed in the first opening OP1. The first supporter SP1 may include a first dummy channel layer 85A, a first dummy memory layer 86A, and a first dummy insulating core 87A. In some embodiments (not shown), the first supporter SP1 may include at least one of the first dummy channel layer 85A, the first dummy memory layer 86A, and the first dummy insulating core 87A. The sidewall of the first supporter SP1 may have a shape transferred from the first opening OP1 and may include a non-step sidewall. The width of the first supporter SP1 may be greater than the width of the channel structure CH.

[0094] The first sub-opening OP2A may be reopened by removing the second sacrificial layer 76B. When the first sacrificial layer 76A is removed, the second sacrificial layer 76B may be removed. Subsequently, a second support SP2 may be formed in the second opening OP2. The second support SP2 may be adjacent to the first support SP1 in the second direction II. The second support SP2 may include a second dummy channel layer 85B, a second dummy memory layer 86B, and a second dummy insulating core 87B. In some embodiments, the second support SP2 may include at least one of the second dummy channel layer 85B, the second dummy memory layer 86B, and the second dummy insulating core 87B. The sidewall of the second support SP2 may have a shape transferred from the second opening OP2, and may include a step difference S on the sidewall. The width of the second support SP2 may be greater than the width of the channel structure CH, and may be less than the width of the first support SP1.

[0095] A third supporter SP3 may be formed in the second opening OP2. The third supporter SP3 may be located between the channel structure CH and the first supporter SP1, and may be adjacent to the first supporter SP1 in the first direction I. The third supporter SP3 may include at least one of a third dummy channel layer 85C, a third dummy memory layer 86C, and a third dummy insulating core 87C. A sidewall of the third supporter SP3 may have a shape transferred from the second opening OP2, and may include a step difference S on the sidewall. A width of the third supporter SP3 may be greater than a width of the channel structure CH, and may be less than a width of the first supporter SP1.

[0096] The first supporter SP1, the second supporter SP2, and the third supporter SP3 may be formed when the channel structure CH is formed, or may be formed in a separate process. In an embodiment, when the channel structure CH is formed, the first supporter SP1, the second supporter SP2, and the third supporter SP3 may be formed. At least one of the first supporter SP1, the second supporter SP2, and the third supporter SP3 may include a dummy channel layer.

[0097] Subsequently, an insulating layer 88 may be formed to cover the channel structure CH, the first support SP1, the second support SP2, and the third support SP3. Subsequently, the first material layer 71 and the second material layer 77 may be replaced with a conductive layer. Thus, a first gate structure GST1 including a first gate line 71A and a first insulating layer 72 stacked alternately may be formed. A second gate structure GST2 including a second gate line 77A and a second insulating layer 78 stacked alternately may be formed. When the first material layer 71 and the second material layer 77 are replaced with a conductive layer, the etch stop layer 73 may remain, or may be replaced by a gate line 73A. The gate line 73A may be included in the first gate structure GST1. For reference, when the first material layer 71 and the second material layer 77 include conductive materials, the replacement process may be omitted. In this case, the first stack ST1 may be the first gate structure GST1, the second stack ST2 may be the second gate structure GST2, and the etch stop layer 73 may remain.

[0098] Reference FIG. 16A to FIG. 16C , a first contact plug CT1 and a second contact plug CT2 may be formed. Each first contact plug CT1 may be located between adjacent first supports SP1, or may be located between adjacent first supports SP1 and adjacent third supports SP3. Each second contact plug CT2 may be located between adjacent second supports SP2. The first contact plug CT1 may include a first metal layer 91A and a first barrier layer 91B. The second contact plug CT2 may include a second metal layer 92A and a second barrier layer 92B.

[0099] According to the manufacturing method as described above, the second stack ST2 can be partially etched using the etching stop layer 73 to open the first contact region CTR1, thereby simultaneously forming the first stepped structure SS1 and the second stepped structure SS2 at different heights. The etching process can be improved by dividing the second opening OP2 into the first sub-opening OP2A and the second sub-opening OP2B and forming the second opening OP2.

[0100] Although the embodiments according to the technical concept of the present disclosure are described with reference to the accompanying drawings, these embodiments are only used to describe examples of the concept according to the present disclosure, and the present disclosure is not limited to the above embodiments. Within the scope of the technical concept of the present disclosure, without departing from the scope of the present disclosure defined in the attached claims, a person skilled in the art to which the present disclosure belongs will be able to make various substitutions, modifications and changes to the embodiments. In addition, these embodiments can be combined to form additional embodiments.

[0101] CROSS-REFERENCE TO RELATED APPLICATIONS

[0102] This application claims priority to Korean Patent Application No. 10-2023-0094529, filed on Jul. 20, 2023, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: A first gate structure including first gate lines, each of which is exposed through a first step structure extending in a first direction; a second gate structure, the second gate structure being disposed on the first gate structure to expose the first stepped structure, and the second gate structure comprising second gate lines, each of the second gate lines being exposed through the second stepped structure extending in the first direction; a channel structure extending through the first gate structure and the second gate structure, the channel structure having a first width; a first support extending through the first step structure, the first support having a second width greater than the first width; as well as A second supporter extends through the second stepped structure and the first gate structure, and has a third width greater than the first width.

2. The semiconductor device according to claim 1, wherein The first width is a width of a top surface of the channel structure, the second width is a width of a top surface of the first supporter, and the third width is a width of a top surface of the second supporter.

3. The semiconductor device according to claim 1, wherein The first stepped structure and the second stepped structure are adjacent to each other in a second direction crossing the first direction.

4. The semiconductor device according to claim 1, wherein The first stepped structure and the second stepped structure are aligned in a second direction.

5. The semiconductor device according to claim 1, further comprising: first contact plugs, the first contact plugs being respectively located between the first supports and connected to the first gate lines; as well as Second contact plugs are respectively located between the second supporters and connected to the second gate lines.

6. The semiconductor device according to claim 1, wherein The channel structure includes a stepped sidewall, and the first supporter and the second supporter include a non-stepped sidewall.

7. The semiconductor device according to claim 6, wherein: The stepped sidewall of the channel structure includes a step difference between the first gate structure and the second gate structure.

8. The semiconductor device according to claim 1, wherein The channel structure and the second supporter include stepped sidewalls, and the first supporter includes non-stepped sidewalls.

9. The semiconductor device according to claim 1, wherein: The second width is greater than the third width.

10. The semiconductor device according to claim 1, further comprising: A third supporter is located between the channel structure and the first supporter, the third supporter extends through the second gate structure and the first gate structure, and has a fourth width greater than the first width and less than the second width.

11. The semiconductor device according to claim 1, wherein At least one of the first supporter and the second supporter includes a dummy channel layer.

12. A semiconductor device, comprising: A first gate structure including first gate lines, each of which is exposed through a first step structure extending in a first direction; a second gate structure, the second gate structure being disposed on the first gate structure to expose the first stepped structure, and the second gate structure comprising second gate lines, each of the second gate lines being exposed through the second stepped structure extending in the first direction; an etch stop layer, the etch stop layer being located between the first gate structure and the second gate structure to expose the first step structure; a channel structure extending through the first gate structure, the etch stop layer, and the second gate structure and comprising a stepped sidewall; a first support extending through the first step structure and including a non-stepped sidewall; as well as A second supporter extends through the second stepped structure, the etch stop layer, and the first gate structure.

13. The semiconductor device according to claim 12, wherein: The first stepped structure and the second stepped structure are aligned in a second direction crossing the first direction.

14. The semiconductor device according to claim 12, wherein: The channel structure has a first width, the first supporter has a second width greater than the first width, and the second supporter has a third width greater than the first width.

15. The semiconductor device according to claim 14, wherein: The first width is a width of a top surface of the channel structure, the second width is a width of a top surface of the first supporter, and the third width is a width of a top surface of the second supporter.

16. The semiconductor device according to claim 14, wherein: The second width is greater than the third width.

17. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first stack including a first cell region and a first contact region; forming an etch stop layer on the first stack; forming a second stack including a second cell region and a second contact region on the etch stop layer; forming a trench extending through the second stack and the etch stop layer and partially exposing the first contact region; as well as A first step structure in the first stack and a second step structure in the second stack are formed by patterning the first contact region and the second contact region in a step shape.

18. The method according to claim 17, wherein: The step of forming the groove comprises the following steps: forming a mask pattern on the second stack; etching the second stack using the mask pattern as an etch barrier to expose the etch stop layer; and The etch stop layer is etched to expose the first contact region.

19. The method according to claim 18, wherein: The second stack includes second material layers and second insulating layers that are alternately stacked, and When the second stack is etched, the second material layer and the second insulating layer are etched using the same recipe.

20. The method according to claim 17, wherein: The step of forming the first step structure and the second step structure comprises the following steps: forming a mask pattern exposing a portion of the first contact region and a portion of the second contact region; and The first contact region and the second contact region are patterned in a step shape extending in a first direction using the mask pattern.

21. The method according to claim 20, wherein: The step of patterning the first and second contact regions in the step shape includes repeatedly performing reduction of the mask pattern and an etching process using the reduced mask pattern.

22. The method according to claim 17, wherein: The first stepped structure and the second stepped structure extend in a first direction and are adjacent to each other in a second direction crossing the first direction.

23. The method according to claim 22, wherein: A first step included in the first step structure and a second step included in the second step structure are aligned in the second direction.

24. The method according to claim 17, further comprising the steps of: forming a first opening extending through the first step structure; as well as A second opening is formed extending through the second step structure and the first stack.

25. The method according to claim 24, further comprising the steps of: forming a first sub-channel hole extending through the etch stop layer and the first cell region of the first stack; as well as A second sub-channel hole is formed, the second sub-channel hole extending through the second unit region of the second stack and connected to the first sub-channel hole.

26. The method according to claim 25, wherein: When forming the second sub-channel hole, a first opening and a second opening are formed.

27. The method according to claim 25, wherein: A width of the first opening and a width of the second opening are greater than a width of the second sub-channel hole.

28. The method according to claim 24, further comprising the steps of: forming a first support including a first dummy channel layer in the first opening; and A second supporter including a second dummy channel layer is formed in the second opening.

29. The method according to claim 17, further comprising the steps of: forming a first sub-opening in the first contact region of the first stack; forming a second sub-opening extending through the second step structure and connected to the first sub-opening; as well as A first opening is formed extending through the first step structure.

30. The method of claim 29, wherein: When the second sub-opening is formed, the first opening is formed.

31. The method of claim 29, wherein: The width of the first opening is greater than the width of the second sub-opening.

32. The method according to claim 29, further comprising the steps of: forming a first support including a first dummy channel layer in the first opening; as well as A second supporter including a second dummy channel layer is formed in the first sub-opening and the second sub-opening.

33. The method according to claim 17, further comprising the steps of: A first material layer included in the first stack, the etch stop layer, and a second material layer included in the second stack are replaced with a conductive layer.

34. The method according to claim 17, further comprising the steps of: forming a first contact plug connected to the first stepped structure; as well as A second contact plug connected to the second stepped structure is formed.

35. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first stack including a first material layer; forming an etch stop layer on the first stack; forming a second stack including a second material layer on the etch stop layer; exposing the etch stop layer by etching the second layer stack; exposing the first stack by etching the etch stop layer; By patterning the first stack and the second stack in a step shape, a first step structure exposing each of the first material layers and a second step structure exposing each of the second material layers and the etch stop layer are formed; replacing the first material layer, the etch stop layer and the second material layer with a third material layer; as well as Contact plugs respectively connected to the third material layers are formed.

36. The method according to claim 35, further comprising the steps of: forming a first opening extending through the first step structure; as well as A second opening is formed extending through the second step structure and the first stack.

37. The method according to claim 36, further comprising the steps of: forming a first sub-channel hole extending through the etch stop layer and the first stack; as well as A second sub-channel hole is formed extending through the second stack and connected to the first sub-channel hole.

38. The method of claim 37, wherein: When forming the second sub-channel hole, the first opening and the second opening are formed.

39. The method of claim 37, wherein: A width of the first opening and a width of the second opening are greater than a width of the second sub-channel hole.

40. The method according to claim 36, further comprising the steps of: forming a first support including a first dummy channel layer in the first opening; and A second supporter including a second dummy channel layer is formed in the second opening.

41. The method according to claim 35, further comprising the steps of: forming a first sub-opening in the first stack; forming a second sub-opening extending through the second step structure and connected to the first sub-opening; as well as A first opening is formed extending through the first step structure.

42. The method according to claim 41, wherein: When the second sub-opening is formed, the first opening is formed.

43. The method of claim 41, wherein: The width of the first opening is greater than the width of the second sub-opening.

44. The method according to claim 41, further comprising the steps of: forming a first support including a first dummy channel layer in the first opening; as well as A second supporter including a second dummy channel layer is formed in the first sub-opening and the second sub-opening.

45. The method according to claim 35, further comprising the steps of: At least one of the first material layer, the etch stop layer, and the second material layer is replaced with a conductive layer.

46. ​​The method according to claim 35, further comprising the steps of: forming first contact plugs respectively connected to the first material layers; as well as Second contact plugs respectively connected to the second material layers are formed.

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