Semiconductor device, manufacturing method thereof and semiconductor system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a semiconductor system. The manufacturing method comprises the steps that an initial laminated structure is provided, the initial laminated structure comprises multiple stages of steps, each stage of step comprises a gate sacrificial layer and an interlayer insulating layer, and the step surface of each stage of step exposes the surface of the gate sacrificial layer; forming a buffer layer covering the step surface and the side wall of each step; wherein the buffer layer comprises a first sub-buffer layer covering the step surface of the step and a second sub-buffer layer covering the side wall of the step; performing doping treatment on the buffer layer to enable at least part of the first sub-buffer layer to form a doped first sub-buffer layer; wherein the etching selection ratio of the second sub-buffer layer to the doped first sub-buffer layer is greater than the etching selection ratio of the second sub-buffer layer to the undoped first sub-buffer layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same, and a semiconductor system. Background Art

[0002] In a three-dimensional memory, gate layers and interlayer insulating layers can be alternately stacked to form a stacked structure, which includes a core region and a step region; wherein the core region can be used to form a channel structure, and the step region can be used to form a step structure. In addition, a contact hole extending to the corresponding gate layer can be formed in the step region, and a conductive material is filled in the contact hole to form a contact structure (Contact, CT) for drawing out the electrical signal of the corresponding gate layer.

[0003] Currently, there is an urgent need to improve the manufacturing method of semiconductor devices to enhance their reliability. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and a semiconductor system.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0007] Providing an initial stacked structure, the initial stacked structure comprising a plurality of steps, each step comprising a gate sacrificial layer and an interlayer insulating layer, and a step surface of each step exposing a surface of the gate sacrificial layer;

[0008] Forming a buffer layer covering the step surface and sidewalls of each step; wherein the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewalls of the step;

[0009] The buffer layer is doped so that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer; wherein the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer is greater than the etching selectivity of the second sub-buffer layer to the undoped first sub-buffer layer.

[0010] In some embodiments, the step of performing doping treatment on the buffer layer includes:

[0011] Performing ion implantation on the buffer layer;

[0012] The buffer layer is annealed.

[0013] In some embodiments, the ion implantation angle in the ion implantation process is substantially perpendicular to the surface of the first sub-buffer layer;

[0014] The step of performing ion implantation on the buffer layer comprises:

[0015] The first sub-buffer layer is subjected to ion implantation.

[0016] In some embodiments, after the buffer layer is doped, the manufacturing method further includes:

[0017] The second sub-buffer layer covering the sidewall of each step is removed by a first wet etching process to expose the sidewall of each step.

[0018] In some embodiments, a portion of the first sub-buffer layer is doped to form the doped first sub-buffer layer, and the undoped first sub-buffer layer is located between the gate sacrificial layer and the doped first sub-buffer layer;

[0019] After removing the second sub-buffer layer covering the sidewall of each step by the first wet etching process to expose the sidewall of each step, the manufacturing method further includes:

[0020] Using a second wet etching process, removing the gate sacrificial layer and the undoped first sub-buffer layer to form a gap; wherein the etching rate of the gate sacrificial layer in the same etching process is greater than the etching rate of the doped first sub-buffer layer;

[0021] A conductive material is filled in the gap to form a gate layer; wherein the gate layer and the interlayer insulating layer together form a stacked structure.

[0022] In some embodiments, the entire first sub-buffer layer is doped to form the doped first sub-buffer layer;

[0023] After removing the second sub-buffer layer covering the sidewall of each step by the first wet etching process to expose the sidewall of each step, the manufacturing method further includes:

[0024] Using a second wet etching process, the gate sacrificial layer is removed to form a gap; wherein the etching rate of the gate sacrificial layer in the same etching process is greater than the etching rate of the doped first sub-buffer layer;

[0025] A conductive material is filled in the gap to form a gate layer; wherein the gate layer and the interlayer insulating layer together form a stacked structure.

[0026] In some embodiments, the etching solution in the first wet etching process includes a phosphoric acid solution or a hydrofluoric acid solution;

[0027] The etching solution in the second wet etching process includes a sulfuric acid solution or a sulfurous acid solution.

[0028] In some embodiments, after filling the gap with a conductive material to form a gate layer, the manufacturing method further includes:

[0029] forming a filling layer covering the doped first sub-buffer layer and the sidewall of each step;

[0030] A contact structure is formed which sequentially penetrates the filling layer and the doped first sub-buffer layer along the stacking direction and extends to the corresponding gate layer.

[0031] In some embodiments, the forming of the contact structure that sequentially penetrates the filling layer and the doped first sub-buffer layer along the stacking direction and extends to the corresponding gate layer includes:

[0032] forming a contact hole penetrating the filling layer along the stacking direction and extending to the corresponding doped first sub-buffer layer; wherein the doped first sub-buffer layer serves as an etch stop layer;

[0033] removing the doped first sub-buffer layer at the bottom of the contact hole so that the contact hole extends to the corresponding gate layer;

[0034] The contact hole is filled with a conductive material to form a contact structure.

[0035] In some embodiments, a material of the buffer layer is the same as a material of the gate sacrificial layer.

[0036] In some embodiments, the doping element in the doping process includes at least one of the following: carbon and boron.

[0037] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:

[0038] A stacked structure, comprising a plurality of steps, each step comprising a gate layer and an interlayer insulating layer, and adjacent steps are isolated by the interlayer insulating layer;

[0039] A doped first sub-buffer layer covers at least a portion of the step surface of each step and exposes the sidewall of each step; wherein the doped first sub-buffer layer is in contact with the gate layer of each step.

[0040] In some embodiments, the doped first sub-buffer layer protrudes from a sidewall of the corresponding step.

[0041] In some embodiments, the semiconductor device further comprises:

[0042] A filling layer, covering the doped first sub-buffer layer and covering the sidewalls of each step;

[0043] The contact structure sequentially penetrates the filling layer and the doped first sub-buffer layer along the stacking direction and extends to the corresponding gate layer.

[0044] In some embodiments, the gate layer includes a portion of the gate layer in contact with the doped first sub-buffer layer and a portion of the gate layer not in contact with the doped first sub-buffer layer;

[0045] The thickness of the portion of the gate layer in contact with the doped first sub-buffer layer along the stacking direction is greater than or equal to the thickness of the portion of the gate layer not in contact with the doped first sub-buffer layer along the stacking direction.

[0046] In some embodiments, the material of the doped first sub-buffer layer includes silicon nitride doped with carbon and / or boron.

[0047] In a third aspect, an embodiment of the present disclosure provides a semiconductor system, the semiconductor system comprising:

[0048] At least one semiconductor device as described in the above technical solution; and

[0049] The controller is coupled to the semiconductor device and is configured to control the semiconductor device.

[0050] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a semiconductor system. In the embodiments of the present disclosure, the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewall of the step, and the buffer layer is doped so that at least part of the first sub-buffer layer forms a doped first sub-buffer layer, so that the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer is greater than the etching selectivity of the second sub-buffer layer to the undoped first sub-buffer layer, so as to increase the process window for removing the second sub-buffer layer and reduce damage to the doped first sub-buffer layer, thereby improving leakage and short circuit between adjacent word lines, and further improving the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A schematic diagram of a process for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0052] FIG. 2A to FIG. 2I A schematic diagram of a cross-sectional structure of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure;

[0053] Figure 3 A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present disclosure;

[0054] Figure 4 A block diagram of a semiconductor system provided for an embodiment of the present disclosure;

[0055] Figure 5 A block diagram of an electronic device provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0057] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0058] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0059] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0060] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0061] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0063] In a three-dimensional memory (e.g., a NAND memory), gate layers and interlayer insulating layers can be alternately stacked to form a stacked structure, and the stacked structure includes a core region and a step region; wherein the core region can be used to form a channel structure, and the step region can be used to form a step structure. In a three-dimensional memory, each gate layer needs to be connected to a contact structure located in the step region, so that each word line (Word Line, WL) can be connected to a metal end. In other words, a voltage is applied to a single word line (i.e., a single memory cell) through a contact structure, so that the three-dimensional memory can be controlled.

[0064] However, from the manufacturing process point of view, different gate layers (i.e., word lines) are located at different heights, that is, the distances between different gate layers and the top film layer (Top Film) are different. At this time, in the process of etching to form contact holes, it is necessary to ensure that the word lines located below are contacted (Reach) while ensuring that the word lines located above are not penetrated. Therefore, it is necessary to increase the thickness (Thick, THK) of the part of the word line connected to the contact structure, so as to increase the process window (CTLanding Window) for forming the contact hole. Usually, the part of the word line where the thickness increases can be called the "big head".

[0065] In a specific example, a gate sacrificial layer (e.g., silicon nitride (SiN)) and an interlayer insulating layer (e.g., silicon oxide) may be alternately stacked to form an initial stacked structure, and the initial stacked structure may be etched to form multiple steps, each step including a gate sacrificial layer and an interlayer insulating layer. Next, a dielectric layer (e.g., topological selectivity SiN (TS SiN)) covering the step surface of each step may be formed, and subsequently in a gate replacement process, the gate sacrificial layer and the dielectric layer may be replaced with a gate layer, i.e., a word line is formed, thereby increasing the thickness of the portion of the word line connected to the contact structure (i.e., forming a "big head"), thereby increasing the process window for forming the contact hole.

[0066] In the above technical solution, it is necessary to remove the dielectric layer covering the sidewalls of the steps to avoid leakage and short circuits between different word lines (WL to WL leakage and shortage). However, it is difficult to accurately remove the dielectric layer covering the sidewalls of the steps in the above technical solution, which easily causes problems of insufficient etching or over-etching (Over Etch). On the one hand, if the dielectric layer covering the sidewalls of the steps is not completely removed, that is, the process window (SideWall Remove Window) for removing the dielectric layer covering the sidewalls of the steps is insufficient, after the gate replacement process is performed, insufficient etching may cause leakage and short circuits between different word lines. On the other hand, if the dielectric layer covering the sidewalls of the steps is completely removed (that is, over-etching), the dielectric layer covering the step surface may be damaged, that is, the film layer may be rough (Film Roughness). When performing the gate replacement process, for example, using tungsten hexafluoride (WF 6 ) to form a tungsten layer, over-etching may lead to the diffusion of fluorine elements, thereby causing a short circuit between different word lines.

[0067] In view of this, the embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a semiconductor system. In the embodiments of the present disclosure, the buffer layer includes a first sub-buffer layer covering the step surface of the step and a second sub-buffer layer covering the sidewall of the step, and the buffer layer is doped so that at least part of the first sub-buffer layer forms a doped first sub-buffer layer, so that the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer is greater than the etching selectivity of the second sub-buffer layer to the undoped first sub-buffer layer, so as to increase the process window for removing the second sub-buffer layer and reduce damage to the doped first sub-buffer layer, thereby improving leakage and short circuit between adjacent word lines, and further improving the reliability of the semiconductor device.

[0068] refer to Figure 1 , Figure 1 The flowchart of the method for manufacturing a semiconductor device provided by the embodiment of the present disclosure is as follows. Figure 1 As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0069] Step S101: providing an initial stacked structure, the initial stacked structure comprising a plurality of steps, each step comprising a gate sacrificial layer and an interlayer insulating layer, and a step surface of each step exposing a surface of the gate sacrificial layer;

[0070] Step S102: forming a buffer layer covering the step surface and sidewalls of each step; wherein the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewalls of the step;

[0071] Step S103: doping the buffer layer so that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer; wherein the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer is greater than the etching selectivity of the second sub-buffer layer to the undoped first sub-buffer layer.

[0072] refer to FIG. 2A to FIG. 2I , FIG. 2A to FIG. 2I A schematic diagram of a cross-sectional structure of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure. Figure 1 as well as FIG. 2A to FIG. 2I , a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure is described in detail.

[0073] Here, the plane where the gate sacrificial layer and the interlayer insulating layer are located is defined as the XY plane, and the stacking direction of the stacked structure is defined as the Z direction. FIG. 2A to FIG. 2I Both of them illustrate schematic cross-sectional structures of the XZ plane during the manufacturing process of the semiconductor device.

[0074] In the disclosed embodiment, in step S101 , an initial stacked structure 200 is provided. The initial stacked structure 200 includes multiple steps 206 . Each step 206 includes a gate sacrificial layer 202 and an interlayer insulating layer 204 . A step surface 208 of each step 206 exposes a surface of the gate sacrificial layer 202 .

[0075] like Figure 2A As shown, the initial stacked structure 200 includes alternately stacked gate sacrificial layers 202 and interlayer insulating layers 204. Etching the initial stacked structure 200 can form multiple steps 206, each of which includes the gate sacrificial layer 202 and the interlayer insulating layer 204. Each step 206 includes a step surface 208 and a sidewall 210, the step surface 208 is parallel to the XY plane, and the sidewall 210 of the step is parallel to the YZ plane; wherein the step surface 208 of each step 206 exposes the surface of the gate sacrificial layer 202, and the sidewall 210 of each step exposes the sidewalls of the gate sacrificial layer 202 and the interlayer insulating layer 204 at the same time.

[0076] Figure 2A Two steps are schematically shown, namely, a first step and a second step, wherein the first step is located above the second step; wherein the first step includes a first step surface and a first side wall, and the second step includes a second step surface and a second side wall, the first step surface and the second step surface have different heights along the Z direction, and there is a first side wall between the first step surface and the second step surface, namely, the first step surface and the second step surface are located on both sides of the first side wall along the X direction.

[0077] The embodiment of the present disclosure does not specifically limit the number of steps included in the initial stacked structure. Figure 2A Only two steps are illustrated, which does not constitute a limitation on the protection scope of the present disclosure.

[0078] In some embodiments, the process of forming the gate sacrificial layer and the interlayer insulating layer may include but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof.

[0079] In some embodiments, the material of the gate sacrificial layer may include but is not limited to silicon nitride, and the material of the interlayer insulating layer may include but is not limited to silicon oxide.

[0080] In the embodiment of the present disclosure, in step S102 , a buffer layer 212 is formed to cover the step surface 208 and the side wall 210 of each step 206 ; wherein the buffer layer 212 includes a first sub-buffer layer 214 covering the step surface 208 of the step 206 and a second sub-buffer layer 216 covering the side wall 210 of the step 206 .

[0081] like Figure 2B As shown, a first sub-buffer layer 214 (eg, Figure 2B The second sub-buffer layer 216 (shown in the dashed box) covering the sidewall 210 of the step 206 is shown in FIG. Figure 2B The first sub-buffer layer 214 and the second sub-buffer layer 216 together form the buffer layer 212. The first sub-buffer layer 214 is parallel to the XY plane, and the second sub-buffer layer 216 is parallel to the YZ plane.

[0082] Here, the material of the first sub-buffer layer is the same as the material of the second sub-buffer layer. In the same etching process, the etching rate of the first sub-buffer layer and the etching rate of the second sub-buffer layer may be the same or different. Exemplarily, the material of the buffer layer may include a topologically selective material, so that the etching rates of the horizontal part of the buffer layer (i.e., the first sub-buffer layer) and the vertical part of the buffer layer (i.e., the second sub-buffer layer) are different. For example, the density of the second sub-buffer layer covering the side wall of the step is less than the density of the first sub-buffer layer covering the step surface, and the topologically selective material forming the buffer layer has an anisotropic etching rate. Therefore, in the same etching process, the etching rate of the second sub-buffer layer may be greater than the etching rate of the first sub-buffer layer.

[0083] In the embodiment of the present disclosure, the material of the buffer layer 212 and the material of the gate sacrificial layer 202 may be the same or different.

[0084] Here, the materials of the buffer layer and the gate sacrificial layer may be the same. In the same etching process, the etching rate of the buffer layer and the etching rate of the gate sacrificial layer may be the same or different. Exemplarily, different processes may be used to form the buffer layer and the gate sacrificial layer. In this way, even if the materials of the buffer layer and the gate sacrificial layer are the same, the etching rate of the buffer layer and the etching rate of the gate sacrificial layer may be different. For example, the step coverage of the buffer layer formed using the ALD process is good, but the film quality of the buffer layer is average. In this way, even if the materials of the buffer layer and the gate sacrificial layer are the same, in the same etching process, the etching rate of the buffer layer may be greater than the etching rate of the gate sacrificial layer.

[0085] In some embodiments, the process of forming the buffer layer may include, but is not limited to, ALD.

[0086] In the embodiment of the present disclosure, in step S103, the buffer layer 212 is doped so that at least a portion of the first sub-buffer layer 214 forms a doped first sub-buffer layer 218, and the remaining first sub-buffer layer 214 forms an undoped first sub-buffer layer 220; wherein the etching selectivity of the second sub-buffer layer 216 to the doped first sub-buffer layer 218 is greater than the etching selectivity of the second sub-buffer layer 216 to the undoped first sub-buffer layer 220.

[0087] In the embodiment of the present disclosure, the buffer layer 212 is doped, including:

[0088] Performing ion implantation on the buffer layer 212 , including: performing ion implantation on the first sub-buffer layer 214 ;

[0089] The buffer layer 212 is subjected to an annealing process, such as a rapid thermal annealing (RTA) process.

[0090] like Figure 2C As shown, the buffer layer 212 is doped, and the doping process includes ion implantation and annealing. More specifically, the first sub-buffer layer 214 covering the step surface 208 of the step 206 is ion implanted, and the buffer layer 212 is annealed. Figure 2C The arrow direction is the direction of ion implantation, and the direction of ion implantation is substantially perpendicular to the surface of the first sub-buffer layer 214 .

[0091] Here, the direction of ion implantation being substantially perpendicular to the surface of the first sub-buffer layer means that the angle between the direction of ion implantation and the XY plane is 90 degrees or the difference between the angle between the direction of ion implantation and the XY plane and 90 degrees meets the process error requirement.

[0092] It should be noted that the orthographic projection of the second sub-buffer layer on the XY plane is within the orthographic projection range of the first sub-buffer layer on the XY plane, so during the process of performing ion implantation on the buffer layer in a direction substantially perpendicular to the XY plane, the second sub-buffer layer is shielded by the first sub-buffer layer. In other words, performing ion implantation on the buffer layer in a direction substantially perpendicular to the XY plane, that is, performing ion implantation on the first sub-buffer layer in a direction substantially perpendicular to the XY plane, will only perform ion implantation on the first sub-buffer layer but will not perform ion implantation on the second sub-buffer layer.

[0093] In the embodiment of the present disclosure, the doping element in the doping process includes at least one of the following: carbon and boron. In other words, the implanted element in the ion implantation process includes carbon and / or boron.

[0094] like Figure 2DAs shown, the buffer layer 212 is annealed to promote the bonding between the ion implanted elements and the elements of the first sub-buffer layer 214, thereby achieving doping. In the same etching process, the etching rate of the undoped first sub-buffer layer 220 is greater than the etching rate of the doped first sub-buffer layer 218, and the etching rate of the second sub-buffer layer 216 is greater than the etching rate of the doped first sub-buffer layer 218.

[0095] Here, the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer is the ratio of the etching rate of the second sub-buffer layer to the etching rate of the doped first sub-buffer layer in the same etching process; the etching selectivity of the second sub-buffer layer to the undoped first sub-buffer layer is the ratio of the etching rate of the second sub-buffer layer to the etching rate of the undoped first sub-buffer layer in the same etching process. Since the etching rate of the undoped first sub-buffer layer is greater than the etching rate of the doped first sub-buffer layer in the same etching process, the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer is greater than the etching selectivity of the second sub-buffer layer to the undoped first sub-buffer layer.

[0096] In some embodiments, in the same etching process, the etching rate of the undoped first sub-buffer layer and the etching rate of the second sub-buffer layer may be the same or different. For example, in the process of forming the buffer layer, the density of the second sub-buffer layer covering the sidewall of the step is less than the density of the first sub-buffer layer covering the step surface, and therefore, in the same etching process, the etching rate of the second sub-buffer layer may be greater than the etching rate of the undoped first sub-buffer layer.

[0097] In some embodiments, Figure 2D As shown, the first sub-buffer layer 214 is divided into a doped first sub-buffer layer 218 and an undoped first sub-buffer layer 220 along the Z direction, and a portion of the first sub-buffer layer 214 is doped to form a doped first sub-buffer layer 218, and the undoped first sub-buffer layer 220 is located between the gate sacrificial layer 202 and the doped first sub-buffer layer 218. In other words, the sum of the thickness of the doped first sub-buffer layer 218 along the Z direction and the thickness of the undoped first sub-buffer layer 220 along the Z direction is the same as the thickness of the first sub-buffer layer 214 along the Z direction. It should be noted that a portion of the first sub-buffer layer is doped to form a doped first sub-buffer layer, and after the gate replacement process is performed, the doped first sub-buffer layer is in "bulk" contact with the gate layer (i.e., word line layer).

[0098] In other embodiments, all first sub-buffer layers are doped to form doped first sub-buffer layers, the doped first sub-buffer layers are located above the gate sacrificial layer, and the doped first sub-buffer layers are in contact with the gate sacrificial layer. In other words, the thickness of the doped first sub-buffer layer along the Z direction is the same as the thickness of the first sub-buffer layer along the Z direction. It should be noted that all first sub-buffer layers are doped to form doped first sub-buffer layers, and after the gate replacement process is performed, the thickness of the gate layer (i.e., word line layer) along the Z direction is uniform, that is, there is no "big head" in the gate layer. In this way, the doped first sub-buffer layer is in contact with the gate layer.

[0099] In the embodiments of the present disclosure, the thickness of the doped first sub-buffer layer along the Z direction and the concentration of the doping element in the doped first sub-buffer layer can be controlled by controlling the parameters of the ion implantation and annealing treatments, such as the ion implantation energy, the ion implantation depth, the ion implantation concentration, and the temperature and time of the annealing treatment. In this way, in the same etching process, the difference between the etching rate of the second sub-buffer layer and the etching rate of the doped first sub-buffer layer can be increased, that is, the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer can be increased.

[0100] In some embodiments, the higher the ion implantation energy and the greater the ion implantation depth, the greater the thickness of the doped first sub-buffer layer along the Z direction.

[0101] In some embodiments, the greater the ion implantation concentration, the greater the difference between the etching rate of the second sub-buffer layer and the etching rate of the doped first sub-buffer layer, that is, the greater the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer.

[0102] In some embodiments, the annealing temperature and time are related to the material type and doping element type of the buffer layer. Generally, the longer the annealing time, the greater the doping depth of the first sub-buffer layer and the greater the thickness of the doped first sub-buffer layer along the Z direction.

[0103] In the embodiment of the present disclosure, after step S103, the manufacturing method further includes:

[0104] The second sub-buffer layer 216 covering the sidewall 210 of each step 206 is removed by a first wet etching process to expose the sidewall 210 of each step 206 .

[0105] like Figure 2EAs shown, in the same etching process, the etching rate of the undoped first sub-buffer layer 220 (or the second sub-buffer layer 216) is greater than the etching rate of the doped first sub-buffer layer 218; by utilizing the first wet etching process, during the process of removing the second sub-buffer layer 216, the process window for removing the second sub-buffer layer 216 can be increased and the damage to the doped first sub-buffer layer 218 can be reduced, that is, while completely removing the second sub-buffer layer 216, damage to the doped first sub-buffer layer 218 can be avoided as much as possible. In this way, the leakage and short circuit between adjacent word lines can be improved, thereby improving the reliability of the semiconductor device.

[0106] In the embodiment of the present disclosure, the etching solution in the first wet etching process may include a phosphoric acid solution (H 3 PO 4 ) or hydrofluoric acid solution (HF).

[0107] Here, a phosphoric acid solution or a hydrofluoric acid solution can be used to remove the second sub-buffer layer covering the side wall of the step. The disclosed embodiment does not specifically limit the concentration of the etching solution in the first wet etching process, and the concentration of the etching solution in the first wet etching process can be specifically adjusted according to the concentration of the doping element doped in the first sub-buffer layer.

[0108] Still Figure 2E As shown, a portion of the first sub-buffer layer is doped to form a doped first sub-buffer layer 218, and the doped first sub-buffer layer 218 protrudes from the sidewall 210 of the corresponding step 206. More specifically, the doped first sub-buffer layer can be divided into a main body 218a and a protruding portion 218b along the X direction, the main body 218a is in contact with the undoped first sub-buffer layer 220, and the protruding portion 218b is not in contact with the undoped first sub-buffer layer 220, and the protruding portion 218b protrudes from the sidewall 210 of the corresponding step 206. In other words, the orthographic projection of the main body 218a on the XY plane coincides with the orthographic projection of the undoped first sub-buffer layer 220 on the XY plane, and the orthographic projection of the protruding portion 218b on the XY plane is located outside the range of the orthographic projection of the undoped first sub-buffer layer 220 on the XY plane.

[0109] It should be noted that Figure 2E The outline of the protrusion 218b in the schematic cross-sectional structure diagram is an arc shape. In fact, the embodiment of the present disclosure has no special limitation on the outline morphology of the protrusion. In the first wet etching process, if the etching rate of the second sub-buffer layer is much greater than the etching rate of the doped first sub-buffer layer, then the morphology of the doped first sub-buffer layer may not be substantially destroyed during the etching and removal of the second sub-buffer layer. At this time, the outline of the protrusion of the doped first sub-buffer layer in the cross-sectional structure diagram may be a rectangular shape.

[0110] In some other embodiments, the entire first sub-buffer layer is doped to form a doped first sub-buffer layer, and the doped first sub-buffer layer protrudes from the sidewall of the corresponding step. More specifically, the doped first sub-buffer layer can be divided into a main body and a protruding portion along the X direction, the main body contacts the gate sacrificial layer, the protruding portion does not contact the gate sacrificial layer, and the protruding portion protrudes from the sidewall of the corresponding step.

[0111] In the embodiment of the present disclosure, the undoped first sub-buffer layer 220 is located between the doped first sub-buffer layer 218 and the gate sacrificial layer 202; after removing the second sub-buffer layer 216 covering the sidewall 210 of each step 206 by a first wet etching process to expose the sidewall 210 of each step 206, the manufacturing method further includes:

[0112] Using a second wet etching process, the gate sacrificial layer 202 and the undoped first sub-buffer layer 220 are removed to form a gap 222; wherein the etching rate of the gate sacrificial layer 202 in the same etching process is greater than the etching rate of the doped first sub-buffer layer 218;

[0113] A conductive material is filled in the gap 222 to form a gate layer 224 ; wherein the gate layer 224 and the interlayer insulating layer 204 together form a stacked structure 226 .

[0114] like Figure 2F As shown, the gate sacrificial layer 202 and the undoped first sub-buffer layer 220 are removed by a second wet etching process to form a gap 222; since the etching rate of the gate sacrificial layer 202 and the etching rate of the undoped first sub-buffer layer 220 in the same etching process are both greater than the etching rate of the doped first sub-buffer layer 218, during the process of removing the gate sacrificial layer 202 and the undoped first sub-buffer layer 220 by wet etching, the process window for removing the gate sacrificial layer 202 and the undoped first sub-buffer layer 220 can be increased and the damage to the doped first sub-buffer layer 218 can be reduced, that is, the gate sacrificial layer 202 and the undoped first sub-buffer layer 220 can be completely removed while avoiding damage to the doped first sub-buffer layer 218 as much as possible.

[0115] Here, a "big head" is formed at one end of the gate layer along the X direction, and the thickness of the "big head" along the Z direction is the sum of the thickness of the gate sacrificial layer along the Z direction and the thickness of the undoped first sub-buffer layer along the Z direction. In other words, the gate layer includes a portion of the gate layer in contact with the doped first sub-buffer layer and a portion of the gate layer not in contact with the doped first sub-buffer layer; the thickness H1 of the portion of the gate layer in contact with the doped first sub-buffer layer along the Z direction is greater than the thickness H2 of the portion of the gate layer not in contact with the doped first sub-buffer layer along the Z direction.

[0116] Still Figure 2FAs shown, a portion of the first sub-buffer layer is doped to form a doped first sub-buffer layer 218, and the doped first sub-buffer layer 218 protrudes from the sidewall 210 of the corresponding step 206. More specifically, the main body 218a of the doped first sub-buffer layer contacts the "big head" of the gate layer 224, and the protruding portion 218b of the doped first sub-buffer layer does not contact the "big head" of the gate layer 224, and the protruding portion 218b protrudes from the sidewall 210 of the corresponding step 206.

[0117] In some other embodiments, the entire first sub-buffer layer is doped to form a doped first sub-buffer layer, and the doped first sub-buffer layer protrudes from the side wall of the corresponding step. More specifically, the main body of the doped first sub-buffer layer contacts the gate layer, and the protruding portion of the doped first sub-buffer layer does not contact the gate layer, and the protruding portion protrudes from the side wall of the corresponding step. In this case, the gate layer does not have a "big head".

[0118] In the embodiment of the present disclosure, the material of the buffer layer 212 is the same as the material of the gate sacrificial layer 202 .

[0119] Here, the material of the buffer layer and the material of the gate sacrificial layer can be the same. Since the material of the buffer layer and the material of the gate sacrificial layer are the same, the same etching solution can be used to remove the gate sacrificial layer and the undoped first sub-buffer layer at the same time, and the process flow is simpler and the cost is lower. Exemplarily, nitride can be used to form the buffer layer and the gate sacrificial layer. For example, the material of the buffer layer and the material of the gate sacrificial layer can both include silicon nitride.

[0120] Of course, other suitable materials can also be selected so that in the same etching process, the etching rate of the buffer layer is greater than the etching rate of the gate sacrificial layer. Exemplarily, silicon nitride can be used to form the gate sacrificial layer, and topologically selective silicon nitride can be used to form the buffer layer (i.e., the undoped first sub-buffer layer). The etching rate of the topologically selective silicon nitride material can be greater than the etching rate of silicon nitride. The etching rate of the undoped first sub-buffer layer is greater than the etching rate of the gate sacrificial layer, so that the gate sacrificial layer and the undoped first sub-buffer layer can be removed more quickly.

[0121] In the embodiment of the present disclosure, the etching solution in the second wet etching process may include a sulfuric acid solution or a sulfurous acid solution.

[0122] Here, a sulfuric acid solution (HSO), that is, a sulfuric acid solution or a sulfurous acid solution, can be used to remove the gate sacrificial layer and the undoped first sub-buffer layer between the gate sacrificial layer and the doped first sub-buffer layer. The disclosed embodiment does not specifically limit the concentration of the etching solution in the second wet etching process, and the concentration of the etching solution in the second wet etching process can be specifically adjusted according to the concentration of the doping element of the doped first sub-buffer layer.

[0123] In the embodiment of the present disclosure, all the first sub-buffer layers are subjected to doping treatment to form a doped first sub-buffer layer, and at this time, the doped first sub-buffer layer is in contact with the gate sacrificial layer; after the second sub-buffer layer covering the sidewall of each step is removed by a first wet etching process to expose the sidewall of each step, the manufacturing method further includes:

[0124] Using a second wet etching process, the gate sacrificial layer is removed to form a gap; wherein the etching rate of the gate sacrificial layer in the same etching process is greater than the etching rate of the doped first sub-buffer layer;

[0125] A conductive material is filled in the gap to form a gate layer; wherein the gate layer and the interlayer insulating layer together form a stacked structure.

[0126] Here, a second wet etching process is used to remove the gate sacrificial layer to form a gap; since the etching rate of the gate sacrificial layer is greater than the etching rate of the doped first sub-buffer layer in the same etching process, during the process of wet etching to remove the gate sacrificial layer, the process window for removing the gate sacrificial layer can be increased and the damage to the doped first sub-buffer layer can be reduced, that is, the gate sacrificial layer can be completely removed while avoiding damage to the doped first sub-buffer layer as much as possible.

[0127] Here, no "big head" is formed at one end of the gate layer, and the thickness of the gate layer along the Z direction is the thickness of the gate sacrificial layer along the Z direction. In other words, the gate layer includes a portion of the gate layer in contact with the doped first sub-buffer layer and a portion of the gate layer not in contact with the doped first sub-buffer layer; the thickness of the portion of the gate layer in contact with the doped first sub-buffer layer along the Z direction is the same as the thickness of the portion of the gate layer not in contact with the doped first sub-buffer layer along the Z direction.

[0128] In the embodiment of the present disclosure, after the gap 222 is filled with a conductive material to form a gate layer 224, the manufacturing method further includes:

[0129] forming a filling layer 228 covering the doped first sub-buffer layer 218 and each step sidewall 210;

[0130] A contact structure 232 is formed that sequentially penetrates the filling layer 228 and the doped first sub-buffer layer 218 along the stacking direction and extends to the corresponding gate layer 224 .

[0131] In the embodiment of the present disclosure, a contact structure 232 is formed that sequentially penetrates the filling layer 228 and the doped first sub-buffer layer 218 along the stacking direction and extends to the corresponding gate layer 224, including:

[0132] A contact hole 230 is formed along the stacking direction, penetrating the filling layer 228 and extending to the corresponding doped first sub-buffer layer 218; wherein the doped first sub-buffer layer 218 serves as an etch stop layer (ESL);

[0133] removing the doped first sub-buffer layer 218 at the bottom of the contact hole 230 , so that the contact hole 230 extends to the corresponding gate layer 224 ;

[0134] The contact hole 230 is filled with a conductive material to form a contact structure 232 .

[0135] like Figure 2G As shown, a filling layer 228 is formed to cover the doped first sub-buffer layer 218 and the sidewall 210 of each step 206. After the gate replacement process is performed, each step includes a step surface and a sidewall, the surface of the gate layer 224 exposed by the step surface is in contact with the doped first sub-buffer layer 218, and the gate layer 224 and the sidewall of the interlayer insulating layer 204 exposed by the sidewall of the step are in direct contact with the filling layer 228.

[0136] In some embodiments, the process of forming the filling layer may include but is not limited to PVD, CVD, ALD or any combination thereof.

[0137] In some embodiments, the material of the filling layer may include, but is not limited to, silicon oxide.

[0138] like Figure 2H As shown, the process of forming the contact hole 230 is divided into two stages: in the first stage, etching is performed sequentially along the Z direction to form the contact hole 230 that penetrates the filling layer 228 and extends to the corresponding doped first sub-buffer layer 218; wherein the doped first sub-buffer layer 218 can be used as an etching stop layer, so that the contact holes 230 corresponding to different gate layers 224 all stay in the doped first sub-buffer layer 218 above the corresponding gate layer 224.

[0139] Here, there is a higher etching selectivity ratio between the filling layer and the doped first sub-buffer layer, so that the doped first sub-buffer layer can be used as an etching stop layer, thereby better improving the leakage phenomenon between word lines caused by over-etching.

[0140] like Fig.2IAs shown, in the second stage, the doped first sub-buffer layer 218 at the bottom of the contact hole 230 is removed, so that the contact hole 230 continues to penetrate the doped first sub-buffer layer 218 downward and extends to the corresponding gate layer 224. In this way, the contact hole 230 is formed by etching in stages, and the doped first sub-buffer layer 218 is used as an etching stop layer, which can ensure that the contact hole 230 extends to the gate layer 224 located below, and also ensure that the gate layer 224 located above is not penetrated by etching, that is, the problems of insufficient etching and over-etching are improved at the same time.

[0141] Still Fig.2I As shown, a conductive material may be filled in the contact hole 230 to form a contact structure 232 extending along the Z direction to the corresponding gate layer 224 .

[0142] In the embodiment of the present disclosure, the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the side wall of the step. The buffer layer is doped so that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer. In this way, the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer is greater than the etching selectivity of the second sub-buffer layer to the undoped first sub-buffer layer. The difference between the etching rate of the second sub-buffer layer and the etching rate of the doped first sub-buffer layer is maximized as much as possible to increase the process window for removing the second sub-buffer layer and reduce damage to the doped first sub-buffer layer, thereby improving leakage and short circuit between adjacent word lines, and further improving the reliability of the semiconductor device.

[0143] In a specific example, first, a gate sacrificial layer (e.g., silicon nitride) and an interlayer insulating layer (e.g., silicon oxide) may be alternately stacked to form an initial stacked structure, and the initial stacked structure may include multiple steps, each step including a gate sacrificial layer and an interlayer insulating layer. Here, the etching rate of the gate sacrificial layer may be defined as S1.

[0144] Secondly, a buffer layer (e.g., topologically selective silicon nitride) is formed to cover the step surface and sidewall of each step, and the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewall of the step; wherein the first sub-buffer layer can be called a flat silicon nitride layer on the step surface (flat SiN film on the stairs), and the second sub-buffer layer can be called a silicon nitride layer on the step sidewall (side wall SiN on the stairs). Here, the etching rate of the first sub-buffer layer can be defined as S2, and the etching rate of the second sub-buffer layer can be defined as S3; wherein S3>S2.

[0145] It should be noted that the buffer layer can be formed using the ALD process, and the etching rate of the buffer layer is greater than the etching rate of the gate sacrificial layer, that is, S3>S1 and S2>S1. Here, the buffer layer formed using the ALD process has better step coverage, but the film quality of the buffer layer is average and is more easily etched and removed.

[0146] In the related technical scheme, the buffer layer is surface treated in situ. For example, plasma treatment (PT) can be used to remove impurity elements in the topological selective silicon nitride on the step surface, and can also make the topological selective silicon nitride on the step surface denser, thereby increasing the difference between the etching rate of the topological selective silicon nitride on the step surface and the etching rate of the topological selective silicon nitride on the step sidewall. However, this surface treatment method has many disadvantages. On the one hand, this method can achieve a certain directionality but cannot form an ion treatment that is completely perpendicular to the horizontal plane, so that the density of the topological selective silicon nitride on the step surface is increased while the density of the topological selective silicon nitride on the step sidewall is increased, so that the difference between the etching rate of the topological selective silicon nitride on the step surface and the etching rate of the topological selective silicon nitride on the step sidewall cannot be maximized; on the other hand, this method cannot form an ion treatment that is completely perpendicular to the horizontal plane, and the energy of the ion treatment is insufficient, so that the topological selective silicon nitride on the step surface at the bottom and the topological selective silicon nitride on the step sidewall are both in the weakest area of ​​the ion treatment, so that the difference between the etching rate of the topological selective silicon nitride on the step surface and the etching rate of the topological selective silicon nitride on the step sidewall is not large enough. In this way, the process of removing the topological selective silicon nitride on the step sidewall may still have the problem of insufficient etching or over-etching.

[0147] In the embodiment of the present disclosure, the buffer layer may then be doped so that at least part of the first sub-buffer layer forms a doped first sub-buffer layer, and the remaining first sub-buffer layer forms an undoped first sub-buffer layer; wherein the undoped first sub-buffer layer is located between the doped first sub-buffer layer and the gate sacrificial layer. Here, the etching rate of the undoped first sub-buffer layer is the same as the etching rate of the first sub-buffer layer, which is still S2, and the etching rate of the doped first sub-buffer layer is defined as S4; wherein S2>S4. In summary, S3>S2>S1>S4.

[0148] Next, the second sub-buffer layer is removed by a first wet etching process. Since the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer (i.e., S3 / S4) is greater than the etching selectivity of the second sub-buffer layer to the undoped first sub-buffer layer (i.e., S3 / S2), the second sub-buffer layer can be completely removed while minimizing damage to the doped first sub-buffer layer.

[0149] Here, by utilizing the characteristic that the direction of ion implantation is basically perpendicular to the horizontal plane during ion implantation, the topologically selective silicon nitride of the first sub-buffer layer is subjected to ex-situ doping, thereby implanting different doping elements (for example, carbon and / or boron) into the topologically selective silicon nitride of the first sub-buffer layer with higher energy, and then annealing is performed to allow the doping elements to form bonds with the topologically selective silicon nitride, thereby increasing the wet etching selectivity of the second sub-buffer layer to the doped first sub-buffer, thereby better achieving selective etching to completely remove the second sub-buffer layer covering the side walls of the step.

[0150] Here, the ion implantation process can achieve strong directionality, and the anisotropic ion implantation process can maximize the difference between the etching rate of the second sub-buffer layer and the etching rate of the doped first sub-buffer layer to achieve a larger etching selectivity.

[0151] Here, the doped first sub-buffer layer can better resist the etching solution (eg, H) than the undoped first sub-buffer layer and the second sub-buffer layer. 3 PO 4 With HF), the second sub-buffer layer can be removed by anisotropic wet etching, while the doped first sub-buffer layer can be well preserved. In other words, in the embodiment of the present disclosure, the difference between the etching rate of the second sub-buffer layer and the etching rate of the doped first sub-buffer layer in the same etching process is increased as much as possible to increase the process window for removing the second sub-buffer layer and reduce the damage to the doped first sub-buffer layer.

[0152] Next, a second wet etching process is used to remove the gate sacrificial layer and the undoped first sub-buffer layer. Due to the etching selectivity of the gate sacrificial layer to the doped first sub-buffer layer (i.e., S1 / S4) and the etching selectivity of the undoped first sub-buffer layer to the doped first sub-buffer layer (i.e., S2 / S4), the gate sacrificial layer and the undoped first sub-buffer layer can be quickly and cleanly removed.

[0153] refer to Figure 3 , Figure 3 Schematic diagram of the cross-sectional structure of a semiconductor device provided by an embodiment of the present disclosure. Figure 3 As shown, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:

[0154] The stacked structure 226 includes a plurality of steps 206 , each step 206 includes a gate layer 224 and an interlayer insulating layer 204 , and adjacent steps 206 are isolated by the interlayer insulating layer 204 ;

[0155] The doped first sub-buffer layer 218 covers at least a portion of the step surface 208 of each step 206 and exposes the sidewall 210 of each step 206 ; wherein the doped first sub-buffer layer 218 is in contact with the gate layer 224 of each step 206 .

[0156] Here, the step surface of each step is parallel to the XY plane, and the side wall of the step is parallel to the YZ plane; wherein the surface of the gate layer exposed by the step surface is in direct contact with the doped first sub-buffer layer, and the gate layer and the side wall of the interlayer insulating layer exposed by the side wall of the step are in direct contact with the filling layer.

[0157] In the disclosed embodiment, the doped first sub-buffer layer 218 protrudes from the sidewall 210 of the corresponding step 206 .

[0158] Here, the doped first sub-buffer layer 218 may be divided into a main body 218 a and a protruding portion 218 b along the X direction. The main body 218 a contacts the gate layer 224 , and the protruding portion 218 b does not contact the gate layer 224 . The protruding portion 218 b protrudes from the sidewall 210 of the step 206 .

[0159] In the embodiment of the present disclosure, the semiconductor device further includes:

[0160] A filling layer 228 covering the doped first sub-buffer layer 218 and covering the sidewall 210 of each step 206;

[0161] The contact structure 232 sequentially penetrates the filling layer 228 and the doped first sub-buffer layer 218 along the stacking direction and extends to the corresponding gate layer 224 .

[0162] like Figure 3 As shown, the contact interface between the protrusion 218b of the doped first sub-buffer layer and the filling layer 228 is in an arc shape. The disclosed embodiment has no special limitation on the shape of the contact interface between the protrusion 218b and the filling layer 228, and the shape of the contact interface between the protrusion 218b and the filling layer 228 can also be a straight line.

[0163] Here, each gate layer needs to lead out an electrical signal through a contact structure, that is, each word line needs to lead out an electrical signal through a contact structure.

[0164] In the embodiment of the present disclosure, the gate layer 224 includes a portion of the gate layer 224 that is in contact with the doped first sub-buffer layer 218 and a portion of the gate layer 224 that is not in contact with the doped first sub-buffer layer 218 ;

[0165] The thickness of the portion of the gate layer 224 in contact with the doped first sub-buffer layer 218 along the stacking direction is greater than or equal to the thickness of the portion of the gate layer 224 not in contact with the doped first sub-buffer layer 218 along the stacking direction.

[0166] In some embodiments, a portion of the first sub-buffer layer is doped to form a doped first sub-buffer layer, and an undoped first sub-buffer layer is located between the doped first sub-buffer layer and the gate sacrificial layer. After the gate replacement process is performed, the thickness H1 of the portion of the gate layer in contact with the doped first sub-buffer layer along the Z direction is greater than the thickness H2 of the portion of the gate layer not in contact with the doped first sub-buffer layer along the Z direction.

[0167] In other embodiments, the entire first sub-buffer layer is doped to form a doped first sub-buffer layer, the doped first sub-buffer layer is located above the gate sacrificial layer and the doped first sub-buffer layer is in contact with the gate sacrificial layer, and after the gate replacement process is performed, the thickness of the portion of the gate layer in contact with the doped first sub-buffer layer along the Z direction is the same as the thickness of the portion of the gate layer not in contact with the doped first sub-buffer layer along the Z direction.

[0168] In the embodiment of the present disclosure, the material doped with the first sub-buffer layer 218 includes silicon nitride doped with carbon and / or boron.

[0169] refer to Figure 4 , Figure 4 A block diagram of a semiconductor system provided by an embodiment of the present disclosure. Figure 4 As shown, the present disclosure provides a semiconductor system 300, which includes:

[0170] At least one semiconductor device 302 as in the above technical solution; and

[0171] The controller 304 is coupled to the semiconductor device 302 and is configured to control the semiconductor device 302 .

[0172] Here, the semiconductor device provided by the embodiment of the present disclosure may be a part of a three-dimensional memory, or the semiconductor device provided by the embodiment of the present disclosure may further include a peripheral circuit, so the semiconductor device provided by the embodiment of the present disclosure may also be a three-dimensional memory.

[0173] Here, the semiconductor system provided by the embodiments of the present disclosure may include at least one semiconductor device and a controller coupled to the semiconductor device.

[0174] Here, the controller can be used to control the semiconductor device to perform erase, read or write operations, and decode, analyze or calculate instructions sent or received in the semiconductor device.

[0175] In some embodiments, the semiconductor system may include, but is not limited to, a solid state drive and a memory card.

[0176] refer to Figure 5 , Figure 5 A block diagram of an electronic device provided by an embodiment of the present disclosure. Figure 5As shown, the embodiment of the present disclosure provides an electronic device 306, which includes: the semiconductor system 300 in the above technical solution. Here, the electronic device may include a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device or a mobile power supply, etc.

[0177] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a semiconductor system. In the embodiments of the present disclosure, the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewall of the step, and the buffer layer is doped so that at least part of the first sub-buffer layer forms a doped first sub-buffer layer, so that the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer is greater than the etching selectivity of the second sub-buffer layer to the undoped first sub-buffer layer, so as to increase the process window for removing the second sub-buffer layer and reduce damage to the doped first sub-buffer layer, thereby improving leakage and short circuit between adjacent word lines, and further improving the reliability of the semiconductor device.

[0178] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0179] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Providing an initial stacked structure, the initial stacked structure comprising a plurality of steps, each step comprising a gate sacrificial layer and an interlayer insulating layer, and a step surface of each step exposing a surface of the gate sacrificial layer; Forming a buffer layer covering the step surface and sidewalls of each step; wherein the buffer layer includes a first sub-buffer layer covering the step surface and a second sub-buffer layer covering the sidewalls of the step; The buffer layer is doped so that at least a portion of the first sub-buffer layer forms a doped first sub-buffer layer; wherein the etching selectivity of the second sub-buffer layer to the doped first sub-buffer layer is greater than the etching selectivity of the second sub-buffer layer to the undoped first sub-buffer layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of performing doping treatment on the buffer layer comprises: Performing ion implantation on the buffer layer; The buffer layer is annealed.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The angle of ion implantation in the ion implantation process is substantially perpendicular to the surface of the first sub-buffer layer; The step of performing ion implantation on the buffer layer comprises: The first sub-buffer layer is subjected to ion implantation.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: After the buffer layer is doped, the manufacturing method further includes: The second sub-buffer layer covering the sidewall of each step is removed by a first wet etching process to expose the sidewall of each step.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: A portion of the first sub-buffer layer is doped to form the doped first sub-buffer layer, and the undoped first sub-buffer layer is located between the gate sacrificial layer and the doped first sub-buffer layer; After removing the second sub-buffer layer covering the sidewall of each step by the first wet etching process to expose the sidewall of each step, the manufacturing method further includes: Using a second wet etching process, removing the gate sacrificial layer and the undoped first sub-buffer layer to form a gap; wherein the etching rate of the gate sacrificial layer in the same etching process is greater than the etching rate of the doped first sub-buffer layer; A conductive material is filled in the gap to form a gate layer; wherein the gate layer and the interlayer insulating layer together form a stacked structure.

6. The method for manufacturing a semiconductor device according to claim 4, wherein: The entire first sub-buffer layer is doped to form the doped first sub-buffer layer; After removing the second sub-buffer layer covering the sidewall of each step by the first wet etching process to expose the sidewall of each step, the manufacturing method further includes: Using a second wet etching process, the gate sacrificial layer is removed to form a gap; wherein the etching rate of the gate sacrificial layer in the same etching process is greater than the etching rate of the doped first sub-buffer layer; A conductive material is filled in the gap to form a gate layer; wherein the gate layer and the interlayer insulating layer together form a stacked structure.

7. The method for manufacturing a semiconductor device according to claim 5 or 6, characterized in that: The etching solution in the first wet etching process includes a phosphoric acid solution or a hydrofluoric acid solution; The etching solution in the second wet etching process includes a sulfuric acid solution or a sulfurous acid solution.

8. The method for manufacturing a semiconductor device according to claim 5 or 6, characterized in that: After the gap is filled with a conductive material to form a gate layer, the manufacturing method further includes: forming a filling layer covering the doped first sub-buffer layer and the sidewalls of each step; A contact structure is formed which sequentially penetrates the filling layer and the doped first sub-buffer layer along the stacking direction and extends to the corresponding gate layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The forming of the contact structure sequentially penetrating the filling layer and the doped first sub-buffer layer along the stacking direction and extending to the corresponding gate layer includes: forming a contact hole penetrating the filling layer along the stacking direction and extending to the corresponding doped first sub-buffer layer; wherein the doped first sub-buffer layer serves as an etch stop layer; removing the doped first sub-buffer layer at the bottom of the contact hole so that the contact hole extends to the corresponding gate layer; The contact hole is filled with a conductive material to form a contact structure.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the buffer layer is the same as that of the gate sacrificial layer.

11. The method for manufacturing a semiconductor device according to claim 1, wherein: The doping element in the doping process includes at least one of the following: carbon element and boron element.

12. A semiconductor device, characterized in that: The semiconductor device comprises: A stacked structure, comprising a plurality of steps, each step comprising a gate layer and an interlayer insulating layer, and adjacent steps are isolated by the interlayer insulating layer; A doped first sub-buffer layer covers at least a portion of the step surface of each step and exposes the sidewall of each step; wherein the doped first sub-buffer layer is in contact with the gate layer of each step.

13. The semiconductor device according to claim 12, characterized in that The doped first sub-buffer layer protrudes from a sidewall of the corresponding step.

14. The semiconductor device according to claim 12, wherein: The semiconductor device further comprises: A filling layer, covering the doped first sub-buffer layer and covering the sidewalls of each step; The contact structure sequentially penetrates the filling layer and the doped first sub-buffer layer along the stacking direction and extends to the corresponding gate layer.

15. The semiconductor device according to claim 12, characterized in that The gate layer includes a portion of the gate layer in contact with the doped first sub-buffer layer and a portion of the gate layer not in contact with the doped first sub-buffer layer; The thickness of the portion of the gate layer in contact with the doped first sub-buffer layer along the stacking direction is greater than or equal to the thickness of the portion of the gate layer not in contact with the doped first sub-buffer layer along the stacking direction.

16. The semiconductor device according to claim 12, wherein: The material of the doped first sub-buffer layer includes silicon nitride doped with carbon and / or boron.

17. A semiconductor system, characterized in that: The semiconductor system comprises: At least one semiconductor device according to any one of claims 12 to 16; and The controller is coupled to the semiconductor device and is configured to control the semiconductor device.

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