Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A semiconductor device may include: a gate structure including gate lines and insulating layers alternately stacked; a channel structure extending through the gate structure; a dummy gate structure including stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure; and an isolation insulating structure including a horizontal portion stacked between the gate structure and the dummy gate structure and a vertical portion extending through the horizontal portion.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to electronic devices, and more particularly, to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a semiconductor device for forming a memory cell in a single layer on a substrate has reached a limit, a three-dimensional semiconductor device for stacking memory cells on a substrate has been proposed. In addition, in order to improve the operational reliability of such a semiconductor device, various structures and manufacturing methods have been developed. Summary of the invention

[0003] In an embodiment, a semiconductor device may include: a gate structure including alternately stacked gate lines and insulating layers; a channel structure extending through the gate structure; a dummy gate structure including stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure; and an isolation insulating structure including a horizontal portion stacked between the gate structure and the dummy gate structure and a vertical portion extending through the horizontal portion.

[0004] In an embodiment, a semiconductor device may include: a gate structure including stacked gate lines; a channel structure extending through the gate structure; contact plugs extending through the gate structure and connected to the gate lines, respectively; a dummy gate structure adjacent to the gate structure in a first direction and including stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure; and an isolation insulating structure located between the gate structure and the dummy gate structure, extending in a second direction intersecting the first direction, and including dummy contact plugs arranged in the second direction.

[0005] In an embodiment, a method for manufacturing a semiconductor device may include: forming a first stack including a first material layer and a second material layer alternately stacked; forming a dummy hole in the first stack; forming a second stack on the first stack, the second stack including a third material layer and a fourth material layer alternately stacked; forming a dummy contact hole in the second stack, the dummy contact hole connected to the dummy hole; forming an isolation trench by etching the first material layer and the third material layer through the dummy contact hole and the dummy hole; and forming an isolation insulating structure in the isolation trench.

[0006] In an embodiment, a method for manufacturing a semiconductor device may include: forming a first stack including a first material layer and a second material layer alternately stacked; forming a dummy hole in the first stack; forming a second stack on the first stack, the second stack including a third material layer and a fourth material layer alternately stacked; forming a dummy contact hole in the second stack, the dummy contact hole being connected to the dummy hole and having a larger width than the dummy hole; forming a contact hole in the second stack, the contact hole exposing the first material layer and the third material layer, respectively; forming an isolation trench by etching the first material layer and the third material layer through the dummy contact hole and the dummy hole; forming an isolation insulating structure in the isolation trench; forming a dummy contact plug in the isolation insulating structure; and forming a contact plug in the contact hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and Figure 1B is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A as well as Figure 2B , Figure 3B , Figure 4B , Figure 5B and Figure 6B 2 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0009] Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A as well as Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B and Fig. 17B 2 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0010] Various embodiments of the present disclosure are directed to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0011] By stacking memory cells three-dimensionally, the integration degree of a semiconductor device can be improved. A semiconductor device having a stable structure and improved reliability can also be provided.

[0012] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0013] Figure 1A and Figure 1B is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 1A is a plan view, and Figure 1B It is along Figure 1A A cross-sectional view taken along line AA′.

[0014] Reference Figure 1A and Figure 1B The semiconductor device may include a gate structure GST, a channel structure CH, a dummy gate structure D_GST, a dummy channel structure D_CH, and an isolation insulating structure IS. The semiconductor device may also include at least one of a slit structure SLS, a contact plug CP, a chip protection structure CG, a first insulating spacer SP1, and a second insulating spacer SP2.

[0015] The semiconductor device may be a chip and may include a protection region GR defined at the edge of the chip. A plurality of planes may be located in the protection region GR. Each plane may include a plurality of memory blocks MB. Each memory block MB may include a block central region BCR and a block edge region BER. The block edge region BER may be located between the block central region BCR and the protection region GR. The gate structure GST may be located in the block central region BCR, and the dummy gate structure D_GST may be located in the block edge region BER and the protection region GR.

[0016] The gate structure GST may include alternately stacked gate lines 11G and insulating layers 12. The gate lines 11G may be word lines, source selection lines, drain selection lines, etc. The gate lines 11G may each include a conductive material such as, for example, polysilicon or metal. The insulating layer 12 insulates the stacked gate lines 11G from each other. The insulating layers 12 may each include an insulating material such as, for example, oxide or nitride. In some embodiments, the insulating layers 12 may each include a gap.

[0017] The gate structure GST may include a cell region CR and a contact region CTR. Figure 1B As shown. The cell region CR may be a region where a memory cell is located. The contact region CTR may be a region where an interconnection structure such as a contact plug and a line is located. The interconnection structure may provide a path for transmitting a bias voltage for driving the stacked memory cell.

[0018] The channel structure CH may extend through the gate structure GST. The channel structure CH may be located in the cell region CR of the gate structure GST. The channel structure CH may include at least one of a channel layer 13, a memory layer 14, and an insulating core 15. The memory layer 14 may include a floating gate, polysilicon, a charge trapping material, a nitride, or a variable resistance material, etc. For reference, some of the channel structures CH that penetrate the gate structure GST may be dummy channel structures. According to an example, the channel structure CH positioned adjacent to the contact region CTR among the channel structures CH may be a dummy channel structure. The channel structure CH positioned adjacent to the dummy gate structure D_GST among the channel structures CH may be a dummy channel structure.

[0019] The contact plug CP may extend through the gate structure GST and may be electrically connected to the gate line 11G. The contact plug CP may be located in the contact region CTR of the gate structure GST. The contact plug CP may include a conductive plug 16 and a barrier layer 17 surrounding the conductive plug 16. The conductive plug 16 may include a metal such as, for example, tungsten or molybdenum. The barrier layer 17 may include a metal nitride such as, for example, titanium nitride. The first insulating spacer SP1 may surround the sidewall of the contact plug CP. The first insulating spacer SP1 may include an insulating material such as, for example, an oxide or a nitride.

[0020] The dummy gate structure D_GST may include stacked dummy gate lines 11D. The dummy gate lines 11D may be located at a height corresponding to the gate lines 11G. The insulating layer 12 may extend between the dummy gate lines 11D, and the dummy gate lines 11D and the insulating layer 12 may be alternately stacked. The dummy gate lines 11D may each include a conductive material such as, for example, polysilicon or metal. The gate structure GST and the dummy gate structure D_GST may be adjacent to each other in the first direction I.

[0021] The dummy gate structure D_GST may include a protection region GR and an edge region ER. The edge region ER may be located between the protection region GR and the cell region CR. The dummy channel structure D_CH may be located in the edge region ER. The chip protection structure CG may be located in the protection region GR.

[0022] At least a portion of the dummy gate structure D_GST may include a sacrificial layer instead of the dummy gate line 11D. For example, the sacrificial layer may be a layer left without being replaced by the dummy gate line 11D in the manufacturing process. According to an example, the sacrificial layer and the insulating layer 12 may be alternately stacked in the protection region GR.

[0023] The dummy channel structure D_CH may extend through the edge region ER of the dummy gate structure D_GST. The dummy channel structure D_CH may have a structure similar to that of the channel structure CH. The dummy channel structure D_CH may include at least one of a dummy channel layer 13D, a dummy memory layer 14D, and a dummy insulating core 15D. The dummy memory layer 14D may include a floating gate, polysilicon, a charge trapping material, a nitride, or a variable resistance material, etc.

[0024] The chip protection structure CG may be located at the edge of the chip. The chip protection structure CG may extend through the protection region GR of the dummy gate structure D_GST. The chip protection structure CG may include a conductive material such as, for example, polysilicon or metal. The second insulating spacer SP2 may surround the sidewall of the chip protection structure CG.

[0025] The isolation insulating structure IS may be located between the gate structure GST and the dummy gate structure D_GST. The isolation insulating structure IS may extend in a second direction II intersecting the first direction I, and may electrically isolate the gate structure GST and the dummy gate structure D_GST from each other. A plurality of isolation insulating structures IS may be arranged along the second direction II, and may be isolated from each other.

[0026] The isolation insulating structure IS may include an isolation layer 6. The isolation layer 6 may include a horizontal portion HP and a vertical portion VP. The horizontal portion HP may be stacked between the gate structure GST and the dummy gate structure D_GST. The horizontal portion HP may be positioned to correspond to the gate line 11G and the dummy gate line 11D, and may be located between the gate line 11G and the dummy gate line 11D. The insulating layer 12 may extend between the horizontal portions HP, and the horizontal portions HP and the insulating layer 12 may be alternately stacked. The vertical portion VP may extend through the horizontal portion HP. The isolation layer 6 may include an insulating material such as, for example, an oxide or a nitride.

[0027] The isolation insulating structure IS may include at least one dummy contact plug D_CP. The dummy contact plug D_CP may be located inside the isolation layer 6, and the isolation layer 6 may surround the dummy contact plug D_CP. The dummy contact plug D_CP may be arranged in the second direction II, and the isolation layer 6 may extend in the second direction II while surrounding the sidewall of the dummy contact plug D_CP.

[0028] The dummy contact plug D_CP may have a structure similar to that of the contact plug CP. The dummy contact plug D_CP may include a conductive plug 18 and a barrier layer 19 surrounding the conductive plug 18. The conductive plug 18 may include a metal such as, for example, tungsten or molybdenum. The barrier layer 19 may include a metal nitride such as, for example, titanium nitride. The dummy contact plug D_CP may be located on the horizontal portion HP. The vertical portion VP may extend along the sidewall of the dummy contact plug D_CP.

[0029] The slit structure SLS may be located between the gate structures GST. The slit structure SLS may be located between the memory blocks MB adjacent to each other in the second direction II, and the memory blocks MB adjacent to each other may be electrically isolated from each other by the slit structure SLS. The slit structure SLS may extend from the block central region BCR to the block edge region BER. The slit structure SLS may also extend to the protection region GR. The slit structure SLS may be formed in the slit during the manufacturing process, and the slit may replace the channel of the sacrificial layer with the active gate line 11G or the dummy gate line 11D. The slit structure SLS may extend along the first direction I, and may insulate the gate structures GST adjacent to each other in the second direction II from each other. The slit structure SLS may extend between the isolation insulating structure IS and between the dummy gate structures D_GST.

[0030] The slit structure SLS may include at least one of an insulating material, a conductive material, and a semiconductor material. According to an example, the slit structure SLS may include an insulating material such as, for example, an oxide or a nitride. The slit structure SLS may include a semiconductor material such as, for example, silicon or germanium. In an embodiment, the slit structure SLS may include a source contact structure therein, and the source contact structure may be electrically connected to the source line.

[0031] According to the above structure, the pattern density of the dummy channel structure D_CH set in the edge region ER and the pattern density of the channel structure CH set in the cell region CR can be substantially the same or similar to each other. Therefore, the bending of the stack, slits, etc. in the area with relatively low pattern density in the manufacturing process can be reduced. The shape of the slit structure SLS may not change to compensate for the pattern density difference, and the slit structure SLS may have a uniform width. In addition, by locating the gate structure GST in the block central region BCR and locating the dummy gate structure D_GST in the block edge region BER, the occurrence of wafer warpage can be reduced. Wafer warpage refers to the deformation or distortion of the wafer.

[0032] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A as well as Figure 2B , Figure 3B , Figure 4B , Figure 5B and Figure 6B 1 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, contents overlapping with previously described contents may be omitted.

[0033] Reference Figure 2A and Figure 2B , a first stack ST1 including first material layers 21 and second material layers 22 alternately stacked may be formed. According to an example, the first stack ST1 may be formed in a block central region BCR and a block edge region BER of a memory block. The first material layer 21 may be used to form a gate line. The first material layers 21 may each include a sacrificial material such as a nitride or a conductive material such as, for example, polysilicon or a metal. The second material layers 22 may each include an insulating material such as, for example, an oxide or a nitride.

[0034] Subsequently, a first dummy hole DH1 may be formed in the first stack ST1. The first dummy hole DH1 may be located in the block edge region BER. A first channel hole CHH1 may be formed in the first stack ST1. The first channel hole CHH1 may be located in the block central region BCR. When the first dummy hole DH1 is formed, the first channel hole CHH1 may be formed. The first dummy hole DH1 and the first channel hole CHH1 may be formed simultaneously. The first dummy hole DH1 and the first channel hole CHH1 may be formed in the block edge region BER and the block central region BCR, respectively, with a uniform pattern density.

[0035] Subsequently, a first sacrificial layer 23A may be formed in the first dummy hole DH1. The first sacrificial layers 23A may each include a material having a high etching selectivity with respect to the first material layer 21 and the second material layer 22. A first sacrificial layer 23B may be formed in the first channel hole CHH1. The first sacrificial layers 23B may each include a material having a high etching selectivity with respect to the first material layer 21 and the second material layer 22. When the first sacrificial layer 23A is formed, the first sacrificial layer 23B may be formed.

[0036] Reference Figure 3A and Figure 3B , a second stack ST2 may be formed on the first stack ST1. The second stack ST2 may include a third material layer 31 and a fourth material layer 32 alternately stacked. According to an example, the second stack ST2 may be formed in a block central region BCR and a block edge region BER of a memory block. The third material layer 31 may be used to form a gate line. The third material layers 31 may each include a sacrificial material such as a nitride or a conductive material such as, for example, polysilicon or a metal. The fourth material layers 32 may each include an insulating material such as, for example, an oxide or a nitride.

[0037] Subsequently, a second dummy hole DH2 may be formed in the second stack ST2. The second dummy hole DH2 may be located in the block edge region BER and may be connected to the first dummy hole DH1. The number of the second dummy holes DH2 may be the same as or different from the number of the first dummy holes DH1. According to an example, the number of the second dummy holes DH2 may be less than the number of the first dummy holes DH1, and some of the first dummy holes DH1 may not be connected to the second dummy holes DH2. The second dummy hole DH2 may not be formed in an area where a dummy contact hole is to be formed in a subsequent process. The second dummy hole DH2 may not be formed in a portion of the block edge region BER adjacent to the block central region BCR.

[0038] The second channel hole CHH2 may be formed in the second stack ST2. The second channel hole CHH2 may be located in the block central region BCR and may be connected to the first channel hole CHH1. The second channel hole CHH2 may be formed when the second dummy hole DH2 is formed.

[0039] Reference Figure 4A and Figure 4B , the first sacrificial layer 23A may be removed through the second dummy hole DH2. Thus, the first dummy hole DH1 may be reopened. The first sacrificial layer 23B may be removed through the second channel hole CHH2. Thus, the first channel hole CHH1 may be reopened.

[0040] Subsequently, a channel structure CH may be formed. According to an example, the channel structure CH may be formed in the first channel hole CHH1 and the second channel hole CHH2 connected to each other. The channel structure CH may include at least one of a channel layer 43, a memory layer 44, and an insulating core 45. A dummy channel structure D_CH may be formed. According to an example, the dummy channel structure D_CH may be formed in the first dummy hole DH1 and the second dummy hole DH2 connected to each other. The dummy channel structure D_CH may include at least one of a dummy channel layer 43D, a dummy memory layer 44D, and a dummy insulating core 45D. When the channel structure CH is formed, the dummy channel structure D_CH may be formed. Because the second dummy hole DH2 is not formed in the region where the dummy contact hole D_CTH is to be formed in a subsequent process, the first sacrificial layer 23A may remain in the first dummy hole DH1 of the corresponding region. The dummy channel structure D_CH may not be formed in the corresponding region. Subsequently, a fourth material layer 32 may be additionally formed to cover the channel structure CH.

[0041] Subsequently, the dummy contact hole D_CTH may be formed in the second stack ST2. According to an example, a mask pattern 34 may be formed on the second stack ST2, and the dummy contact hole D_CTH may be formed by etching the second stack ST2 using the mask pattern 34 as an etch barrier.

[0042] In a plan view, the dummy contact hole D_CTH may have a larger size than the first dummy hole DH1. According to an example, the first dummy hole DH1 may have a first width W1, and the dummy contact hole D_CTH may have a second width W2 greater than the first width W1. The dummy contact hole D_CTH may be connected to the plurality of first dummy holes DH1. The dummy contact hole D_CTH may be located in the block edge region BER and may be located between the dummy channel structure D_CH and the channel structure CH. The first dummy hole DH1 and the first sacrificial layer 23A may be exposed through the dummy contact hole D_CTH.

[0043] Reference Figure 5A and Figure 5B , the first sacrificial layer 23A may be removed through the dummy contact hole D_CTH. Thus, the first dummy hole DH1 may be reopened. Subsequently, the first material layer 21 and the third material layer 31 exposed through the first dummy hole DH1 and the dummy contact hole D_CTH may be etched. The first material layer 21 between adjacent first dummy holes DH1 may be removed, and adjacent first dummy holes DH1 may be connected to each other. Irregularities may be formed on the sidewalls of the dummy contact hole D_CTH. Thus, the isolation trench IST may be formed.

[0044] When a dummy channel structure D_CH is formed in the region where the isolation trench IST is to be formed, the dummy channel structure D_CH should be removed to form the isolation trench IST. According to an embodiment of the present disclosure, since the second dummy hole DH2 is not formed in the region where the isolation trench IST is to be formed, the dummy channel structure D_CH may not be formed in the corresponding region. Therefore, the isolation trench IST may be formed without removing the dummy channel structure D_CH.

[0045] The first material layer 21 formed in the block central region BCR and the first material layer 21 formed in the block edge region BER may be isolated from each other by the isolation trench IST. The third material layer 31 formed in the block central region BCR and the third material layer 31 formed in the block edge region BER may be isolated from each other by the isolation trench IST. The first material layer 21 and the third material layer 31 may be selectively etched, and the second material layer 22 and the fourth material layer 32 may maintain their shapes extending from the block central region BCR to the block edge region BER.

[0046] Reference Fig. 6A and Figure 6B, an isolation insulating structure IS may be formed in the isolation trench IST. First, an isolation layer 36 may be formed in the isolation trench IST. The isolation layer 36 may include a material having a high etching selectivity relative to the first material layer 21 and the third material layer 31. The isolation layer 36 may be formed by depositing an insulating material such as, for example, an oxide or a nitride. The isolation layer 36 may be formed to a thickness sufficient to fill the first dummy hole DH1, and may be formed along the inner surface of the dummy contact hole D_CTH. The central area of ​​the dummy contact hole D_CTH may not be filled with the isolation layer 36, and may be open. Subsequently, a dummy contact plug D_CP may be formed in the isolation layer 36. The dummy contact plug D_CP may be located in the dummy contact hole D_CTH. According to an example, a barrier layer 39 may be formed in the isolation layer 36, and a conductive plug 38 may be formed to gap-fill the space defined by the barrier layer 39.

[0047] The first material layer 21 and the third material layer 31 may be replaced with the fifth material layer 41. The replacement process may be performed through a slit. The fifth material layers 41 may each include a metal such as, for example, tungsten or molybdenum, and may be a gate line 41G or a dummy gate line 41D. According to an example, the first material layer 21 and the third material layer 31 may be selectively etched, and the fifth material layer 41 may be formed in the regions where the first material layer 21 and the third material layer 31 are removed, respectively.

[0048] Thus, a gate structure GST located in the block central region BCR and a dummy gate structure D_GST located in the block edge region BER may be formed. The gate structure GST may include alternately stacked gate lines 41G and second material layers 22 and alternately stacked gate lines 41G and fourth material layers 32. The dummy gate structure D_GST may include alternately stacked dummy gate lines 41D and second material layers 22 and alternately stacked dummy gate lines 41D and fourth material layers 32.

[0049] According to the above-described manufacturing method, when the channel structure CH is formed in the block central region BCR, a dummy channel structure D_CH may be formed in the block edge region BER. By making the pattern density of the block central region BCR and the block edge region BER uniform, the bending of the end of the stack ST when the first material layer 21 and the third material layer 31 are replaced with the fifth material layer 41 may be reduced. In addition, the isolation insulating structure IS may be formed using the process of forming the channel structure CH.

[0050] The exposed first material layer 21 and the third material layer 31 around the first dummy hole DH1 and the dummy contact hole D_CTH may be replaced with the isolation layer 36. Thus, the first material layer 21 and the third material layer 31 may be removed in advance in a portion of the block edge region BER adjacent to the block central region BCR. Therefore, the dummy gate structure D_GST and the gate structure GST may be isolated from each other by the isolation insulating structure IS.

[0051] Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A as well as Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B and Fig. 17B 1 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, contents overlapping with previously described contents may be omitted.

[0052] Reference Fig. 7A and Figure 7B , a first stack ST1 including alternating first material layers 51 and second material layers 52 may be formed. According to an example, the first stack ST1 may be formed in a central region and an edge region of a memory block. The first stack ST1 may include a cell region CR, a contact region CTR, and an edge region ER arranged along a first direction I (see Fig. 8A ). The edge region ER may be an end portion or an edge region of the first stack ST1. The cell region CR may be located between the edge region ER and the contact region CTR.

[0053] Subsequently, a first dummy hole DH1 may be formed in the first stack ST1. The first dummy hole DH1 may be located in the edge region ER. A first channel hole CHH1 may be formed in the first stack ST1. The first channel hole CHH1 may be located in the cell region CR. When the first dummy hole DH1 is formed, the first channel hole CHH1 may be formed. The first dummy hole DH1 and the first channel hole CHH1 may be formed simultaneously. The first dummy hole DH1 and the first channel hole CHH1 may be formed in the edge region ER and the cell region CR, respectively, with a uniform pattern density.

[0054] Subsequently, a first sacrificial layer 53A may be formed in the first dummy hole DH1. A first sacrificial layer 53B may be formed in the first channel hole CHH1. When the first sacrificial layer 53A is formed, the first sacrificial layer 53B may be formed. The first sacrificial layer 53A and the first sacrificial layer 53B may be formed simultaneously.

[0055] Reference Fig. 8A and Figure 8B , a second stack ST2 may be formed on the first stack ST1. The second stack ST2 may include third material layers 61 and fourth material layers 62 alternately stacked. The second stack ST2 may include a cell region CR, a contact region CTR, and an edge region ER. The edge region ER may be an end portion of the second stack ST2. The cell region CR may be located between the edge region ER and the contact region CTR.

[0056] Subsequently, a second dummy hole DH2 may be formed in the second stack ST2. The second dummy hole DH2 may be located in the edge region ER and may be connected to the first dummy hole DH1. The second dummy hole DH2 may not be formed in a portion of the edge region ER adjacent to the cell region CR. A second channel hole CHH2 may be formed in the second stack ST2. The second channel hole CHH2 may be located in the cell region CR and may be connected to the first channel hole CHH1. When the second dummy hole DH2 is formed, the second channel hole CHH2 may be formed.

[0057] Subsequently, a second sacrificial layer 63A may be formed in the second dummy hole DH2. The second sacrificial layers 63A may each include a material having a high etching selectivity with respect to the third material layer 61 and the fourth material layer 62. A second sacrificial layer 63B may be formed in the second channel hole CHH2. The second sacrificial layers 63B may each include a material having a high etching selectivity with respect to the third material layer 61 and the fourth material layer 62. When the second sacrificial layer 63A is formed, the second sacrificial layer 63B may be formed.

[0058] Reference Fig.9A and Fig. 9B , the first dummy hole DH1 and the second dummy hole DH2 may be reopened by removing the second sacrificial layer 63A and the first sacrificial layer 53A. The first channel hole CHH1 and the second channel hole CHH2 may be reopened by removing the second sacrificial layer 63B and the first sacrificial layer 53B. When the first dummy hole DH1 and the second dummy hole DH2 are reopened, the first channel hole CHH1 and the second channel hole CHH2 may be reopened.

[0059] Subsequently, a dummy channel structure D_CH may be formed in the first dummy hole DH1 and the second dummy hole DH2 connected to each other. A channel structure CH may be formed in the first channel hole CHH1 and the second channel hole CHH2 connected to each other. The channel structure CH may include at least one of a channel layer 64, a memory layer 65, and an insulating core 66. The dummy channel structure D_CH may include at least one of a dummy channel layer 64D, a dummy memory layer 65D, and a dummy insulating core 66D. When the channel structure CH is formed, the dummy channel structure D_CH may be formed.

[0060] Subsequently, a hard mask pattern 67 may be formed on the second stack ST2. According to an example, the hard mask pattern 67 may be formed by forming a hard mask layer on the second stack ST2 and etching the hard mask layer using the first mask pattern 71 as an etching barrier. The hard mask pattern 67 may include an opening OPA corresponding to a position where a contact plug is to be formed in a subsequent process and an opening OPB corresponding to a position where a dummy contact plug is to be formed in a subsequent process. The second stack ST2 may be exposed through the openings OPA and OPB. In the process of forming the hard mask pattern 67, the second stack ST2 may be partially etched, and a preliminary contact hole PHA connected to the opening OPA and a preliminary contact hole PHB connected to the opening OPB may be formed. The hard mask pattern 67 may include polysilicon, and the first mask pattern 71 may include a photoresist.

[0061] Reference Fig. 10A and Fig. 10B A sacrificial layer 68 may be formed on the hard mask pattern 67, and a second mask pattern 72 may be formed on the sacrificial layer 68. The sacrificial layer 68 may be formed in the preliminary contact holes PHA and PHB, and may include voids V respectively located in the preliminary contact holes PHA and PHB. The sacrificial layer 68 may include amorphous carbon, and the second mask pattern 72 may include a photoresist.

[0062] Reference Fig.11A and Fig. 11B , the sacrificial layer 68 may be etched using the second mask pattern 72 as an etching barrier. Thus, at least one of the preliminary contact holes PHA may be exposed, and the preliminary contact hole PHB may be exposed. Subsequently, the second stack ST2 may be etched using the second mask pattern 72 and the hard mask pattern 67 as etching barriers. Thus, the exposed preliminary contact holes PHA and PHB may extend into the second stack ST2. A contact hole CTH may be formed in the contact region CTR, and a dummy contact hole D_CTH may be formed in the edge region ER. The contact hole CTH and the dummy contact hole D_CTH may have substantially the same depth.

[0063] Reference Fig. 12A and Fig. 12B , the second mask pattern 72 may be reduced. By etching the second mask pattern 72 to expand the opening, the number of exposed preliminary contact holes PHA may be increased. Subsequently, the sacrificial layer 68 may be etched using the reduced second mask pattern 72A as an etching barrier. Subsequently, the second stack ST2 may be etched using the second mask pattern 72A and the hard mask pattern 67 as etching barriers. Thus, the previously formed contact holes CTH and the dummy contact holes D_CTH may extend into the second stack ST2. The newly exposed preliminary contact holes PHA may extend into the second stack ST2.

[0064] The process of reducing the second mask pattern 72A and etching the sacrificial layer 68 and the second stack ST2 may be repeatedly performed. Thus, contact holes CTH that expose the third material layer 61 included in the second stack ST2 may be formed. At least one of the contact holes CTH may extend into the first stack ST1 and may expose at least one of the first material layers 51. In addition, a dummy contact hole D_CTH that exposes the first sacrificial layer 53A may be formed. When the contact hole CTH is formed, the dummy contact hole D_CTH may be formed. As the contact hole CTH extends into the second stack ST2, the dummy contact hole D_CTH may also extend into the second stack ST2. When the contact hole CTH extends into the first stack ST1, the dummy contact hole D_CTH may also extend into the first stack ST1. The contact hole CTH having the largest depth among the contact holes CTH and the dummy contact hole D_CTH may have substantially the same depth. The dummy contact hole D_CTH may expose the first sacrificial layer 53A and may be connected to the first dummy hole DH1.

[0065] For reference, as the processes of reducing the second mask pattern 72A and etching the sacrificial layer 68 and the second stack ST2 are repeatedly performed, the upper surface of the hard mask pattern 67 may be etched. Irregularities, a step structure, etc. may be formed on the upper surface of the hard mask pattern 67.

[0066] Reference Fig.13A and Fig. 13B , the second mask pattern 72 and the sacrificial layer 68 may be removed. Subsequently, the first sacrificial layer 53A in the first dummy hole DH1 may be removed through the dummy contact hole D_CTH. For reference, when the second mask pattern 72 or the sacrificial layer 68 is removed, the first sacrificial layer 53A may be removed.

[0067] Subsequently, a third mask pattern 73 may be formed. The third mask pattern 73 may cover the edge region ER and the cell region CR, and may expose a portion of the contact region CTR. The third mask pattern 73 may cover some of the contact holes CTH and expose other contact holes CTH. The third mask pattern 73 may be formed in the first dummy hole DH1 and the dummy contact hole D_CTH, and may be formed in some of the contact holes CTH. The third mask pattern 73 may include a photoresist.

[0068] Subsequently, the first stack ST1 may be etched using the third mask pattern 73 and the hard mask pattern 67 as an etching barrier. Thus, the other contact holes CTH may extend into the first stack ST1. The extended other contact holes CTH may expose the first material layer 51, respectively. Therefore, the contact holes CTH may have different depths and may expose the first material layer 51 and the third material layer 61, respectively.

[0069] Reference Fig.14A and Fig. 14B , the third mask pattern 73 may be removed. Subsequently, a fourth mask pattern 74 may be formed. The fourth mask pattern 74 may cover the contact region CTR and may expose the edge region ER. The fourth mask pattern 74 may cover at least a portion of the cell region CR. Thus, the first dummy hole DH1 and the dummy contact hole D_CTH may be exposed. The fourth mask pattern 74 may be formed in the contact hole CTH. The fourth mask pattern 74 may include a photoresist.

[0070] Subsequently, the first material layer 51 and the third material layer 61 may be etched through the dummy contact hole D_CTH and the first dummy hole DH1 , Thus, the isolation trench IST may be formed in the first and second stacks ST1 and ST2 .

[0071] By selectively etching the first material layer 51, the first dummy hole DH1 can be expanded in the horizontal direction and can be connected to each other. The expanded first dummy hole E_DH1 can be located in the first stack ST1. By selectively etching the third material layer 61, the dummy contact hole D_CTH can be expanded in the horizontal direction. The expanded dummy contact hole E_DCTH can be located in the second stack ST2. Depending on the interval between the dummy contact holes D_CTH adjacent to each other in the second direction II, the expanded dummy contact holes E_DCTH can be connected or isolated from each other. Thus, an isolation trench IST including the expanded first dummy hole E_DH1 and the expanded dummy contact hole E_DCTH can be formed.

[0072] Reference Fig.15A and Fig. 15B, an insulating liner 76 may be formed in the isolation trench IST. The insulating liner 76 may partially fill the isolation trench IST. According to an example, the insulating liner 76 may be filled in the enlarged first dummy hole E_DH1 and may extend along the inner wall of the enlarged dummy contact hole E_DCTH. The central area of ​​the enlarged dummy contact hole E_DCTH may be open without being filled with the insulating liner 76.

[0073] An insulating liner 76 may be formed in the contact hole CTH. The insulating liner 76 may be formed along the inner surface of the contact hole CTH and may partially fill the contact hole CTH. The insulating liner 76 may extend along the upper surface of the second stack ST2. The insulating liner 76 formed in the isolation trench IST and the insulating liner 76 formed in the contact hole CTH may be connected to each other.

[0074] The insulating liner 76 may include a material having a high etching selectivity relative to the first material layer 51 and the third material layer 61. The insulating liner 76 may include an insulating material such as, for example, oxide or nitride. By forming the insulating liner 76 using an insulating material, the generation of bridges between gate lines formed in subsequent processes can be reduced.

[0075] Subsequently, a sacrificial layer 77 may be formed in the insulating liner 76. The sacrificial layer 77 may be located in the enlarged dummy contact hole E_DCTH and the contact hole CTH, respectively. The sacrificial layer 77 may include a material having an etching selectivity with respect to the insulating liner 76. According to an example, the sacrificial layer 77 may include polysilicon.

[0076] Reference Fig.16A and Fig. 16B , the first material layer 51 and the third material layer 61 may be replaced with a fifth material layer 81. According to an example, a slit SL extending through the second stack ST2 and the first stack ST1 may be formed. Subsequently, an opening may be formed by selectively etching the first material layer 51 and the third material layer 61 through the slit SL. When etching the first material layer 51 and the third material layer 61, the insulating liner 76 may be used as an etching stop layer. Subsequently, a fifth material layer 81 may be formed in the opening. The fifth material layer 81 may be a gate line 81G or a dummy gate line 81D. Thus, a gate structure GST located in the cell region CR and the contact region CTR may be formed. A dummy gate structure D_GST located in the edge region ER may be formed.

[0077] Reference Fig.17A and Fig. 17B, the sacrificial layer 77 can be removed. According to an example, a dip-out process can be used to remove the sacrificial layer 77. Subsequently, insulating spacers 76A can be formed in the contact holes CTH, respectively. An isolation layer 76B can be formed in the isolation trench IST. According to an example, the insulating liner 76 can be etched using an etch-back process. Thus, a portion of the insulating liner 76 formed on the upper surface of the gate structure GST and a portion of the insulating liner 76 formed on the upper surface of the dummy gate structure D_GST can be removed. A portion of the insulating liner 76 formed on the bottom surface of the contact hole CTH can be removed, and the gate line 81G can be exposed. The portion of the insulating liner 76 formed in the isolation trench IST can be locally etched.

[0078] Subsequently, a contact plug CP may be formed. The contact plugs CP may be respectively located in the contact holes CTH and may be electrically connected to the gate line 81G. A barrier layer 87 may be formed in the contact hole CTH, and a conductive plug 86 may be formed to gap-fill the space defined by the barrier layer 87. A dummy contact plug D_CP may be formed. The dummy contact plug D_CP may be located in the dummy contact hole D_CTH. A barrier layer 89 may be formed in the isolation layer 76B, and a conductive plug 88 may be formed to gap-fill the space defined by the barrier layer 89. Thus, an isolation insulating structure IS including the isolation layer 76B and the dummy contact plug D_CP may be formed.

[0079] The dummy contact plug D_CP may have an electrically floating state. When the dummy contact plug D_CP is formed, the contact plug CP may also be formed.

[0080] According to the above-mentioned manufacturing method, when the channel structure CH is formed in the cell region CR, a dummy channel structure D_CH may be formed in the edge region ER. By making the pattern density of the cell region CR and the edge region ER uniform, the bending of the first stack ST1 and the second stack ST2 when forming the slit SL may be reduced. The shape of the slit SL may not change to prevent the bending of the first stack ST1 and the second stack ST2. The slit SL may be formed in a line shape with a uniform width. In addition, the isolation insulating structure IS may be formed using the process of forming the channel structure CH and the process of forming the contact plug CP.

[0081] Although the embodiments according to the technical ideas of the present disclosure have been described above with reference to the accompanying drawings, this is only used to describe the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the technical ideas of the present disclosure defined in the attached claims, technicians in the field to which the present disclosure belongs can make various types of replacements, modifications and variations to the embodiments, and it should be interpreted that these replacements, modifications and variations belong to the scope of the present disclosure. In addition, the embodiments can be combined to form additional embodiments.

[0082] CROSS-REFERENCE TO RELATED APPLICATIONS

[0083] This application claims priority to Korean Patent Application No. 10-2023-0094449, filed on Jul. 20, 2023, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: A gate structure, the gate structure comprising alternately stacked gate lines and insulating layers; a channel structure extending through the gate structure; A dummy gate structure, the dummy gate structure comprising stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure; as well as An isolation insulating structure includes a horizontal portion stacked between the gate structure and the dummy gate structure and a vertical portion extending through the horizontal portion.

2. The semiconductor device according to claim 1, wherein The horizontal portion is positioned to correspond to the gate line and the dummy gate line.

3. The semiconductor device according to claim 2, wherein: The insulating layer extends between the horizontal portions and between the dummy gate lines.

4. The semiconductor device according to claim 1, wherein The isolation and insulation structure comprises: an isolation layer, the isolation layer comprising the horizontal portion and the vertical portion; and A dummy contact plug is located in the isolation layer.

5. The semiconductor device according to claim 4, wherein: The dummy contact plug is located on the horizontal portion, and the vertical portion extends along a sidewall of the dummy contact plug.

6. The semiconductor device according to claim 1, wherein In a memory block, the dummy gate structure and the isolation insulating structure are located in a block edge region, and the gate structure is located in a block central region. 7 . The semiconductor device according to claim 1 , further comprising a contact plug extending through the gate structure and electrically connected to the gate line. 8 . The semiconductor device according to claim 7 , further comprising an insulating spacer surrounding a sidewall of the contact plug.

9. The semiconductor device according to claim 1, further comprising a chip protection structure, wherein: The dummy gate structure is located between the chip protection structure and the isolation insulation structure.

10. The semiconductor device according to claim 1, wherein The gate structure extends in a first direction, and the isolation insulating structure extends in a second direction crossing the first direction.

11. The semiconductor device according to claim 10, wherein The isolation insulating structure includes dummy contact structures arranged in the second direction.

12. A semiconductor device, comprising: A gate structure, the gate structure comprising stacked gate lines; a channel structure extending through the gate structure; contact plugs extending through the gate structure and connected to the gate lines respectively; a dummy gate structure, the dummy gate structure being adjacent to the gate structure in a first direction and comprising stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure; as well as An isolation insulating structure is located between the gate structure and the dummy gate structure, extends in a second direction crossing the first direction, and includes dummy contact plugs arranged in the second direction.

13. The semiconductor device according to claim 12, wherein: The isolation insulating structure includes an isolation layer including a horizontal portion between the gate line and the dummy gate line and a vertical portion extending through the horizontal portion.

14. The semiconductor device according to claim 13, wherein: The dummy contact plug is located on the horizontal portion, and the vertical portion surrounds a sidewall of the dummy contact plug. 15 . The semiconductor device according to claim 12 , further comprising a chip protection structure extending through the dummy gate structure.

16. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a first stack including alternately stacked first material layers and second material layers; forming a dummy hole in the first stack; forming a second stack on the first stack, the second stack comprising third material layers and fourth material layers alternately stacked; forming a dummy contact hole in the second stack, the dummy contact hole being connected to the dummy hole; forming an isolation trench by etching the first material layer and the third material layer through the dummy contact hole and the dummy hole; as well as An isolation insulating structure is formed in the isolation trench.

17. The manufacturing method according to claim 16, further comprising the following steps: forming a first channel hole in the first stack; and A second channel hole is formed in the second stack, the second channel hole being connected to the first channel hole.

18. The manufacturing method according to claim 17, wherein: When the dummy hole is formed, the first channel hole is formed.

19. The manufacturing method according to claim 17, wherein: When forming the dummy contact hole, the second channel hole is formed.

20. The manufacturing method according to claim 16, wherein: In a plan view, the dummy contact hole has a larger size than the dummy hole.

21. The manufacturing method according to claim 16, wherein: The steps of forming the isolation insulating structure include the following steps: forming an isolation layer in the isolation trench; and A dummy contact plug is formed in the isolation layer.

22. The manufacturing method according to claim 21, wherein: The dummy contact plug is located in the dummy contact hole.

23. The manufacturing method according to claim 16, further comprising the following steps: replacing the first material layer and the third material layer with a fifth material layer; as well as A contact plug electrically connected to the fifth material layer is formed.

24. The manufacturing method according to claim 23, wherein: When forming the contact plug, a dummy contact plug is formed in the isolation insulating structure.

25. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a first stack including alternately stacked first material layers and second material layers; forming a dummy hole in the first stack; forming a second stack on the first stack, the second stack comprising third material layers and fourth material layers alternately stacked; forming a dummy contact hole in the second stack, the dummy contact hole being connected to the dummy hole and having a greater width than the dummy hole; forming contact holes in the second stack, the contact holes exposing the first material layer and the third material layer respectively; forming an isolation trench by etching the first material layer and the third material layer through the dummy contact hole and the dummy hole; forming an isolation insulating structure in the isolation trench; forming a dummy contact plug in the isolation insulating structure; as well as A contact plug is formed in the contact hole.

26. The manufacturing method according to claim 25, further comprising the following steps: forming a hard mask pattern on the second stack, The dummy contact hole and the contact hole are formed by etching the second stack using the hard mask pattern as an etching barrier.

27. The manufacturing method according to claim 25, wherein: When forming the dummy contact hole, the contact hole is formed.

28. The manufacturing method according to claim 25, wherein: The step of forming the contact hole comprises the following steps: forming a contact hole exposing the third material layer; forming a mask pattern covering the dummy contact hole and some of the contact holes; and The exposed contact holes are extended into the first stack.

29. The manufacturing method according to claim 25, wherein: The step of forming the isolation trench comprises the following steps: forming an enlarged dummy hole by etching the first material layer through the dummy hole; and An enlarged dummy contact hole is formed by etching the third material layer through the dummy contact hole.

30. The manufacturing method according to claim 29, further comprising the following steps: forming an insulating liner in the isolation trench and the contact hole; forming a sacrificial layer in the isolation trench and the contact hole; as well as The first material layer and the third material layer are replaced with a fifth material layer.

31. The manufacturing method according to claim 30, wherein: The insulating liner fills the enlarged dummy contact hole and extends along an inner wall of the enlarged dummy contact hole.

32. The manufacturing method according to claim 30, further comprising the following steps: removing the sacrificial layer; as well as An insulating spacer is formed in the contact hole by etching the insulating liner.

33. The manufacturing method according to claim 30, further comprising the following steps: removing the sacrificial layer; as well as An isolation layer located in the isolation trench is formed by etching the insulation liner.

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