Semiconductor device and preparation method thereof, and storage system

Abstract

The invention provides a semiconductor device and a preparation method. The semiconductor device includes a first device structure, and a first contact structure and a second contact structure on a first side of the first device structure. The first contact structure extends along a first direction and is connected with the first device structure; the second contact structures extend in the first direction and are connected with the first contact structures, and the size of the end faces, connected with the second contact structures, of the first contact structures is larger than that of the end faces, connected with the first contact structures, of the second contact structures.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and manufacturing, and more specifically, to a semiconductor device, a method for preparing a semiconductor device, and a storage system. Background Art

[0002] Taking 3D memory as an example, in order to further accelerate the development and application of semiconductor devices, it is necessary to continuously improve the bit density of semiconductor devices and reduce their bit cost at the same time. However, as the structure of semiconductor devices continues to develop towards high layers and high density, the size of the peripheral circuits included in it has become an increasingly critical factor in determining the size of the entire chip.

[0003] Therefore, how to effectively reduce the size of peripheral circuits without affecting the overall performance of semiconductor devices is a problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a semiconductor device and a method for manufacturing the same which can at least partially solve the above-mentioned problems existing in the related art.

[0005] On the one hand, the present application provides a semiconductor device, which includes: a first device structure; and a first contact structure and a second contact structure located on a first side of the first device structure, the first contact structure extending along a first direction and connected to the first device structure; and the second contact structure extending along the first direction and connected to multiple first contact structures, wherein the size of an end surface where the first contact structure is connected to the second contact structure is larger than the size of an end surface where the second contact structure is connected to the first contact structure.

[0006] In one embodiment of the present application, the first contact structure is connected to the contact area of ​​the first device structure, wherein the type of the contact area includes at least one of a gate area, a source area, and a drain area; and multiple first contact structures connected to the same second contact structure are connected to contact areas of the same type.

[0007] In one embodiment of the present application, the semiconductor device also includes a second device structure, which includes: a memory cell array, and a first interconnection structure or a third contact structure connected to the memory cell array, wherein the second contact structure is connected to the first interconnection structure or the third contact structure.

[0008] In one embodiment of the present application, the first contact structure includes a first end face connected to the first device structure and a second end face connected to the second contact structure, wherein the size of the second end face is larger than the size of the first end face.

[0009] In one embodiment of the present application, the second contact structure includes a plurality of connection parts and a root part connected to the plurality of connection parts, wherein at least one of the plurality of connection parts includes a third end face and a fourth end face opposite to each other in the first direction, the third end face is connected to the first contact structure, and the fourth end face is connected to the root part.

[0010] In one embodiment of the present application, the semiconductor device further includes a substrate and a fourth contact structure, wherein the substrate is located on a second side of the first device structure opposite to the first side, wherein the fourth contact structure extends into the substrate along the first direction.

[0011] In one embodiment of the present application, the second contact structure is connected to the fourth contact structure in the first direction, wherein the size of the end surface where the fourth contact structure is connected to the second contact structure is larger than the size of the end surface where the second contact structure is connected to the fourth contact structure.

[0012] In one embodiment of the present application, the semiconductor device also includes a fifth contact structure, which extends along the first direction and is connected to the first contact structure or the fourth contact structure, wherein the size of the end surface where the first contact structure is connected to the fifth contact structure is larger than the size of the end surface where the fifth contact structure is connected to the first contact structure; and the size of the end surface where the fourth contact structure is connected to the fifth contact structure is larger than the size of the end surface where the fifth contact structure is connected to the fourth contact structure.

[0013] In one embodiment of the present application, the semiconductor device also includes a second device structure, wherein the second device structure includes: a memory cell array; and a first interconnect structure or a third contact structure connected to the memory cell array, wherein the fifth contact structure is connected to the first interconnect structure or the third contact structure.

[0014] In one embodiment of the present application, the semiconductor device also includes an interconnection layer and a sixth contact structure, wherein the second contact structure and the sixth contact structure both extend in the interconnection layer along the first direction; and the depth of the second contact structure in the first direction is greater than the depth of the sixth contact structure in the first direction.

[0015] In one embodiment of the present application, the semiconductor device also includes a second device structure, wherein the second device structure includes: a memory cell array; and a first interconnect structure or a third contact structure connected to the memory cell array, wherein the sixth contact structure is connected to the first interconnect structure or the third contact structure.

[0016] In one embodiment of the present application, a dimension D1 of an end surface where the first contact structure is connected to the first device structure and a depth H1 of the first contact structure in the first direction satisfy: 1 / 8≤D1 / H1≤1 / 7.

[0017] In one embodiment of the present application, a dimension D2 of an end surface where the second contact structure is connected to the first contact structure and a depth H2 of the second contact structure in the first direction satisfy: 1 / 8≤D2 / H2≤1 / 7.

[0018] In one embodiment of the present application, a depth of the second contact structure in the first direction is less than or equal to a depth of the first contact structure in the first direction.

[0019] On the other hand, the present application provides a method for preparing a semiconductor device, the method comprising: forming a first device structure and a first contact structure extending to the first device structure along a first direction; forming an interconnection layer covering at least the first device structure and the first contact structure, and forming a second initial contact hole in the interconnection layer extending to the first contact structure along the first direction; removing a portion of the sidewalls of a plurality of the second initial contact holes to form a second contact hole; and filling the second contact hole to form a second contact structure connected to the plurality of the first contact structures, wherein a radial dimension of a portion of the first contact structure close to the second initial contact hole is greater than a radial dimension of a portion of the second initial contact hole close to the first contact structure.

[0020] In one embodiment of the present application, removing a portion of the side walls of multiple second initial contact holes to form a second contact hole includes: filling the multiple second initial contact holes with a first sacrificial filling layer, wherein at least two of the multiple second initial contact holes are adjacent in a plane perpendicular to the first direction and have adjacent side walls adjacent to each other; and removing a portion of the adjacent side walls along the first direction to form the second contact hole.

[0021] In one embodiment of the present application, forming the first contact structure includes: forming an isolation covering layer covering at least the first device structure, and forming a first contact hole in the isolation covering layer extending along the first direction to a contact area of ​​the first device structure; and filling the first contact hole to form the first contact structure, wherein the type of the contact area includes at least one of a gate area, a source area, and a drain area; and after forming the first contact hole, the method further includes doping the contact area of ​​the first device structure through the first contact hole.

[0022] In one embodiment of the present application, a plurality of first contact structures corresponding to a plurality of the second initial contact holes whose sidewalls are partially removed are connected to contact regions of the same type.

[0023] Another aspect of the present application provides a storage system, which includes a controller and the semiconductor device provided in one aspect of the present application, and the controller is used to store data in the semiconductor device.

[0024] According to the semiconductor device, the method for preparing the semiconductor device and the storage system provided by at least one embodiment of the present application, the first device structure of the semiconductor device is connected to the second device structure or the back-end metal wire of the semiconductor device through the first contact structure and the second contact structure located on one side of the first device structure. Among them, the first contact structure is connected to the first device structure, and the second contact structure is connected to multiple first contact structures, so that the size of the contact structure in the peripheral circuit of the external semiconductor device can be effectively reduced while stabilizing the comprehensive performance of the semiconductor device. In addition, the size of the end surface where the first contact structure is connected to the second contact structure is larger than the size of the end surface where the second contact structure is connected to the first contact structure, which can enhance the effect of reducing the size of the contact structure of the peripheral circuit while achieving stable connection between the first contact structure and the second contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0026] Figure 1 is a flow chart of a method for preparing a semiconductor device according to one embodiment of the present application; and

[0027] Figures 2 to 15 They are respectively process schematic diagrams of a preparation method according to one embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first contact structure discussed in this application may also be referred to as the second contact structure, the first side may also be referred to as the second side, and vice versa.

[0030] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0031] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0032] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0033] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0034] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0035] Figure 1is a partial top view of a semiconductor device 1000 according to one embodiment of the present application. Figure 2 yes Figure 1 The semiconductor device is shown as a schematic cross-sectional view taken along line AA′. Figure 3 yes Figure 1 The semiconductor device is shown as a schematic cross-sectional view taken along line BB′.

[0036] like Figures 1 to 3 As shown, the semiconductor device 1000 may include: a first device structure 200 and a first contact structure 300 and a second contact structure 400 located at a first side 01 of the first device structure 200, wherein the first device structure 200 is as shown in FIG. Figure 2 and Figure 3 The x-direction, y-direction and z-direction are perpendicular to each other. The first contact structure 300 extends along the first direction (z-direction) and is connected to the first device structure 200. The second contact structure 400 extends along the z-direction and is connected to the plurality of first contact structures 300. Figure 2 As shown in the oval dotted box, a size D3 of the end surface where the first contact structure 300 and the second contact structure 400 are connected is larger than a size D2 of the end surface where the second contact structure 400 and the first contact structure 300 are connected.

[0037] According to the semiconductor device provided by at least one embodiment of the present application, the first device structure of the semiconductor device is connected to the second device structure or the back-end metal wire of the semiconductor device through the first contact structure and the second contact structure located on one side of the first device structure. The first contact structure is connected to the first device structure, and the second contact structure is connected to multiple first contact structures, so that the size of the contact structure in the peripheral circuit of the external semiconductor device can be effectively reduced while stabilizing the comprehensive performance of the semiconductor device. In addition, the size of the end surface where the first contact structure is connected to the second contact structure is larger than the size of the end surface where the second contact structure is connected to the first contact structure, which can enhance the effect of reducing the size of the contact structure of the peripheral circuit while achieving stable connection between the first contact structure and the second contact structure.

[0038] Specifically, taking a three-dimensional memory as an example, the semiconductor device may include at least two device structures, such as a first device structure and a second device structure. Optionally, the second device structure may include a memory cell array, and the first device structure may include a peripheral circuit. As an option, the first device structure and the second device structure may be formed on the same plane of the same substrate, and the first device structure and the second device structure are connected through an interconnection structure or a contact structure; as another option, the first device structure and the second device structure may be formed on different substrates, thereby effectively reducing the overall size of the semiconductor device and improving the storage density of the semiconductor device, wherein the first device structure and the second device structure are connected through an interconnection structure or a contact structure.

[0039] Based on voltage classification, the peripheral circuit may include high voltage circuits, low voltage circuits, and ultra low voltage circuits, etc. Based on function classification, the peripheral circuit may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a driver, a charge pump, and any active or passive components required in the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). In some embodiments, the peripheral circuit may be formed by CMOS technology, but is not limited thereto, and this application will not elaborate on this.

[0040] Optionally, the first device structure 200 includes a contact region 210, and the contact region 210 may have a doped region. The contact region 210 may include at least one of a gate region, a source region, and a drain region. Taking a transistor as an example, the contact region may generally be a gate, a source, or a drain of the transistor. Figure 3 As shown, the multiple first contact structures 300 connected to the same second contact structure 400 are connected to the same type of contact regions, so as to better achieve synchronous switching of the multiple first device structures.

[0041] like Figure 3 As shown, in some embodiments of the present application, the first contact structure 300 may include a first conductive material layer 320 formed in a first contact hole (not shown), and a first adhesive layer 310 located between the first contact hole and the first conductive material layer 320. Optionally, the material forming the first conductive material layer 320 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, etc. The material forming the first adhesive layer 310 includes, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the first contact structure 300 may further include a first barrier layer (not shown) formed between the first contact hole and the first adhesive layer 310. The material forming the first barrier layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or any combination thereof. The first adhesive layer 310 is used to block the diffusion of metal materials and to improve the adhesion between the first conductive material layer 320 and the first barrier layer.

[0042] Optionally, the first contact structure 300 may have a cylindrical or columnar shape extending in the z direction. In other words, the outer contour shape of the first contact structure 300 is not limited to a truncated cone, and may also be, for example, a cylinder or a prism. The shape of the end surface where the first contact structure 300 and the second contact structure 400 are connected may include a plane and a curved surface, for example, the shape of the end surface where the first contact structure 300 and the second contact structure 400 are connected is an arc surface. Similarly, the shape of the end surface where the second contact structure 400 and the first contact structure 300 are connected may include a plane and a curved surface, for example, the shape of the end surface where the second contact structure 400 and the first contact structure 300 are connected is an arc surface. Therefore, the size D3 of the end surface where the first contact structure 300 and the second contact structure 400 are connected may be understood as the maximum size of the end surface where the first contact structure 300 and the second contact structure 400 are connected, and the size D2 of the end surface where the second contact structure 400 and the first contact structure 300 are connected may be understood as the maximum size of the end surface where the second contact structure 400 and the first contact structure 300 are connected.

[0043] Those skilled in the art can understand that the shapes of the end faces of the multiple contact structures (for example, the first contact structure to the sixth contact structure) described below in this application can include planes and curved surfaces, and the dimensions of the end faces can be understood as the maximum dimensions of the end faces.

[0044] The dimension D2 of the end surface where the second contact structure 400 is connected to the first contact structure 300 is smaller than the dimension D3 of the end surface where the first contact structure 300 is connected to the second contact structure 400, which can effectively reduce the interval between adjacent contact structures in a plurality of contact structures (for example, a plurality of first contact structures and a plurality of second contact structures), and reduce the size of the contact structure of the peripheral circuit, thereby effectively reducing the size of the peripheral circuit.

[0045] Optionally, refer to Figure 2 and Figure 3 , the first contact structure 300 may include a first end face connected to the first device structure 200 and a second end face connected to the second contact structure 400, wherein the size of the second end face may be larger than the size of the first end face. As the size of devices such as MOS transistors in peripheral circuits decreases, the sizes of their source regions, drain regions, channel regions, and gate structures also decrease. Therefore, the size of the bottom end face (first end face) of the first contact structure connected to the above-mentioned contact region is also reduced accordingly. By setting the size of the second end face of the first contact structure 300 to be larger than the size of the first end face, the contact structure with a smaller bottom end face size can achieve good conduction performance, which is conducive to the integration of smaller device structures.

[0046] Reference again Figure 2In one embodiment of the present application, the second contact structure 400 may include a second conductive material layer 420, and a second adhesive layer 410 surrounding the second conductive material layer 420. Optionally, the material forming the second conductive material layer 420 includes, but is not limited to, tungsten, cobalt, copper, aluminum, silicide, etc. The material forming the second adhesive layer 410 includes, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the second contact structure 400 may further include a second barrier layer (not shown) surrounding the second adhesive layer 410. The material forming the second barrier layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or any combination thereof. The second adhesive layer 410 is used to block the diffusion of metal materials and to improve the adhesion between the second conductive material layer 420 and the second barrier layer.

[0047] refer to Figure 2 and Figure 3 The second contact structure 400 may include a plurality of connection portions 402 and a root portion 401 connected to the plurality of connection portions 402 , wherein at least one of the plurality of connection portions 402 includes a third end face and a fourth end face opposite to each other in the z direction, the third end face is connected to the first contact structure 300 , and the fourth end face is connected to the root portion 401 .

[0048] Optionally, the size of the fourth end face of the connecting portion 402 may be larger than the size of the third end face. Setting the size of the top end face of the connecting portion 402 to be larger than the size of its bottom end face can effectively reduce the interval between adjacent second contact structures and reduce the size of the contact structure of the peripheral circuit, thereby effectively reducing the size of the peripheral circuit.

[0049] As described above, in one embodiment of the present application, the semiconductor device 1000 may include at least two device structures, such as a first device structure 200 and a second device structure (not shown). Optionally, the second device structure may include a memory cell array (not shown), and the first device structure 200 may include a peripheral circuit. As an option, the first device structure 200 and the second device structure may be located on the same plane of the same substrate; as another option, the first device structure 200 and the second device structure may be located on different substrates, and the two may be combined by, for example, bonding. The first device structure 200 and the second device structure are connected through an interconnect structure or a contact structure. Specifically, the second device structure may include a memory cell array, and a first interconnect structure (not shown) or a third contact structure (not shown) connected to the memory cell array. Optionally, the memory cell array is located on a first substrate (not shown), and a plurality of first interconnect structures extend laterally in a direction parallel to the first substrate, and a plurality of third contact structures extend in a direction perpendicular to the first substrate. Exemplarily, a plurality of first interconnect structures and a plurality of third contact structures may be arranged alternately. Exemplary materials for forming the first interconnect structure and the third contact structure may include tungsten, cobalt, copper, aluminum, silicide, or any combination thereof. The second contact structure 400 is connected to the first interconnect structure or the third contact structure to achieve electrical connection between the peripheral circuit of the first device structure and the memory cell array of the second device structure.

[0050] In addition, if Figure 2 As shown, in one embodiment of the present application, the semiconductor device 1000 further includes a substrate 100 and a fourth contact structure 500, the substrate 100 is located on a second side 02 of the first device structure 200 opposite to the first side 01, wherein the fourth contact structure 500 extends into the substrate 100 along the z direction. Optionally, the fourth contact structure 500 may have a cylindrical or columnar shape extending in the z direction. In other words, the outer contour shape of the fourth contact structure 500 is not limited to a truncated cone, and may also be, for example, a cylinder or a prism.

[0051] Specifically, as described above, the semiconductor device 1000 may include at least two device structures, such as a first device structure 200 and a second device structure (not shown). As an option, the first device structure 200 and the second device structure may be located on the same plane of the same substrate; as another option, the first device structure 200 and the second device structure may be located on different substrates, for example, the first device structure 200 and the second device structure are located on the first substrate and the second substrate respectively, and the first device structure 200 and the second device structure may be combined by, for example, bonding, and electrically connected by an interconnect structure or a contact structure. Therefore, the substrate 100 may be understood as a first substrate used only to carry the first device structure 200, or as the same substrate that carries the first device structure 200 and the second device structure.

[0052] The fourth contact structure 500 extends into the substrate 100 along the z direction. When the substrate 100 is the first substrate, the fourth contact structure 500 can be understood as a contact structure associated with the first device structure 200. When the substrate 100 is the same substrate that carries the first device structure 200 and the second device structure, the fourth contact structure 500 can be understood as a contact structure associated with the first device structure 200 or the second device structure.

[0053] Optionally, the fourth contact structure 500 may include a fourth conductive material layer 520 formed in a fourth contact hole (not shown), and a fourth adhesive layer 510 located between the fourth contact hole and the fourth conductive material layer 520. Optionally, the material forming the fourth conductive material layer 520 includes, but is not limited to, tungsten, cobalt, copper, aluminum, silicide, etc. The material forming the fourth adhesive layer 510 includes, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the fourth contact structure 500 may further include a fourth barrier layer (not shown) formed between the fourth contact hole and the fourth adhesive layer 510. The material forming the fourth barrier layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or any combination thereof. The fourth adhesive layer 510 is used to block the diffusion of metal materials and to improve the adhesion between the fourth conductive material layer 520 and the fourth barrier layer.

[0054] Optionally, the second contact structure 400 is connected to the fourth contact structure 500 in the z direction, wherein the size of the end surface where the fourth contact structure 500 is connected to the second contact structure 400 is larger than the size of the end surface where the second contact structure 400 is connected to the fourth contact structure 500. Through the above arrangement, the interval between adjacent contact structures in the plurality of contact structures (for example, the plurality of second contact structures and the plurality of fourth contact structures) can be effectively reduced, and the size of the contact structure of the peripheral circuit can be reduced, so as to effectively reduce the size of the peripheral circuit.

[0055] In addition, refer again Figure 2 The semiconductor device 1000 further includes a fifth contact structure 700, which extends along the z direction and is connected to the first contact structure 300 or the fourth contact structure 500. The difference between the fifth contact structure 700 and the second contact structure 400 at least includes that the second contact structure 400 is connected to multiple first contact structures 300 or multiple fourth contact structures 500, while the fifth contact structure 700 is only connected to a single first contact structure 300 or a single fourth contact structure 500.

[0056] Optionally, the fifth contact structure 700 may have a cylindrical or columnar shape extending in the z direction. In other words, the outer contour shape of the fifth contact structure 700 is not limited to a truncated cone, and may also be a cylinder or a prism, for example.

[0057] The fifth contact structure 700 may include a fifth conductive material layer 720 formed in a fifth contact hole (not shown), and a fifth adhesive layer 710 located between the fifth contact hole and the fifth conductive material layer 720. Optionally, the material forming the fifth conductive material layer 720 includes, but is not limited to, tungsten, cobalt, copper, aluminum, silicide, etc. The material forming the fifth adhesive layer 710 includes, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the fifth contact structure 700 may further include a fifth barrier layer (not shown) formed between the fifth contact hole and the fifth adhesive layer 710. The material forming the fifth barrier layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or any combination thereof. The fifth adhesive layer 710 is used to block the diffusion of metal materials and to improve the adhesion between the fifth conductive material layer 720 and the fifth barrier layer.

[0058] Optionally, the size of the end surface where the first contact structure 300 is connected to the fifth contact structure 700 is larger than the size of the end surface where the fifth contact structure 700 is connected to the first contact structure 300; the size of the end surface where the fourth contact structure 500 is connected to the fifth contact structure 700 is larger than the size of the end surface where the fifth contact structure 700 is connected to the fourth contact structure 500. Through the above arrangement, the interval between adjacent contact structures in the plurality of contact structures (for example, the plurality of first contact structures, the plurality of fourth contact structures, and the plurality of fifth contact structures) can be effectively reduced, and the size of the contact structure of the peripheral circuit can be reduced, so as to effectively reduce the size of the peripheral circuit.

[0059] In addition, the fifth contact structure 700 is connected to the first interconnect structure or the third contact structure included in the second device structure to achieve electrical connection between the peripheral circuit of the first device structure and the memory cell array of the second device structure.

[0060] like Figure 2 and Figure 3 As shown, in some embodiments of the present application, the semiconductor device 1000 further includes an interconnection layer 600 and a sixth contact structure 800. As an option, the interconnection layer 600 may include multiple interlayer dielectric layers (not shown), and multiple contact structures, such as the first contact structure 300, the second contact structure 400, the fourth contact structure 500, the fifth contact structure 700, and the sixth contact structure 800, may be located in multiple interlayer dielectric layers. Optionally, the material of the interlayer dielectric layer may include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0061] It should be noted that the number of the first contact structure 300 , the second contact structure 400 , the fourth contact structure 500 , the fifth contact structure 700 and the sixth contact structure 800 provided in the interconnection layer 600 is only exemplary, and the embodiments of the present application are not limited thereto.

[0062] Optionally, the second contact structure 400 and the sixth contact structure 800 both extend in the interconnect layer 600 along the z direction, wherein the depth of the second contact structure 400 in the z direction is greater than the depth of the sixth contact structure 800 in the z direction. The semiconductor device 1000 further includes a plurality of interconnect line structures (not shown) extending in a direction perpendicular to the z direction. As an option, the sixth contact structure 800 may be connected to the interconnect line structure. As an option, the interconnect line structure in the interconnect layer 600 may be connected to the first interconnect structure or the third contact structure of the second device structure through the sixth contact structure 800.

[0063] like Figure 2 As shown, the sixth contact structure 800 may include a sixth conductive material layer 820 formed in a sixth contact hole (not shown), and a sixth adhesive layer 810 located between the sixth contact hole and the sixth conductive material layer 820. Optionally, the material forming the sixth conductive material layer 820 includes, but is not limited to, tungsten, cobalt, copper, aluminum, silicide, etc. The material forming the sixth adhesive layer 810 includes, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the sixth contact structure 800 may further include a sixth barrier layer (not shown) formed between the sixth contact hole and the sixth adhesive layer 810. The material forming the sixth barrier layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or any combination thereof. The sixth adhesive layer 810 is used to block the diffusion of metal materials and to improve the adhesion between the sixth conductive material layer 820 and the sixth barrier layer.

[0064] Optionally, as described above, the first contact structure 300, the second contact structure 400, the fourth contact structure 500, the fifth contact structure 700, and the sixth contact structure 800 may include the same layer structure and layer material. On this basis, in order to simplify the preparation process of the semiconductor device and save production costs, the first contact structure 300 and the fourth contact structure 500 may be formed in the same process; and the second contact structure 400, the fifth contact structure 700, and the sixth contact structure 800 may be formed in the same process.

[0065] In one embodiment of the present application, the dimension D1 of the end surface where the first contact structure 300 is connected to the first device structure 200 (which can be understood as the width of the first contact structure 300), and the depth H1 of the first contact structure 300 in the z direction satisfy: 1 / 8≤D1 / H1≤1 / 7. The first contact structure 300 has a low depth-to-width ratio, which is beneficial to improving the filling quality of the first conductive material layer in the first contact structure 300, thereby improving the comprehensive performance of the formed semiconductor device. In addition, after forming the first contact hole of the first contact structure 300, ion implantation can be performed on the bottom of the first contact hole to reduce the contact resistance between the first contact structure 300 and the first device structure 200. Since the depth-to-width ratio of the first contact hole is small, when the photoresist is used for development and exposure to define the ion implantation area, it is not easy for the photoresist to remain in the first contact hole, which can increase the process window, improve the effect of ion implantation, and improve the quality of the first contact structure 300 formed subsequently.

[0066] In one embodiment of the present application, the dimension D2 of the end surface where the second contact structure 400 is connected to the first contact structure 300 and the depth H2 of the second contact structure 400 in the z direction satisfy: 1 / 8≤D2 / H2≤1 / 7. The second contact structure 400 has a low depth-to-width ratio, which is beneficial to improving the filling quality of the second conductive material layer in the second contact structure 400, thereby improving the overall performance of the formed semiconductor device.

[0067] In one embodiment of the present application, the depth H2 of the second contact structure 400 in the z direction is less than or equal to the depth H1 of the first contact structure 300 in the z direction. In order to reduce the size of the peripheral circuit of the semiconductor device while stabilizing the comprehensive performance of the semiconductor device, the present application connects the first contact structure with the first device structure, and the second contact structure with multiple first contact structures, thereby effectively reducing the size of the contact structure of the peripheral circuit. On this basis, the depth H2 of the second contact structure 400 in the z direction is less than or equal to the depth H1 of the first contact structure 300 in the z direction, so that both the first contact structure 300 and the second contact structure 400 have a lower aspect ratio.

[0068] Figures 4 to 6 It is an intermediate formed in the preparation process of a semiconductor device preparation method.

[0069] like Figure 4 As shown, in a method for preparing a semiconductor device, forming an intermediate 1 includes: forming a first device structure 200 on a substrate 100; forming a first covering layer 201 covering the first device structure 200; and sequentially forming a hard mask layer 11 and a patterned photoresist layer 12 on the first covering layer 201, wherein the pattern in the photoresist layer 12 defines an area of ​​a contact hole connecting the first device structure 2002.

[0070] like Figure 4 and Figure 5 As shown, forming the intermediate body 2 includes: etching the hard mask layer 11 and the first capping layer 201 ; and removing the etched hard mask layer 11 to form a contact hole 31 , wherein the contact hole 31 extends to the first device structure 200 .

[0071] like Figure 5 and Figure 6 As shown, forming the intermediate body 3 includes: forming a contact structure 30 connected to the first device structure 200 in the contact hole 31 .

[0072] As mentioned above, as the structure of semiconductor devices continues to develop toward high layers and high densities, the size of the peripheral circuits included therein is increasingly becoming a key factor in determining the size of the entire chip. Figures 4 to 6 An implementation method of connecting a single contact structure to a first device structure is shown. In this implementation method, the single contact structure has a high aspect ratio, and the filling quality of the conductive material layer included therein is poor, which may lead to a decrease in the overall performance of the semiconductor device finally formed. In addition, in this implementation method, the overall planar size of the contact structure in the peripheral circuit included in the semiconductor device is large, which is not conducive to reducing the size of the peripheral circuit. Therefore, how to effectively reduce the size of the peripheral circuit without affecting the overall performance of the semiconductor device is a problem that needs to be solved urgently. In order to at least partially solve the above-mentioned problems existing in the related art, the present application provides a semiconductor device and a method for preparing the same.

[0073] Figure 7 FIG. 2 is a flow chart of a method 2000 for manufacturing a semiconductor device according to an embodiment of the present application. Figure 7 As shown, the present application provides a method 2000 for preparing a semiconductor device, comprising:

[0074] S1, forming a first device structure and a first contact structure extending to the first device structure along a first direction.

[0075] S2, forming an interconnection layer covering at least the first device structure and the first contact structure, and forming a second initial contact hole in the interconnection layer extending along the first direction to the first contact structure, wherein the radial dimension of a portion of the first contact structure close to the second initial contact hole is larger than the radial dimension of a portion of the second initial contact hole close to the first contact structure.

[0076] S3, removing a portion of the sidewalls of the plurality of second initial contact holes to form second contact holes.

[0077] S4, filling the second contact hole to form a second contact structure connected to the plurality of first contact structures.

[0078] The following will be combined Figures 7 to 14CThe specific process of each step of the above-mentioned preparation method 2000 is described in detail.

[0079] Step S1

[0080] Figure 8 It is a schematic cross-sectional view of a structure formed after forming a first device structure 200 according to a preparation method in one embodiment of the present application. Fig. 9 It is a cross-sectional schematic diagram of a structure formed after forming a first contact hole 300 ′ according to a preparation method in one embodiment of the present application. Fig.10 It is a schematic cross-sectional view of a structure formed after forming the first contact structure 300 according to a preparation method in one embodiment of the present application.

[0081] like Figures 7 to 10 As shown, step S1 of forming a first device structure and a first contact structure extending along a first direction to the first device structure may, for example, include: providing a substrate 100; forming a first device structure 200 on the substrate 100; forming a first contact hole 300' extending along a z direction to the first device structure 200; and forming a first contact structure 300 in the first contact hole 300'.

[0082] Specifically, taking a three-dimensional memory as an example, the semiconductor device may include at least two device structures, such as a first device structure and a second device structure. Optionally, the second device structure may include a memory cell array, and the first device structure may include a peripheral circuit. As an option, the first device structure and the second device structure may be formed on the same plane of the same substrate, and the first device structure and the second device structure are connected through an interconnection structure or a contact structure; as another option, the first device structure and the second device structure may be formed on different substrates, thereby effectively reducing the overall size of the semiconductor device and improving the storage density of the semiconductor device, wherein the first device structure and the second device structure are connected through an interconnection structure or a contact structure.

[0083] Based on voltage classification, the peripheral circuits may include high voltage circuits, low voltage circuits, and ultra low voltage circuits, etc. Based on function classification, the peripheral circuits may include one or more of page buffers, decoders (e.g., row decoders and column decoders), drivers, charge pumps, and any active or passive components required in the circuit (e.g., transistors, diodes, resistors, or capacitors).

[0084] When the first device structure and the second device structure are formed on the same plane of the same substrate, the substrate 100 can be understood as the same substrate mentioned above; when the first device structure and the second device structure are formed on different substrates, for example, the first device structure is formed on the first substrate and the second device structure is formed on the second substrate, the substrate 100 can be understood as the first substrate.

[0085] Alternatively, if Figure 8 As shown, in one embodiment of the present application, the preparation material of the substrate 100 can be selected from any suitable semiconductor material, for example, it can be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or gallium arsenide and other III-V compounds.

[0086] As an option, the substrate 100 may also include a substrate sacrificial stack (not shown). The substrate sacrificial stack may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In addition, the substrate sacrificial stack may also include a high dielectric constant dielectric layer. As another option, the substrate sacrificial stack may include a first barrier layer (not shown), a substrate semiconductor layer (not shown), and a second barrier layer (not shown) arranged in sequence, wherein the first barrier layer and the second barrier layer may be, for example, a silicon oxide layer, and the substrate semiconductor layer may be, for example, a polysilicon layer. Optionally, in the substrate semiconductor layer, a well region formed by doping with an N-type or P-type dopant via an ion implantation or diffusion process may be formed. The dopant may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present application, the well region may be prepared by selecting the same dopant or different dopant. Further, the doping concentration of the well region may be the same or different, and the present application does not limit this.

[0087] In addition, the first barrier layer may be disposed on the surface of the substrate 100 and may include a single layer, multiple layers or a suitable composite layer. Alternatively, when the first barrier layer is a composite layer, it may include any one or more of a dielectric material, a semiconductor material and a conductive material.

[0088] Optionally, in the case of selecting a single crystal silicon layer in a silicon-on-insulator SOI as the substrate 100, the silicon-on-insulator SOI includes a substrate and a single crystal silicon layer, wherein the substrate may include a relatively thick body substrate layer (e.g., a silicon substrate layer) and a relatively thin insulating silicon dioxide intermediate layer. The substrate is mainly used to provide mechanical support. The thickness of the single crystal silicon layer is very thin relative to the substrate, and is disposed above the substrate, and an etching circuit can be formed on the single crystal silicon layer. Using an ultra-thin single crystal silicon layer in a silicon-on-insulator as the substrate 100 can improve the latch-up effect, short channel effect, and radiation resistance of peripheral high-voltage circuits such as high-voltage MOS transistors.

[0089] In one embodiment of the present application, a substrate 100 for supporting a device structure thereon may be formed by sequentially arranging a plurality of layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0090] The semiconductor device may include a memory array and a peripheral circuit. The array structure of the semiconductor device is different from the structure of the peripheral circuit and must be manufactured separately. The peripheral circuit may include a high voltage circuit, a low voltage circuit, and an ultra-low voltage circuit. Among them, the preparation process of the peripheral high voltage circuit is easily compatible with the preparation process of the three-dimensional memory array. As an option, the peripheral high voltage circuit and the three-dimensional memory array can be formed on the same plane of the same substrate, and a relatively large number of peripheral low voltage circuits and peripheral ultra-low voltage circuits are arranged on the peripheral circuit chip, thereby effectively reducing the overall size of the semiconductor device and improving the storage density of the semiconductor device.

[0091] In one embodiment of the present application, after forming the substrate 100, a first device structure 200 may be formed on the substrate 100. Optionally, the first device structure 200 includes a peripheral circuit. Specifically, the preparation process of the first device structure 200 may adopt an existing conventional process and be prepared according to actual needs. For example, the peripheral circuit may be formed by CMOS technology, but is not limited thereto, and this application will not elaborate on this.

[0092] Optionally, the first device structure 200 may include a shallow trench isolation structure, which can effectively isolate adjacent devices. In addition, the first device structure 200 also includes a gate structure, a source and a drain. The first contact structure formed subsequently is connected to the contact area of ​​the first device structure 200, wherein the type of the contact area includes at least one of a gate area where the gate structure is located, a source area where the source is located, and a drain area where the drain is located.

[0093] like Figures 8 to 10As shown, after forming the first device structure 200, a first contact structure 300 may be formed. In one embodiment of the present application, forming the first contact structure 300 may include: forming z, and forming a first contact hole 300' extending along the z direction to the contact region 210 of the first device structure 200 in the isolation cover layer 201'; and filling the first contact hole 300' to form the first contact structure 300, wherein the type of the contact region 210 includes at least one of a gate region, a source region, and a drain region; and after forming the first contact hole 300', doping the contact region of the first device structure 200 through the first contact hole 300'.

[0094] Specifically, Figure 8 As shown, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to prepare an isolation capping layer 201' that at least covers the first device structure 200. Optionally, the material of the isolation capping layer 201' may include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics or any combination thereof.

[0095] After forming the isolation cover layer 201', a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to sequentially form a hard mask layer 11 and a patterned photoresist layer 12 on the isolation cover layer 201', wherein the pattern in the photoresist layer 12 defines the area of ​​the first contact hole 300' connecting the first device structure 2002.

[0096] like Figure 8 and Fig. 9 As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., to remove part of the hard mask layer 11 and the isolation cover layer 201' through the patterned photoresist layer 12; and after this operation, continue to remove the remaining hard mask layer 11, and form a first contact hole 300' in the isolation cover layer 201'.

[0097] After forming the first contact hole 300', an ion implantation process is used to dope the contact region of the first device structure 200 through the first contact hole 300' to reduce the first contact structure 300 ( Fig.10 The contact resistance between the device structure 200 and the first device structure 200 is shown.

[0098] In addition, as an option, the aspect ratio of the first contact hole 300' can be set to a range of 1 / 8 to 1 / 7. The lower aspect ratio of the first contact hole 300' is beneficial to improving the filling quality of the first conductive material layer subsequently formed in the first contact hole 300', thereby improving the overall performance of the semiconductor device finally formed.

[0099] Afterwards, if Fig. 9 and Fig.10 As shown, the first contact structure 300 may be formed in the first contact hole 300 ′ by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0100] Optionally, the first contact structure 300 may include a first conductive material layer 320 formed in the first contact hole 300', and a first adhesive layer 310 located between the first contact hole 300' and the first conductive material layer 320. The material forming the first conductive material layer 320 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, etc. The material forming the first adhesive layer 310 includes, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the first contact structure 300 may further include a first barrier layer (not shown) formed between the first contact hole 300' and the first adhesive layer 310. The material forming the first barrier layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or any combination thereof. The first adhesive layer 310 is used to block the diffusion of metal materials and to improve the adhesion between the first conductive material layer 320 and the first barrier layer.

[0101] The first contact structure 300 may include a first end face connected to the first device structure 200 and a second end face connected to a second contact structure formed subsequently, wherein the size of the second end face may be larger than the size of the first end face. As the size of devices such as MOS transistors in peripheral circuits decreases, the size of the source region where the source is located, the drain region where the drain is located, the channel region, and the gate region where the gate structure is located also decrease. Therefore, the size of the bottom end face (first end face) of the first contact structure connected to the above-mentioned contact region is also reduced accordingly. By setting the size of the second end face of the first contact structure 300 to be larger than the size of the first end face, the contact structure with a smaller bottom end face size can achieve good conduction performance, which is conducive to the integration of smaller device structures.

[0102] In addition, in some embodiments of the present application, in the process of forming the first contact structure, a fourth contact structure 500 may also be formed. The fourth contact structure 500 extends into the substrate 100 along the z direction. Optionally, the fourth contact structure 500 may have a cylindrical or columnar shape extending in the z direction. In other words, the outer contour shape of the fourth contact structure 500 is not limited to a truncated cone, and may also be, for example, a cylinder or a prism.

[0103] Specifically, Figure 8 and Fig. 9 As shown, the fourth contact hole 500' can be formed by the same process as the process of forming the first contact hole 300'. Fig. 9 and Fig.10 As shown, the fourth contact hole 500 ′ can be filled with the same process as that of filling the first contact hole 300 ′ to form the fourth contact structure 500 .

[0104] Optionally, the fourth contact structure 500 may include a fourth conductive material layer 520 formed in the fourth contact hole 500', and a fourth adhesive layer 510 located between the fourth contact hole 500' and the fourth conductive material layer 520. Materials forming the fourth conductive material layer 520 include, but are not limited to, tungsten, cobalt, copper, aluminum, silicide, etc. Materials forming the fourth adhesive layer 510 include, but are not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the fourth contact structure 500 may further include a fourth barrier layer (not shown) formed between the fourth contact hole 300' and the fourth adhesive layer 510. Materials forming the fourth barrier layer include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, high-k dielectrics, or any combination thereof. The fourth adhesive layer 510 is used to block the diffusion of metal materials and to improve the adhesion between the fourth conductive material layer 520 and the fourth barrier layer.

[0105] Step S2

[0106] Fig.11 It is a cross-sectional schematic diagram of a structure formed after forming a patterned photoresist layer 12 according to a preparation method in one embodiment of the present application. Fig.12 It is a schematic cross-sectional view of a structure formed after forming a second initial contact hole 400 - 1 according to a preparation method in one embodiment of the present application.

[0107] like Figures 10 to 12 As shown, step S2 forms an interconnection layer covering at least the first device structure and the first contact structure, and forms a second initial contact hole in the interconnection layer extending along the first direction to the first contact structure, which may for example include: forming an interconnection layer 600; and forming a second initial contact hole 400-1.

[0108] Specifically, Figure 10 to Figure 11As shown, in one embodiment of the present application, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to form an interconnection layer 600 that at least covers the first device structure 200 and the first contact structure 300.

[0109] Optionally, the interconnect layer 600 may include multiple interlayer dielectric layers (not shown), and the multiple contact structures connected to the first device structure 200 may be located in the multiple interlayer dielectric layers. Optionally, the material of the interlayer dielectric layer may include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0110] In addition, as an option, the isolation capping layer 201 ′ covering at least the first device structure 200 may be a part of the interconnection layer 600 and does not need to be removed.

[0111] like Figure 11 to Figure 12 As shown, the second initial contact hole 400-1 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to form the second initial contact hole 400-1.

[0112] The second initial contact hole 400-1 has a cylindrical or columnar shape extending along the z direction to the first contact structure 300 or the fourth contact structure 500. Since the cross section of the second initial contact hole 400-1 in the zy plane is the same or similar to the cross section in the zx plane, wherein the x direction, the y direction and the z direction are perpendicular to each other. Therefore, the present application only Fig.11 A cross-sectional view of the second initial contact hole 400 - 1 in the zy plane is shown.

[0113] Optionally, in one embodiment of the present application, in the process of forming the second contact hole, the fifth contact hole 700' may be formed by the same process. The fifth contact hole 700' has a cylindrical or columnar shape extending to the first contact structure 300 or the fourth contact structure 500 along the z direction.

[0114] The fifth contact hole 700' is used to form a fifth contact structure later, and the second initial contact hole 400-1 is used to form a second contact hole later, and the second contact hole can accommodate the second contact structure. The difference between the fifth contact structure and the second contact structure at least includes that the second contact structure is connected to multiple first contact structures 300 or multiple fourth contact structures 500, while the fifth contact structure is only connected to a single first contact structure 300 or a single fourth contact structure 500.

[0115] In addition, if Fig.12As shown, the radial dimension d1 of the portion of the first contact structure 300 close to the second initial contact hole 400-1 is greater than the radial dimension d2 of the portion of the second initial contact hole 400-1 close to the first contact structure 300. The second initial contact hole 400-1 is used to form a second contact hole for accommodating the second contact structure, and the radial dimension d1 of the portion of the first contact structure 300 close to the second initial contact hole 400-1 is greater than the radial dimension d2 of the portion of the second initial contact hole 400-1 close to the first contact structure 300, which can enhance the effect of reducing the size of the contact structure of the peripheral circuit while achieving stable connection between the first contact structure and the second contact structure.

[0116] Step S3

[0117] Fig.13 It is a cross-sectional schematic diagram of a structure formed after forming a first sacrificial filling layer 430 according to a preparation method in one embodiment of the present application. Fig.14A It is a schematic top view of a structure formed after forming a second contact hole 400 - 2 according to a preparation method in one embodiment of the present application. Fig. 14B for Fig.14A The semiconductor device is shown as a schematic cross-sectional view taken along line CC′. Fig. 14C yes Fig.14A The semiconductor device is shown in a schematic cross-sectional view taken along line DD′.

[0118] like Figures 12 to 14C As shown, step S3 of removing a portion of the side walls of the plurality of second initial contact holes to form a second contact hole may, for example, include: filling the plurality of second initial contact holes 400-1 with a first sacrificial filling layer 430, wherein at least two of the plurality of second initial contact holes 400-1 are adjacent in a plane (xy plane) perpendicular to the z direction and have adjacent side walls adjacent to each other; and removing a portion of the adjacent side walls along the z direction to form a second contact hole 400-2.

[0119] Specifically, combined Figure 12 to Figure 13 The plurality of second initial contact holes 400-1 may be filled with a first sacrificial filling layer 430 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The material of the first sacrificial filling layer 430 includes but is not limited to polysilicon.

[0120] Combination Figures 12 to 14C, can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove a portion of the adjacent side walls of at least two of the multiple second initial contact holes 400-1 in the xy plane along the z direction to form a second contact hole 400-2.

[0121] In addition, if Fig.12 and Fig. 14C As shown, through the above process, the tops of the plurality of second initial contact holes 400 - 1 can be connected. The plurality of first contact structures 300 corresponding to the plurality of second initial contact holes 400 - 1 with part of the sidewall removed are connected to the contact regions 210 of the same type.

[0122] Optionally, in one embodiment of the present application, in the process of forming the second contact hole, the sixth contact hole 800' can also be formed by the same process. The sixth contact hole 800' has a cylindrical or columnar shape extending along the z direction. The second contact hole 400-2 and the sixth contact hole 800' both extend in the interconnection layer 600 along the z direction, and the depth of the second contact hole 400-2 in the z direction is greater than the depth of the sixth contact hole 800' in the z direction.

[0123] Step S4

[0124] Combination Figures 1 to 3 as well as FIG. 14A to FIG. 14C , step S4 fills the second contact hole to form a second contact structure connected to the multiple first contact structures, wherein the radial size of a portion of the first contact structure close to the second initial contact hole is larger than the radial size of a portion of the second initial contact hole close to the first contact structure, which may, for example, include: forming a second contact structure 400 in the second contact hole 400-2 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0125] Specifically, the second contact structure 400 may include a second conductive material layer 420, and a second adhesive layer 410 surrounding the second conductive material layer 420. Optionally, the material forming the second conductive material layer 420 includes, but is not limited to, tungsten, cobalt, copper, aluminum, silicide, etc. The material forming the second adhesive layer 410 includes, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the second contact structure 400 may further include a second barrier layer (not shown) surrounding the second adhesive layer 410. The material forming the second barrier layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or any combination thereof. The second adhesive layer 410 is used to block the diffusion of metal materials and to improve the adhesion between the second conductive material layer 420 and the second barrier layer.

[0126] In one embodiment of the present application, an initial second barrier layer (not shown), an initial second adhesive layer (not shown), and an initial second conductive material layer (not shown) may be sequentially formed on the surface of the interconnection layer 600 away from the substrate 100 and in the second contact hole 400-2 by a thin film deposition process. After the above layers are formed, they may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove the portions of the above layers located on the surface of the interconnection layer 600 away from the substrate 100, thereby forming the second barrier layer, the second adhesive layer 410, and the second conductive material layer 420.

[0127] Optionally, in order to simplify the manufacturing process of the semiconductor device and save production costs, the fifth contact structure 700 and the sixth contact structure 800 are formed in the process of forming the above-mentioned layers of the second contact structure 400 .

[0128] Since the contents and structures involved in the description of the semiconductor device 1000 above may be fully or partially applicable to the method for preparing a semiconductor device described herein, the related or similar contents will not be described in detail.

[0129] Although an exemplary method for preparing and structure of a semiconductor device is described herein, it is understood that one or more features may be omitted, replaced, or added to the structure of the semiconductor device. For example, various well regions may be formed in the substrate as required. In addition, the materials of the various layers exemplified are merely exemplary.

[0130] Fig.15 It is a schematic diagram of the structure of a storage system 30000 according to one embodiment of the present application.

[0131] like Fig.15 As shown, at least one embodiment of the present application further provides a storage system 30000. The storage system 30000 may include a controller 32200 and at least one semiconductor device 32100. The semiconductor device 32100 may be the same as the semiconductor device described in any embodiment above, and the present application will not repeat it.

[0132] The controller 32200 may be coupled to the semiconductor device 32100 through a channel CH to control the semiconductor device 32100 to store data. The semiconductor device 32100 may receive a command CMD and an address ADDR from the controller 32200 through the channel CH and access an area selected from the memory cell array in response to the address. In other words, the semiconductor device 32100 may perform an internal operation corresponding to the command on the area selected by the address.

[0133] In some embodiments, the storage system 30000 may be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system and the method for preparing the semiconductor device provided in the present application have the same beneficial effects as the semiconductor device because the semiconductor device provided in the present application is provided, and are not described in detail here.

[0134] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A semiconductor device, characterized in that: include: a first device structure; as well as a first contact structure and a second contact structure located on a first side of the first device structure, The first contact structure extends along a first direction and is connected to the first device structure; as well as The second contact structure extends along the first direction and is connected to a plurality of the first contact structures. The size of the end surface where the first contact structure is connected to the second contact structure is larger than the size of the end surface where the second contact structure is connected to the first contact structure.

2. The semiconductor device according to claim 1, wherein The first contact structure is connected to the contact region of the first device structure, Wherein, the type of the contact region includes at least one of a gate region, a source region and a drain region; and A plurality of first contact structures connected to the same second contact structure are connected to contact regions of the same type.

3. The semiconductor device according to claim 1, wherein The semiconductor device further includes a second device structure, The second device structure includes: a memory cell array, and a first interconnect structure or a third contact structure connected to the memory cell array, Wherein, the second contact structure is connected to the first interconnection structure or the third contact structure.

4. The semiconductor device according to claim 1, wherein: The first contact structure comprises a first end surface connected to the first device structure and a second end surface connected to the second contact structure, Wherein, the size of the second end surface is greater than that of the first end surface.

5. The semiconductor device according to claim 1, wherein The second contact structure includes a plurality of connection parts and a root part connected to the plurality of connection parts. At least one of the plurality of connection portions includes a third end surface and a fourth end surface opposite to each other in the first direction, the third end surface is connected to the first contact structure, and the fourth end surface is connected to the root portion.

6. The semiconductor device according to claim 5, wherein: The size of the fourth end surface is greater than that of the third end surface.

7. The semiconductor device according to claim 1, wherein The semiconductor device further comprises a substrate and a fourth contact structure, wherein the substrate is located on a second side of the first device structure opposite to the first side, Wherein, the fourth contact structure extends into the substrate along the first direction.

8. The semiconductor device according to claim 7, wherein: The second contact structure is connected to the fourth contact structure in the first direction, The size of the end surface where the fourth contact structure is connected to the second contact structure is larger than the size of the end surface where the second contact structure is connected to the fourth contact structure.

9. The semiconductor device according to claim 7, wherein: The semiconductor device further includes a fifth contact structure, which extends along the first direction and is connected to the first contact structure or the fourth contact structure. Wherein, the size of the end surface where the first contact structure is connected to the fifth contact structure is larger than the size of the end surface where the fifth contact structure is connected to the first contact structure; and The size of the end surface where the fourth contact structure is connected to the fifth contact structure is larger than the size of the end surface where the fifth contact structure is connected to the fourth contact structure.

10. The semiconductor device according to claim 9, further comprising a second device structure, wherein: The second device structure includes: a memory cell array; and a first interconnect structure or a third contact structure connected to the memory cell array, Wherein, the fifth contact structure is connected to the first interconnection structure or the third contact structure.

11. The semiconductor device according to claim 1, wherein The semiconductor device further comprises an interconnect layer and a sixth contact structure, Wherein, the second contact structure and the sixth contact structure both extend in the interconnect layer along the first direction; and A depth of the second contact structure in the first direction is greater than a depth of the sixth contact structure in the first direction.

12. The semiconductor device according to claim 11, further comprising a second device structure, wherein: The second device structure includes: a memory cell array; and a first interconnect structure or a third contact structure connected to the memory cell array, Wherein, the sixth contact structure is connected to the first interconnection structure or the third contact structure.

13. The semiconductor device according to claim 1, wherein A dimension D1 of an end surface of the first contact structure connected to the first device structure and a depth H1 of the first contact structure in the first direction satisfy: 1 / 8≤D1 / H1≤1 / 7.

14. The semiconductor device according to claim 1, wherein A dimension D2 of an end surface of the second contact structure connected to the first contact structure and a depth H2 of the second contact structure in the first direction satisfy: 1 / 8≤D2 / H2≤1 / 7.

15. The semiconductor device according to claim 1, wherein A depth of the second contact structure in the first direction is less than or equal to a depth of the first contact structure in the first direction.

16. A method for preparing a semiconductor device, characterized in that: include: forming a first device structure and a first contact structure extending to the first device structure along a first direction; forming an interconnection layer covering at least the first device structure and the first contact structure, and forming a second initial contact hole in the interconnection layer extending along the first direction to the first contact structure; removing a portion of the sidewalls of the plurality of second initial contact holes to form second contact holes; as well as filling the second contact hole to form a second contact structure connected to the plurality of first contact structures, The radial dimension of a portion of the first contact structure close to the second initial contact hole is greater than the radial dimension of a portion of the second initial contact hole close to the first contact structure.

17. The method according to claim 16, wherein: Removing a portion of the sidewalls of the plurality of second initial contact holes to form the second contact holes comprises: Filling a plurality of the second initial contact holes with a first sacrificial filling layer, wherein at least two of the plurality of the second initial contact holes are adjacent in a plane perpendicular to the first direction and have adjacent side walls adjacent to each other; and A portion of the adjacent sidewall is removed along the first direction to form the second contact hole.

18. The method according to claim 16, wherein: Forming the first contact structure includes: forming an isolation cover layer covering at least the first device structure, and forming a first contact hole in the isolation cover layer extending along the first direction to a contact region of the first device structure; and filling the first contact hole to form the first contact structure, Wherein, the type of the contact region includes at least one of a gate region, a source region and a drain region; and After forming the first contact hole, the method further includes doping a contact region of the first device structure through the first contact hole.

19. The method according to claim 18, wherein: The plurality of first contact structures corresponding to the plurality of second initial contact holes whose sidewalls are partially removed are connected to contact regions of the same type.

20. A storage system, characterized in that: include: Controller; as well as The semiconductor device according to any one of claims 1 to 15, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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