Semiconductor device and preparation method thereof, and storage system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises a laminated structure and a contact structure. The laminated structure comprises gate layers and first dielectric layers which are alternately stacked. The contact structure extends in the laminated structure in the stacking direction and comprises a plurality of connecting layers connected with the plurality of gate layers, and at least part of the gate layers are located at different stacking heights in the plurality of gate layers connected with the plurality of connecting layers.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and manufacturing, and more specifically, to a structure of a semiconductor device, a method for preparing a semiconductor device, and a storage system. Background Art

[0002] Taking three-dimensional memory as an example, some semiconductor devices include a stacked structure. As the number of stacked layers in the stacked structure continues to increase, the depth of etching required for the contact holes (CT) extending to different word lines (WL) is getting deeper and deeper, and higher requirements are also put forward for the CT etching process and the process of etching the stop layer. In order to reduce the process difficulty and simplify the process steps, the SCT (self-align contact) architecture is proposed in the relevant technology. The SCT process uses the step (SS) cutting process to accurately stop the contact hole on each layer of WL, thereby realizing the merger of the SS process and the CT process.

[0003] It should be understood that the contents described in this background technology section are only used to help understand the technical solutions disclosed in this application, and do not necessarily belong to the prior art before the filing date of this application. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor device and a method for manufacturing the same, and a storage system that can at least partially solve the above-mentioned problems or other problems existing in the related art.

[0005] On the one hand, the present application provides a semiconductor device, which includes: a stacked structure, including alternately stacked gate layers and first dielectric layers; and a contact structure, which extends in the stacked structure along a stacking direction and includes multiple connecting layers connected to the multiple gate layers, wherein, among the multiple gate layers connected to the multiple connecting layers, at least some of the gate layers are located at different stacking heights.

[0006] In one embodiment of the present application, the semiconductor device further includes a gate line isolation structure penetrating the stacked structure along the stacking direction, wherein at least one of the plurality of gate line isolation structures extends in a first direction perpendicular to the stacking direction and penetrates the contact structure.

[0007] In one embodiment of the present application, the contact structure includes a first part and a second part separated by the gate line isolation structure, wherein, in the first part, the multiple connection layers include a first connection layer and a second connection layer from the outside to the inside, and in the second part, the multiple connection layers include a third connection layer and a fourth connection layer from the outside to the inside, wherein the first connection layer, the second connection layer, the third connection layer and the fourth connection layer respectively extend in the stacking structure along the stacking direction and are respectively connected to the gate layers at different stacking heights.

[0008] In one embodiment of the present application, the gate layers respectively connected to the first connection layer and the second connection layer are adjacent to the same first dielectric layer in the stacking direction; and / or the gate layers respectively connected to the third connection layer and the fourth connection layer are adjacent to the same first dielectric layer in the stacking direction.

[0009] In one embodiment of the present application, the contact structure includes a first part and a second part separated by the gate line isolation structure, wherein, in the first part, the multiple connection layers include a first connection layer and a second connection layer from the outside to the inside, and in the second part, the multiple connection layers include a third connection layer and a fourth connection layer from the outside to the inside; the first connection layer and the third connection layer respectively extend in the stacking structure along the stacking direction and are connected to the first gate layer, the second connection layer and the fourth connection layer respectively extend in the stacking structure along the stacking direction and are connected to the second gate layer, and the first gate layer and the second gate layer have different stacking heights.

[0010] In one embodiment of the present application, the first gate layer and the second gate layer are both adjacent to the same first dielectric layer in the stacking direction.

[0011] In one embodiment of the present application, at least one of the first connection layer, the second connection layer, the third connection layer and the fourth connection layer includes a conductive portion and a spacing dielectric portion, wherein in a plane perpendicular to the stacking direction, the conductive portion is adjacent to the gate line isolation structure.

[0012] In one embodiment of the present application, the stacked structure includes a storage area and a contact area distributed along the first direction, and the gate layer extends from the storage area to the contact area; and the multiple gate line isolation structures include at least one of a first gate line isolation structure, a second gate line isolation structure, a third gate line isolation structure and a fourth gate line isolation structure, wherein the first gate line isolation structure continuously extends through the storage area and the contact area along the first direction; the second gate line isolation structure intermittently extends through the storage area and the contact area along the first direction; the third gate line isolation structure extends in the storage area along the first direction; and the fourth gate line structure extends in the contact area along the first direction.

[0013] In one embodiment of the present application, at least one of the first gate line isolation structure, the second gate line isolation structure, and the fourth gate line isolation structure penetrates the contact structure in the first direction.

[0014] In one embodiment of the present application, the plurality of contact structures penetrated by different gate line isolation structures are aligned with each other or staggered with each other in the second direction, wherein the first direction, the second direction and the stacking direction are perpendicular to each other.

[0015] In one embodiment of the present application, the contact area includes a second dielectric layer alternately stacked with the first dielectric layer in the stacking direction, wherein the second dielectric layer is connected to the gate layer in a second direction, and the first direction, the second direction and the stacking direction are perpendicular to each other.

[0016] In one embodiment of the present application, the storage area corresponds to at least one contact area, and at least one contact area is located in the middle or periphery of the storage area.

[0017] On the other hand, the present application provides a method for preparing a semiconductor device, the method comprising: alternately stacking a first dielectric layer and a second dielectric layer to form a stacked structure; forming a first opening in the stacked structure, wherein the first opening extends along the stacking direction to the second dielectric layer at a first stacking height, and forming a first sacrificial layer connected to the second dielectric layer at the first stacking height in the first opening; extending the first opening along the stacking direction to the second dielectric layer at a second stacking height to form a second opening, and forming a second sacrificial layer connected to the second dielectric layer at the second stacking height in the second opening; and removing a portion of the first sacrificial layer, a portion of the second sacrificial layer and a portion of the second dielectric layer to form a sacrificial gap, and forming a gate layer and a plurality of connection layers respectively connected to the gate layers at different stacking heights in the sacrificial gap.

[0018] In one embodiment of the present application, the second dielectric layer at the second stack height and the second dielectric layer at the first stack height are both adjacent to the same first dielectric layer in the stacking direction.

[0019] In one embodiment of the present application, the method also includes: forming a gate line gap that passes through the stacking structure along the stacking direction; and removing a portion of the first sacrificial layer, a portion of the second sacrificial layer and a portion of the second dielectric layer through the gate line gap to form the sacrificial gap, wherein at least one of the plurality of gate line gaps extends in a first direction perpendicular to the stacking direction and passes through the second opening formed with the second sacrificial layer.

[0020] In one embodiment of the present application, forming a first opening in the stacking structure includes: forming an initial first opening in the stacking structure, wherein the initial first opening extends along the stacking direction to a first dielectric layer on a second dielectric layer at the first stacking height; forming a first initial isolation layer that at least covers the initial first opening; removing a portion of the first initial isolation layer located at the bottom of the initial first opening to form a first sidewall isolation layer; and extending the initial first opening along the stacking direction to the second dielectric layer at the first stacking height to form the first opening.

[0021] In one embodiment of the present application, forming a first sacrificial layer in the first opening connected to the second dielectric layer at the first stack height includes: forming an initial first sacrificial layer, the initial first sacrificial layer at least covering the first sidewall isolation layer, the side of the second dielectric layer at the first stack height exposed in the first opening, and the bottom of the first opening; and removing a portion of the initial first sacrificial layer located at the bottom of the first opening to form the first sacrificial layer.

[0022] In one embodiment of the present application, extending the first opening along the stacking direction to form a second opening includes: extending the first opening formed with the first sacrificial layer to the next first dielectric layer along the stacking direction to form an initial second opening, wherein the next first dielectric layer is located above the second dielectric layer at the second stacking height; forming a second initial isolation layer that at least covers the initial second opening; removing a portion of the second initial isolation layer located at the bottom of the initial second opening to form a second sidewall isolation layer; and extending the initial second opening to the second dielectric layer at the second stacking height along the stacking direction to form the second opening.

[0023] In one embodiment of the present application, forming a second sacrificial layer in the second opening connected to the second dielectric layer at the second stack height includes: forming an initial second sacrificial layer, the initial second sacrificial layer at least covering the second sidewall isolation layer, the side of the second dielectric layer at the second stack height exposed in the second opening, and the bottom of the second opening; and removing a portion of the initial second sacrificial layer located at the bottom of the second opening to form the second sacrificial layer.

[0024] In one embodiment of the present application, after forming the second sacrificial layer, the method further includes: forming a contact hole dielectric filling layer that at least fills a remaining space of the second opening.

[0025] On the other hand, the present application provides a method for preparing a semiconductor device, the method comprising: forming a stacking structure comprising a plurality of stacking layers, wherein each of the stacking layers comprises a first dielectric layer and a second dielectric layer; forming a first opening in the stacking structure, and forming a first sacrificial layer in the first opening that is respectively connected to the second dielectric layers at different stacking heights, wherein the first opening is divided into a first branch opening and a second branch opening in a first direction perpendicular to the stacking direction, and the first branch opening and the second branch opening respectively extend along the stacking direction to the second dielectric layers at different stacking heights; extending the first opening along the stacking direction to form the second opening, and forming a second sacrificial layer in the second opening that is respectively connected to the different next second dielectric layers, wherein the second opening is divided into a third branch opening and a fourth branch opening in the first direction, and the third branch opening and the fourth branch opening respectively extend along the stacking direction to the different next second dielectric layers; and removing a portion of the first sacrificial layer, a portion of the second sacrificial layer and a portion of the second dielectric layer to form a sacrificial gap, and forming a gate layer and a plurality of connection layers respectively connected to the gate layers at different stacking heights in the sacrificial gap. In one embodiment of the present application, the different next second dielectric layers and the second dielectric layers at different stacking heights are respectively adjacent to the same first dielectric layer in the stacking direction.

[0026] In one embodiment of the present application, the method also includes: forming a gate line gap that runs through the stacking structure along the stacking direction; and removing a portion of the first sacrificial layer, a portion of the second sacrificial layer and a portion of the second dielectric layer through the gate line gap to form the sacrificial gap, wherein at least one of the plurality of gate line gaps extends in the first direction and runs through the third branch opening and the fourth branch opening where the second sacrificial layer is formed.

[0027] In one embodiment of the present application, forming a first opening in the stacking structure includes: removing a portion of at least two top stacking layers in a predetermined area of ​​the stacking structure; forming an initial first opening, wherein the initial first opening is divided into a first initial branch opening and a second initial branch opening in the first direction, and the first initial branch opening or the second initial branch opening is located in the predetermined area; and forming the first opening via the initial first opening.

[0028] In one embodiment of the present application, the number of the plurality of connection layers is the same as the number of the at least two stacked layers that are removed.

[0029] In one embodiment of the present application, the first initial branch opening and the second initial branch opening respectively extend to different first dielectric layers along the stacking direction, and the different first dielectric layers are respectively located above the second dielectric layers at different stacking heights.

[0030] In one embodiment of the present application, forming the first opening through the initial first opening includes: forming a first initial isolation layer that at least covers the initial first opening; removing a portion of the first initial isolation layer located at the bottom of the initial first opening to form a first sidewall isolation layer; and extending the initial first opening along the stacking direction to the second dielectric layer at the different stacking heights to form the first opening.

[0031] In one embodiment of the present application, forming a first sacrificial layer in the first opening that is respectively connected to the second dielectric layers at different stacking heights includes: forming an initial first sacrificial layer, the initial first sacrificial layer at least covering the first sidewall isolation layer, the side of the second dielectric layer at different stacking heights exposed in the first opening, and the bottom of the first opening; and removing a portion of the initial first sacrificial layer located at the bottom of the first opening to form the first sacrificial layer.

[0032] In one embodiment of the present application, extending the first opening along the stacking direction to form the second opening includes: extending the first opening formed with the first sacrificial layer along the stacking direction to form an initial second opening, wherein the initial second opening is divided into a third initial sub-opening and a fourth initial sub-opening in the first direction, and the third initial sub-opening and the fourth initial sub-opening respectively extend to different next first dielectric layers along the stacking direction, and the different next first dielectric layers are respectively located above the different next second dielectric layers; forming a second initial isolation layer that at least covers the initial second opening; removing a portion of the second initial isolation layer located at the bottom of the initial second opening to form a second sidewall isolation layer; and extending the initial second opening to the different next second dielectric layer along the stacking direction to form the second opening.

[0033] In one embodiment of the present application, forming a second sacrificial layer in the second opening that is respectively connected to the different next second dielectric layers includes: forming an initial second sacrificial layer, the initial second sacrificial layer at least covering the second sidewall isolation layer, the side of the different next second dielectric layer exposed in the second opening, and the bottom of the second opening; and removing a portion of the initial second sacrificial layer located at the bottom of the second opening to form the second sacrificial layer.

[0034] Another aspect of the present application provides a storage system, which includes: a controller; and the semiconductor device provided in any one of the aspects of the present application, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0035] In one embodiment of the present application, the semiconductor device includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0036] According to the semiconductor device and its preparation method and storage system provided by at least one embodiment of the present application, there is no need to form a step and a word line contact located on the step in the semiconductor device. Specifically, the semiconductor device may include a stacked structure and a plurality of contact structures arranged in the stacked structure, and the electrical connection between the gate layer located at different stacking heights and the external circuit can be achieved through the connection layer of the contact structure, thereby simplifying the preparation process and reducing the production cost, while improving the unit storage density, reliability and overall performance of the semiconductor device.

[0037] In addition, the contact structure includes multiple connection layers, and among the multiple gate layers connected to the multiple connection layers of the same contact structure, at least some of the gate layers are located at different stacking heights. Therefore, the electrical connection between at least two gate layers with different stacking heights and the external circuit can be achieved through the multiple connection layers of a contact structure, effectively reducing the actual space of the contact area where the contact structure is located. While stabilizing the comprehensive performance of the semiconductor device, the unit storage density is further improved and the cost of the unit storage unit is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. In the drawings:

[0039] Figure 1 is a partial top view schematic diagram of a semiconductor device according to one embodiment of the present application;

[0040] Figure 2 yes Figure 1 The semiconductor device is shown as an enlarged schematic top view at position E;

[0041] Figure 3 yes Figure 1 A schematic cross-sectional view of the semiconductor device shown is taken along line AA';

[0042] Figure 4 yes Figure 1 A schematic cross-sectional view of the semiconductor device shown is taken along line BB';

[0043] Figure 5 yes Figure 1 A schematic cross-sectional view of the semiconductor device shown is taken along line CC';

[0044] Figure 6 yes Figure 1 A schematic cross-sectional view of the semiconductor device shown is taken along line DD';

[0045] Figure 7 is a partial top view schematic diagram of a semiconductor device according to another embodiment of the present application;

[0046] Figure 8 yes Figure 7 The semiconductor device is shown as an enlarged schematic top view at F;

[0047] Fig. 9 yes Figure 7 A schematic cross-sectional view of the semiconductor device shown is taken along line G-G';

[0048] Fig.10 yes Figure 7 A schematic cross-sectional view of the semiconductor device shown is taken along line H-H'; Fig.11 yes Figure 7 A schematic cross-sectional view of the semiconductor device shown is taken along line II';

[0049] Fig.12 yes Figure 7 A schematic cross-sectional view of the semiconductor device shown is taken along line J-J';

[0050] Figure 13-Figure 15 They are respectively partial top views of a semiconductor device according to an embodiment of the present application;

[0051] Fig.16 is a schematic top view of a stacked structure according to one embodiment of the present application;

[0052] Fig.17 is a schematic top view of a stacked structure according to another embodiment of the present application;

[0053] Fig.18 The present invention is a flow chart of a method for preparing a semiconductor device according to one embodiment of the present application.

[0054] Figure 19- Fig.34B They are respectively process schematic diagrams of a method for preparing a semiconductor device according to an embodiment of the present application;

[0055] Fig.35 is a flow chart of a method for preparing a semiconductor device according to one embodiment of the present application;

[0056] Fig.36A is a schematic top view of a structure formed after an initial first opening is formed according to a preparation method of one embodiment of the present application;

[0057] Fig.36B is a schematic cross-sectional view of a structure formed after an initial first opening is formed according to a preparation method of one embodiment of the present application; and

[0058] Fig.37 It is a schematic diagram of the storage system structure according to one embodiment of the present application.

[0059] Specific method

[0060] The present application will be described in detail below in conjunction with the accompanying drawings. The exemplary embodiments mentioned herein are only used to explain the present application and are not used to limit the scope of the present application. Throughout the specification, the same reference numerals refer to the same elements.

[0061] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximation, not degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0062] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "including", "including", "having", "having" and / or "having" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or parts, but do not exclude the presence or addition of one or more other features, elements, parts and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. When describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0063] In addition, when the expressions “connected”, “covered” and / or “formed on” are used in the present application, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or inferred from the context.

[0064] Unless otherwise specified, all words (including technical terms and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. In addition, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0065] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0066] Figure 1 is a partial top view of a semiconductor device 1000 according to an embodiment of the present application. Figure 2 yes Figure 1 The semiconductor device 1000 is shown as an enlarged schematic top view at E.

[0067] Figure 3 yes Figure 1 The semiconductor device 1000 is shown as a schematic cross-sectional view taken along line AA′.

[0068] Figure 4 yes Figure 1 The semiconductor device 1000 is shown as a schematic cross-sectional view taken along line BB′.

[0069] Figure 5 yes Figure 1 The semiconductor device 1000 is shown as a schematic cross-sectional view taken along line CC′.

[0070] Figure 6 yes Figure 1 The semiconductor device 1000 is shown in a schematic cross-sectional view taken along line DD′.

[0071] Figure 7 is a partial top view of a semiconductor device 1000 according to another embodiment of the present application. Figure 8 yes Figure 7 The semiconductor device 1000 is shown as an enlarged schematic top view at F. Fig. 9 yes Figure 7The semiconductor device 1000 is shown as a schematic cross-sectional view taken along line GG′. Fig.10 yes Figure 7 The semiconductor device 1000 is shown as a schematic cross-sectional view taken along line HH′. Fig.11 yes Figure 7 The semiconductor device 1000 is shown as a schematic cross-sectional view taken along line II′. Fig.12 yes Figure 7 The semiconductor device 1000 is shown as a schematic cross-sectional view taken along line JJ′.

[0072] like Figure 1-Figure 12 As shown, the semiconductor device 1000 may include: a stacked structure 200 and a contact structure 500. The stacked structure 200 includes a plurality of first dielectric layers 210 and a plurality of gate layers 230 that are alternately stacked, wherein the plurality of gate layers 230 may include, for example, a first gate layer 231, a second gate layer 232, a third gate layer 233, and a fourth gate layer 234. The contact structure 500 extends in the stacked structure 200 along the stacking direction (z direction), and includes a plurality of connection layers 530 connected to the plurality of gate layers 230. For example, a first connection layer 531, a second connection layer 532, a third connection layer 533, and a fourth connection layer 534, wherein among the plurality of gate layers 230 connected to the plurality of connection layers 530, at least some of the gate layers are located at different stacking heights.

[0073] For example, in this application Figure 1-Figure 6 In the embodiment shown, the first connection layer 531 and the third connection layer 533 are respectively connected to the first gate layer 231; the second connection layer 532 and the fourth connection layer 534 are respectively connected to the second gate layer 232, and the first gate layer 231 and the second gate layer 232 are located at different stacking heights; in the present application Figure 7-Figure 12 In the illustrated embodiment, the first connection layer 531 is connected to the first gate layer 231; the second connection layer 532 is connected to the second gate layer 232; the third connection layer 533 is connected to the third gate layer 233; and the fourth connection layer 534 is connected to the fourth gate layer 234, wherein the first gate layer 231, the second gate layer 232, the third gate layer 233 and the fourth gate layer 234 are all located at different stacking heights.

[0074] It can be understood by those skilled in the art that Figure 1-Figure 12 The number of the plurality of gate layers 230, the number of the plurality of first dielectric layers 210, the number of the contact structures 500, and the number of the plurality of connection layers 530 included in the contact structure 500 are shown for the sake of illustration only, and the present application is not limited thereto, and the specific number can be set according to actual needs. In fact, the number of the plurality of connection layers 530 included in the contact structure 500 can be greater than or equal to 4.

[0075] According to the semiconductor device provided by at least one embodiment of the present application, there is no need to form a step and a word line contact located on the step in the semiconductor device. Specifically, the semiconductor device may include a stacked structure and a plurality of contact structures arranged in the stacked structure, and the electrical connection between the gate layer located at different stacking heights and the external circuit can be achieved through the connection layer of the contact structure, thereby simplifying the preparation process and reducing the production cost, while improving the unit storage density, reliability and overall performance of the semiconductor device.

[0076] In addition, the contact structure includes multiple connection layers, and among the multiple gate layers connected to the multiple connection layers of the same contact structure, at least some of the gate layers are located at different stacking heights. Therefore, the electrical connection between at least two gate layers with different stacking heights and the external circuit can be achieved through the multiple connection layers of a contact structure, effectively reducing the actual space of the contact area where the contact structure is located. While stabilizing the comprehensive performance of the semiconductor device, the unit storage density is further improved and the cost of the unit storage unit is reduced.

[0077] Figure 13-Figure 15 Each of them is a partial top view of a semiconductor device 1000 according to an embodiment of the present application.

[0078] Specifically, combined Figure 3-Figure 6 as well as Figure 13-Figure 15 The stacked structure 200 can be arranged on a substrate and includes a storage area 02 and a contact area 01 adjacently distributed in a plane parallel to the substrate (xy plane, in which the x direction, the y direction and the z direction are perpendicular to each other), wherein the storage area 02 includes a plurality of first dielectric layers 210 and a plurality of gate layers 230 stacked alternately; the contact area 01 includes a plurality of first dielectric layers 210 and a plurality of second dielectric layers 220' stacked alternately.

[0079] The gate layer 230 may include a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon or silicide. The first dielectric layer 210 may be used as an isolation stacking layer, including but not limited to insulating dielectric material layers such as silicon oxide layers. Among them, the first dielectric layer 210 and the second dielectric layer 220' are two different insulating dielectric material layers. For example, the second dielectric layer 220' may include but not limited to insulating dielectric material layers such as silicon nitride layers. In addition, multiple second dielectric layers 220' and multiple gate layers 230 may have the same stacking height. In addition, the number of layers of the stacked structure 200 is not limited to the number of layers shown in the figure, and can be set separately as needed, such as 32 layers, 64 layers, 128 layers, etc.

[0080] In addition, with the increasing demand for the storage capacity of semiconductor devices, the above-mentioned storage stacking layers are gradually increasing. The stacking structure 200 may include a plurality of sub-stacked structures formed by adopting a double stacking technology or a multi-stacked technology. A plurality of sub-stacked structures may be stacked in sequence in the stacking direction to form a stacking structure 200, wherein each sub-stacked structure may include a storage area and a contact area adjacently distributed in a plane perpendicular to the stacking direction. The storage area includes a first dielectric layer and a gate layer stacked on each other, and the contact area includes a first dielectric layer and a second dielectric layer stacked on each other. The number of layers of each sub-stacked structure may be the same or different. The content of a single stacked structure described in this article may be fully or partially applicable to a stacked structure formed by a plurality of sub-stacked structures, and therefore the content related or similar thereto will not be repeated.

[0081] The contact region 01 may include alternately stacked first dielectric layers 210 and composite layers, wherein each of the plurality of composite layers may include a second dielectric layer 220 ′ and a gate layer 230 connected and distributed to each other in an xy plane, wherein the gate layer 230 extends from the storage region 02 into the contact region 01 .

[0082] Each of the plurality of connection layers 530 may include a conductive material, such as any one or combination of tungsten, cobalt, copper, aluminum, doped crystalline silicon or silicide, so that the gate layer 230 can be electrically connected to an external circuit through the corresponding connection layer. Specifically, each of the plurality of connection layers 530 may extend in a direction substantially in the z direction in the stacked structure 200 to the corresponding gate layer, and extend in the xy plane at the corresponding gate layer to form a connection with the corresponding gate layer.

[0083] Taking three-dimensional memory as an example, semiconductor devices generally include a stacked structure formed by alternating gate layers and dielectric layers, wherein the word line contact located in the step area of ​​the stacked structure can realize the electrical connection between the gate layer and the external circuit. However, as the number of stacked layers increases, the formation of word line contacts in the step area requires multiple processes such as photolithography and etching to form the stepped morphology of the steps, which greatly increases the manufacturing cost of semiconductor devices; at the same time, the more steps there are, the larger the area of ​​the step area to be formed, which is not conducive to improving the integration of semiconductor devices. In addition, the more stacked layers there are, the more severe the warping of the wafer, and it will be more difficult to align the word line contact with the step surface in the step area, resulting in the degradation of the reliability of the semiconductor device or the low yield of the electrical test, and ultimately affecting the reliability and overall performance of the semiconductor device.

[0084] The semiconductor device provided in the embodiment of the present application does not need to form steps and word line contacts located on the steps. Electrical connection between gate layers located at different stacking heights and external circuits can be achieved by providing multiple contact structures in the second area of ​​the stacked structure. This can simplify the preparation process and reduce the production cost, while improving the unit storage density, reliability and overall performance of the semiconductor device.

[0085] In addition, the contact structure includes multiple connection layers, and among the multiple gate layers connected to the multiple connection layers of the same contact structure, at least some of the gate layers are located at different stacking heights. Therefore, the multiple connection layers of a contact structure can realize electrical connection between at least two gate layers with different stacking heights and an external circuit, effectively reducing the actual space of the contact area where the contact structure is located. While stabilizing the comprehensive performance of the semiconductor device, the unit storage density is further improved and the cost of the unit storage unit is reduced.

[0086] In addition, in one embodiment of the present application, the semiconductor device 1000 also includes a gate line isolation structure 400 that penetrates the stacked structure 200 along the z direction, wherein at least one of the multiple gate line isolation structures 400 extends in a first direction (for example, the x direction) perpendicular to the z direction and penetrates the contact structure 500.

[0087] like Figure 13-Figure 15 As shown, the plurality of gate line isolation structures 400 may include at least one of a first gate line isolation structure 401, a second gate line isolation structure 402, a third gate line isolation structure 403, and a fourth gate line isolation structure 404. The first gate line isolation structure 401 extends continuously through the storage area 02 and the contact area 01 along the x direction; the second gate line isolation structure 402 extends intermittently through the storage area 02 and the contact area 01 along the x direction; the third gate line isolation structure 403 extends in the storage area 02 along the x direction; and the fourth gate line structure 404 extends in the contact area 01 along the x direction.

[0088] Optionally, the first gate line isolation structure 401 adjacently distributed along the y direction divides the semiconductor device 1000 into a plurality of storage block regions b (block), each storage block region b includes a plurality of contact structures 500 and a plurality of channel structures 300 arranged in an array, wherein the plurality of contact structures 500 are distributed in the contact area 01, and the plurality of channel structures 300 form a storage array and are distributed in the storage area 02. The second gate line isolation structure 402, the third gate line isolation structure 403 and the fourth gate line isolation structure 404 further divide each storage block region into a plurality of storage finger regions f (finger).

[0089] It should be noted that Figure 13-Figure 15To facilitate observation of the distribution of the contact structures 500 located in the contact region 01 , the entire top view of the semiconductor device 1000 is not shown. For example, a large number of channel structures 300 are omitted, and only a plurality of channel structures 300 close to the contact region 01 are shown.

[0090] In one embodiment of the present application, at least one of the first gate line isolation structure 401 , the second gate line isolation structure 402 , and the fourth gate line isolation structure 404 penetrates the contact structure 500 located in the contact region 01 along the x direction.

[0091] Optionally, the plurality of contact structures 500 penetrated by different gate line isolation structures 400 are aligned with each other or staggered with each other in the y direction. Fig.13 As shown, the multiple contact structures 500 penetrated by different first gate line isolation structures 401 are aligned with each other in the y direction; Fig.14 As shown, the multiple contact structures 500 penetrated by different second gate line isolation structures 402 are arranged staggered with each other in the y direction; Fig.15 As shown, the plurality of contact structures 500 penetrated by different fourth gate line isolation structures 404 are arranged staggered with each other in the y direction.

[0092] The multiple connection layers of the contact structure can realize the electrical connection between at least two gate layers with different stacking heights and the external circuit. On this basis, the layout of multiple contact structures 500 can be reasonably planned in different storage block areas b and storage finger areas f according to actual needs to further reduce the actual space of the contact area where the contact structure is located. While stabilizing the comprehensive performance of the semiconductor device, the unit storage density is further improved and the cost of the unit storage unit is reduced.

[0093] In one embodiment of the present application, the gate 230 may be formed by a gate-last process. In other words, the first dielectric layer 210 and the gate sacrificial layer (e.g., the second dielectric layer) may be alternately stacked to form a stacked structure (not shown); a portion of the gate sacrificial layer in the stacked structure may be removed by a process such as wet etching through a gate line gap (not shown) that accommodates the gate line isolation structure 400 to form a sacrificial gap (not shown); and the sacrificial gap may be filled with a conductive material to form a gate layer 230, thereby forming a stacked structure 200. Therefore, the second dielectric layer 220' included in the stacked structure 200 is the gate sacrificial layer remaining through the above process.

[0094] In the above process of removing part of the second dielectric layer in the stacked structure, the gate line gap can be used as a path for providing etchant and chemical precursor. In other words, the etchant and chemical precursor need to contact each second dielectric layer through the gate line gap generated when forming the gate line isolation structure 400, and then remove part of the second dielectric layer.

[0095] In one embodiment of the present application, at least one of the plurality of gate line isolation structures 400 extends in the x direction and penetrates the contact structure 500. Therefore, at least one of the plurality of gate line gaps also extends in the x direction and penetrates the initial contact structure (not shown) used to form the contact structure 500. Considering that the contact structure 500 can be made of the same material as the gate layer 230, the contact structure 500 can be formed in the process of forming the gate layer 230, and the etchant and the chemical precursor contact each second dielectric layer and each sacrificial layer of the initial contact structure through the gate line gap, and then remove a portion of the second dielectric layer and a portion of each sacrificial layer, thereby forming a sacrificial gap for accommodating the gate layer 230 and a connection gap (not shown) for accommodating the conductive portion of the connection layer in the contact structure 500. Through the above process, the manufacturing process of the semiconductor device can be simplified and the production cost of the semiconductor device can be reduced.

[0096] In addition, in one embodiment of the present application, reference Figure 2 , Figure 6 , Figure 8 and Fig.13 The gate line isolation structure 400 that penetrates the contact structure 500 divides the complete contact structure 500 into two parts, a first part 501 and a second part 502 .

[0097] like Figure 2 and Figure 6 As shown, as an option, in the first part 501, the multiple connection layers of the contact structure 500 include, for example, a first connection layer 531 and a second connection layer 532 from the outside to the inside; in the second part 502, the multiple connection layers of the contact structure 500 include, for example, a third connection layer 533 and a fourth connection layer 534 from the outside to the inside, wherein the first connection layer 531 and the third connection layer 533 extend in the stacked structure 200 along the z direction respectively and are connected to the first gate layer 231; the second connection layer 532 and the fourth connection layer 534 extend in the stacked structure 200 along the z direction respectively and are connected to the second gate layer 232, wherein the first gate layer 231 and the second gate layer 232 have different stacking heights, and the first gate layer 231 respectively connected to the first connection layer 531 and the third connection layer 533 belong to different storage block regions b (such as Fig.13 as shown) or different storage areas f (such as Fig.13 As shown), the second gate layer 232 connected to the second connection layer 532 and the fourth connection layer 534 respectively also belongs to different storage block regions b or different storage finger regions f.

[0098] Optionally, in the above embodiments of the present application, the first gate layer 231 and the second gate layer 232 are both adjacent to the same first dielectric layer 211 in the z direction.

[0099] like Figure 8 and Fig.11 As shown, as another option, in the first part 501, the multiple connection layers of the contact structure 500 include, from the outside to the inside, for example, a first connection layer 531 and a second connection layer 532; in the second part 502, the multiple connection layers of the contact structure 500 include, from the outside to the inside, for example, a third connection layer 533 and a fourth connection layer 534, wherein the first connection layer 531, the second connection layer 532, the third connection layer 533 and the fourth connection layer 534 extend in the stacked structure 200 along the z direction, respectively, and are connected to the gate layers at different stacking heights, for example, the first connection layer 531 is connected to the first gate layer 231; the second connection layer 532 is connected to the second gate layer 232; the third connection layer 533 is connected to the third gate layer 233; and the fourth connection layer 534 is connected to the fourth gate layer 234, wherein the first gate layer 231, the second gate layer 232, the third gate layer 233 and the fourth gate layer 234 all have different stacking heights.

[0100] Optionally, in the above embodiment of the present application, the first gate layer 231 and the second gate layer 232 are adjacent to the same first dielectric layer 211 in the z direction. The third gate layer 233 and the fourth gate layer 234 are adjacent to the same third dielectric layer 213 in the z direction.

[0101] In addition, refer again Figure 1-Figure 12 In one embodiment of the present application, at least one of the multiple connection layers included in the contact structure 500 includes a conductive section and a spacing dielectric section, for example, the first connection layer 531 includes a conductive section 531-1 and a spacing dielectric section 531-2; the second connection layer 532 includes a conductive section 532-1 and a spacing dielectric section 532-2; the third connection layer 533 includes a conductive section 533-1 and a spacing dielectric section 533-2; and the fourth connection layer 534 includes a conductive section 534-1 and a spacing dielectric section 534-2.

[0102] Optionally, the projection of at least one of the plurality of connection layers in the xy plane is arc-shaped. For example, the projections of the first connection layer 531 , the second connection layer 532 , the third connection layer 533 , and the fourth connection layer 534 in the xy plane are all arc-shaped.

[0103] In addition, in the xy plane, the conductive subdivision of at least one of the plurality of connection layers is adjacent to the gate line isolation structure 400. The conductive subdivision 531-1 of the first connection layer 531, the conductive subdivision 532-1 of the second connection layer 532, the conductive subdivision 533-1 of the third connection layer 533, and the conductive subdivision 534-1 of the fourth connection layer 534 are adjacent to the gate line isolation structure 400 in the xy plane.

[0104] As described above, in the process of forming the contact structure 500 and the gate layer 230, the gate line gap accommodating the gate line isolation structure 400 can be used as a passage for providing an etchant and a chemical precursor, and a portion of the second dielectric layer in the stacked structure is removed through the gate line gap to form a sacrificial gap accommodating the gate layer 230; and a portion of each sacrificial layer of the initial contact structure is removed through the gate line gap to form a connection gap accommodating the conductive portion of the connection layer in the contact structure 500. Therefore, the conductive portion subsequently formed in the connection gap is adjacent to the gate line isolation structure 400, and the spacer dielectric portion of the connection layer in the contact structure 500 is the remaining sacrificial layer of the initial contact structure in the process of forming the connection gap.

[0105] In addition, reference Fig.13 In one embodiment of the present application, a dummy channel structure may not be provided in a region 11 where the contact structure 500 of the contact region 01 is located, wherein the region 11 is shown as a square virtual frame in the figure.

[0106] Specifically, the channel structure 300 and the stacked structure 200 included in the semiconductor device 1000 can form a storage cell string for data storage together. The channel structure 300 may include a functional layer (not shown) and a channel layer (not shown) having a circular shape on the xy plane and extending in the stacked structure 200 in the z direction, and the functional layer may include a barrier layer (e.g., silicon oxide), a charge trapping layer (e.g., silicon nitride), and a tunneling layer (e.g., silicon oxide). The channel layer may be prepared from any appropriate semiconductor material (such as polycrystalline silicon or single crystal silicon), and the semiconductor material may be selected to be undoped, or may be selected to include P-type or N-type doped conductive impurities. In addition, the channel structure 300 may also include a channel filling dielectric layer (not shown) surrounded by the channel layer.

[0107] The virtual channel structure 600 and the channel structure 300 may have partially the same internal structure. For example, in the process of forming the functional layer, the channel layer and the channel filling dielectric layer of the channel structure 300, the functional layer, the channel layer and the channel filling dielectric layer may also be filled in the virtual channel hole of the virtual channel junction 600. In addition, as another option, based on the virtual channel structure 600 not having a storage function, an insulating dielectric material layer such as a silicon oxide layer may also be filled in the virtual channel hole.

[0108] The dummy channel structure 600 can be used for process and electrical buffering. For example, taking a three-dimensional memory as an example, in the process of preparing a semiconductor device, multiple dummy channel structures 600 are arranged in the contact area 01, which can provide strong structural support for the operation of removing part of the second dielectric layer in the process of forming the gate layer.

[0109] Alternatively, if Figure 13-Figure 15As shown, the dummy channel structure 600 may not be provided in the region 11 of the contact region 01. In at least one embodiment of the present application, in the portion of the second dielectric layer of the stacked structure located in the region 11 and the sacrificial layer of the initial contact structure, only the portion adjacent to the gate line isolation structure 400 is replaced with a conductive gate layer and a conductive distribution, and most of the remaining sacrificial layer of the initial contact structure and most of the second dielectric layer located in the region 11 are retained. Therefore, in the above replacement process, since only a small amount of the second dielectric layer and the sacrificial layer are replaced with the gate layer and the conductive distribution, the region where the initial contact structure of the stacked structure is located has a reduced possibility of collapse, and there is no need to provide a dummy channel structure 600 for structural support in this region.

[0110] In other words, in some embodiments of the present application, no dummy channel structure may be provided in the region 11 where the contact structure 500 of the contact region 01 is located.

[0111] Fig.16 It is a schematic top view of a stacked structure 200 according to one embodiment of the present application. Fig.17 It is a schematic top view of a stacked structure 200 according to another embodiment of the present application.

[0112] In addition, if Figure 3 , Fig. 9 , Figure 13-Figure 17 As shown, in the semiconductor device 1000 provided in at least one embodiment of the present application, the stacked structure 200 may have a plurality of contact areas 01 and a plurality of storage areas 02, each storage area 02 corresponds to at least one contact area 01, wherein the contact area 01 can be used to form a plurality of contact structures 500, and the storage area 02 can be used to form a storage array composed of a plurality of channel structures 300 arranged and distributed, and the corresponding gate layers in the storage array are connected and conducted through the plurality of connection layers of the contact structure 500.

[0113] like Fig.16 As shown, according to some embodiments, at least one contact area 01 may be disposed on one side edge or multiple side edges of the storage area 02. Fig.17 As shown, according to some embodiments, at least one contact area 01 may be disposed in the middle of the storage area 02, and the storage area 02 may be divided into at least two sub-storage areas. The present application does not limit the relative position and specific structure of the contact area 01 and the storage area 02. In addition, the stacked structure 200 may also include a peripheral circuit area for forming a peripheral circuit.

[0114] Therefore, the semiconductor device provided by at least one embodiment of the present application has good scalability and compatibility, can be adapted to different device architectures, and is not limited by the number of stacked layers in the stacked structure.

[0115] In addition, reference Figure 1 and Figure 5 As an option, multiple contact structures 500 may include the same number of connection layers 530; as another option, multiple contact structures 500 may include different numbers of connection layers 530, and the specific number of multiple connection layers included in the contact structure in the semiconductor device can be set according to actual needs.

[0116] In addition, if Figure 3 and Fig. 9 As shown, the contact structure 500 may further include a sidewall spacer 520, for example, a first sidewall spacer 521 surrounding the first connection layer 531, and a second sidewall spacer 522 surrounding the second connection layer 532. In other words, in the xy plane, the sidewall spacer 520 is spaced apart from the connection layer 530. The material of the sidewall spacer 520 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or any combination thereof.

[0117] Fig.18 is a flow chart of a method 2000 for preparing a semiconductor device according to one embodiment of the present application. Figures 19A-34B They are respectively process schematic diagrams of a method 2000 for preparing a semiconductor device according to an embodiment of the present application.

[0118] like Fig.18 As shown, the method 2000 for preparing a semiconductor device may include:

[0119] S11, alternately stacking first dielectric layers and second dielectric layers to form a stacked structure.

[0120] S12, forming a first opening in the stack structure, wherein the first opening extends along the stacking direction to the second dielectric layer at the first stacking height, and forming a first sacrificial layer connected to the second dielectric layer at the first stacking height in the first opening.

[0121] S13, extending the first opening along the stacking direction to the second dielectric layer at the second stacking height to form a second opening, and forming a second sacrificial layer in the second opening connected to the second dielectric layer at the second stacking height.

[0122] S14, removing a portion of the first sacrificial layer, a portion of the second sacrificial layer and a portion of the second dielectric layer to form a sacrificial gap, and forming a gate layer and a plurality of connection layers respectively connected to the gate layers at different stacking heights in the sacrificial gap.

[0123] The following will be combined Figures 18 to 34B The specific process of each step of the above-mentioned preparation method 2000 in one embodiment of the present application is described in detail.

[0124] Step S11

[0125] Fig.19A It is a schematic top view of a structure formed after a stacked structure 200 ′ is formed according to a preparation method of an embodiment of the present application. Fig.19B It is a schematic cross-sectional view of a structure formed after forming a stacked structure 200 ′ according to a preparation method of one embodiment of the present application.

[0126] like Figure 18-19B As shown, step S11 of alternately stacking first dielectric layers and second dielectric layers to form a stacked structure may include, for example: providing an initial substrate 100; and alternately stacking first dielectric layers 210 and gate sacrificial layers 220 on the initial substrate 100 to form a stacked structure 200'.

[0127] In the subsequent step, a portion of the gate sacrificial layer 220 is replaced by Figure 3 In the gate layer 230 of the stacked structure 200 shown in FIG. 1 , another portion of the gate sacrificial layer 220 is retained as Figure 4 The second dielectric layer 220 ′ in the stacked structure 200 , and thus the gate sacrificial layer 220 , is also referred to as the second dielectric layer 220 hereinafter.

[0128] Specifically, in one embodiment of the present application, the material for preparing the initial substrate 100 can be any suitable semiconductor material, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or III-V compounds such as gallium arsenide. As an option, the initial substrate 100 can be selected from single crystal silicon.

[0129] In one embodiment of the present application, the initial substrate 100 may be, for example, a composite substrate for supporting a device structure thereon. The initial substrate 100 may be formed by sequentially arranging a plurality of layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0130] In one embodiment of the present application, the initial substrate 100 may include a substrate sacrificial layer for subsequently forming a semiconductor connection layer connecting the channel structure. The substrate sacrificial layer may include a single layer, a multilayer or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. As an option, the substrate sacrificial layer may be a high dielectric constant dielectric layer. As another option, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer and a dielectric layer arranged in sequence, wherein the dielectric layer may be a silicon nitride layer and the sacrificial layer may be a silicon oxide layer. As another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material and a conductive material. For example, the sacrificial layer may be single crystal silicon or polycrystalline silicon. Specifically, in one embodiment of the present application, an exemplary material for forming the sacrificial layer may be polycrystalline silicon.

[0131] Part of the initial substrate 100 may also form a well region doped with an N-type or P-type dopant via ion implantation or diffusion. The dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb); or any one or a combination of boron (B), gallium (Ga) or indium (In). In some embodiments of the present application, the well region may be prepared with the same dopant or with different dopants. Furthermore, the doping concentration of the well region may be the same or different, which is not limited in the present application.

[0132] After forming the initial substrate 100, a stacked structure 200' may be formed on the initial substrate 100 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in the present application.

[0133] The stack structure 200' may include a plurality of pairs of first dielectric layers 210 and second dielectric layers 220 alternately stacked with each other. For example, the stack structure may include 64 pairs, 128 pairs, or more than 128 pairs of first dielectric layers 210 and second dielectric layers 220.

[0134] In some embodiments, the first dielectric layer 210 and the second dielectric layer 220 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the first dielectric layer 210 and the second dielectric layer 220 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stacking layer, and the silicon nitride layer may be used as a sacrificial stacking layer. Subsequently, a portion of the sacrificial stacking layer may be etched away, and the etched portion of the sacrificial stacking layer may be replaced with a conductor layer including a conductive material to form a gate layer of the semiconductor device.

[0135] In addition, the stack structure may further include a cover layer 240, which is located at the highest point of the stack structure. The cover layer 240 includes but is not limited to an insulating dielectric material layer such as a silicon oxide layer.

[0136] The preparation method of a single stacking structure is described above. In fact, as the storage demand of semiconductor devices continues to increase, the storage stack gradually increases. In order to break through the limitations of traditional process limits, a double stacking technology or a multi-stack technology can also be used to form a stacking structure by stacking multiple sub-stack structures stacked in sequence in the direction of the thickness of the stacking structure, wherein each sub-stack structure may include a plurality of first dielectric layers and second dielectric layers alternately stacked. The number of layers of each sub-stack structure may be the same or different. Since the content and structure involved in the preparation process of the single stacking structure described above may be fully or partially applicable to the stacking structure formed by multiple sub-stack structures described here, the content related or similar thereto will not be repeated. However, it can be understood by those skilled in the art that subsequent preparation processes can be performed on the basis of a multi-stack structure or a single stack structure.

[0137] Furthermore, in one embodiment of the present application, after forming the stack structure 200 ′, the method 2000 for manufacturing a semiconductor device may further include: forming a channel structure 300 and a dummy channel structure 600 in the stack structure 200 ′.

[0138] In one embodiment of the present application, a first region (not shown) and a second region (not shown) adjacent to each other may be defined on the surface of the initial substrate 100. Subsequently, a stacked structure 200 (such as Figure 3 As shown), the stacked structure 200 may include a storage area 02 and a contact area 01 adjacently distributed in an xy plane (a plane perpendicular to the stacking direction (z direction)) parallel to the initial substrate 100, wherein the storage area 02 and the contact area 01 may be formed in the above-mentioned first area and second area, respectively, and include stacked layers formed of different materials.

[0139] Fig. 20 yes Fig.19B An enlarged schematic cross-sectional view of the channel structure 300 is shown.

[0140] like Fig.19B and Fig. 20 As shown, according to a preparation method of an embodiment of the present application, forming a plurality of channel structures 300 extending along the z direction in the stacked structure 200 ′ may include: forming a channel hole 310 ; and sequentially forming a functional layer 320 and a channel layer 330 on the inner wall of the channel hole 310 .

[0141] The channel structure 300 may include a semiconductor layer and a composite dielectric layer filled in the channel hole. The functional layer 320 and the channel layer 330 may be formed on the inner wall of the channel hole 310 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0142] Specifically, the channel hole 310 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The channel hole 310 may have a cylindrical or columnar shape extending in the z-direction in the stacked structure 200'. As an option, the channel hole 300 may extend into the initial substrate 100.

[0143] The functional layer 320 may include a blocking layer 321 formed on the inner wall of the channel hole 310 to block the outflow of charges, a charge capture layer 322 formed on the surface of the blocking layer 321 to store charges during operation of the semiconductor device, and a tunneling layer 323 formed on the surface of the charge capture layer 322.

[0144] In some embodiments, the functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 320 may have a structure different from the ONO configuration. The channel layer 330 may be formed on the surface of the tunneling layer 323 and can be used to transport the required charges (electrons or holes).

[0145] However, those skilled in the art should understand that, without departing from the teachings of the present application, they may choose to form a functional layer on the sidewalls and bottom surface of the channel hole, or form a functional layer on the sidewalls of the channel hole according to different semiconductor device architectures, and the present application does not limit this.

[0146] For example, as an option, according to one embodiment of the present application, a functional layer 320 may be formed on the sidewalls and bottom surface of the channel hole 310, and a channel layer 330 may be formed on the surface of the tunneling layer 323 of the functional layer 320 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0147] As another option, according to one embodiment of the present application, an epitaxial layer (not shown) may be first formed on the bottom surface of the channel hole 310, and a functional layer 320 may be formed on the sidewalls of the channel hole 310 and the surface of the epitaxial layer. After removing the portion of the functional layer 320 located on the surface of the epitaxial layer, a channel layer 330 may be formed on the surface of the tunneling layer of the remaining functional layer 320 and the surface of the epitaxial layer through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0148] In some embodiments, the channel layer 330 may be made of a semiconductor material such as polysilicon or monocrystalline silicon, and may have conductive impurities. For example, the channel layer 330 may be an N-type doped or P-type doped polysilicon layer. Similar to the channel hole 310, the channel layer 330 may also have a cylindrical or columnar shape extending in the z-direction in the stacked structure 200'. As an option, the channel layer 330 may also extend into the initial substrate 100.

[0149] In addition, a channel plug 350 may be formed at one end of the channel hole 310 away from the initial substrate 100 (which may be understood as the top of the channel structure 300). Specifically, after forming the functional layer 320 and the channel layer 330, the remaining space of the channel hole 310 may be filled with a channel filling dielectric layer 340. The channel filling dielectric layer 340 may include an oxidized dielectric layer, such as silicon oxide. Further, during the filling process, a plurality of insulating gaps may be formed in the channel filling dielectric layer 340 by controlling the channel filling process to relieve structural stress. Then, a channel plug 350 is formed in the portion of the channel filling dielectric layer 340 located at the top of the channel hole 310. The material of the channel plug 350 may be prepared from the same material as the channel layer 330, such as N-type doped or P-type doped polysilicon. The channel plug 340 is connected to the channel layer 330.

[0150] After forming the channel structure 300 , a dummy channel structure 600 having a spacing from the channel structure 300 in the first direction (x direction) may be formed in the same manner as described above, and thus related or similar contents are not described in detail herein.

[0151] In addition, as an option, based on the fact that the virtual channel structure 600 does not have a storage function, generally, in the virtual channel hole (not shown) of the virtual channel structure 600, only an insulating dielectric material layer such as a silicon oxide layer can be filled by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Similarly, by controlling the channel filling process, a plurality of insulating gaps can be formed in the insulating dielectric material layer to reduce the structural stress of the virtual channel structure.

[0152] After forming the channel structure 300 and the dummy channel structure 600, a plurality of channel structures 300 may form a channel structure array, and a plurality of dummy channel structures 600 may form a dummy channel structure array, and each array may be arranged in multiple rows and columns in the x direction and the y direction. The channel structure array may be distributed in the storage area 02. It should be noted that, Fig.19A and Fig.19B A large number of channel structures 300 are omitted, and only a plurality of channel structures 300 close to the contact region 01 are shown.

[0153] A plurality of dummy channel structures 600 may be distributed in the storage area 02 or the contact area 01. Since only a small amount of the second dielectric layer and the sacrificial layer of the initial contact structure are replaced with the gate layer and the conductive distribution in the subsequent steps, the area where the initial contact structure of the stacked structure is located has a reduced possibility of collapse, and it is not necessary to set a dummy channel structure 600 for structural support in this area. In other words, the dummy channel structure 600 may not be set in the area of ​​the contact area 01 used to set the contact structure.

[0154] Step S12

[0155] Fig.21A It is a schematic top view of a structure formed after an initial first opening 511 is formed according to a preparation method of an embodiment of the present application. Fig. 21B It is a schematic cross-sectional view of a structure formed after an initial first opening 511 is formed according to a preparation method of an embodiment of the present application. Fig.22A It is a schematic top view of a structure formed after forming a first sidewall isolation layer 521 according to a preparation method of an embodiment of the present application. Fig. 22B It is a schematic cross-sectional view of a structure formed after forming a first sidewall isolation layer 521 according to a preparation method of an embodiment of the present application. Fig.23A It is a schematic top view of a structure formed after forming a first opening 512 according to a preparation method of an embodiment of the present application. Fig. 23B It is a schematic cross-sectional view of a structure formed after forming the first opening 512 according to a preparation method of one embodiment of the present application. Fig.24A It is a schematic top view of a structure formed after forming an initial first sacrificial layer 531 - 1 according to a preparation method of one embodiment of the present application. Fig. 24B It is a schematic cross-sectional view of a structure formed after forming an initial first sacrificial layer 531 - 1 according to a preparation method of one embodiment of the present application. Fig.25A It is a schematic top view of a structure formed after forming a first sacrificial layer 531 ′ according to a preparation method of an embodiment of the present application. Fig.25B It is a schematic cross-sectional view of a structure formed after forming a first sacrificial layer 531 ′ according to a preparation method of an embodiment of the present application.

[0156] like Figures 19A-25B As shown, step S12 forms a first opening in the stacking structure, wherein the first opening extends along the stacking direction to the second dielectric layer at the first stacking height, and forming a first sacrificial layer connected to the second dielectric layer at the first stacking height in the first opening may, for example, include: forming a first opening in the stacking structure, wherein the first opening extends along the stacking direction to the second dielectric layer at the first stacking height; and forming a first sacrificial layer 531' in the first opening 512.

[0157] Specifically, Figures 19A-23B As shown, in one embodiment of the present application, forming a first opening 512 in a stacking structure 200' may include: forming an initial first opening 511 in the stacking structure 200', wherein the initial first opening 511 extends along the z direction to the first dielectric layer 211 on the second dielectric layer 221 at the first stacking height; forming a first initial isolation layer (not shown) that at least covers the initial first opening 511; removing a portion of the first initial isolation layer located at the bottom of the initial first opening 511 to form a first sidewall isolation layer 521; and extending the initial first opening 511 along the z direction to the second dielectric layer 221 at the first stacking height to form the first opening 512.

[0158] like Figures 19A-21B As shown, a plurality of initial first openings 511 may be formed in the contact region 01 of the stacked structure 200' by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The initial first openings 511 extend along the z direction to the first dielectric layer 211 on the second dielectric layer 221 at the first stack height.

[0159] like Figure 21A-Figure 22B As shown, a first initial isolation layer (not shown) may be formed on the upper surface of the stacked structure 200', the sidewalls and the bottom of the initial first opening 511 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The material forming the first initial isolation layer includes, but is not limited to, silicon oxide, silicon oxynitride, low-k dielectric, high-k dielectric or any combination thereof.

[0160] After the first initial isolation layer is formed, the portion of the first initial isolation layer located at the bottom of the initial first opening 511 and the portion of the first initial isolation layer located on the upper surface of the stacked structure 200' can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed to form a first sidewall isolation layer 521.

[0161] like Figure 22A-Figure 23B As shown, after the first isolation layer 521 is formed, the initial first opening 511 can be expanded along the z direction to the second dielectric layer 221 at the first stack height to form a first opening 512 by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed.

[0162] Alternatively, if Figure 23A-Figure 25B As shown, in one embodiment of the present application, forming a first sacrificial layer 531' connected to the second dielectric layer 221 at the first stack height in the first opening 512 may include: forming an initial first sacrificial layer 531-1, the initial first sacrificial layer 531-1 at least covering the first sidewall isolation layer 521, the side of the second dielectric layer 221 at the first stack height exposed in the first opening, and the bottom of the first opening 512; and removing a portion of the initial first sacrificial layer 531-1 located at the bottom of the first opening 512 to form a first sacrificial layer 531'.

[0163] Specifically, Figure 23A-Figure 24B As shown, an initial first sacrificial layer 531-1 is formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and the initial first sacrificial layer 531-1 at least covers the first sidewall isolation layer 521, the side of the second dielectric layer 221 at the first stack height exposed in the first opening, and the bottom of the first opening 512. Optionally, the initial first sacrificial layer 531-1 can be made of the same material as the second dielectric layer 220 of the stacked structure 200', so that it can be removed in the same process in subsequent steps. Optionally, the initial first sacrificial layer 531-1 can also be made of a different material from the second dielectric layer 220 of the stacked structure 200', and the material for preparing the initial first sacrificial layer 531-1 includes but is not limited to silicon nitride.

[0164] like Figure 24A-Figure 25B As shown, by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., are also performed to remove the portion of the initial first sacrificial layer 531-1 located at the bottom of the first opening 512 to form a first sacrificial layer 531', and the first sacrificial layer 531' is connected to the second dielectric layer 221 at the first stack height.

[0165] Step S13

[0166] Fig.26A It is a schematic top view of a structure formed after an initial second opening 513 is formed according to a preparation method of an embodiment of the present application. Fig.26B It is a schematic cross-sectional view of a structure formed after an initial second opening 513 is formed according to a preparation method of an embodiment of the present application. Fig.27A It is a schematic top view of a structure formed after forming a second initial isolation layer 522 - 1 according to a preparation method of one embodiment of the present application. Fig.27B It is a schematic cross-sectional view of a structure formed after forming a second initial isolation layer 522 - 1 according to a preparation method of an embodiment of the present application. Fig.28A It is a schematic top view of a structure formed after forming a second sidewall isolation layer 522 according to a preparation method of an embodiment of the present application. Fig.28B It is a schematic cross-sectional view of a structure formed after forming a second sidewall isolation layer 522 according to a preparation method of an embodiment of the present application. Fig.29A It is a schematic top view of a structure formed after forming the second opening 514 according to a preparation method of an embodiment of the present application. Fig.29B It is a schematic cross-sectional view of a structure formed after forming the second opening 514 according to a preparation method of an embodiment of the present application. Fig. 30A It is a schematic top view of a structure formed after forming an initial second sacrificial layer 532 - 1 according to a preparation method of one embodiment of the present application. Fig. 30B It is a schematic cross-sectional view of a structure formed after forming an initial second sacrificial layer 532 - 1 according to a preparation method of one embodiment of the present application. Fig.31A It is a schematic top view of a structure formed after forming a second sacrificial layer 532 ′ according to a preparation method of an embodiment of the present application. Fig.31B It is a schematic cross-sectional view of a structure formed after forming a second sacrificial layer 532 ′ according to a preparation method of an embodiment of the present application. Fig.32A It is a schematic top view of a structure formed after forming a contact hole dielectric filling layer 523 according to a preparation method of an embodiment of the present application. Fig.32B It is a schematic cross-sectional view of a structure formed after forming a contact hole dielectric filling layer 523 according to a preparation method of an embodiment of the present application.

[0167] like Figures 25A-32B As shown, step S13 extends the first opening along the stacking direction to the second dielectric layer at the second stacking height to form a second opening, and forms a second sacrificial layer in the second opening connected to the second dielectric layer at the second stacking height. It may, for example, include: extending the first opening along the stacking direction to the second dielectric layer at the second stacking height to form a second opening; and forming a second sacrificial layer in the second opening connected to the second dielectric layer at the second stacking height.

[0168] Specifically, Figure 25A-Figure 29BAs shown, in one embodiment of the present application, extending the first opening along the stacking direction to form the second opening includes: extending along the z direction to form the first opening 512 (eg, Fig. 23B The invention further comprises the steps of: extending the first dielectric layer 212 from the first dielectric layer 214 to the second dielectric layer 222 at the second stacking height; forming a second initial isolation layer 522-1 at least covering the initial second opening 513; removing a portion of the second initial isolation layer 522-1 located at the bottom of the initial second opening 513 to form a second sidewall isolation layer 522; and extending the initial second opening 513 along the z direction to the second dielectric layer 222 at the second stacking height to form a second opening 514.

[0169] Alternatively, if Figure 25A-Figure 26B As shown, the first opening 512 (such as the first opening 512 of the first sacrificial layer 531') can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, can also be performed to expand along the z direction to form the first opening 512 having the first sacrificial layer 531'. Fig. 23B As shown in FIG. 1 , the first dielectric layer 212 is extended to form an initial second opening 513 .

[0170] In one embodiment of the present application, the second dielectric layer 222 at the second stack height and the second dielectric layer 221 at the first stack height are both adjacent to the same first dielectric layer 212 in the z direction. The next first dielectric layer 212 is located above the second dielectric layer 222 at the second stack height.

[0171] like Figure 26A-Figure 27B As shown, a second initial isolation layer 522-1 may be formed on the upper surface of the stacked structure 200', the sidewall and the bottom of the initial second opening 513 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The material forming the second initial isolation layer 522-1 includes, but is not limited to, silicon oxide, silicon oxynitride, low-k dielectric, high-k dielectric or any combination thereof. Optionally, the second initial isolation layer 522-1 may be prepared using the same material as the first initial isolation layer.

[0172] like Figure 27A-Figure 28B As shown, the portion of the second initial isolation layer 522-1 located at the bottom of the initial second opening 513 can be removed to form a second sidewall isolation layer 522 by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed.

[0173] like Fig.26A , Fig.26B , Figure 28A-Figure 29B As shown, after forming the second sidewall isolation layer 522, the initial second opening 513 can be expanded along the z direction to the second dielectric layer 222 at the second stack height to form a second opening 514 by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed.

[0174] like Figures 29A-32B As shown, in one embodiment of the present application, forming a second sacrificial layer connected to the second dielectric layer at the second stack height in the second opening includes: forming an initial second sacrificial layer 532-1, the initial second sacrificial layer 532-1 at least covering the second sidewall isolation layer 522, the side of the second dielectric layer 222 at the second stack height exposed in the second opening 514, and the bottom of the second opening 514; and removing a portion of the initial second sacrificial layer 532-1 located at the bottom of the second opening 514 to form a second sacrificial layer 532'.

[0175] Specifically, Figures 29A-30B As shown, an initial second sacrificial layer 532-1 is formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and the initial second sacrificial layer 532-1 at least covers the second sidewall isolation layer 522, the side of the second dielectric layer 222 at the second stack height exposed in the second opening 514, and the bottom of the second opening 514.

[0176] like Figure 30A-Figure 31B As shown, by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., are also performed to remove the initial second sacrificial layer 532-1 located at the second opening 514 (such as Fig.29B As shown in the figure), a bottom portion of the sacrificial layer 532' is formed.

[0177] Alternatively, if Figure 31A-Figure 32B As shown, after forming the second sacrificial layer 532', the method 2000 for preparing a semiconductor device further includes: forming at least filling the second opening 514 (such as Fig.29B The contact hole dielectric filling layer 523 fills the remaining space of the contact hole.

[0178] Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof is used to deposit a thin film in the second opening 514 (eg, Fig.29BThe remaining space of the contact hole dielectric filling layer 523 is formed. The material forming the contact hole dielectric filling layer 523 includes but is not limited to silicon oxide, silicon oxynitride, low-k dielectric, high-k dielectric or any combination thereof. As an option, the contact hole dielectric filling layer 523, the second initial isolation layer and the first initial isolation layer can be made of the same material.

[0179] After forming the contact hole dielectric filling layer 523, an initial contact structure 500' may be formed in the stack structure 200'. The initial contact structure 500' includes a plurality of sacrificial layers respectively connected to the second dielectric layer 220 at different stack heights in the stack structure 200', such as a first sacrificial layer 531' and a second sacrificial layer 532'.

[0180] It can be understood by those skilled in the art that the above steps and related drawings only show the formation process of the first sacrificial layer 531' and the second sacrificial layer 532', but the number of the initial contact structure 500' and the number of the multiple sacrificial layers included in the initial contact structure 500' are only shown for the convenience of illustration. In fact, the number of the multiple sacrificial layers included in the initial contact structure 500' may be greater than or equal to 2, and the preparation process of the sacrificial layer may be formed according to the formation process of the first sacrificial layer 531' and the second sacrificial layer 532'.

[0181] In addition, it should be noted that Figures 21A-32B In the figure, since the cross-sectional shapes of the initial first opening 511, the first opening 512, the initial second opening 513 and the second opening 514 formed in step S12 and step S13 in the yz plane are similar to their cross-sectional shapes in the xz plane, the cross-sectional shapes of the first initial isolation layer, the first side wall isolation layer 521, the second initial isolation layer 522-1, the second side wall isolation layer 522, the initial first sacrificial layer 531-1, the first sacrificial layer 531', the initial second sacrificial layer 532-1 and the second sacrificial layer 532' in the yz plane are similar to their cross-sectional shapes in the xz plane, only the top view schematic diagram of the preparation intermediate in the xy plane and the cross-sectional schematic diagram in the yz plane of the preparation method according to one embodiment of the present application are shown.

[0182] Step S14

[0183] Fig.33A It is a schematic top view of a structure formed after a gate line gap 410 is formed according to a preparation method of an embodiment of the present application. Fig.33B yes Fig.33A The intermediate body 1001 is shown as a schematic cross-sectional view taken along line KK′. Fig.33C yes Fig.33A The intermediate body 1001 is shown as a schematic cross-sectional view taken along line LL'.

[0184] like Figure 1-Figure 6 , Figure 33A-Figure 33C As shown, step S14 removes part of the first sacrificial layer, part of the second sacrificial layer and part of the second dielectric layer to form a sacrificial gap, and forms a gate layer and a plurality of connection layers respectively connected to the gate layers at different stacking heights in the sacrificial gap, which may include, for example: forming a gate line gap 410; removing part of the first sacrificial layer 531', part of the second sacrificial layer 532' and part of the second dielectric layer 220 through the gate line gap 410 to form a sacrificial gap (not shown); forming a gate layer 230 and a plurality of connection layers 530 respectively connected to the gate layers at different stacking heights in the sacrificial gap.

[0185] Specifically, after the initial contact structure 500' is formed, a gate line gap 410 that passes through the stacked structure 200' along the z direction and extends in the x direction may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. As an option, the gate line gap 410 may pass through the stacked structure 200' along the z direction and extend into the initial substrate 100. The gate line gap 410 may serve as a passage for providing an etchant, and a wet etching or equivalent etching process may be used to remove a portion of the second dielectric layer 220 in the stacked structure 200', thereby forming a gate layer 230.

[0186] In addition, in the process of removing part of the second dielectric layer 220 through the gate line gap 410 , part of the first sacrificial layer 531 ′ and part of the second sacrificial layer 532 ′ of the initial contact structure 500 ′ can be removed by the same process to form the connection layer 530 .

[0187] It can be understood by those skilled in the art that the above steps and related drawings only show the initial contact structure 500' including the first sacrificial layer 531' and the second sacrificial layer 532', but the number of the initial contact structures 500' and the number of the multiple sacrificial layers included in the initial contact structure 500' are only shown for the convenience of illustration. In fact, the number of the multiple sacrificial layers included in the initial contact structure 500' can be greater than or equal to 2, and in the process of removing part of the second dielectric layer 220 in the stacked structure 200', a part of each sacrificial layer in all the sacrificial layers included in the initial contact structure 500' can be removed, so as to form the connection layer 530.

[0188] By forming the gate layer 230 and the connection layer 530 in the same process, the process of manufacturing the semiconductor device can be simplified and the production cost can be saved.

[0189] Specifically, refer to Fig.14 and Fig.33AThe stacked structure 200 provided in the embodiment of the present application includes a storage area 02 and a contact area 01, wherein the storage area 02 may include a channel structure 300, and the contact area 01 may include a contact structure 500. Therefore, the intermediate 1001 used to form the stacked structure 200 also includes the storage area 02 and the contact area 01 correspondingly.

[0190] In one embodiment of the present application, the gate line gap 410 may include at least one of a first gate line gap 411, a second gate line gap 412, a third gate line gap (not shown); and a fourth gate line gap (not shown). The first gate line gap 411 extends continuously through the storage area 02 and the contact area 01 along the x direction; the second gate line gap 412 extends intermittently through the storage area 02 and the contact area 01 along the x direction; the third gate line gap extends in the storage area 02 along the x direction; and the fourth gate line gap extends in the contact area 01 along the x direction.

[0191] Fig.34A It is a schematic top view of a structure formed after a gate line gap 410 is formed according to a preparation method of an embodiment of the present application. Fig.34B yes Fig.34A The intermediate body 1001 is shown as a schematic cross-sectional view taken along the line MM′.

[0192] like FIG. 33A to FIG. 34B As shown, forming a sacrificial gap for accommodating the gate layer 230 and the connecting layer 530 may include: forming a gate line gap 410 that penetrates the stacked structure 200' along the z direction, wherein the gate line gap 410 includes a first gap 410-1 located in the storage area 02 and a second gap 410-2 located in the contact area 01; filling the first gap 410-1, and removing a portion of the second dielectric layer 220, a portion of the first sacrificial layer 531' and a portion of the second sacrificial layer 532' based on the second gap 410-2 to form a first gap (not shown); exposing the first gap, and filling the second gap 410-2 and the first gap; and based on the exposed first gap 410-1, continuing to remove a portion of the second dielectric layer 220 located in the memory 02 to form a second gap (not shown), wherein the first gap and the second gap that are connected to each other are formed as a sacrificial gap. The gate line gaps 410 can be used to remove part of the second dielectric layer 220 in the stacked structure 200 ′ in batches in the above steps, for example, the entire second dielectric layer 220 in the memory 02 and a part of the second dielectric layer 220 in the contact area 01 .

[0193] After removing part of the second dielectric layer to form the gate layer, the contact area may include an insulating dielectric material stacking layer formed by the first dielectric layer and the retained second dielectric layer stacked on each other. By setting the contact structure in the insulating dielectric material stacking layer, the contact structure can be electrically connected to the corresponding gate layer, and short circuits between different gate layers can be prevented. Therefore, in order to achieve the above effect, the semiconductor device manufacturing method provided in the embodiment of the present application only removes part of the second dielectric layer, and the shape and size of the gate layer finally formed can be controlled by removing part of the second dielectric layer in batches.

[0194] As an option, in one embodiment of the present application, in the process of removing part of the second dielectric layer by a process such as wet etching, the process parameters such as the type of etchant in the gate line gap, the concentration of the etchant, the etching time and the etching speed can be adjusted, so that in the process of etching part of the second dielectric layer, both the part of the second dielectric layer located in the storage area and the part of the second dielectric layer located in the contact area and adjacent to the gate line gap can be fully etched without insufficient etching; and it can be ensured that the etching process can accurately retain part of the second dielectric layer in the contact area of ​​the stacked structure to improve over-etching.

[0195] As another option, in one embodiment of the present application, some of the plurality of gate line gaps 410 may define a first gap 410-1 and a second gap 410-2 in the x direction, wherein the first gap 410-1 may be located in the storage area 02, and the second gap 410-2 may be located in the contact area 01. In addition, some of the plurality of gate line gaps 410 may also include only the first gap 410-1 located in the storage area 02; or only the second gap 410-2 located in the contact area 01.

[0196] A first filling sacrificial layer (not shown) can be used to fill the first gap 410-1 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and a portion of the second dielectric layer 220, a portion of the first sacrificial layer 531' and a portion of the second sacrificial layer 532' are removed based on the unfilled second gap 410-2, for example, a portion of the second dielectric layer 220 is located in the contact area 01 and adjacent to the gate line gap 410; a portion of the first sacrificial layer 531' is adjacent to the gate line gap 410; and a portion of the second sacrificial layer 532' is adjacent to the gate line gap 410.

[0197] Optionally, the first filling sacrificial layer may be a polysilicon layer. The material of the first filling sacrificial layer is different from that of the second dielectric layer 220, so that the first filling sacrificial layer and the second dielectric layer 220 can have different etching rates for the same etchant, which is convenient for removing part of the second dielectric layer 220 by an etching process in the subsequent process. In addition, since the first filling sacrificial layer needs to be removed in the subsequent steps, a carbon layer, a polysilicon layer, etc. may be used as the first filling sacrificial layer, so as to prevent damage to the stacked structure 200' in the subsequent process step of removing the first filling sacrificial layer, and reduce the cost of manufacturing the semiconductor device.

[0198] Optionally, the first filling sacrificial layer may be used to fill the entire gate line gap 410 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Thereafter, a portion of the first filling sacrificial layer located in the second gap 410-2 is removed by, for example, a dry etching process or a combination of dry and wet etching processes to expose the second gap 410-2, and the remaining first filling sacrificial layer is located only in the first gap 410-1.

[0199] By filling the remaining first filling sacrificial layer in the first gap 410-1, the second gap 410-2 can be exposed. The exposed second gap 410-2 can be used as a path for providing an etchant. By adopting a wet etching equivalent etching process, for example, a part of the second dielectric layer 220 located in the contact area 01 and a part of the first sacrificial layer 531' and a part of the second sacrificial layer 532' can be removed to form a first gap. In this process, by adjusting the process parameters such as the type of etchant, the concentration of the etchant, the etching time and the etching speed in the second gap 410-2, in the process of etching part of the second dielectric layer 220, the part of the second dielectric layer 220 located in the contact area 01 and adjacent to the gate line gap 410 can be fully etched without insufficient etching; and it can be ensured that the etching process can accurately retain the part of the second dielectric layer 220 of the stacked structure 200' in the contact area 01 to improve over-etching.

[0200] In addition, after forming the first void, a dry etching process or a combination of dry and wet etching processes may be used, or other manufacturing processes may be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove the first filling sacrificial layer in the first gap 410-1, and through the exposed first gap 410-1, a wet etching or equivalent etching process may be used to remove the portion of the second dielectric layer 220 located in the storage area 02 to form a second void. This step may also include filling the formed first void with a second filling sacrificial layer (not shown). Optionally, a carbon layer may be used as the second filling sacrificial layer to fill the first void.

[0201] In some embodiments of the present application, after the second gap is formed, the connected first gap and second gap are formed as a sacrificial gap. The gate layer 230 (e.g., Figure 1-Figure 6 ) and a connecting layer 530 (as shown Figure 1-Figure 6 The gate layer 230 may include a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon or silicide. The connection layer 530 is made of the same material as the gate layer 230.

[0202] In addition, in some embodiments of the present application, after forming the gate layer 230 and the connection layer 530, a gate line isolation structure 400 (eg, Figure 1-Figure 6 As shown). Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to sequentially fill the gate line gap 410 with a sidewall isolation layer and a dielectric filling layer to form a gate line isolation structure 400. The dielectric filling layer may be made of insulating dielectric materials such as silicon oxide, silicon nitride and silicon oxynitride, or may be made of semiconductor materials such as polysilicon, which is not limited in the present application. After the gate line isolation structure 400 and the gate layer 230 are formed in the stacked structure 200', the stacked structure 200' is formed into a stacked structure 200 (as shown in FIG. Figure 1-Figure 6 shown).

[0203] Fig.35 is a flow chart of a method 3000 for preparing a semiconductor device according to one embodiment of the present application. Fig.36A It is a schematic top view of a structure formed after an initial first opening 515 is formed according to a preparation method of an embodiment of the present application. Fig.36B It is a schematic cross-sectional view of a structure formed after an initial first opening 515 is formed according to a preparation method of an embodiment of the present application.

[0204] like Fig.35 As shown, the method 3000 for preparing a semiconductor device may include:

[0205] S21 , forming a stack structure including a plurality of stack layers, wherein each stack layer includes a first dielectric layer and a second dielectric layer.

[0206] S22, forming a first opening in the stacking structure, and forming a first sacrificial layer in the first opening which is respectively connected to the second dielectric layers at different stacking heights, wherein the first opening is divided into a first branch opening and a second branch opening in a second direction perpendicular to the stacking direction, and the first branch opening and the second branch opening respectively extend along the stacking direction to the second dielectric layers at different stacking heights.

[0207] S23, expanding the first opening along the stacking direction to form a second opening, and forming a second sacrificial layer in the second opening that is respectively connected to different next second dielectric layers, wherein the second opening is divided into a third branch opening and a fourth branch opening in the second direction, and the third branch opening and the fourth branch opening respectively extend to different next second dielectric layers along the stacking direction.

[0208] S24, removing a portion of the first sacrificial layer, a portion of the second sacrificial layer and a portion of the second dielectric layer to form a sacrificial gap, and forming a gate layer and a plurality of connection layers respectively connected to the gate layers at different stacking heights in the sacrificial gap.

[0209] Combination Figure 7-Figure 12 as well as Figure 35-36B According to the semiconductor device manufacturing method 3000, the semiconductor device 1000 is finally formed, and its contact structure 500 includes four connection layers 530, such as a first connection layer 531, a second connection layer 532, a third connection layer 533 and a fourth connection layer 534, wherein the first connection layer 531 is connected to the first gate layer 231; the second connection layer 532 is connected to the second gate layer 232; the third connection layer 533 is connected to the third gate layer 233; the fourth connection layer 534 is connected to the fourth gate layer 234, wherein the first gate layer 231, the second gate layer 232, the third gate layer 233 and the fourth gate layer 234 are all located at different stacking heights.

[0210] Since the contents involved in the manufacturing method described in the semiconductor device manufacturing method 2000 above can be fully or partially applied to the semiconductor device manufacturing method described here, the contents related or similar thereto are not repeated. However, it can be understood by those skilled in the art that the semiconductor device 1000 (such as the semiconductor device 1000) can be formed according to the semiconductor device manufacturing method 2000. Figure 1-Figure 6 ), the semiconductor device 1000 (as shown) can also be formed according to the method 3000 for preparing the semiconductor device Figure 7-Figure 12 Based on this, the methods 2000 and 3000 for preparing the semiconductor device have the same beneficial effects as the semiconductor structure 1000, which will not be described in detail herein.

[0211] Refer to Figure 19. Fig.36A and Fig.36BIn one embodiment of the present application, forming a stacking structure including a plurality of stacking layers in step 21, wherein each stacking layer includes a first dielectric layer and a second dielectric layer, may for example include: providing an initial substrate 100; and alternately stacking first dielectric layers 210 and second dielectric layers 220 on the initial substrate 100 to form a stacking structure 200', wherein adjacent first dielectric layers 210 and second dielectric layers 220 form a stacking layer. For example, adjacent first dielectric layers 211 and second dielectric layers 221 form a stacking layer; adjacent first dielectric layers 212 and second dielectric layers 222 form a stacking layer.

[0212] like Fig.36A and Fig.36B As shown, in one embodiment of the present application, in step S22, a first opening is formed in the stacking structure, and a first sacrificial layer connected to the second dielectric layers at different stacking heights is formed in the first opening, wherein the first opening is divided into a first branch opening and a second branch opening in a second direction perpendicular to the stacking direction, and the first branch opening and the second branch opening extend along the stacking direction to the second dielectric layers at different stacking heights, respectively, which may include, for example: removing a predetermined area of ​​the stacking structure 200' (such as Fig.36A and Fig.36B An initial first opening 515 is formed, wherein the initial first opening 515 is divided into a first initial branch opening 515-1 and a second initial branch opening 515-2 in the y direction, and the first initial branch opening 515-1 or the second initial branch opening 515-2 is located in a predetermined area; and a first opening (not shown) is formed through the initial first opening 515.

[0213] Optionally, combined Figure 7-Figure 12 as well as Figure 35-36B In one embodiment of the present application, the number of the plurality of connection layers 530 is the same as the number of the at least two stacked layers that are removed.

[0214] By dividing the initial first opening 515 into two branch openings with a step difference along the y direction, the subsequently formed sacrificial layer (as shown in FIG. 32 ) can be connected to the second dielectric layer 220 (as shown in FIG. 19 ) at different stacking heights.

[0215] For example, the first initial opening 515-1 and the second initial opening 515-2 extend along the z direction to different first dielectric layers (the first dielectric layer 211 and the first dielectric layer 212), respectively, wherein the first dielectric layer 211 is located above the second dielectric layer 221, the first dielectric layer 212 is located above the second dielectric layer 222, and the second dielectric layer 221 and the second dielectric layer 222 are located at different stacking heights, respectively.

[0216] After the initial first opening 515 is formed, a first opening may be formed through the initial first opening 515. Specifically, a first initial isolation layer (not shown) is formed to at least cover the initial first opening 515; a portion of the first initial isolation layer located at the bottom of the initial first opening 515 is removed to form a first sidewall isolation layer (not shown); and the initial first opening 515 is extended along the z direction to the second dielectric layer 220 at different stacking heights to form the first opening. The specific implementation process of the above steps can refer to step S12 of the method 2000 for preparing a semiconductor device.

[0217] After forming the first opening, a first sacrificial layer (not shown) connected to the second dielectric layer 220 at different stacking heights may be formed in the first opening. Specifically, forming the first sacrificial layer may include: forming an initial first sacrificial layer, the initial first sacrificial layer at least covering the first sidewall isolation layer, the side of the second dielectric layer at different stacking heights exposed in the first opening, and the bottom of the first opening; and removing the portion of the initial first sacrificial layer located at the bottom of the first opening to form the first sacrificial layer. The specific implementation process of the above steps may refer to step S12 of the method 2000 for preparing a semiconductor device.

[0218] Step S23 extends the first opening along the stacking direction to form a second opening, and forms a second sacrificial layer connected to different next second dielectric layers in the second opening, wherein the second opening is divided into a third branch opening and a fourth branch opening in the second direction, and the third branch opening and the fourth branch opening extend to different next second dielectric layers along the stacking direction respectively. It may, for example, include: extending the first opening along the stacking direction to form a second opening; and forming a second sacrificial layer connected to different next second dielectric layers in the second opening.

[0219] Specifically, in one embodiment of the present application, extending the first opening along the stacking direction to form the second opening may include: extending the first opening formed with the first sacrificial layer along the stacking direction to form an initial second opening, wherein the initial second opening is divided into a third initial sub-opening and a fourth initial sub-opening in the second direction, and the third initial sub-opening and the fourth initial sub-opening extend to different next first dielectric layers along the stacking direction, respectively, and different next first dielectric layers are respectively located above different next second dielectric layers; forming a second initial isolation layer that at least covers the initial second opening; removing a portion of the second initial isolation layer located at the bottom of the initial second opening to form a second sidewall isolation layer; and extending the initial second opening along the stacking direction to different next second dielectric layers to form the second opening. Optionally, different next second dielectric layers are respectively adjacent to the same first dielectric layer in the stacking direction with second dielectric layers at different stacking heights. The specific implementation process of the above steps can refer to step S13 of the method 2000 for preparing a semiconductor device.

[0220] After forming the second opening, a second sacrificial layer connected to different next second dielectric layers can be formed in the second opening. Specifically, an initial second sacrificial layer is formed, which at least covers the second sidewall isolation layer, the side of the different next second dielectric layer exposed in the second opening, and the bottom of the second opening; and a portion of the initial second sacrificial layer located at the bottom of the second opening is removed to form the second sacrificial layer. The specific implementation process of the above steps can refer to step S13 of the method 2000 for preparing a semiconductor device.

[0221] After forming the first sacrificial layer and the second sacrificial layer, step S24 removes part of the first sacrificial layer, part of the second sacrificial layer and part of the second dielectric layer to form a sacrificial gap, and forms a gate layer and a plurality of connection layers respectively connected to the gate layers at different stacking heights in the sacrificial gap, which may include, for example: forming a gate line gap penetrating the stacking structure along the stacking direction; and removing part of the first sacrificial layer, part of the second sacrificial layer and part of the second dielectric layer through the gate line gap to form a sacrificial gap, wherein at least one of the plurality of gate line gaps extends in the first direction and penetrates the third and fourth openings formed with the second sacrificial layer, wherein the stacking direction, the first direction and the second direction are perpendicular to each other. The specific implementation process of the above steps may refer to step S14 of the method 2000 for preparing a semiconductor device.

[0222] Fig.37 It is a schematic diagram of the structure of a storage system 30000 according to one embodiment of the present application.

[0223] like Fig.37 As shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any embodiment above, and the present application will not repeat it. The semiconductor device 20000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. The following will be described by taking a three-dimensional semiconductor device as an example.

[0224] As an option, the three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0225] The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and this application will not repeat them. The controller 32000 may control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 may perform operations based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access an area selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 may perform an internal operation corresponding to the command on the area selected by the address.

[0226] In some embodiments, the three-dimensional storage system can be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system provided in the present application has the same beneficial effects as the semiconductor device provided in the present application because the semiconductor device provided in the present application is provided, and no further description is given here.

[0227] Although an exemplary method and structure of manufacturing a semiconductor device are described herein, it is understood that one or more features may be omitted, replaced or added from the structure of the semiconductor device. In addition, the materials of each layer exemplified are merely exemplary.

[0228] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by the selected combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A semiconductor device, characterized in that: include: A stacked structure comprising alternately stacked gate layers and first dielectric layers; as well as a contact structure extending in the stacked structure along a stacking direction and comprising a plurality of connection layers connected to the plurality of gate layers, Among the multiple gate layers connected to the multiple connection layers, at least some of the gate layers are located at different stacking heights.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes a gate line isolation structure penetrating the stacked structure along the stacking direction. At least one of the plurality of gate line isolation structures extends in a first direction perpendicular to the stacking direction and penetrates the contact structure.

3. The semiconductor device according to claim 2, wherein: The contact structure includes a first portion and a second portion separated by the gate line isolation structure, Wherein, in the first part, the plurality of connection layers include, from the outside to the inside, a first connection layer and a second connection layer, In the second part, the plurality of connection layers include, from outside to inside, a third connection layer and a fourth connection layer, The first connection layer, the second connection layer, the third connection layer and the fourth connection layer respectively extend in the stacking structure along the stacking direction and are respectively connected to the gate layers at different stacking heights.

4. The semiconductor device according to claim 3, wherein: The gate layers respectively connected to the first connection layer and the second connection layer are both adjacent to the same first dielectric layer in the stacking direction; and / or The gate layers respectively connected to the third connection layer and the fourth connection layer are adjacent to the same first dielectric layer in the stacking direction.

5. The semiconductor device according to claim 2, wherein: The contact structure includes a first portion and a second portion separated by the gate line isolation structure, Wherein, in the first part, the plurality of connection layers include a first connection layer and a second connection layer from the outside to the inside, and in the second part, the plurality of connection layers include a third connection layer and a fourth connection layer from the outside to the inside; The first connection layer and the third connection layer extend in the stacking structure along the stacking direction and are connected to the first gate layer, the second connection layer and the fourth connection layer extend in the stacking structure along the stacking direction and are connected to the second gate layer, The first gate layer and the second gate layer have different stacking heights.

6. The semiconductor device according to claim 5, wherein: The first gate layer and the second gate layer are both adjacent to the same first dielectric layer in the stacking direction.

7. The semiconductor device according to claim 3 or 5, wherein: At least one of the first connection layer, the second connection layer, the third connection layer and the fourth connection layer comprises a conductive section and a spacer dielectric section, Wherein, in a plane perpendicular to the stacking direction, the conductive portion is adjacent to the gate line isolation structure.

8. The semiconductor device according to claim 2, wherein: The stacked structure comprises a storage area and a contact area distributed along the first direction, and the gate layer extends from the storage area to the contact area; and The plurality of gate line isolation structures include at least one of a first gate line isolation structure, a second gate line isolation structure, a third gate line isolation structure, and a fourth gate line isolation structure, Wherein, the first gate line isolation structure continuously extends through the storage area and the contact area along the first direction; The second gate line isolation structure extends intermittently along the first direction through the storage area and the contact area; The third gate line isolation structure extends in the storage area along the first direction; and The fourth gate line structure extends in the contact region along the first direction.

9. The semiconductor device according to claim 8, wherein: At least one of the first gate line isolation structure, the second gate line isolation structure, and the fourth gate line isolation structure penetrates the contact structure in the first direction.

10. The semiconductor device according to claim 2 or 8, wherein: The plurality of contact structures penetrated by different gate line isolation structures are aligned with each other or staggered with each other in a second direction, wherein the first direction, the second direction and the stacking direction are perpendicular to each other.

11. The semiconductor device according to claim 8, wherein The contact area includes a second dielectric layer alternately stacked with the first dielectric layer in the stacking direction, The second dielectric layer is connected to the gate layer in a second direction, and the first direction, the second direction and the stacking direction are perpendicular to each other.

12. The semiconductor device according to claim 8, wherein The storage area corresponds to at least one contact area, and at least one contact area is located in the middle or periphery of the storage area.

13. A method for preparing a semiconductor device, characterized in that: include: Alternatingly stacking the first dielectric layer and the second dielectric layer to form a stacked structure; forming a first opening in the stack structure, wherein the first opening extends along the stack direction to the second dielectric layer at the first stack height, and forming a first sacrificial layer connected to the second dielectric layer at the first stack height in the first opening; Extending the first opening along the stacking direction to the second dielectric layer at a second stacking height to form a second opening, and forming a second sacrificial layer in the second opening connected to the second dielectric layer at the second stacking height; as well as A portion of the first sacrificial layer, a portion of the second sacrificial layer and a portion of the second dielectric layer are removed to form a sacrificial gap, and a gate layer and a plurality of connection layers respectively connected to the gate layers at different stacking heights are formed in the sacrificial gap.

14. The method according to claim 13, wherein: The second dielectric layer at the second stack height and the second dielectric layer at the first stack height are both adjacent to the same first dielectric layer in the stacking direction.

15. The method according to claim 13, wherein: The method further comprises: forming a gate line gap penetrating the stack structure along the stacking direction; and removing part of the first sacrificial layer, part of the second sacrificial layer and part of the second dielectric layer through the gate line gap to form the sacrificial gap, At least one of the plurality of gate line gaps extends in a first direction perpendicular to the stacking direction and penetrates the second opening formed with the second sacrificial layer.

16. The method according to claim 13, wherein: Forming a first opening in the stack structure includes: forming an initial first opening in the stack structure, wherein the initial first opening extends along the stacking direction to the first dielectric layer on the second dielectric layer at the first stacking height; forming a first initial isolation layer at least covering the initial first opening; removing a portion of the first initial isolation layer located at a bottom of the initial first opening to form a first sidewall isolation layer; and The initial first opening is extended along the stacking direction to the second dielectric layer at the first stacking height to form the first opening.

17. The method according to claim 16, wherein: Forming a first sacrificial layer in the first opening connected to the second dielectric layer at the first stack height includes: forming an initial first sacrificial layer, the initial first sacrificial layer at least covering the first sidewall spacer, the side surface of the second dielectric layer at the first stack height exposed in the first opening, and the bottom of the first opening; and A portion of the initial first sacrificial layer located at a bottom of the first opening is removed to form the first sacrificial layer.

18. The method according to claim 17, wherein: Extending the first opening along the stacking direction to form a second opening comprises: Extending the first opening formed with the first sacrificial layer to the next first dielectric layer along the stacking direction to form an initial second opening, wherein the next first dielectric layer is located above the second dielectric layer at the second stacking height; forming a second initial isolation layer at least covering the initial second opening; removing a portion of the second initial isolation layer located at a bottom of the initial second opening to form a second sidewall isolation layer; and The initial second opening is extended along the stacking direction to the second dielectric layer at the second stacking height to form the second opening.

19. The method according to claim 18, wherein: Forming a second sacrificial layer in the second opening connected to the second dielectric layer at the second stack height includes: forming an initial second sacrificial layer, the initial second sacrificial layer at least covering the second sidewall spacer, the side of the second dielectric layer at the second stack height exposed in the second opening, and the bottom of the second opening; and A portion of the initial second sacrificial layer located at a bottom of the second opening is removed to form the second sacrificial layer.

20. The method according to claim 13 or 19, wherein: After forming the second sacrificial layer, the method further includes: A contact hole dielectric filling layer is formed to fill at least a remaining space of the second opening.

21. A method for preparing a semiconductor device, characterized in that: include: forming a stacked structure comprising a plurality of stacked layers, wherein each of the stacked layers comprises a first dielectric layer and a second dielectric layer; A first opening is formed in the stacking structure, and a first sacrificial layer connected to the second dielectric layers at different stacking heights is formed in the first opening, wherein the first opening is divided into a first branch opening and a second branch opening in a second direction perpendicular to the stacking direction, and the first branch opening and the second branch opening extend to the second dielectric layers at different stacking heights along the stacking direction respectively; Extending the first opening along the stacking direction to form a second opening, and forming a second sacrificial layer connected to the different next second dielectric layers in the second opening, wherein the second opening is divided into a third branch opening and a fourth branch opening in the second direction, and the third branch opening and the fourth branch opening extend to different next second dielectric layers along the stacking direction respectively; as well as A portion of the first sacrificial layer, a portion of the second sacrificial layer and a portion of the second dielectric layer are removed to form a sacrificial gap, and a gate layer and a plurality of connection layers respectively connected to the gate layers at different stacking heights are formed in the sacrificial gap.

22. The method according to claim 21, wherein: The different next second dielectric layers and the second dielectric layers at different stacking heights are respectively adjacent to the same first dielectric layer in the stacking direction.

23. The method according to claim 21, wherein: The method further comprises: forming a gate line gap penetrating the stack structure along the stacking direction; and removing part of the first sacrificial layer, part of the second sacrificial layer and part of the second dielectric layer through the gate line gap to form the sacrificial gap, At least one of the plurality of gate line gaps extends in a first direction and penetrates the third opening and the fourth opening where the second sacrificial layer is formed, wherein the stacking direction, the first direction and the second direction are perpendicular to each other.

24. The method according to claim 21, wherein: Forming a first opening in the stack structure includes: removing a portion of at least two uppermost stacking layers in a predetermined area of ​​the stacking structure; forming an initial first opening, wherein the initial first opening is divided into a first initial sub-opening and a second initial sub-opening in the second direction, and the first initial sub-opening or the second initial sub-opening is located in the predetermined area; and The first opening is formed via the initial first opening.

25. The method according to claim 24, wherein: The number of the plurality of connection layers is the same as the number of the at least two stacked layers that are removed.

26. The method according to claim 24, wherein: The first initial branch opening and the second initial branch opening extend to different first dielectric layers along the stacking direction respectively, and the different first dielectric layers are respectively located above the second dielectric layers at different stacking heights.

27. The method according to claim 24, wherein: Forming the first opening via the initial first opening comprises: forming a first initial isolation layer at least covering the initial first opening; removing a portion of the first initial isolation layer located at a bottom of the initial first opening to form a first sidewall isolation layer; and The initial first opening is extended along the stacking direction to the second dielectric layer at the different stacking heights to form the first opening.

28. The method according to claim 27, wherein: Forming a first sacrificial layer in the first opening that is respectively connected to the second dielectric layers at different stack heights comprises: forming an initial first sacrificial layer, the initial first sacrificial layer at least covering the first sidewall isolation layer, the side surface of the second dielectric layer at different stacking heights exposed in the first opening, and the bottom of the first opening; and A portion of the initial first sacrificial layer located at a bottom of the first opening is removed to form the first sacrificial layer.

29. The method according to claim 28, wherein: Extending the first opening along the stacking direction to form the second opening comprises: The first opening having the first sacrificial layer formed thereon is extended along the stacking direction to form an initial second opening, wherein the initial second opening is divided into a third initial branch opening and a fourth initial branch opening in the second direction, the third initial branch opening and the fourth initial branch opening respectively extend to different next first dielectric layers along the stacking direction, and the different next first dielectric layers are respectively located above the different next second dielectric layers; forming a second initial isolation layer at least covering the initial second opening; removing a portion of the second initial isolation layer located at a bottom of the initial second opening to form a second sidewall isolation layer; and The initial second opening is extended along the stacking direction to the different next second dielectric layer to form the second opening.

30. The method of claim 29, wherein: Forming a second sacrificial layer in the second opening that is respectively connected to the different next second dielectric layer comprises: forming an initial second sacrificial layer, the initial second sacrificial layer at least covering the second sidewall spacer, the side of the different next second dielectric layer exposed in the second opening, and the bottom of the second opening; and A portion of the initial second sacrificial layer located at a bottom of the second opening is removed to form the second sacrificial layer.

31. A storage system, characterized in that: include: Controller; as well as The semiconductor device according to any one of claims 1 to 12, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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