Semiconductor structure, preparation method thereof and storage system

Abstract

The invention provides a semiconductor structure, a preparation method thereof and a storage system, relates to the technical field of semiconductor chips, and aims to improve the storage density of the semiconductor structure. The semiconductor structure includes a stack structure and a memory pillar. The stacked structure includes gate insulating layers and gate layers alternately stacked in a first direction. The storage columns penetrate through the stacking structure in the first direction; the storage column comprises a first channel structure, a second channel structure and an isolation part; the first channel structure and the second channel structure are oppositely arranged along a second direction, and the second direction is perpendicular to the first direction; the isolation part is located between the first channel structure and the second channel structure, and the isolation part isolates the first channel structure from the second channel structure. The semiconductor structure is divided into the first channel structures and the second channel structures through the isolation part, so that the total number of the first channel structures and the second channel structures in the embodiment is large, and the storage density of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, and a storage system. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate. However, three-dimensional memory still has the problem of increasing storage density. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and a storage system, which are intended to improve the storage density of the semiconductor structure.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor structure is provided. The semiconductor structure includes a stacked structure and a storage column. The stacked structure includes a gate insulating layer and a gate layer alternately stacked along a first direction. The storage column penetrates the stacked structure along the first direction; the storage column includes a first channel structure, a second channel structure and an isolation portion; the first channel structure and the second channel structure are arranged opposite to each other along a second direction, and the second direction is perpendicular to the first direction; the isolation portion is located between the first channel structure and the second channel structure, and the isolation portion isolates the first channel structure from the second channel structure.

[0007] The isolation part is used to separate the first channel structure and the second channel structure, so that the total number of the first channel structure and the second channel structure in this embodiment is large, thereby improving the storage density of the semiconductor structure. In each storage column, the isolation part is arranged to separate the first channel structure from the second channel structure, thereby improving the mutual interference between the first channel structure and the second channel structure (for example, improving the problem of short circuit between the first channel structure and the second channel structure).

[0008] In some embodiments, the first channel structure and the second channel structure both include a channel layer. The isolation portion includes two first isolation portions and one second isolation portion; the two first isolation portions are arranged opposite to each other along a third direction, the third direction is perpendicular to the first direction, and the third direction intersects with the second direction; the second isolation portion is located between the two first isolation portions and the channel layer of the first channel structure and the channel layer of the second channel structure.

[0009] In some embodiments, the material of the first isolation portion is the same as the material of the second isolation portion.

[0010] In some embodiments, the channel layer of the first channel structure and the channel layer of the second channel structure include first end surfaces opposite to each other along the second direction, and the first isolation portion covers the first end surfaces.

[0011] In some embodiments, the first channel structure and the second channel structure both further include a storage function layer; the storage function layer is located between the channel layer and the stacked structure. The storage function layer of the first channel structure and the storage function layer of the second channel structure include second end faces opposite to each other along the second direction, and the first isolation portion also covers the second end faces.

[0012] In some embodiments, the storage function layer includes: a tunneling layer away from the channel layer, a storage layer and a barrier layer. The first isolation portion also covers the tunneling layer and the storage layer.

[0013] In some embodiments, a dimension of the first isolation portion along the second direction is greater than or equal to one quarter of a dimension of the storage pillar along the second direction, and less than or equal to one half of a dimension of the storage pillar along the second direction.

[0014] In some embodiments, a dimension of the first isolation portion along the second direction is equal to one third of a dimension of the storage pillar along the second direction.

[0015] In some embodiments, a surface perpendicular to the first direction is defined as a reference surface. The orthographic projections of the first channel structure and the second channel structure on the reference surface are both arc-shaped projections, and the opening directions of the two arc-shaped projections are opposite along the second direction.

[0016] In some embodiments, the first channel structure and the second channel structure are symmetrically arranged along the second direction.

[0017] In some embodiments, the number of storage pillars is multiple, and the multiple storage pillars are arranged in sequence along a third direction, the third direction is perpendicular to the first direction, and the third direction intersects the second direction. The semiconductor structure also includes a separator. The separator includes a plurality of sub-separators arranged in sequence along the third direction, the sub-separators penetrate the stacked structure along the first direction, and connect the isolation parts in two adjacent storage pillars along the third direction.

[0018] In some embodiments, the material of the partition portion is the same as the material of the isolation portion.

[0019] On the other hand, a method for preparing a semiconductor structure is provided. The preparation method includes: forming a stacked structure, the stacked structure including a gate insulating layer and a gate layer alternately stacked along a first direction; forming a storage column, the storage column penetrating the stacked structure along the first direction; the storage column includes a first channel structure, a second channel structure and an isolation part; the first channel structure and the second channel structure are arranged opposite to each other along the second direction, and the second direction is perpendicular to the first direction; the isolation part is located between the first channel structure and the second channel structure, and the isolation part isolates the first channel structure from the second channel structure.

[0020] In some embodiments, forming a stacked structure and forming a storage column include: forming a stacked structure on a substrate; the stacked structure includes a first film layer and a second film layer alternately stacked along a first direction. Forming a channel hole, the channel hole penetrates the stacked structure along the first direction. Forming a storage function film and a channel film on the inner wall of the channel hole in sequence, and filling the first material in the inner side of the channel film. Forming a separation groove, the separation groove penetrates the stacked structure along the first direction, and the separation groove extends along a third direction, the third direction is perpendicular to the first direction, and the third direction intersects with the second direction; the separation groove opens part of the storage function film, and exposes two target parts in the channel film that are opposite to each other along the third direction. Processing the target part through the separation groove to obtain a first isolation part, the first isolation part is a part of the isolation part.

[0021] In some embodiments, processing the target portion through the separation trench includes: performing an oxidation process on the target portion.

[0022] In some embodiments, the step of forming the separation groove includes: arranging a mask plate on a side of the stacked structure away from the substrate; the mask plate has a plurality of hollow areas; the hollow areas extend along the third direction, and the plurality of hollow areas are arranged along the second direction. Each hollow area is used to remove the stacked structure and a portion of the storage functional film to form the separation groove.

[0023] In some embodiments, the step of using each hollow area to remove the stacked structure and part of the storage functional film to form a separation groove includes: using an etching liquid in a wet etching process to pass through each hollow area to etch the stacked structure and part of the storage functional film to form a separation groove. The etching rate of the etching liquid on the storage functional film and the stacked structure is greater than the etching rate of the etching liquid on the channel film and the first material.

[0024] In some embodiments, forming the stacked structure and forming the storage pillar further includes: removing the first material; the first material includes a compound or organic matter or metal of carbon atoms, silicon atoms and oxygen atoms. Filling a third material between the two first isolation parts and the channel layer of the first channel structure and the channel layer of the second channel structure to form a second isolation part; the third material includes an oxide.

[0025] In some embodiments, the first film layer is a gate insulating layer, and the second film layer is a gate sacrificial layer, forming a stacked structure and forming a storage column, and also includes: after processing the target portion, replacing the gate sacrificial layer with the gate layer through the separation groove to obtain a stacked structure.

[0026] In some embodiments, after processing the target portion, replacing the gate sacrificial layer with the gate layer via the separation groove includes: removing the gate sacrificial layer via the separation groove, filling the separation groove with gate material to form the gate layer to obtain a stacked structure, and removing the gate material in the separation groove to separate the multiple gate layers.

[0027] In some embodiments, forming the stacked structure and forming the storage pillars further includes: filling a second material in the separation grooves to form separation parts.

[0028] In another aspect, a storage system is provided, which includes: the semiconductor structure and a controller coupled to the semiconductor structure.

[0029] On the other hand, an electronic device is provided, comprising the above storage system.

[0030] It can be understood that the beneficial effects that can be achieved by the semiconductor structure preparation method, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0032] Figure 1 is a schematic diagram of the structure of a storage system according to some embodiments;

[0033] Figure 2 is a schematic diagram of the structure of a storage system according to some other embodiments;

[0034] Figure 3 is a schematic diagram of the structure of a three-dimensional memory according to some embodiments;

[0035] Figure 4 is a top view of a semiconductor structure according to some embodiments;

[0036] Figure 5 for Figure 4Diagram along line AA;

[0037] Figure 6 for Figure 4 A partial enlarged view of the middle Ⅰ area;

[0038] Figure 7 is a structural diagram of a memory cell string according to some embodiments;

[0039] Figure 8 for Figure 7 Equivalent circuit diagram of the storage cell string in FIG.

[0040] Fig. 9 is a structural diagram of a storage unit string provided according to some other embodiments;

[0041] Fig.10 for Fig. 9 Equivalent circuit diagram of the storage cell string in FIG.

[0042] Fig.11 is a schematic diagram of the structure of another three-dimensional memory according to some embodiments;

[0043] Fig.12 is a flow chart of a method for preparing a semiconductor structure according to some embodiments;

[0044] Fig.13 is a flow chart of another method for preparing a semiconductor structure according to some embodiments;

[0045] Figure 14 to Figure 23 is a process diagram of a method for preparing a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0047] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0051] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0055] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0056] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0057] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0058] Figure 1 is a schematic diagram of the structure of a storage system according to some embodiments. Figure 2 is a schematic diagram of the structure of a storage system according to some other embodiments.

[0059] See also Figure 1 and Figure 2, some embodiments of the present disclosure provide a storage system 1000. The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic products, for example, mobile phones (such as mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0060] The storage system 1000 includes a controller 20 and a three-dimensional memory 10, wherein the controller 20 is coupled to the three-dimensional memory 10. The controller 20 is used to control the three-dimensional memory 10 to store data.

[0061] For example, see Figure 1 The storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card. The memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

[0062] Also illustratively, see Figure 2 The storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0063] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smart phones, tablets, and laptops, as well as enterprise storage arrays.

[0064] Exemplarily, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). Exemplarily, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. Exemplarily, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. Exemplarily, the controller 20 may also be configured to process error correction codes regarding data read from or written to the three-dimensional memory 10.

[0065] Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0066] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0067] Figure 3 FIG. 1 is a schematic diagram of the structure of a three-dimensional memory 10 according to some embodiments.

[0068] See also Figure 3 The three-dimensional memory 10 may include a semiconductor structure 110 and a source layer SL. The source layer SL is coupled to the semiconductor structure 110 .

[0069] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0070] Figure 4 is a top view of a semiconductor structure 110 according to some embodiments. Figure 5 for Figure 4 Diagram along line AA. Figure 6 for Figure 4 A partial enlarged view of area I.

[0071] See also Figures 4 to 6 The semiconductor structure 110 may include a stacked structure 111. The stacked structure 111 includes gate insulating layers 1112 and gate layers 1111 alternately stacked along a first direction X.

[0072] The first direction X is the direction in which the plurality of gate insulating layers 1112 and the plurality of gate layers 1111 are alternately stacked. That is, the first direction X is as follows: Figure 5 The third direction Z is perpendicular to the first direction X, and the third direction Z intersects (e.g., is perpendicular to) the second direction Y. The third direction Z is perpendicular to the second direction Y; therefore, the first direction X, the second direction Y, and the third direction Z can form a three-dimensional coordinate system.

[0073] It should be noted that, in this document, the first direction X in all the drawings can be understood as: Figure 4 The arrow direction of the first direction X shown may also be as follows Figure 4 The third direction Z and the second direction Y in all the drawings can be understood with reference to the first direction X.

[0074] The stacked structure 111 includes a plurality of gate layers 1111 stacked together, and a gate insulating layer 1112 is disposed between each two adjacent gate layers 1111. In addition, a gate insulating layer 1112 may be disposed above a gate layer 1111 located at the top. A gate insulating layer 1112 may also be disposed below a gate layer 1111 located at the bottom. Each gate layer 1111 may include a plurality of gate lines.

[0075] The material of the gate insulating layer 1112 is an insulating material, and the insulating material may be, for example, a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials. The gate layer 1111 may include a conductive material, including but not limited to any combination of one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicide. In some embodiments, each gate layer 1111 may be a metal layer, such as a tungsten layer. In some other embodiments, each gate layer 1111 may be a doped polysilicon layer.

[0076] In some examples, the semiconductor structure 110 may further include a substrate 115, which refers to a material layer on which subsequent layers may be added. The subsequent layers added to the substrate 115 may be patterned or may remain unpatterned. For example, the stacked structure 111 may be disposed on the substrate 115, which itself may be patterned.

[0077] In some examples, the substrate 115 may be partially or fully doped; in this case, the substrate 115 may serve as a source layer SL; accordingly, the substrate 115 may include at least one of a variety of semiconductor materials such as amorphous silicon, polycrystalline silicon, single crystal silicon, single crystal germanium, III-V group compound semiconductor materials, II-VI group compound semiconductor materials, etc.; for example, it may include at least one of a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc.

[0078] like Figure 5 As shown, in the embodiment of the present disclosure, the substrate 115 is located between the stacking structure 111 and the source layer SL, and the stacking structure 111, the substrate 115 and the source layer SL are sequentially stacked along the first direction X. Accordingly, the substrate 115 can be made of a non-conductive material such as glass, plastic or sapphire wafer.

[0079] Please continue to see Figures 4 to 6 The semiconductor structure 110 in the embodiment of the present disclosure may include a plurality of channel holes CH (Channel Hole), and the channel holes CH penetrate the stack structure 111 along the first direction X. Storage pillars 112 may be disposed in at least some of the channel holes CH, and the storage pillars 112 penetrate the stack structure 111 along the first direction X.

[0080] The storage column 112 includes a first channel structure 1121, a second channel structure 1122 and an isolation portion 1123. The first channel structure 1121 and the second channel structure 1122 are arranged opposite to each other along a second direction Y, and the isolation portion 1123 is located between the first channel structure 1121 and the second channel structure 1122 arranged opposite to each other. At this time, the second direction Y can be understood as a straight line passing through the isolation portion 1123.

[0081] like Figure 6 As shown, the first channel structure 1121 and the second channel structure 1122 each include a channel layer GC and a storage function layer CGC. The storage function layer CGC is located between the channel layer GC and the stacked structure 111. The material of the channel layer GC may include a semiconductor material, and the semiconductor material may be, for example, a combination of one or more of amorphous silicon, polycrystalline silicon or single crystal silicon. The channel layer GC may be electrically connected to the source layer SL.

[0082] Among them, the storage function layer CGC may include a tunneling layer SC, a storage layer CC and a blocking layer ZC away from the channel layer GC. The material of the tunneling layer SC may include an insulating material, and the insulating material may be, for example, a combination of one or more of silicon oxide, silicon nitride or silicon oxynitride. Electrons and holes in the channel layer GC may tunnel into the storage layer CC through the tunneling layer SC. The storage layer CC may be configured to store charges, and one or more storage cells in the storage cell string may be operated by storing charges in the storage layer CC or removing charges from the storage function layer CGC. The material of the storage layer CC may include a combination of one or more of silicon nitride, silicon oxynitride, and silicon. The blocking layer ZC may be configured to prevent the charges stored in the storage layer CC from leaking to the gate layer 1111. The material of the blocking layer ZC may include an insulating material, for example, the material of the blocking layer ZC may be a combination of one or more of silicon oxide, silicon nitride or silicon oxynitride.

[0083] In some examples, the first channel structure 1121 and the second channel structure 1122 both extend into the substrate 115, thereby electrically connecting the first channel structure 1121 and the second channel structure 1122 to the source layer SL. Figure 5 As shown, the bottom of the first channel structure 1121 and the second channel structure 1122 may be flush with the lower surface of the substrate 115 (the surface away from the stacked structure 111). For another example, the bottom of the first channel structure 1121 and the second channel structure 1122 do not penetrate the lower surface of the substrate 115, or in other words, a portion of the substrate 115 is located below the first channel structure 1121 and the second channel structure 1122.

[0084] Please continue to refer to Figures 4 to 6 The isolation part 1123 is made of insulating material, which can be silicon oxide, silicon nitride or silicon oxynitride. The isolation part 1123 is used to isolate the channel layer GC and the storage function layer CGC in the first channel structure 1121 and the second channel structure 1122, and to improve the mutual interference between the first channel structure 1121 and the second channel structure 1122 (for example, to improve the problem of short circuit between the first channel structure 1121 and the second channel structure 1122).

[0085] In some examples, the semiconductor structure 110 may also include a separator 114, which includes a sub-separator 1141 that is respectively in contact with both sides of the isolation portion 1123 in the third direction Z; that is, the isolation portion 1123 may be arranged between two sub-separators 1141 arranged at intervals along the third direction Z.

[0086] The sub-partition 1141 in the partition 114 extends along the third direction Z and penetrates the stacked structure 111 along the first direction X. The material of the partition 114 is an insulating material, which can be silicon oxide, silicon nitride or silicon oxynitride. The isolation portion 1123 and the partition 114 can be made of the same material or different materials.

[0087] The setting of the separation portion 114 is used to separate the stacking structure 111 into two parts corresponding to the first channel structure 1121 and the second channel structure 1122, wherein, in the stacking structure 111 where the separation portion 114 and the isolation portion 1123 are located on the same side as the first channel structure 1121, the gate layer 1111 can be constructed as a gate line coupled to the first channel structure 1121; in the stacking structure 111 where the separation portion 114 and the isolation portion 1123 are located on the same side as the second channel structure 1122, the gate layer 1111 can be constructed as a gate line coupled to the second channel structure 1122.

[0088] Figure 7 is a structural diagram of a memory cell string according to some embodiments, Figure 8 for Figure 7 The equivalent circuit diagram of the storage unit string in ; Figure 7 and Figure 8 As shown, in the semiconductor structure 110 provided in the embodiment of the present disclosure, each storage pillar 112 and a plurality of gate lines G (gate layer 1111) surrounding the storage pillar 112 can form two storage cell transistor strings 400 (referred to herein as "storage cell strings", such as NAND storage cell strings), namely, a first storage cell string 400a and a second storage cell string 400b. The source layer SL can be coupled to the source end of the storage cell string 400 (including the first storage cell string 400a and the second storage cell string 400b).

[0089] like Figure 7 and Figure 8 As shown, the first memory cell string 400a includes a plurality of transistors T formed by a first channel structure 1121 and a plurality of gate lines G, a transistor T (eg Figure 8The transistors T1 to T6 in the first memory cell string 400a can be set as a memory cell, and these transistors T are connected together to form a first memory cell string 400a. A transistor T (for example, each transistor T) can be formed by a first channel structure 1121 and a gate line G surrounding the first channel structure 1121. The gate line G is configured to control the conduction state of the transistor.

[0090] It should be noted that Figures 7 and 8 The number of transistors in the first memory cell string 400a is only illustrative. The first memory cell string 400a of the three-dimensional memory provided by the embodiment of the present disclosure may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0091] In some embodiments, along the third direction Z, the gate line located at the bottom among the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) can be constructed as a source selection gate SGS1, and the source selection gate SGS1 is configured to control the conduction state of the transistor T6, thereby being able to control the conduction state of the source channel in the first storage cell string 400a. The gate line located at the top among the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) can be constructed as a drain selection gate SGD1, and the drain selection gate SGD1 is configured to control the conduction state of the transistor T1, thereby being able to control the conduction state of the drain channel in the first storage cell string 400a. The gate line located in the middle among the multiple gate lines G can be constructed as a plurality of word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word line WL, data writing, reading, and erasing of each memory cell (eg, transistor T) in the first memory cell string 400a can be completed.

[0092] Please continue to refer to Figure 7 and Figure 8 The second memory cell string 400b includes a plurality of transistors T formed by the second channel structure 1122 and a plurality of gate lines G, a transistor T (eg Figure 8 The transistors T7 to T12 in the second memory cell string 400b may be configured as a memory cell, and these transistors T are connected together to form a second memory cell string 400b. A transistor T (for example, each transistor T) may be formed by a second channel structure 1122 and a gate line G surrounding the second channel structure 1122. The gate line G is configured to control the conduction state of the transistor.

[0093] It should be noted that Figures 7 and 8 The number of transistors in the second storage cell string 400b is only illustrative. The second storage cell string 400b of the three-dimensional memory provided by the embodiment of the present disclosure may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0094] In some embodiments, along the third direction Z, the gate line located at the bottom among the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) can be constructed as a source selection gate SGS2, and the source selection gate SGS2 is configured to control the conduction state of the transistor T12, thereby being able to control the conduction state of the source channel in the second storage cell string 400b. The gate line located at the top among the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) can be constructed as a drain selection gate SGD2, and the drain selection gate SGD2 is configured to control the conduction state of the transistor T7, thereby being able to control the conduction state of the drain channel in the second storage cell string 400b. The gate line located in the middle among the multiple gate lines G can be constructed as a plurality of word lines WL, for example, including word lines WL4, word lines WL5, word lines WL6, and word lines WL7. By writing different voltages on the word line WL, data writing, reading, and erasing of each memory cell (eg, transistor T) in the second memory cell string 400 b can be completed.

[0095] The embodiment of the present disclosure also provides another semiconductor structure, wherein the structure of the semiconductor structure at the channel hole is as follows: Fig. 9 and Fig.10 As shown, according to Fig. 9 and Fig.10 It can be seen that in the semiconductor structure provided in this embodiment, only one memory cell string 400 can be formed at the location of one channel hole.

[0096] By comparison, it can be found that compared with a semiconductor structure in which only one memory cell string 400 can be formed in one channel hole (eg Fig. 9 and Fig.10 ), a storage column 112 (the storage column 112 includes a first channel structure 1121, a second channel structure 1122 and an isolation portion 1123) is provided in the channel hole CH. The semiconductor structure 110 (such as Figures 4 to 8 In the embodiment shown in the figure), more memory cell strings 400 can be formed in the same number of channel holes CH, thereby improving the storage density of the semiconductor structure 110.

[0097] In some examples, such as Figure 4 and Figure 6As shown, the first channel structure 1121 and the second channel structure 1122 can be symmetrically arranged along the second direction Y; that is, the surface perpendicular to the first direction X is defined as the reference plane 113. For example, the reference plane 113 can be the plane where the gate layer 1111 or the gate insulation layer 1112 is located. For example, the reference plane 113 can also be the YZ plane formed by the second direction Y and the third direction Z. The orthographic projection areas of the first channel structure 1121 and the second channel structure 1122 on the reference plane 113 are the same. Such a design is conducive to the processing and manufacturing of the first channel structure 1121 and the second channel structure 1122.

[0098] In some examples, the number of storage columns 112 may be multiple, and further reference is made to Figure 4 , the plurality of storage pillars 112 may be divided into a plurality of storage pillar groups CCZ, and the plurality of storage pillar groups CCZ may be sequentially spaced along the second direction Y. Each storage pillar group CCZ may include a plurality of storage pillars 112 sequentially spaced along the third direction Z. The storage pillars 112 in two adjacent storage pillar groups CCZ may be staggered.

[0099] In a possible implementation, the size of two adjacent storage pillar groups CCZ along the second direction may be equal to the size of the storage pillar 112 along the second direction Y. Figure 6 As shown, the distance between two adjacent storage column groups CCZ in the second direction Y is 3R, and the size occupied by the storage column 112 in the second direction Y is also 3R.

[0100] Please continue to refer to Figure 6 In some examples, in each storage column 112, the isolation portion 1123 may include two first isolation portions GEL1 and one second isolation portion GEL2. The two first isolation portions GEL1 are arranged relatively along a third direction Z. At this time, the third direction Z can be understood as a straight line passing through the second isolation portion GEL2 and is perpendicular to both the first direction X and the second direction Y. The second isolation portion GEL2 is located between the two first isolation portions GEL1 and the channel layer GC of the first channel structure 1121 and the channel layer GC of the second channel structure 1122.

[0101] In some examples, the channel layer GC of the first channel structure 1121 and the channel layer GC of the second channel structure 1122 both include first surfaces BM1 opposite to each other along the second direction Y. At this time, the second isolation portion GEL2 may be located between the two first isolation portions GEL1 and the first surface BM1 of the first channel structure 1121 and the first surface BM1 of the second channel structure 1122 .

[0102] The material of the first isolation part GEL1 is an insulating material, which can be silicon oxide, silicon nitride or silicon oxynitride. The material of the second isolation part GEL2 is an insulating material, and the insulating material can refer to the relevant description that the material of the first isolation part GEL1 is an insulating material. Exemplarily, the material of the first isolation part GEL1 is the same as the material of the second isolation part GEL2; in this way, the process steps and equipment can be reduced, which is conducive to reducing costs. For example, the material of the first isolation part GEL1 and the material of the second isolation part GEL2 can both be silicon oxide. Among the insulating materials, the price of silicon oxide is relatively cheap, which can reduce costs. Another exemplary embodiment, the material of the first isolation part GEL1 and the material of the second isolation part GEL2 can be different, and the insulating performance of the first isolation part GEL1 is greater than the insulating performance of the second isolation part GEL2. For example, the material of the first isolation part GEL1 is silicon nitride, and the material of the second isolation part GEL2 is silicon oxide.

[0103] The channel layer GC of the first channel structure 1121 and the channel layer GC of the second channel structure 1122 both include first end faces DM1 opposite to each other along the second direction Y. The storage function layer CGC of the first channel structure 1121 and the storage function layer CGC of the second channel structure 1122 both include second end faces DM2 opposite to each other along the second direction Y (the second end face DM2 can be understood as an end face composed of an end face of the barrier layer ZC, an end face of the tunneling layer SC, and an end face of the storage layer CC).

[0104] The first isolation portion GEL1 may cover the first end surface DM1, and may also cover part or all of the second end surface DM2. With such a design, the storage function layer CGC may be protected (at least partially) by covering the second end surface DM2, thereby improving the problem of the storage function layer CGC being affected and damaged in subsequent processing, so as to ensure the storage performance of the storage unit.

[0105] For example, when the first isolation portion GEL1 covers the first end surface DM1, the first isolation portion GEL1 can also cover the entire second end surface DM2. The entire second end surface DM2 can be understood as an end surface composed of the end surface of the blocking layer ZC, the end surface of the tunneling layer SC and the end surface of the storage layer CC.

[0106] For another example, when the first isolation portion GEL1 covers the first end surface DM1, the first isolation portion GEL1 may also cover a portion of the second end surface DM2; illustratively, the first isolation portion GEL1 only covers portions of the tunneling layer SC and the storage layer CC in the second end surface DM2, and a portion of the blocking layer ZC in the second end surface DM2 is not covered by the first isolation portion.

[0107] In the case where the first isolation portion GEL1 covers a portion of the second end surface DM2, another portion of the second end surface DM2 not covered by the first isolation portion GEL1 may be covered by the isolation portion 114. Exemplarily, the first isolation portion GEL1 covers portions of the tunneling layer SC and the storage layer CC in the second end surface DM2; a portion of the barrier layer ZC in the second end surface DM2 is covered by the isolation portion 114; at this time, a portion of the second end surface DM2 may be understood as an end surface composed of an end surface of the tunneling layer SC and an end surface of the storage layer CC, and another portion of the second end surface DM2 may be understood as an end surface of the barrier layer ZC.

[0108] In some other embodiments, the first isolation portion GEL1 covers the first end surface DM1 and does not cover the second end surface DM2 . The second end surface DM2 may be covered by the partition portion 114 .

[0109] In some embodiments, the size of the first isolation portion GEL1 along the second direction Y may be greater than or equal to one quarter of the size of the storage pillar 112 along the second direction Y, and less than or equal to one half of the size of the storage pillar 112 along the second direction Y. Exemplarily, the size of the first isolation portion GEL1 along the second direction Y may be greater than or equal to one third of the size of the storage pillar 112 along the second direction Y, and less than or equal to one half of the size of the storage pillar 112 along the second direction Y. In some examples, the size of the first isolation portion GEL1 along the second direction Y may be equal to one quarter, one third, or one half of the size of the storage pillar 112 along the second direction Y. For example, Figure 6 As shown, the size occupied by the storage column 112 in the second direction Y is 3R, and the size occupied by the first isolation part GEL1 in the second direction Y is R; the size of the first isolation part GEL1 along the second direction Y is equal to one third of the size of the storage column 112 along the second direction Y.

[0110] With such a design, while meeting the manufacturing process requirements of the storage column 112 , the uniformity of the layout of the first channel structure 1121 , the second channel structure 1122 and the isolation portion 1123 in the storage column 112 in the channel hole CH can be improved, thereby facilitating the processing and manufacturing of the storage column 112 .

[0111] In some examples, a size of the partition 114 along the second direction Y may be equal to a size of the first isolation portion GEL1 along the second direction Y.

[0112] In some embodiments, the orthographic projections of the first channel structure 1121 and the second channel structure 1122 on the reference plane 113 may both be arc-shaped projections.

[0113] The storage function layer CGC of the first channel structure 1121 and the storage function layer CGC of the second channel structure 1122 both include a second surface BM2 opposite to each other along the second direction Y (the second surface BM2 can be understood as the surface of the barrier layer ZC, and is in contact with the stacked structure 111). At this time, the arc-shaped projection can be the orthographic projection of the first surface BM1, the first end surface DM1, the second end surface DM2, the second surface BM2, the second end surface DM2 and the first end surface DM1 connected end to end in sequence on the reference plane 113. Among them, the first surface BM1 and the second surface BM2 are arc-shaped surfaces; the first end surface DM1 and the second end surface DM2 can be planes.

[0114] The opening directions of the two arc-shaped projections may be opposite along the second direction Y. In some examples, the opening directions of the two arc-shaped projections are symmetrically arranged along the second direction Y. The opening of the arc-shaped projection may be in the shape of an orthographic projection of the first surface BM1 on the reference surface 113 .

[0115] In some embodiments, the partition 114 in the semiconductor structure 110 may include a plurality of sub-partitions 1141 sequentially spaced apart along the third direction Z, and the sub-partitions 1141 penetrate the stacked structure 111 along the first direction X. Each sub-partition 1141 connects the isolation portions 1123 in two adjacent storage pillars 112 along the third direction Z. For example, each sub-partition 1141 connects the first isolation portions GEL1 in two adjacent storage pillars 112 along the third direction Z.

[0116] In some examples, the material of the partition 114 may be the same as the material of the isolation portion 1123; that is, the material of the partition 114, the material of the first isolation portion GEL1, and the material of the second isolation portion GEL2 are all the same; for example, the material of the partition 114 and the material of the isolation portion 1123 may both be silicon oxide. In other examples, the material of the partition 114 may be different from the material of the isolation portion 1123; that is, the material of the first isolation portion GEL1 and the material of the second isolation portion GEL2 are the same, and different from the material of the partition 114; for example, the material of the partition 114 may be silicon nitride, and the material of the isolation portion 1123 (that is, the first isolation portion GEL1 and the second isolation portion GEL2) may be silicon oxide.

[0117] In some embodiments, the semiconductor structure 110 may further include an array interconnect layer that may be coupled to the memory cell string 400 in the semiconductor structure 110 .

[0118] Fig.11 FIG. 1 is a schematic diagram of the structure of another three-dimensional memory 10 according to some embodiments.

[0119] In some embodiments, the three-dimensional memory 10 may further include a peripheral device 120. The semiconductor structure 110 is coupled to the peripheral device 120, and the peripheral device 120 may be disposed on a side of the semiconductor structure 110 away from the source layer SL. The controller 20 may be coupled to the peripheral device 120.

[0120] The peripheral device 120 may include peripheral circuits configured to control and sense the semiconductor structure 110 (e.g., an array device). The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs)) or storage circuits (e.g., static random access memories (SRAMs)).

[0121] In some examples, the peripheral circuit may include at least one (eg, one, or more) transistor.

[0122] Exemplarily, the peripheral device 120 may further include a peripheral interconnect layer, which is coupled to the peripheral circuit to transmit electrical signals between the peripheral circuit and the peripheral interconnect layer. For example, the peripheral interconnect layer may be coupled to the transistor to transmit electrical signals between the transistor and the peripheral interconnect layer.

[0123] The peripheral interconnect layer can be coupled to the array interconnect layer, so that the semiconductor structure 110 and the peripheral device 120 can be coupled. Specifically, since the peripheral interconnect layer is coupled to the array interconnect layer, the peripheral circuit in the peripheral device 120 can be coupled to the memory cell string in the semiconductor structure 110 to achieve the transmission of electrical signals between the peripheral circuit and the memory cell string.

[0124] In some possible implementations, a bonding interface may be provided between the peripheral interconnection layer and the array interconnection layer, and the peripheral interconnection layer and the array interconnection layer may be bonded and coupled to each other through the bonding interface.

[0125] Fig.12 The present invention is a flow chart of a method for preparing a semiconductor structure according to some embodiments.

[0126] The embodiments of the present disclosure also provide a method for preparing a semiconductor structure. Fig.12The preparation method includes: step S100 and step S200.

[0127] Step S100 : forming a stacked structure 111 , wherein the stacked structure 111 includes gate insulating layers 1112 and gate layers 1111 alternately stacked along a first direction X.

[0128] Step S200, forming a storage column 112, the storage column 112 penetrates the stack structure 111 along the first direction X; the storage column 112 includes a first channel structure 1121, a second channel structure 1122 and an isolation portion 1123; the first channel structure 1121 and the second channel structure 1122 are arranged opposite to each other along the second direction Y, and the second direction Y is perpendicular to the first direction X; the isolation portion 1123 is located between the first channel structure 1121 and the second channel structure 1122, and the isolation portion 1123 isolates the first channel structure 1121 from the second channel structure 1122.

[0129] It should be noted that the description of step S100 and step S200 may refer to the relevant description of the semiconductor structure 110. The effect of the semiconductor structure formed by step S100 and step S200 may refer to the relevant description of the effect of the semiconductor structure 110.

[0130] Fig.13 FIG. 4 is a flow chart of another method for preparing a semiconductor structure according to some embodiments. Figure 14 to Figure 23 is a process diagram of a method for preparing a semiconductor structure according to some embodiments.

[0131] See also Fig.13 , step S100 and step S200 may include: step S310 to step S350.

[0132] Step S310, see Fig.14 , a stacked structure CD is formed on the substrate 115. The stacked structure CD includes first film layers M1 and second film layers M2 alternately stacked along a first direction X.

[0133] In some examples, the first film layer M1 may be a gate layer 1111, and the second film layer M2 may be a gate insulating layer 1112, forming a stacked structure 111. The stacked structure 111 may refer to the related description of the stacked structure 111 in the semiconductor structure 110 above.

[0134] In some other examples, the first film layer M1 may be a gate sacrificial layer, and the second film layer M2 may be a gate insulating layer 1112 .

[0135] The gate sacrificial layer may include a material having a high etching selectivity with the gate insulating layer 1112. In some examples, each gate insulating layer 1112 includes a silicon oxide layer, and each gate sacrificial layer includes a silicon nitride layer. That is, multiple silicon nitride layers and multiple silicon oxide layers may be alternately deposited on the substrate 115.

[0136] The gate insulating layer 1112 and the gate sacrificial layer can be formed using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Among them, silicon oxide and silicon nitride are material pairs with high etching selectivity. Specifically, the etching selectivity between silicon oxide and silicon nitride is greater than 10. Of course, the gate sacrificial layer and the gate insulating layer 1112 can also be other material pairs with high etching selectivity, which is only used as an example and is not intended to be limiting. For example, the material of the gate insulating layer 1112 can also refer to the relevant description of the material of the gate insulating layer 1112 in the semiconductor structure 110.

[0137] Step S320, see Fig.15 and Fig.16 , forming a channel hole CH, wherein the channel hole CH penetrates the stacked structure CD along the first direction X.

[0138] For example, photolithography technology can be used to define the channel hole CH pattern in the photoresist, and the channel hole CH penetrating the stacked structure CD is formed by wet etching and / or dry etching. For example, the etching process can be deep reactive ion etching (DRIE). Among them, the positional relationship of the channel hole CH can refer to the relevant description of the positional relationship of the storage pillar 112 in the semiconductor structure 110. The orthographic projection of the channel hole CH on the reference plane 113 can be a regular figure such as an ellipse, a circle, etc., or it can be an irregular figure similar to a regular figure such as an ellipse, a circle, etc.

[0139] Step S330, see Fig.17 and Fig.18 , a storage function film CGM and a channel film GM are sequentially formed on the inner wall of the channel hole CH, and the first material CL1 is filled in the inner side of the channel film GM.

[0140] In some examples, when the first film layer M1 is a gate layer 1111 and the second film layer M2 is a gate insulating layer 1112; or when the first film layer M1 is a gate insulating layer 1112 and the second film layer M2 is a gate sacrificial layer; the first material CL1 may include a compound of carbon atoms, silicon atoms and oxygen atoms or an organic substance or a metal; for example, the first material CL1 may be SOC. The metal may be a metal element, such as copper, iron, aluminum, silver, etc.; it may also be a metal alloy, such as an alloy of the above metal elements.

[0141] The material of the storage function film CGM may refer to the relevant description of the storage function layer CGC in the semiconductor structure 110 . The material of the channel film GM may refer to the relevant description of the channel layer GC in the semiconductor structure 110 .

[0142] Step S340, see Fig.19 , forming a separation groove FG, the separation groove FG penetrates the stacked structure CD along the first direction X, and the separation groove FG extends along the third direction Z, the third direction Z is perpendicular to the first direction X, and the third direction Z intersects the second direction Y; the separation groove FG opens part of the storage functional film CGM, and exposes two target portions MB in the channel film GM that are opposite to each other along the third direction Z.

[0143] In some embodiments of semiconductor structures and methods for manufacturing the same, the array device includes a gate line gap, which is at least used to replace the gate sacrificial layer with the gate layer. In this embodiment, the separation groove FG formed can be used to remove part of the storage functional film CGM in a channel hole CH, and the remaining storage functional film CGM is the storage functional layer CGC of the first channel structure 1121 and the storage functional layer CGC of the second channel structure 1122. In addition, the gate sacrificial layer can also be removed through the formed separation groove FG, and the gate layer can be formed through the separation groove FG. Therefore, compared with the solution of using the gate line gap to make the gate layer, the separation groove FG in this embodiment can be used to form the first channel structure and the second channel structure, and can also be used to replace the gate sacrificial layer with the gate layer.

[0144] The two target portions MB can be understood as two portions of the channel film GM exposed by the separation groove FG in one channel hole CH. Portions of the channel film GM except the two target portions MB are the channel layer GC of the first channel structure 1121 and the channel layer GC of the second channel structure 1122 .

[0145] Specifically, the step of forming the separation groove FG includes: arranging a mask plate on a side of the laminated structure CD away from the substrate 115; the mask plate has a plurality of hollow areas; the hollow areas extend along the third direction Z, and the plurality of hollow areas are arranged along the second direction Y. Each hollow area is used to remove the laminated structure CD and a portion of the storage functional film CGM to form the separation groove FG.

[0146] In some examples, the orthographic projection of the hollow area on the reference plane 113 may include a regular shape such as a rectangle or a square, or may be an irregular shape similar to a regular shape such as a rectangle or a square. It should be noted that the arrangement of the plurality of hollow areas may refer to the description of the semiconductor structure 110 in which the plurality of storage pillar groups CCZ are sequentially arranged in intervals along the second direction Y.

[0147] In some examples, an etching solution in a wet etching process is used to pass through each hollow area to etch the stacked structure CD and a portion of the storage functional film CGM to form a separation groove FG.

[0148] The etching rate of the etching liquid on the storage function film CGM and the stacked structure CD is greater than the etching rate of the etching liquid on the channel film GM and the first material CL1, so that the etching liquid can avoid etching the channel film GM and the first material CL1.

[0149] For example, the ratio of the etching rate of the etching solution on the storage functional film CGM and the stacked structure CD to the etching rate of the etching solution on the channel film GM and the first material CL1 is greater than 10 (for example, equal to 10, equal to 15, equal to 20, equal to 30, etc.); this is just an example and is not intended to be limiting.

[0150] The dimensions of the separation groove FG, part of the storage functional film CGM, the target portion MB, and the hollow area along the second direction Y are equal to the dimensions of the first isolation portion GEL1 in the semiconductor structure 110 along the second direction Y. For example, the dimensions of the separation groove FG, part of the storage functional film CGM, the target portion MB, and the hollow area along the second direction Y are equal to one third of the dimensions of the storage pillar 112 along the second direction Y.

[0151] In the case where the size of the separation groove FG along the second direction Y is equal to one-fourth of the size of the storage pillar 112 along the second direction Y, the etching liquid can just etch through the stacked structure CD to form the separation groove FG; in this way, the area of ​​the remaining storage functional film CGM is larger, so that the areas of the first channel structure 1121 and the second channel structure 1122 formed are larger. In the case where the size of the separation groove FG along the second direction Y is equal to one-half of the size of the storage pillar 112 along the second direction Y, the etching liquid can remove the gate sacrificial layer faster and form the gate layer 1111 faster.

[0152] Step S350, see Fig. 20 , the target portion MB is processed through the separation groove FG to obtain the first isolation portion GEL1, which is a part of the isolation portion 1123.

[0153] In some examples, the target portion MB is oxidized to form oxide. For example, the material of the channel film GM may be single crystal silicon, and the material of the target portion MB may also be single crystal silicon, and the target portion MB is oxidized to form silicon oxide.

[0154] In some other examples, the target portion MB is removed (eg, etched by a wet etching process or a dry etching process), and is filled with oxide (eg, silicon oxide) to obtain the first isolation portion GEL1.

[0155] In some embodiments, the preparation method further comprises: Fig.21 In the case where the first film layer M1 is a gate insulating layer 1112 and the second film layer M2 is a gate sacrificial layer, after processing the target portion MB, the gate sacrificial layer is replaced with the gate layer 1111 through the separation groove FG to obtain a stacked structure 111. Fig. 22 , a second material is filled in the separation groove FG to form a separation portion 114 .

[0156] The selection of the second material may refer to the related description of the material of the partition 114 in the semiconductor structure 110 .

[0157] Specifically, the gate sacrificial layer is removed through the separation groove FG. The gate material is filled through the separation groove FG to form a gate layer 1111, thereby obtaining a stacked structure 111. The gate material in the separation groove FG is removed to separate the multiple gate layers 1111 and avoid electrical connection between the gate layers 1111.

[0158] In some embodiments, the preparation method further includes: removing the first material CL1; the first material CL1 may include a compound of carbon atoms, silicon atoms and oxygen atoms or an organic substance or a metal. Fig.23 A third material is filled between the two first isolation parts GEL1 and the channel layer GC of the first channel structure 1121 and the channel layer GC of the second channel structure 1122 to form a second isolation part GEL2; the third material may include oxide (eg, silicon oxide).

[0159] It should be noted that, after the two target parts MB of the channel film GM are processed, the two first isolation parts GEL1 and the unprocessed channel film GM are the channel layer GC of the first channel structure 1121 and the channel layer GC of the second channel structure 1122. At this time, the first material CL1 is located in the channel film GM, which can be replaced by the first material CL1 being located between the two first isolation parts GEL1 and the channel layer GC of the first channel structure 1121 and the channel layer GC of the second channel structure 1122. Accordingly, the third material can be filled between the two first isolation parts GEL1 and the channel layer GC of the first channel structure 1121 and the channel layer GC of the second channel structure 1122.

[0160] The semiconductor structure and method provided by the embodiments of the present disclosure can increase storage density and reduce costs.

[0161] The above is only a specific embodiment of the present disclosure, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A stacked structure comprising gate insulating layers and gate layers alternately stacked along a first direction; A storage column runs through the stack structure along the first direction; the storage column includes a first channel structure, a second channel structure and an isolation portion; the first channel structure and the second channel structure are arranged relative to each other along the second direction, and the second direction is perpendicular to the first direction; the isolation portion is located between the first channel structure and the second channel structure, and the isolation portion isolates the first channel structure from the second channel structure.

2. The semiconductor structure according to claim 1, characterized in that: The first channel structure and the second channel structure each include a channel layer; The isolation part includes two first isolation parts and one second isolation part; the two first isolation parts are arranged relatively to each other along a third direction, the third direction is perpendicular to the first direction, and the third direction intersects with the second direction; the second isolation part is located between the two first isolation parts and the channel layer of the first channel structure and the channel layer of the second channel structure.

3. The semiconductor structure according to claim 2, characterized in that: The material of the first isolation portion is the same as that of the second isolation portion.

4. The semiconductor structure according to claim 2, characterized in that: The channel layer of the first channel structure and the channel layer of the second channel structure include first end surfaces opposite to each other along the second direction, and the first isolation portion covers the first end surfaces.

5. The semiconductor structure according to claim 4, characterized in that: The first channel structure and the second channel structure each further include a storage function layer; the storage function layer is located between the channel layer and the stacking structure; The storage function layer of the first channel structure and the storage function layer of the second channel structure include second end surfaces opposite to each other along the second direction, and the first isolation portion also covers the second end surfaces.

6. The semiconductor structure according to claim 5, characterized in that: The storage function layer includes: a tunneling layer, a storage layer and a barrier layer away from the channel layer; The first isolation portion also covers the tunneling layer and the storage layer.

7. The semiconductor structure according to claim 2, characterized in that: A dimension of the first isolation portion along the second direction is greater than or equal to one quarter of a dimension of the storage column along the second direction, and less than or equal to one half of a dimension of the storage column along the second direction.

8. The semiconductor structure according to claim 7, characterized in that: A dimension of the first isolation portion along the second direction is equal to one third of a dimension of the storage pillar along the second direction.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that: defining a surface perpendicular to the first direction as a reference surface; The orthographic projections of the first channel structure and the second channel structure on the reference plane are both arc-shaped projections, and the opening directions of the two arc-shaped projections are opposite to each other along the second direction.

10. The semiconductor structure according to any one of claims 1 to 8, characterized in that: The first channel structure and the second channel structure are arranged symmetrically.

11. The semiconductor structure according to any one of claims 1 to 8, characterized in that: The number of the storage columns is multiple, and the multiple storage columns are sequentially spaced along a third direction, the third direction is perpendicular to the first direction, and the third direction intersects with the second direction; The semiconductor structure further comprises: The partition includes a plurality of sub-partitions sequentially arranged at intervals along the third direction, wherein the sub-partitions penetrate the stacking structure along the first direction and connect the isolation parts in two adjacent storage columns along the third direction.

12. The semiconductor structure according to claim 11, characterized in that: The material of the partition part is the same as that of the isolation part.

13. A method for preparing a semiconductor structure, characterized in that: include: forming a stacked structure, the stacked structure comprising gate insulating layers and gate layers alternately stacked along a first direction; A storage column is formed, and the storage column penetrates the stack structure along the first direction; the storage column includes a first channel structure, a second channel structure and an isolation part; the first channel structure and the second channel structure are arranged relative to each other along the second direction, and the second direction is perpendicular to the first direction; the isolation part is located between the first channel structure and the second channel structure, and the isolation part isolates the first channel structure from the second channel structure.

14. The preparation method according to claim 13, characterized in that: The forming of the stacked structure and the forming of the storage column include: Forming a stacked structure on a substrate; the stacked structure includes a first film layer and a second film layer alternately stacked along a first direction; forming a channel hole, wherein the channel hole penetrates the stacked structure along the first direction; forming a storage function film and a channel film in sequence on the inner wall of the channel hole, and filling a first material inside the channel film; forming a separation groove, wherein the separation groove penetrates the stacked structure along the first direction and extends along a third direction, the third direction is perpendicular to the first direction and intersects the second direction; the separation groove opens a portion of the storage functional film and exposes two target portions in the channel film that are opposite to each other along the third direction; The target portion is processed through the separation groove to obtain a first isolation portion, where the first isolation portion is a portion of the isolation portion.

15. The preparation method according to claim 14, characterized in that: The processing of the target portion through the separation groove includes: performing an oxidation process on the target portion.

16. The preparation method according to claim 14, characterized in that: The step of forming the separation groove comprises: A mask plate is arranged on a side of the stacked structure away from the substrate; the mask plate has a plurality of hollow areas; the hollow areas extend along the third direction, and the plurality of hollow areas are arranged along the second direction; The stacked structure and part of the storage functional film are removed by using each hollow area to form the separation groove.

17. The preparation method according to claim 16, characterized in that: The step of removing the stacked structure and part of the storage functional film by using each hollow area to form the separation groove comprises: Using an etching solution in a wet etching process to pass through each hollow area, etching the stacked structure and part of the storage functional film to form the separation groove; Wherein, the etching rate of the etching solution on the storage functional film and the stacked structure is greater than the etching rate of the etching solution on the channel film and the first material.

18. The preparation method according to any one of claims 14 to 17, characterized in that: The forming of the stacked structure and the forming of the storage pillar further include: removing the first material; the first material comprises a compound or an organic matter or a metal of carbon atoms, silicon atoms and oxygen atoms; A third material is filled between the two first isolation parts and the channel layer of the first channel structure and the channel layer of the second channel structure to form a second isolation part; the third material includes oxide.

19. The preparation method according to any one of claims 14 to 17, characterized in that: The first film layer is a gate insulating layer, the second film layer is a gate sacrificial layer, and the forming of the stacked structure and the forming of the storage pillar further include: After processing the target portion, the gate sacrificial layer is replaced with a gate layer via the separation groove to obtain the stacked structure.

20. The preparation method according to claim 19, characterized in that: After processing the target portion, replacing the gate sacrificial layer with a gate layer via the separation groove comprises: removing the gate sacrificial layer through the separation groove; Filling the separation groove with a gate material to form a gate layer, thereby obtaining the stacked structure; The gate material in the separation groove is removed to separate the plurality of gate layers.

21. The preparation method according to claim 19, characterized in that: The forming of the stacked structure and the forming of the storage pillar further include: A second material is filled in the separation groove to form a separation portion.

22. A storage system, characterized in that: include: A semiconductor structure, which is a semiconductor structure as claimed in any one of claims 1 to 12; A controller is coupled to the semiconductor structure.

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