Method for forming PN junction of large-through-flow TVS (Transient Voltage Suppressor) diode

Abstract

The invention belongs to the field of design and manufacturing of semiconductors / integrated circuits, and particularly relates to a method for forming a PN junction of a large-through-flow TVS diode. Comprising the following steps: selecting a doped silicon substrate, forming an oxide layer on the surface of the substrate, developing trench overlook patterns with different shapes on the oxide layer, etching a trench on the substrate through an etching process, filling doped polycrystalline silicon which is inverted with the substrate into the trench, sealing, carrying out reverse etching on the doped polycrystalline silicon, and carrying out high-temperature diffusion and junction pushing. And then depositing an oxide layer as a through hole dielectric layer and forming a through hole, finally depositing metal on the dielectric layer through a deposition process to form a front electrode, grinding and thinning the back surface of the substrate, depositing multiple layers of metal to form a back electrode, and carrying out interconnection packaging. According to the method, the requirement for higher surge current absorption capacity can be met, meanwhile, lower clamping voltage is achieved, the performance of the TVS diode is improved, and the TVS diode has higher product competitiveness.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor / integrated circuit design and manufacturing, and in particular relates to a method for forming a PN junction of a large through-current TVS diode. Background Art

[0002] Transient Voltage Suppressor (TVS) diodes play a vital role in modern electronic circuits. With the rapid development of electronic technology, the application scenarios of various electronic devices are becoming increasingly complex, and the requirements for circuit stability and safety are becoming higher and higher.

[0003] During the operation of the circuit, it is often disturbed by various transient voltages, such as lightning strikes, electrostatic discharge, circuit switching, etc., which may generate instantaneous high voltage pulses. If these transient voltages are not suppressed, they will cause serious damage to various components in the circuit, leading to circuit failures and even damage to the entire electronic equipment.

[0004] The core function of TVS diode is to withstand and conduct large current in a very short time, clamping the surge voltage at a minimum level to protect other components in the circuit. It can respond to transient voltage in nanoseconds or even shorter time and quickly activate its protection mechanism.

[0005] Traditional TVS diodes have achieved certain results in meeting some basic protection needs. However, with the continuous development of terminal equipment, the requirements for safety are increasing, and higher requirements are also placed on TVS diodes. For example, in some fields with extremely high reliability requirements such as industrial control equipment, communication base station equipment, and automotive electronic equipment, TVS diodes are required to have higher surge current absorption capabilities to cope with more complex and strong transient voltage interference. At the same time, in order to better protect sensitive components in the circuit, TVS diodes are also required to achieve lower clamping voltages.

[0006] At present, the conventional method to increase the surge current absorption capacity of TVS is to increase the PN junction area. However, this method has obvious limitations. Simply increasing the PN junction area will lead to an increase in body resistance, which will not only increase the clamping voltage, greatly reducing the protection effect, but also increase the volume of the TVS device. With the trend of modern electronic equipment pursuing miniaturization, lightweight and high performance, TVS devices with increased volume obviously do not have good product competitiveness and are difficult to meet market demand. Therefore, it is necessary to explore a new method to form the PN junction of the TVS diode to overcome the shortcomings of the existing technology and improve the performance of the TVS diode. Summary of the invention

[0007] In view of the shortcomings of the prior art, the present invention proposes a method for forming a PN junction of a large through-current TVS diode, which can increase the PN junction area and the ability of the TVS to absorb surge current, and on the other hand, reduce the body resistance and clamping voltage, thereby forming a more competitive TVS device.

[0008] The technical solution of the present invention is as follows:

[0009] A method for forming a PN junction of a large through-current TVS diode, comprising:

[0010] Select a doped silicon substrate, first oxidize the substrate surface by thermal oxidation or chemical vapor deposition, and then develop a trench top view of different shapes by photolithography;

[0011] Through the etching process, the required trench is etched on the substrate;

[0012] Through a deposition process, doped polysilicon that is inversely proportional to the substrate is filled into the trench and sealed;

[0013] Reversely etch the doped polysilicon to keep only the poly at the trench lead-out position, and then diffuse the junction at high temperature to meet the required junction voltage performance;

[0014] Through a deposition process, an oxide layer is deposited as a through-hole dielectric layer, and a through hole is opened at the trenchpoly position through a photolithography and etching process;

[0015] Through the deposition process, metal is deposited on the dielectric layer to form a front electrode, and the back side of the substrate is ground and thinned, and multiple layers of metal are deposited to form a back electrode.

[0016] The doped silicon substrate is selected <100> or <111> A doped silicon substrate with a crystalline orientation forms an oxide layer of 100-10000A on the surface of the doped silicon substrate.

[0017] The trench top view shapes of different shapes include rectangle, square, circle, ellipse or polygon.

[0018] The process of forming trench top view shapes of different shapes is: uniformly coating photoresist on the surface of the substrate, and developing trench top view shapes of different shapes on the oxide layer through exposure and development operations; wherein the photoresist is uniformly coated on the surface of the oxide layer by wheel coating or spraying.

[0019] The etching process is selected from dry etching or wet etching; after the etching process is completed, the oxide layer is removed, wherein the oxide layer is removed by chemical etching or dry etching.

[0020] The deposition process includes chemical vapor deposition and physical vapor deposition, the sealing method adopts chemical vapor deposition sealing or uses silicon dioxide or silicon nitride as sealing material in chemical vapor deposition sealing, and deposits by using silane and oxygen as reaction gases;

[0021] Physical vapor deposition sealing or reactive sputtering in physical vapor deposition sealing uses silicon dioxide as a target for deposition.

[0022] The front electrode is formed by depositing metal on the through hole and the surface of the doped silicon substrate and patterning the metal to form the front electrode;

[0023] The back electrode is formed by depositing metal on the back of the thinned substrate and patterning it to form the back electrode;

[0024] The front electrode and the back electrode are connected by bonding or other interconnection techniques.

[0025] The conditions satisfied by the trench are: the sum of the side areas between the two trenches is greater than the bottom area of ​​the active area between the trenches, so as to ensure that the sum of the areas of each trench is greater than the area of ​​all trenches as a whole; the spacing between the two trenches must ensure that the diffusion areas formed after high-temperature diffusion do not hold hands and there is still a gap.

[0026] The beneficial effects of the present invention are as follows: the present invention is based on existing process technology and utilizes doped polysilicon instead of ion implantation to form a PN junction with uniform concentration and precisely controllable depth / width, which is beneficial to precisely control the clamping voltage. In addition, multiple trenches are connected in parallel, which can increase the PN junction area and effectively increase the surge current absorption capacity on the one hand, and on the other hand, the parallel PN junctions can reduce the body resistance and obtain a low clamping voltage.

[0027] The doping region formed by the trench poly in the present invention has a more uniform concentration distribution than the doping region formed by ion implantation. At the same time, the shape, size and depth of the trench poly can be precisely designed and controlled, and the clamping voltage can be precisely controlled. Compared with the PN junction area of ​​the entire conventional TVS diode, the total PN junction area of ​​the trench poly formed by the present invention is much larger than the area of ​​the entire PN junction, which can effectively increase the surge current absorption capacity of the TVS. The front metal connects each trench poly in parallel through a through hole, which can reduce the body resistance of the PN junction, thereby obtaining a low clamping voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is the overall flow chart of the present invention;

[0029] Figure 2 This is an example of a trench top view diagram using a rectangle as an example;

[0030] Figure 3 is a schematic diagram of the etching process;

[0031] Figure 4 This is a schematic diagram of the process of filling and sealing the trench;

[0032] Figure 5 It is a schematic diagram of reverse etching and high temperature diffusion junction pushing;

[0033] Figure 6 Schematic diagram of through-hole formation and electrode preparation;

[0034] Figure 7 Schematic diagram of the TVS diode structure formed. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] See also Figure 1 , which shows a method for forming a PN junction of a large through-current TVS diode provided by an embodiment of the present invention, comprising:

[0037] S100: Select <100> or <111> The doped silicon substrate with a crystal orientation is first oxidized on the surface of the substrate by thermal oxidation or chemical vapor deposition process, and then a trench top view of different shapes is developed by photolithography process.

[0038] S200: etching a required trench on the substrate through an etching process.

[0039] S300: Through a deposition process, doped polysilicon having an inverse type to the substrate is filled into the trench and sealed.

[0040] S400: Reversely etch the doped polysilicon to retain only the poly at the trench lead-out position, and then diffuse the junction at high temperature to meet the required junction voltage performance.

[0041] S500: depositing an oxide layer as a through-hole dielectric layer through a deposition process, and opening a through hole at a trenchpoly position through a photolithography and etching process.

[0042] S600: depositing metal on the dielectric layer through a deposition process to form a front electrode, grinding and thinning the back side of the substrate, and depositing multiple layers of metal to form a back side electrode.

[0043] S100 involves selecting a doped silicon substrate, forming an oxide layer on the substrate surface through thermal oxidation or chemical vapor deposition, and finally developing a trench top view of different shapes using a photolithography process. This step can provide a good foundation for the subsequent manufacture of a large-current TVS diode PN junction by rationally selecting the substrate and precisely controlling each process step. The precisely formed trench pattern helps to optimize the electrical performance of the diode and improve its stability and reliability in the circuit. Different process selections and control methods can meet diverse design requirements.

[0044] S100 specifically includes:

[0045] S110: Select <100> or <111> crystal orientation of a doped silicon substrate.

[0046] choose <100> or <111> The doping of the silicon substrate in the crystal orientation is a key step of the present invention. The crystal orientation refers to the specific direction of the arrangement of atoms in the crystal. The doping types are divided into n-type and p-type. The doping concentration affects the electrical properties of the substrate. Too high or too low has different effects. When selecting the crystal orientation, from the perspective of electrical properties, <100> The crystal orientation has a higher electron mobility and is suitable for certain high-frequency applications. <111> Crystal orientation affects hole mobility under certain conditions and may provide higher breakdown voltage suitable for power devices. From the perspective of process compatibility, different crystal orientations affect the diffusion speed and direction of impurities, the effects of lithography and etching processes, such as <100> The crystal orientation is easier to etch vertically.

[0047] S120: forming an oxide layer of 100-10000A on the surface of the substrate by thermal oxidation or chemical vapor deposition.

[0048] Forming an oxide layer of 100-10000A on the surface of the substrate through a thermal oxidation process is a process that requires precise control of multiple parameters. First, the appropriate oxidation temperature must be determined, which usually ranges from several hundred degrees Celsius to more than one thousand degrees Celsius. Different temperatures have a significant impact on the growth rate and quality of the oxide layer. At lower temperatures, the oxide layer may grow slower but more dense, while at higher temperatures, the growth is faster but defects may occur. Secondly, the oxidation time must be adjusted according to the thickness of the required oxide layer. The longer the time, the thicker the oxide layer. Furthermore, the gas environment is also a key factor. Generally, oxygen or a mixed gas containing oxygen is used. The flow rate and purity of the gas will affect the growth of the oxide layer. Too much flow may cause uneven gas distribution and affect the uniform growth of the oxide layer. Too little flow may not provide enough oxidation source to slow the growth of the oxide layer.

[0049] The chemical vapor deposition process forms an oxide layer of 100-10000A on the substrate surface. It is necessary to select appropriate reaction gases (such as silane and oxygen) and precisely control the deposition conditions. The deposition temperature is generally around several hundred degrees Celsius, and different temperatures affect the reaction rate and the quality of the deposited layer. The pressure will affect the diffusion and reaction of gas molecules and needs to be adjusted within a suitable range, generally 1-100kPa. At the same time, the reaction gas flow ratio must be precisely controlled. Different flow ratios affect the chemical composition and quality of the generated silicon oxide. Through the reasonable control of these parameters, an oxide layer is formed on the substrate surface.

[0050] S130: uniformly coating the surface of the substrate with photoresist, and developing different shapes of trench top view images on the oxide layer through exposure and development operations.

[0051] Trench top view graphics of different shapes, including but not limited to rectangle, square, circle, oval, polygon. Figure 2 Rectangular case shown.

[0052] In one possible implementation, the photoresist is evenly coated on the surface of the oxide layer by wheel coating or spraying, and the thickness is controlled according to the trench pattern size and the etching process.

[0053] Use a light source such as ultraviolet light or deep ultraviolet light to expose the coated photoresist through a mask, and then use a developer to remove the photoresist in the exposed area to form a trench pattern.

[0054] S200 includes two parts: etching process and oxide layer removal. This step can accurately etch the required trench on the substrate and effectively remove the oxide layer, providing a good foundation for subsequent processes.

[0055] S200 specifically includes:

[0056] S210: Select an etching process.

[0057] In one possible implementation, dry etching is selected. The specific operation steps are: select etching gases such as CF4, SF6, etc. and prepare PECVD equipment, set the etching gas flow, time and power, and adjust the parameters according to the etching effect during the process to ensure that a trench that meets the requirements is etched and avoid damaging the substrate.

[0058] In one possible implementation, wet etching is selected. The specific operation steps are: select a hydrofluoric acid solution and prepare an immersion tank or spray equipment, control the solution concentration, etching time and temperature, and adjust the parameters in time through monitoring to ensure the etching effect and substrate quality.

[0059] S220: Etching is completed and the oxide layer is removed.

[0060] In one possible implementation, a chemical etching method is selected to remove the oxide layer. The specific steps are: prepare a hydrofluoric acid solution of appropriate concentration and safety protection equipment, place the substrate in the solution for etching, determine the time according to the thickness of the oxide layer and the concentration of the solution, monitor and adjust the time appropriately during the process to avoid excessive corrosion of the substrate.

[0061] In one possible implementation, dry removal of the oxide layer is selected. The specific steps are: prepare plasma oxide layer removal equipment and select appropriate gas, set gas flow and plasma power, and adjust parameters according to monitoring results to ensure that the oxide layer is removed and the substrate is not damaged.

[0062] By etching and removing the oxide layer, a Figure 3 The structure shown.

[0063] S300 fills the trench with doped polysilicon that is inversely proportional to the substrate through a deposition process and seals the trench.

[0064] S300 specifically includes:

[0065] S310: Select a deposition process, and use the selected deposition process to fill doped polysilicon having a doping type opposite to that of the substrate into the trench structure.

[0066] In one possible implementation, chemical vapor deposition is selected, and the specific operating steps are: prepare silane and corresponding doping gas and detect the purity, check the equipment gas supply system and sealing and preheat the reaction chamber, set the deposition temperature and monitor the adjustment, adjust the pressure and monitor the adjustment, accurately control the gas flow ratio and monitor the adjustment in real time.

[0067] In one possible implementation, physical vapor deposition is selected, and the specific operating steps are: select a polysilicon target with a purity of more than 99.9% and check the installation, debug the equipment power supply, gas supply system and sealing, set the sputtering power and adjust it in real time, adjust the distance between the target and the substrate and adjust it in real time, determine the deposition time according to the trench situation and adjust it in real time.

[0068] S320: After the trench is filled, the sediment layer is gradually sealed at the top of the trench.

[0069] For chemical vapor deposition sealing, the sealing process of the deposited layer at the top can be promoted by adjusting the reaction gas flow rate, gradually reducing the flow rate of silane while increasing the flow rate of the doping gas, and appropriately increasing the deposition temperature.

[0070] For physical vapor deposition sealing, the sputtering power is reduced while the deposition time is extended so that the deposited layer gradually seals at the top of the trench.

[0071] In addition, in a possible step, an additional deposition step is used, such as using silicon dioxide or silicon nitride as a sealing material in chemical vapor deposition sealing, and depositing it under suitable temperature and pressure conditions by using silane and oxygen as reaction gases; using reactive sputtering in physical vapor deposition sealing, using silicon dioxide as a target material, and depositing it under suitable sputtering power, target-substrate distance and deposition time conditions to ensure that the sealing material is evenly deposited on the top of the trench to achieve a good sealing effect.

[0072] Figure 4 This is a schematic diagram of an example structure for filling doped polysilicon into a trench structure and sealing it.

[0073] S400 includes two steps: reverse etching and high-temperature diffusion and junction pushing. Reverse etching requires coating photoresist on the surface of the structure after filling and sealing, defining the pattern, selecting appropriate gas and equipment, and setting etching parameters to ensure that only the poly at the trench lead-out position is retained. High-temperature diffusion and junction pushing require preparation of diffusion equipment and setting of the environment, determination of diffusion temperature and time, and monitoring to ensure that the junction voltage performance is met. Its advantage is that it can accurately control the retained area of ​​polysilicon and the junction voltage performance, providing a structure and electrical performance foundation that meets the requirements for subsequent processes.

[0074] S400 specifically includes:

[0075] S410: evenly coating the surface of the filled and sealed structure with photoresist, defining the poly pattern of the trench lead-out position to be retained through a photolithography process, and performing reverse etching on the doped polysilicon.

[0076] The conditions that the trenches must meet are: 1) The sum of the side areas between the two trenches is greater than the bottom area of ​​the active area between the trenches, so as to ensure that the sum of the areas of each trench is greater than the area of ​​all trenches as a whole. 2) The spacing between the two trenches must ensure that the diffusion areas formed after high-temperature diffusion do not hold hands and there is still a gap.

[0077] S420: diffusing doped polysilicon into the substrate.

[0078] The specific operation steps are as follows: select a suitable high-temperature diffusion furnace, put in the sample and set a nitrogen or argon atmosphere, control the gas flow rate at 10-30sccm, set the diffusion temperature at 900-1200℃, determine the specific value through experiments and simulations, and monitor in real time to ensure that the temperature fluctuation is within the range of ±10℃, determine the diffusion time at 10-90 minutes, monitor and adjust in time through electrical performance test equipment to ensure that the junction voltage performance is met.

[0079] Through reverse etching and high temperature diffusion, the junction is formed. Figure 5 The structure shown.

[0080] S500 includes depositing an oxide layer on the polysilicon layer to form an etch barrier layer, and then opening precise through holes in the oxide layer through photolithography and etching processes to create conditions for metal deposition.

[0081] S500 specifically includes:

[0082] S510: depositing an oxide layer on the surface of the doped silicon substrate to provide an etching barrier for subsequent formation of through holes.

[0083] For example, a CVD device is selected, silane and oxygen are used as reaction gases, the temperature is set to 300-600°C, the pressure is 1-10 kPa, and the gas flow ratio is 1:2-1:5, and an oxide layer is deposited on the surface of the doped silicon substrate.

[0084] S520: Precise through holes are opened in the oxide layer through photolithography and etching processes to expose the doped silicon substrate.

[0085] Coat photoresist on the surface of the oxide layer, define the pattern with a photolithography mask, transfer the pattern through exposure and development, and ensure the accuracy of the photoresist pattern. Select CF4, SF6 and other gases and PECVD equipment, set the flow rate to 10-30sccm, power to 100-300W and time to 5-15 minutes, and ensure that the through holes that meet the requirements are etched through monitoring and adjustment.

[0086] like Figure 6 As shown, it is a schematic diagram of the structure of depositing an oxide layer on the surface of a doped silicon substrate and opening a through hole.

[0087] S600 prepares metal electrodes on the front and back of the TVS diode respectively, and connects the two through interconnection technology to complete the electrode preparation and electrical connection.

[0088] S600 specifically includes:

[0089] S610: Preparation of front electrodes: Deposit metal on the through holes and the surface of the doped silicon substrate and pattern it to form front electrodes, providing contact points for electrical connections.

[0090] Exemplarily, a PVD device is selected, and the temperature is set to 100-300° C., the pressure to 1-10 kPa, and the deposition rate to 0.5-2 μm / min, and metal AlCu or AlSiCu is deposited to a thickness of 3-5 um to form a front electrode.

[0091] S620: Preparation of back electrode: Deposit metal on the back of the thinned substrate and pattern it to form a back electrode, which is electrically connected to the front electrode.

[0092] Exemplarily, a CEM device is selected, and the grinding pressure is set to 10-50 kPa and the speed is set to 10-50 m / min. The back side of the substrate is ground and thinned, and then multiple layers of metal TiNiAg or TiNiSnCuAg are deposited to form a back electrode with a thickness of 2-10 um.

[0093] S630: Interconnection and packaging. Connect the front electrode and the back electrode through bonding or other interconnection technology to complete the electrical interconnection and packaging of the TVS diode. Figure 7 TVS diode shown.

[0094] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0095] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0096] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0097] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features of the present invention.

[0098] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for forming a PN junction of a large through-current TVS diode, characterized in that: include: Select a doped silicon substrate, first oxidize the substrate surface by thermal oxidation or chemical vapor deposition, and then develop a trench top view of different shapes by photolithography; Through the etching process, the required trench is etched on the substrate; Through a deposition process, doped polysilicon that is inversely proportional to the substrate is filled into the trench and sealed; Reversely etch the doped polysilicon to keep only the poly at the trench lead-out position, and then diffuse the junction at high temperature to meet the required junction voltage performance; Through a deposition process, an oxide layer is deposited as a through-hole dielectric layer, and a through hole is opened at the trenchpoly position through a photolithography and etching process; Through the deposition process, metal is deposited on the dielectric layer to form a front electrode, and the back side of the substrate is ground and thinned, and multiple layers of metal are deposited to form a back electrode.

2. The method for forming a PN junction of a large through-current TVS diode according to claim 1, characterized in that: The doped silicon substrate is selected <100> or <111> A doped silicon substrate with a crystalline orientation forms an oxide layer of 100-10000A on the surface of the doped silicon substrate.

3. The method for forming a PN junction of a large current-carrying TVS diode according to claim 1, characterized in that: The trench top view shapes of different shapes include rectangle, square, circle, ellipse or polygon.

4. The method for forming a PN junction of a large through-current TVS diode according to claim 3, characterized in that: The process of forming trench top view shapes of different shapes is: uniformly coating photoresist on the surface of the substrate, and developing trench top view shapes of different shapes on the oxide layer through exposure and development operations; wherein the photoresist is uniformly coated on the surface of the oxide layer by wheel coating or spraying.

5. The method for forming a PN junction of a large through-current TVS diode according to claim 1, characterized in that: The etching process is selected from dry etching or wet etching; after the etching process is completed, the oxide layer is removed, wherein the oxide layer is removed by chemical etching or dry etching.

6. The method for forming a PN junction of a large current-carrying TVS diode according to claim 1, characterized in that: The deposition process includes chemical vapor deposition and physical vapor deposition, the sealing method adopts chemical vapor deposition sealing or uses silicon dioxide or silicon nitride as sealing material in chemical vapor deposition sealing, and deposits by using silane and oxygen as reaction gases; Physical vapor deposition sealing or reactive sputtering in physical vapor deposition sealing uses silicon dioxide as a target for deposition.

7. The method for forming a PN junction of a large through-current TVS diode according to claim 1, characterized in that: The front electrode is formed by depositing metal on the through hole and the surface of the doped silicon substrate and patterning the metal to form the front electrode; The back electrode is formed by depositing metal on the back of the thinned substrate and patterning it to form the back electrode; The front electrode and the back electrode are connected by bonding or other interconnection techniques.

8. A method for forming a PN junction of a large through-current TVS diode according to any one of claims 1 to 7, characterized in that: The conditions satisfied by the trench are: the sum of the side areas between the two trenches is greater than the bottom area of ​​the active area between the trenches, so as to ensure that the sum of the areas of each trench is greater than the area of ​​all trenches as a whole; the spacing between the two trenches must ensure that the diffusion areas formed after high-temperature diffusion do not hold hands and there is still a gap.

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