IGBT device based on PNP triode and preparation method thereof

Abstract

The invention discloses an IGBT device based on a PNP triode and a preparation method thereof. The IGBT device comprises a P+ injection layer, an N-type substrate, a first insulating layer, a first conductive layer, a second insulating layer and a second conductive layer, an IGBT collector is constructed on the P+ injection layer, an N-drift region is formed on the N-type substrate, two P-type wells are formed on the N-drift region, an N+ region is formed on the P-type well, a P+ region is formed on one of the N+ regions, an IGBT emitter, an IGBT gate, a PNP collector, a PNP base and a PNP emitter are constructed on the second conductive layer, the IGBT emitter is connected to the two N+ regions on a P-type well, the IGBT gate is connected to the PNP collector and to the first conductive layer, the PNP collector is connected to another P-type well, the PNP base is connected to the N+ region on another P-type well, and the PNP emitter is connected to the P+ region.

Description

Technical Field

[0001] The present invention relates to the technical field of IGBT devices, and in particular to an IGBT device based on a PNP triode and a method for preparing the IGBT device. Background Art

[0002] IGBT refers to Insulated Gate Bipolar Transistor, which is a semiconductor device that combines the advantages of field effect transistor (FET) and bipolar transistor (BJT). The structure of IGBT is similar to a combination of a MOSFET and a BJT. There is a P+ layer on the N-type substrate to form a PNP structure, and then a MOSFET structure is built on it. IGBT devices are usually used in a variety of high-voltage and high-current applications such as motors, inverters, PFC, etc. IGBT plays a vital role in the field of power electronics and motor control. It provides efficient power conversion and control capabilities, especially in high-power applications. With the development of technology, IGBT is also constantly improving to improve its performance, reduce switching losses and enhance heat resistance. The electromagnetic waves generated by semiconductor devices such as IGBT during operation may cause interference to other electronic devices or systems, namely EMI (electromagnetic interference). This interference can be conductive (conducted through wires or circuits) or radiative (transmitted through the air). Therefore, controlling and reducing EMI is an important topic. In the field of IGBT, large EMI (electromagnetic interference) can lead to many defects, such as signal interference, increased power loss, reduced reliability, electromagnetic compatibility issues, noise, interference in the control system, voltage spikes and overvoltage. The main reason for poor EMI is the rapid change of current during the IGBT switching process, that is, the di / dt (instantaneous current change) is too large. Therefore, it is urgent to improve the existing IGBT devices to solve the problem of large EMI generated during the IGBT switching process. Summary of the invention

[0003] In order to solve the above technical problems, the purpose of the present invention is to provide an IGBT device based on a PNP triode and a method for preparing the IGBT device, so as to reduce the electromagnetic interference generated during the IGBT switching process.

[0004] To this end, on the one hand, the present invention provides an IGBT device based on a PNP triode, comprising a P+ injection layer, an N-type substrate, a first insulating layer, a first conductive layer, a second insulating layer and a second conductive layer arranged from bottom to top, an IGBT collector is constructed on the P+ injection layer, an N-drift region is formed on the N-drift region, a first P-type well and a second P-type well are formed on the N-drift region, two N+ regions are formed on the first P-type well, an N+ region is formed on the second P-type well and a P+ region is formed on the N+ region, the first conductive layer is constructed with a first conductive portion, and the second conductive layer is constructed with a first conductive portion. An IGBT emitter, an IGBT gate, a PNP collector, a PNP base and a PNP emitter are constructed, wherein the IGBT emitter is connected to the two N+ regions on the first P-type well through the second insulating layer, the IGBT gate is connected to the PNP collector and is connected to the first conductive portion through the second insulating layer, the PNP collector is connected to the second P-type well through the second insulating layer, the PNP base is connected to the N+ region on the second P-type well through the second insulating layer, and the PNP emitter is connected to the P+ region through the second insulating layer.

[0005] According to an embodiment of the present invention, the invention further includes a FS layer formed between the P+ injection layer and the N-drift region, wherein the thickness of the FS layer is between 0.2 μm and 2 μm.

[0006] According to an embodiment of the present invention, the first conductive portion is formed on an upper surface of an N-drift region between the first P-type well and the second P-type well.

[0007] According to an embodiment of the present invention, the PNP collector and the IGBT gate are formed integrally.

[0008] According to one embodiment of the present invention, the thickness of the P+ injection layer is between 0.01μm and 0.5μm, the depth of the first P-type well and the depth of the second P-type well are both between 0.1μm and 2μm, the depth of the N+ region is between 50nm and 200nm, and the depth of the P+ region is between 30nm and 100nm and is less than the depth of the N+ region.

[0009] According to an embodiment of the present invention, both the first insulating layer and the second insulating layer are made of silicon dioxide material, and the first conductive portion is made of polysilicon material.

[0010] According to an embodiment of the present invention, the thickness of the first conductive layer is between 50 nm and 500 nm, and the thickness of the first insulating layer is between 10 nm and 100 nm.

[0011] On the other hand, the present invention also provides a method for preparing an IGBT device based on a PNP transistor, comprising the following steps: S1. providing an N-type substrate, forming an N-drift region on the N-type substrate, and forming a first P-type well and a second P-type well on the N-drift region; S2. depositing an insulating material on the upper surface of the N-drift region to form a first insulating layer, and depositing a conductive material on the first insulating layer to form a first conductive layer, wherein the first conductive layer is configured with a first conductive portion; S3. forming two N+ regions on the first P-type well, forming an N+ region on the second P-type well and forming a P+ region on the N+ region; S4. depositing an insulating material on the upper surface of the N-drift region to form a second insulating layer covering the first conductive layer; S5. depositing a conductive material on the second insulating layer to form a second conductive layer covering the first conductive layer; The insulating layer is etched to form a plurality of holes penetrating the second insulating layer, wherein a portion of the holes extend to the two N+ regions of the first P-type well, a portion of the holes extend to the first conductive portion and the second P-type well, a portion of the holes extend to the N+ region of the second P-type well, and another portion of the holes extend to the P+ region; S6. A conductive material is deposited on the second insulating layer to fill the plurality of holes with the conductive material to form an IGBT emitter, an IGBT gate, a PNP collector connected to the IGBT gate, a PNP base and a PNP emitter; S7. A P+ injection layer is formed on the lower surface of the N-type substrate, and an IGBT collector is formed on the P+ injection layer, and finally an IGBT device based on a PNP triode is prepared.

[0012] According to one embodiment of the present invention, in step S2, the insulating material is one of silicon dioxide, silicon oxynitride, aluminum nitride, and hafnium oxide, and the conductive material is one of polysilicon, aluminum, copper, tungsten, titanium, and platinum, or any two or more thereof.

[0013] According to an embodiment of the present invention, in the step S7, a FS layer is formed on the lower surface of the N-type substrate, and then the P+ injection layer is formed on the lower surface of the FS layer.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] When the di / dt (instantaneous current change) is large during the IGBT switching process, a PNP transistor is set between the IGBT driver IC and the IGBT gate, and its threshold voltage is set to about 4V. When the di / dt generated by the IGBT device switching is large, the IGBT emitter stray inductance will produce a voltage drop, which is connected to the base and emitter ends of the PNP transistor. The higher the base voltage of the PNP transistor, the greater the RDSON (on-resistance) of the PNP transistor itself. The larger the RDSON, the greater the IGBT gate drive resistance, reducing the IGBT drive current, and reducing the IGBT turn-on speed, thereby reducing di / dt to improve EMI.

[0016] It can ensure the stable operation of equipment, make the electronic system more stable, extend the product life and improve the product market competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flow chart of a method for preparing an IGBT device based on a PNP triode according to an embodiment of the present invention;

[0018] Figure 2 is in accordance with Figure 1 Schematic diagram of the structure of an IGBT device based on a PNP triode prepared by the preparation method shown in ;

[0019] Figure 3 The schematic diagram is a circuit diagram of an IGBT device based on a PNP triode according to an embodiment of the present invention.

[0020] The reference numerals are as follows:

[0021] 10. N-type substrate; 11. N-drift region; 12. first P-type well; 13. second P-type well; 14. N+ region; 15. P+ region;

[0022] 20. a first insulating layer;

[0023] 31. a first conductive portion;

[0024] 40. A second insulating layer;

[0025] 50, second conductive layer; 51, IGBT emitter; 52, IGBT gate; 53, PNP base; 54, PNP emitter;

[0026] 60. P+ injection layer; 61. IGBT collector;

[0027] 70. FS layer. DETAILED DESCRIPTION

[0028] It is easy to understand that according to the technical solution of the present invention, without changing the essential spirit of the present invention, a person skilled in the art can propose a variety of interchangeable structural modes and implementation modes. Therefore, the following specific implementation modes and drawings are only exemplary descriptions of the technical solution of the present invention, and should not be regarded as the whole of the present invention or as a limitation or restriction to the technical solution of the present invention.

[0029] In the description of the present invention, it should be noted that, unless otherwise clearly stipulated and limited, the directions or positional relationships indicated by terms such as center, up, down, front, back, left, right, vertical, horizontal, top, bottom, inside, outside, etc. are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0030] In the description of the present invention, it should be noted that, unless otherwise expressly specified and limited, the terms first and second are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as first and second may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, the meaning of multiple is two or more.

[0031] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms installation, connection, and connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] according to Figure 1As shown, an embodiment of the present invention provides a method for preparing an IGBT device based on a PNP transistor, and the process steps are as follows: S1. Provide an N-type substrate 10, form an N-drift region 11 on the N-drift region 11, and form a first P-type well 12 and a second P-type well 13 on the N-drift region 11; S2. Deposit an insulating material on the upper surface of the N-drift region 11 to form a first insulating layer 20, and deposit a conductive material on the first insulating layer 20 to form a first conductive layer, wherein the first conductive layer is configured with a first conductive portion 31; S3. Form two N+ regions 14 on the first P-type well 12, form an N+ region 14 on the second P-type well 13, and form a P+ region 15 on the N+ region 14; S4. Deposit an insulating material on the upper surface of the N-drift region 11 to form a second insulating layer 40 covering the first conductive layer; S5. The insulating layer 40 is etched to form a plurality of holes penetrating the second insulating layer 40, wherein a portion of the holes extend to the two N+ regions 14 of the first P-type well 12, a portion of the holes extend to the first conductive portion 31 and the second P-type well 13, a portion of the holes extend to the N+ region 14 of the second P-type well 13, and another portion of the holes extend to the P+ region 15; S6. A conductive material is deposited on the second insulating layer 40 to fill the plurality of holes with the conductive material to form a second conductive layer 50, forming an IGBT emitter 51, an IGBT gate 52, a PNP collector connected to the IGBT gate, a PNP base 53 and a PNP emitter 54; S7. A P+ injection layer 60 is formed on the lower surface of the N-type substrate 10, and an IGBT collector 61 is formed on the P+ injection layer, and finally an IGBT device based on a PNP triode is prepared.

[0033] Specifically, in step S1, an N-type doped silicon wafer is selected as an N-type substrate, cleaned and polished, and the N-type substrate is photolithographically processed to form a mask pattern. A low concentration of N-type impurities is injected into the open area of ​​the mask through an ion deep ion implantation process to form a deep and uniform N-drift region. An annealing process is performed to activate the impurities and adjust the electrical properties of the N-drift region. Thereby providing a high breakdown voltage and a low on-resistance. In some embodiments, multiple ion implantation and annealing steps may be required to form a deeper or more complex N-drift region structure, without specific limitation. Among them, the thickness of the N-type substrate can be selected between 100 μm and 250 μm, and the thickness of the N-drift region can be selected between 30 μm and 60 μm, without specific limitation.

[0034] Further, a photoresist is coated on the N-drift region where the first P-type well is to be formed, and a mask pattern is formed by a photolithography process. The depth of the first P-type well is 1 μm. In some embodiments, the depth of the first P-type well can be designed to be between 0.1 μm and 2 μm, without specific limitation. Then select a suitable P-type impurity, such as boron. Through ion implantation equipment, a high concentration of P-type impurities is injected into the N-drift region. An annealing process is performed at a high temperature (generally around 1000°C) for several seconds to several minutes to activate the injected impurities and adjust the electrical properties of the P-type well (such as resistivity and doping depth). The photoresist and mask are removed by chemical solvent or plasma etching technology to form a first P-type well.

[0035] Furthermore, the above process steps are repeated to form a second P-type well spaced apart from the first P-type well.

[0036] In step S2, the surface of the N-drift region is cleaned to remove pollutants and residues to ensure that the surface is clean. If necessary, the surface can also be polished, without specific restrictions. Then, a photoresist is applied to the area where silicon dioxide needs to be formed, and a mask pattern is formed by a photolithography process. Then, by low-pressure chemical vapor deposition (LPCVD): under low pressure, a gas source such as silicon tetrachloride (SiCl4) or dichlorodihydrogen silicon (SiH2Cl2) is used to react with oxygen (O2) or silicon nitride (N2O) to deposit silicon dioxide, and the temperature is controlled between 400°C and 800°C to form a first insulating layer. In other embodiments, plasma enhanced chemical vapor deposition (PECVD) can also be used: in a plasma environment, a gas source such as silicon tetrachloride (SiCl4) or tetraethoxysilane (TEOS) is used to react with oxygen to deposit silicon dioxide, and the temperature is controlled between 200°C and 400°C, without specific restrictions. Then annealing is performed to improve the quality of the silicon dioxide layer. Finally, the mask and the photoresist are removed by chemical solvent or plasma etching technology to form the required first insulating layer. In other embodiments, the insulating material in step S2 may also be one of silicon oxynitride, aluminum nitride, and hafnium oxide, without specific limitation.

[0037] Further, the surface of the first insulating layer is cleaned to remove pollutants and residues to ensure that the surface is clean. If necessary, the surface can also be polished, without specific limitation. Then, a photoresist is applied to the area where the first conductive layer is to be formed, and a mask pattern is formed by a photolithography process. Then, by LPCVD (low pressure chemical vapor deposition): a gas source such as silane (SiH4) or dichlorodihydrogen silicon (SiH2Cl2) is used to react at low pressure to deposit polysilicon. The temperature is usually between 550°C and 650°C. An annealing process is performed to improve the quality of the polysilicon layer, such as reducing defects and increasing grain size. The annealing temperature is usually between 900°C and 1000°C. In some embodiments, doping is usually required to improve the conductivity of the polysilicon layer. Impurities (such as phosphorus, arsenic or boron) can be introduced during the deposition process by ion implantation or doping gas to form N-type or P-type polysilicon, without specific limitation. Finally, the photoresist and mask are removed using a chemical solvent or plasma etching technology to obtain a first conductive layer having a first conductive portion. The thickness of the first conductive layer is between 50 nm and 500 nm, and the thickness of the first insulating layer is between 10 nm and 100 nm, without specific limitation. In some embodiments, the conductive material is one or any two or more of aluminum, copper, tungsten, titanium, and platinum, without specific limitation.

[0038] In step S3, a photoresist is applied to two P-type wells where an N+ region is to be formed, and a mask pattern is formed by a photolithography process. A suitable N-type impurity is selected, usually phosphorus or arsenic. A high concentration of N-type impurities is injected into the two P-type wells through an ion implantation device. An annealing process is performed, usually at a high temperature (such as about 1000°C) for a few seconds to a few minutes. The injected impurities are activated to become effective dopants. The annealing process can also adjust the electrical properties of the N+ region, such as resistivity and doping depth. The photoresist and mask are removed using a chemical solvent or plasma etching technique to obtain an N+ region. The thickness of the N+ region can be selected between 50nm and 200nm, without specific limitation.

[0039] Further, a photoresist is coated on the N+ region where the P+ region is to be formed, and a mask pattern is formed by a photolithography process. A suitable N-type impurity is selected, usually phosphorus or arsenic. A high concentration of P-type impurities is injected into the N+ region through an ion implantation device. An annealing process is performed, usually at a high temperature (such as about 1000°C) for a few seconds to a few minutes. The injected impurities are activated to become effective dopants. The annealing process can also adjust the electrical properties of the N+ region, such as resistivity and doping depth. The photoresist and mask are removed using a chemical solvent or plasma etching technology to obtain a P+ region. Among them, the depth of the P+ region is less than that of the N+ region and the depth of the P+ region can be selected between 30nm and 100nm, without specific limitation.

[0040] In step S4, the surface of the N-drift region is cleaned to remove contaminants and residues to ensure that the surface is clean. If necessary, the surface may be polished to ensure flatness. Photoresist is applied to the area where the ILD material is required to be formed, and a mask pattern is formed by a photolithography process. PECVD (plasma enhanced chemical vapor deposition): In a plasma environment, a gas source such as silicon tetrachloride (SiCl4) or tetraethoxysilane (TEOS) is reacted with oxygen to deposit silicon dioxide or a low dielectric constant material. The temperature is usually between 200°C and 400°C. In order to ensure the uniformity of the ILD material and reduce the surface roughness, a chemical mechanical polishing (CMP) process may be required. Finally, a chemical solvent or plasma etching technique is used to remove the photoresist and mask to obtain a second insulating layer. In some embodiments, in addition to depositing silicon dioxide, the ILD material may also be fluorinated silicon glass (FSG), a low dielectric constant material (Low-k), etc., without specific limitation.

[0041] In step S5, a photoresist is coated on the second insulating layer where the holes are to be formed, and a mask pattern is formed by a photolithography process. Plasma etching: Use plasma (such as CF4, SF6, CHF3, etc.) to etch the ILD material to construct holes. Among them, a part of the holes extends to the two N+ regions of the first P-type well, a part of the holes extends to the first conductive part and the second P-type well, a part of the holes extends to the N+ region of the second P-type well, and another part of the holes extends to the P+ region. Clean the inner wall of the hole to remove etching residues and contaminants to ensure that the inner wall of the hole is clean.

[0042] In step S6, metal material is deposited in the engraved hole to form a conductive connection. PVD (Physical Vapor Deposition): such as sputtering or evaporation, used to deposit metals such as tungsten (W), titanium (Ti), aluminum (Al), etc. Finally, a chemical solvent or plasma etching technique is used to remove the photoresist and mask to form an IGBT emitter, an IGBT gate, a PNP collector connected to the IGBT gate, a PNP base, and a PNP emitter.

[0043] In step S7, the bottom surface of the N-type substrate is cleaned to remove contaminants and residues to ensure a clean surface. If necessary, surface polishing may be performed to ensure flatness. Photoresist is coated on the bottom surface of the N-type substrate, and a mask pattern is formed by a photolithography process. Suitable N-type impurities, usually phosphorus or arsenic, are selected, and a high concentration of N-type impurities are injected into the bottom surface of the N-type substrate through an ion implantation device, and an annealing process is performed, usually at a high temperature (such as about 1000°C) for a few seconds to a few minutes. The photoresist and mask are removed using a chemical solvent or plasma etching technology to form a FS layer 70. The thickness of the FS layer is between 0.2μm and 2μm. In some embodiments, the step of forming the FS layer is not necessary and is not specifically limited.

[0044] Furthermore, a photoresist is coated on the bottom surface of the FS layer where a P+ injection layer is to be formed, and a mask pattern is formed by a photolithography process. A suitable P-type impurity, usually boron, is selected, and a high concentration of P-type impurities is injected into the bottom surface of the FS layer through an ion implantation device, and an annealing process is performed, usually at a high temperature (such as about 1000°C) for a few seconds to a few minutes. A chemical solvent or plasma etching technique is used to remove the photoresist and mask to form a P+ injection layer. The thickness of the P+ injection layer is between 0.01μm and 0.5μm.

[0045] Finally, a suitable metal material is selected, such as aluminum (Al), tungsten (W), titanium (Ti), etc., and a suitable adhesion layer (such as titanium or tantalum nitride) is usually selected to improve the adhesion between the metal and silicon. A layer of metal is deposited on the P+ layer by physical vapor deposition (PVD) such as sputtering or chemical vapor deposition (CVD) to form the IGBT collector. Finally, an IGBT device based on a PNP triode is prepared.

[0046] according to Figure 2As shown, according to the above preparation method, an IGBT device based on a PNP triode is finally prepared, which includes a P+ injection layer 60, an N-type substrate 10, a first insulating layer 20, a first conductive layer, a second insulating layer 40 and a second conductive layer 50 arranged from bottom to top, an IGBT collector 61 is constructed on the P+ injection layer 60, an N-drift region 11 is formed on the N-drift region 11, a first P-type well 12 and a second P-type well 13 are formed on the N-drift region 11, two N+ regions 14 are formed on the first P-type well 12, an N+ region 14 is formed on the second P-type well 13 and a P+ region 15 is formed on the N+ region 14, and the first conductive layer is constructed with a first conductive layer. The first conductive portion 31 is formed on the upper surface of the N-drift region 11 between the first P-type well 12 and the second P-type well 13. The second conductive layer 50 is constructed with an IGBT emitter 51, an IGBT gate 52, a PNP collector, a PNP base 53 and a PNP emitter 54. The IGBT emitter 51 is connected to the two N+ regions 14 on the first P-type well 12 through the second insulating layer 40. The IGBT gate is connected to the PNP collector and connected to the first conductive portion 31 through the second insulating layer 40. The PNP collector is connected to the second P-type well 13 through the second insulating layer 40. The PNP base 53 is connected to the N+ region 14 on the second P-type well 13 through the second insulating layer 40. The PNP emitter 54 is connected to the P+ region 15 through the second insulating layer 40. The first conductive portion 31 is formed on the upper surface of the N-drift region 11 between the first P-type well 12 and the second P-type well 13. It should be noted that the PNP collector is formed integrally with the IGBT gate.

[0047] according to Figure 3 As shown in the figure, when the di / dt (instantaneous current change) is large during the IGBT switching process, a PNP transistor is set between the IGBT driver IC and the IGBT gate, and its threshold voltage is set to about 4V. When the di / dt generated by the IGBT device switching is large, the IGBT emitter stray inductance will produce a voltage drop, which will increase the conduction voltage drop of the PNP transistor, thereby increasing the RDSON (on-resistance) of the PNP transistor itself. The increase in RDSON will increase the gate drive resistance, reduce the IGBT drive current, reduce the IGBT turn-on speed, and thus reduce di / dt to improve EMI.

[0048] Taking the 650V50A IGBT TO247 package as an example, the di / dt when the IGBT is turned on is 695A / us, and the internal integrated inductor of TO247 is about 13nH. When di / dt occurs, a voltage drop of 9V is generated, which means that the base voltage of the PNP transistor rises from 0V to 9V when it is turned on, which will reduce the base current of the PNP transistor and increase RDSON, thereby increasing the IGBT drive resistance and reducing the di / dt of the IGBT switching process.

[0049] It can ensure the stable operation of equipment, make the electronic system more stable, extend the product life and improve the product market competitiveness.

[0050] The technical scope of the present invention is not limited to the contents in the above description. Those skilled in the art can make various deformations and modifications to the above embodiments without departing from the technical idea of ​​the present invention, and these deformations and modifications should all fall within the protection scope of the present invention.

Claims

1. An IGBT device based on a PNP triode, characterized in that: The invention comprises a P+ injection layer, an N-type substrate, a first insulating layer, a first conductive layer, a second insulating layer and a second conductive layer arranged from bottom to top, wherein an IGBT collector is constructed on the P+ injection layer, an N-drift region is formed on the N-drift region, a first P-type well and a second P-type well are formed on the N-drift region, two N+ regions are formed on the first P-type well, an N+ region is formed on the second P-type well and a P+ region is formed on the N+ region, the first conductive layer is constructed with a first conductive portion, the second conductive layer is constructed with an IGBT emitter, an IGBT A gate, a PNP collector, a PNP base and a PNP emitter, the IGBT emitter is connected to the two N+ regions on the first P-type well through the second insulating layer, the IGBT gate is connected to the PNP collector and is connected to the first conductive portion through the second insulating layer, the PNP collector is connected to the second P-type well through the second insulating layer, the PNP base is connected to the N+ region on the second P-type well through the second insulating layer, and the PNP emitter is connected to the P+ region through the second insulating layer.

2. The IGBT device based on the PNP triode according to claim 1, characterized in that: The invention also includes a FS layer formed between the P+ injection layer and the N-drift region, wherein the thickness of the FS layer is between 0.2 μm and 2 μm.

3. The IGBT device based on the PNP triode according to claim 1, characterized in that: The first conductive portion is formed on an upper surface of an N-drift region between the first P-type well and the second P-type well.

4. The IGBT device based on the PNP triode according to claim 1, characterized in that: The PNP collector is formed integrally with the IGBT gate.

5. The IGBT device based on the PNP triode according to claim 1, characterized in that: The thickness of the P+ injection layer is between 0.01μm and 0.5μm, the depth of the first P-type well and the depth of the second P-type well are both between 0.1μm and 2μm, the depth of the N+ region is between 50nm and 200nm, and the depth of the P+ region is between 30nm and 100nm and is less than the depth of the N+ region.

6. The IGBT device based on the PNP triode according to claim 1, characterized in that: The first insulating layer and the second insulating layer are both made of silicon dioxide material, and the first conductive portion is made of polysilicon material.

7. The IGBT device based on the PNP triode according to claim 1, characterized in that: The thickness of the first conductive layer is between 50 nm and 500 nm, and the thickness of the first insulating layer is between 10 nm and 100 nm.

8. A method for preparing an IGBT device based on a PNP triode, characterized in that: The following steps are involved: S1. Providing an N-type substrate, forming an N-drift region on the N-type substrate, and forming a first P-type well and a second P-type well on the N-drift region; S2. depositing an insulating material on the upper surface of the N-drift region to form a first insulating layer, and depositing a conductive material on the first insulating layer to form a first conductive layer, wherein the first conductive layer is configured with a first conductive portion; S3. forming two N+ regions on the first P-type well, forming an N+ region on the second P-type well and forming a P+ region on the N+ region; S4. Depositing an insulating material on the upper surface of the N-drift region to form a second insulating layer covering the first conductive layer; S5. Etching the second insulating layer to form a plurality of holes penetrating the second insulating layer, wherein a portion of the holes extend to the two N+ regions of the first P-type well, a portion of the holes extend to the first conductive portion and the second P-type well, a portion of the holes extend to the N+ region of the second P-type well, and another portion of the holes extend to the P+ region; S6. depositing a conductive material on the second insulating layer to fill the plurality of holes with the conductive material to form an IGBT emitter, an IGBT gate, a PNP collector connected to the IGBT gate, a PNP base and a PNP emitter; S7. A P+ injection layer is formed on the lower surface of the N-type substrate, and an IGBT collector is formed on the P+ injection layer, and finally an IGBT device based on a PNP triode is prepared.

9. The method according to claim 8, characterized in that: In step S2, the insulating material is one of silicon dioxide, silicon oxynitride, aluminum nitride, and hafnium oxide, and the conductive material is one of polysilicon, aluminum, copper, tungsten, titanium, and platinum, or any two or more thereof.

10. The method according to claim 8, characterized in that: In the step S7, a FS layer is formed on the lower surface of the N-type substrate, and then the P+ injection layer is formed on the lower surface of the FS layer.

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