Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a semiconductor substrate with a gate region, dielectric layers and a field plate structure, the dielectric layers comprise a first dielectric layer, a second dielectric layer and a third dielectric layer which are stacked in sequence, a first contact hole and a second contact hole are formed in the dielectric layers, the first dielectric layer covers the gate region, and the second dielectric layer covers the field plate structure. The field plate structure comprises a first field plate region formed on the first dielectric layer and a second field plate region formed on the second dielectric layer, the first field plate region comprises a first field plate layer, a first contact hole penetrates through the second dielectric layer and the third dielectric layer to expose the first field plate layer, and the second field plate region comprises a second field plate layer and a second buffer layer; the third contact hole penetrates through the third dielectric layer, and the second buffer layer exposes the second field plate layer. By arranging the second buffer layer, the etching time difference caused by different position heights can be compensated when the contact hole is formed, the problems of over-etching, under-etching and the like are avoided, the etching difficulty is reduced, and the degree of freedom and realizability of the height design of the field plate of the device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Gallium nitride high electron mobility transistor (GaN HEMT) devices have the unique physical properties of wide bandgap materials, and have excellent characteristics such as high breakdown field strength, low on-resistance, and fast electron saturation drift speed compared to silicon power devices, which can significantly improve conversion efficiency and reduce energy loss in power systems. They are widely used in wireless communications, automobiles, radars, power grid transmission, and aerospace. With the development of semiconductor technology, higher requirements are placed on the performance of semiconductor devices. In order to improve power characteristics, gallium nitride devices are required to have good breakdown characteristics. The use of field plate technology can effectively improve the breakdown voltage of GaN power devices, thereby ensuring the reliability and durability of the devices.

[0003] In the prior art, in order to further ensure the effect of the field plate on improving the withstand voltage of GaN power devices, a multi-layer field plate structure is often used. When the GaN power devices are metal-interconnected, due to the large difference in the spatial height between the first layer of field plates and the top layer of field plates, when etching the dielectric layer to obtain contact holes, the top layer of field plates are often over-etched or the bottom layer of field plates are under-etched, resulting in the field plate layer failing to achieve the designed effect, reducing the performance of GaN power devices, and limiting the design flexibility of devices with multi-layer field plates. Therefore, a new semiconductor device and a preparation method thereof are urgently needed to solve the above technical problems. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a semiconductor device and a method for preparing the same, so as to solve the problem of over-etching or under-etching of the field plate when forming contact holes in the prior art, which can effectively reduce the contact resistance, reduce the etching difficulty, and improve the device performance.

[0005] In order to achieve the above-mentioned object and other related objects, the present application provides a semiconductor device, comprising:

[0006] A semiconductor substrate, comprising a substrate, a base layer stacked on the substrate along a first direction, and a gate region formed on the base layer;

[0007] a dielectric layer, formed on the base layer, comprising a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence along the first direction, wherein the first dielectric layer covers the gate region, and a vertical through hole, a first contact hole and a second contact hole are provided in the dielectric layer, wherein the vertical through hole penetrates the first dielectric layer and the second dielectric layer and exposes the gate region;

[0008] The field plate structure is located in the dielectric layer and includes a first field plate region and a second field plate region; wherein,

[0009] The first field plate region is formed on the first dielectric layer, the second dielectric layer covers the first field plate region, the first field plate region includes a first field plate layer, and the first contact hole penetrates the second dielectric layer and the third dielectric layer and exposes the first field plate layer;

[0010] The second field plate region is formed on the second dielectric layer and is located on a side of the first field plate region away from the semiconductor substrate, and includes a second field plate layer and a second buffer layer. The second field plate layer contacts the gate region through the vertical through hole, the second buffer layer is located between the second field plate layer and the third dielectric layer, and the second contact hole penetrates the third dielectric layer and the second buffer layer to expose the second field plate layer.

[0011] Optionally, the thickness d2 of the second buffer layer satisfies the following relationship d2 / v2=(h2+L 12 ) / v0;

[0012] Wherein, v0 and v2 are the etching rates of the dielectric layer and the second buffer layer respectively, h2 is the thickness of the second field plate region, L 12 is the distance between the first field plate region and the second field plate region along the first direction.

[0013] Optionally, the first field plate region further includes a first buffer layer, the first buffer layer is located between the first field plate layer and the second dielectric layer, the first contact hole penetrates the third dielectric layer, the second dielectric layer and the first buffer layer to expose the first field plate layer, and the thickness of the second buffer layer is greater than the thickness of the first buffer layer.

[0014] Optionally, the thickness of the first buffer layer is less than 30 nm, and the thickness of the second buffer layer is 40 nm to 60 nm.

[0015] Optionally, the dielectric layer further includes fourth to N+1th dielectric layers formed on the third dielectric layer and sequentially stacked along the first direction; wherein N is a positive integer greater than 3;

[0016] The field plate structure further includes third to Nth field plate regions, wherein in the third to Nth field plate regions, the i-th field plate region is formed on the i-th dielectric layer, and the i+1-th dielectric layer covers the i-th field plate region, wherein i is a positive integer greater than 2 and less than N+1;

[0017] The i-th field plate region includes an i-th field plate layer and an i-th buffer layer, and the i-th buffer layer is located between the i+1-th dielectric layer and the i-th field plate layer;

[0018] The dielectric layer is also provided with third to Nth contact holes, wherein the i-th contact hole penetrates the i-th buffer layer and the i+1-th to N+1-th dielectric layers and exposes the i-th field plate layer.

[0019] Optionally, the thickness of the i-th buffer layer is greater than or equal to the thickness of the (i-1)-th buffer layer.

[0020] Optionally, the semiconductor substrate further includes a drain region and a source region formed on the substrate layer, the gate region is located between the source region and the drain region, and when looking down at the semiconductor device along the first direction, the field plate structure is located between the gate region and the drain region.

[0021] This embodiment also provides a method for manufacturing a semiconductor device, which is used to manufacture any semiconductor device in the aforementioned embodiments, and includes the following steps:

[0022] Providing a semiconductor substrate, the semiconductor substrate comprising a substrate, a base layer stacked on the substrate along a first direction, and a gate region formed on the base layer;

[0023] forming a first dielectric layer on the base layer; wherein the first dielectric layer covers the gate region;

[0024] Depositing a first field plate layer on the surface of the first dielectric layer, and performing photolithography molding;

[0025] forming a second dielectric layer covering the first field plate layer on the first dielectric layer, and etching the second dielectric layer to form a vertical through hole exposing the gate region;

[0026] A second field plate layer and a second buffer layer are sequentially deposited on the surface of the second dielectric layer, and photolithography is performed, and the second field plate layer is in contact with the gate region through the vertical through hole;

[0027] forming a third dielectric layer on the second dielectric layer and covering the second buffer layer;

[0028] The dielectric layer is etched to form a first contact hole exposing the first field plate layer and a second contact hole exposing the second field plate layer.

[0029] Optionally, after the first field plate layer is deposited on the surface of the first dielectric layer, the method further comprises the following steps:

[0030] A first buffer layer is deposited on the first field plate layer; wherein the thickness of the second buffer layer is greater than the thickness of the first buffer layer, and the etching rate of the second buffer layer is less than the etching rate of the dielectric layer, and is less than or equal to the etching rate of the first buffer layer.

[0031] Optionally, after forming a third dielectric layer covering the second buffer layer on the second dielectric layer, the method further includes the following steps:

[0032] Depositing the i-th field plate layer and the i-th buffer layer on the surface of the i-th dielectric layer in sequence, and performing photolithography molding;

[0033] forming an (i+1)th dielectric layer covering the (i)th buffer layer on the (i)th dielectric layer;

[0034] i is sequentially set to a positive integer from 3 to N+1, and the above steps are repeated until the N+1th dielectric layer is formed;

[0035] Etching the dielectric layer to form third to Nth contact holes respectively;

[0036] Wherein, N is a positive integer greater than 3, and the i-th contact hole exposes the i-th field plate layer, and the etching rate of the i-th buffer layer is less than or equal to the etching rate of the i-1-th buffer layer.

[0037] The semiconductor device and the method for manufacturing the same provided by the present application have at least the following beneficial effects:

[0038] In the semiconductor device of the present application, by arranging a second buffer layer on the second field plate layer, the difference in etching time caused by the different positions can be compensated when forming the first contact hole and the second contact hole, thereby preventing the occurrence of problems such as over-etching and under-etching of the field plate structure, and reducing the etching difficulty and contact resistance; by forming the first buffer layer on the first field plate layer, in cooperation with the second buffer layer, the controllability of the contact hole etching time is further improved; by arranging multiple field plate layers spaced along the first direction, the voltage resistance of the device can be improved, and by controlling the thickness and etching rate of each buffer layer, the controllability of the etching time of each contact hole is further enhanced, so that the etching effect is easier to meet the design requirements, and at the same time, the freedom and feasibility of the device field plate height design are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 Shown is a schematic diagram of the structure of a semiconductor device provided in Example 1 of the present application.

[0041] Figure 2 Shown is a schematic structural diagram of a semiconductor device provided as an optional embodiment in Embodiment 1 of the present application.

[0042] Figure 3 Shown is a schematic diagram of the structure of a semiconductor device provided in Example 2 of the present application.

[0043] Figure 4 Shown is a schematic flow chart of a method for preparing a semiconductor device provided in Example 3 of the present application.

[0044] Figure 5 Display as Figure 4 A schematic structural diagram of a semiconductor substrate in the method shown.

[0045] Figure 6 Display as Figure 4 A schematic structural diagram of forming a first dielectric layer in the method shown.

[0046] Figure 7 Display as Figure 4 A schematic structural diagram of forming a first field plate layer in the method shown.

[0047] Figure 8 Shown is a schematic diagram of the structure of forming a first buffer layer provided in Example 3 of the present application.

[0048] Fig. 9 Shown is a schematic diagram of the structure of forming a second dielectric layer provided in Example 3 of the present application.

[0049] Fig.10 It is a schematic structural diagram of forming a second field plate region on a second dielectric layer provided in the third embodiment of the present application.

[0050] Fig.11 Shown is a schematic diagram of the structure of forming a third dielectric layer provided in the third embodiment of the present application.

[0051] Fig.12 Shown is a schematic diagram of a process of forming a multi-layer field plate region provided in an optional embodiment of the third embodiment of the present application.

[0052] Fig.13 Shown is a schematic structural diagram of forming a third field plate region provided in an optional embodiment of the third embodiment of the present application.

[0053] Fig.14 Shown is a schematic structural diagram of forming a fourth dielectric layer provided in an optional embodiment of the third embodiment of the present application.

[0054] Reference numerals:

[0055] 11. semiconductor substrate; 111. substrate; 112. substrate layer; 1120. substrate buffer layer; 1121. first nitride layer; 1122. second nitride layer; 113. gate region; 1131. third nitride layer; 1132. gate metal layer; 114. drain region; 115. source region; 12. dielectric layer; 121. first dielectric layer; 1211. first contact hole; 122. second dielectric layer; 1221. third nitride layer; 1132. gate metal layer; 114. drain region; 115. source region; 12. dielectric layer; 121. first dielectric layer; 1211. first contact hole; 122. second dielectric layer; 1221. third nitride layer; 1132. Two contact holes; 1222, vertical through hole; 123, third dielectric layer; 1231, third contact hole; 124, fourth dielectric layer; 13, field plate structure; 131, first field plate region; 1311, first field plate layer; 1312, first buffer layer; 132, second field plate region; 1321, second field plate layer; 1322, second buffer layer; 133, third field plate region; 1331, third field plate layer; 1332, third buffer layer. DETAILED DESCRIPTION

[0056] In order to make the technical purpose, technical solution and technical effect of the present application clearer, the technical solution in the present application will be clearly and completely described in conjunction with the embodiments below. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of the present application is not intended to limit the scope of the present application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0058] In the description of the present application, it should be noted that the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more implementations or examples in a suitable manner.

[0059] Embodiment 1

[0060] This embodiment provides a semiconductor device for solving the problem of over-etching or under-etching of the field plate when forming a contact hole in the prior art. Figure 1 The semiconductor device provided in this embodiment includes a semiconductor substrate 11 , a dielectric layer 12 , and a field plate structure 13 disposed in the dielectric layer 12 .

[0061] The semiconductor substrate 11 includes a substrate 111 and a base layer 112, and a gate region 113 formed on the base layer 112. The base layer 112 is formed on the substrate 111 along a first direction, that is, the first direction is perpendicular to the substrate 111 and points to the base layer 112. Optionally, the semiconductor substrate 11 also includes a drain region 114 and a source region 115, the gate region 113 is located between the source region 115 and the drain region 114, and the field plate structure 13 is arranged between the gate region 113 and the drain region 114 when the semiconductor device is viewed from above along the first direction.

[0062] In an alternative embodiment, reference Figure 2 The base layer 112 includes a first nitride layer 1121 and a second nitride layer 1122 stacked in sequence along a first direction, and a heterojunction is formed between the first nitride layer 1121 and the second nitride layer 1122; the gate region 113 is formed on the second nitride layer 1122, and includes a third nitride layer 1131 and a gate metal layer 1132; optionally, a base buffer layer 1120 is further provided between the first nitride layer 1121 and the substrate 111; further, the first nitride layer 1121 is a gallium nitride layer, the second nitride layer 1122 is an aluminum gallium nitride layer, and the third nitride layer 1131 is a P-type gallium nitride layer.

[0063] The dielectric layer 12 is formed on the base layer 112, including a first dielectric layer 121, a second dielectric layer 122 and a third dielectric layer 123. The first dielectric layer 121, the second dielectric layer 122 and the third dielectric layer 123 are sequentially stacked on the base layer 112 along a first direction, and the first dielectric layer 121 covers the gate region 113. The dielectric layer 12 is provided with a first contact hole 1211 and a second contact hole 1221. The first contact hole 1211 and the second contact hole 1221 extend from the dielectric layer 12 to the field plate structure 13 to realize the electrical extraction of the field plate structure 13. Optionally, a vertical through hole 1222 is further provided in the dielectric layer 12, and the vertical through hole 1222 penetrates the first dielectric layer 121 and the second dielectric layer 122 and exposes the gate region 113. Preferably, the vertical through hole 1222 is located directly above the gate region 113. Furthermore, the first dielectric layer 121 , the second dielectric layer 122 and the third dielectric layer 123 are formed by depositing the same material. For example, the dielectric layer 12 is made of silicon dioxide.

[0064] The field plate structure 13 is disposed in the dielectric layer 12, and includes a first field plate region 131 and a second field plate region 132. The first field plate region 131 is formed on the first dielectric layer 121, and the second dielectric layer 122 covers the first field plate region 131. Optionally, the first field plate region 131 includes a first field plate layer 1311, and the first contact hole 1211 penetrates the second dielectric layer 122 and the third dielectric layer 123 and exposes the first field plate layer 1311. The second field plate region 132 is formed on the second dielectric layer 122 and is located on a side of the first field plate region 131 away from the semiconductor substrate 11. Optionally, the second field plate region 132 includes a second field plate layer 1321 and a second buffer layer 1322. The second field plate layer 1321 contacts the gate region 113 through a vertical through hole 1222. The second buffer layer 1322 is formed on the second field plate layer 1321 and is located between the second field plate layer 1321 and the third dielectric layer 123. The second contact hole 1221 penetrates the third dielectric layer 123 and the second buffer layer 1322 to expose the second field plate layer 1321.

[0065] In an optional embodiment, the material of the first field plate layer 1311 and the second field plate layer 1321 may be, for example, titanium nitride, titanium, aluminum or other suitable materials, or a laminated structure formed by two or more of the above materials. The materials of the first field plate layer 1311 and the second field plate layer 1321 may be the same material or different materials. The structure of the first field plate layer 1311 and the second field plate layer 1321 may be a single-layer structure or a laminated structure, or a single-layer structure and a laminated structure respectively. The material of the second buffer layer 1322 may be, for example, a dielectric material with a relatively slow etching rate such as silicon nitride and aluminum oxide; or a suitable metal material may be used, such as titanium or titanium nitride.

[0066] In this embodiment, by providing the second buffer layer 1322 on the second field plate layer 1321, the etching time caused by the position difference between the first field plate layer 1311 and the second field plate layer 1321 along the first direction can be compensated when forming the first contact hole 1211 and the second contact hole 1221, effectively preventing the over-etching or under-etching problem of the field plate structure 13, reducing the contact resistance, and avoiding adverse effects on device performance. In addition, the second buffer layer 1322 can also avoid the formation of an overly thick second field plate layer 1321, which makes it difficult to climb the slope during subsequent dielectric deposition, thereby causing process problems such as insufficient sidewall dielectric thickness.

[0067] In an optional embodiment, the first field plate region 131 includes a first field plate layer 1311, the second field plate region 132 includes a second field plate layer 1321 and a second buffer layer 1322, the etching rates of the dielectric layer 12 and the second buffer layer 1322 are respectively recorded as v0 and v2, the thickness of the second field plate region 132 is recorded as h2, and the spacing between the first field plate region 131 and the second field plate region 132 along the first direction is recorded as L12 The thickness d2 of the second buffer layer 1322 satisfies the following formula: d2 / v2=(h2+L 12 ) / v0.

[0068] In this embodiment, refer to Figure 2 The first field plate region 131 may also include a first buffer layer 1312, which is formed on the first field plate layer 1311 and is located between the first field plate layer 1311 and the second dielectric layer 122. The first contact hole 1211 penetrates the third dielectric layer 123, the second dielectric layer 122 and the first buffer layer 1312 to expose the first field plate layer 1311. The thickness of the first buffer layer 1312 may be set according to actual design requirements. By providing the first buffer layer 1312 and the second buffer layer 1322, the controllability of the etching time of the first contact hole 1211 and the etching time of the second contact hole 1221 can be further improved during the contact hole etching process, avoiding the problem of over-etching or under-etching of the field plate structure 13, reducing the difficulty of contact hole etching, reducing contact resistance, and improving device performance.

[0069] In an optional embodiment, the second buffer layer 1322 and the first buffer layer 1312 can be made of the same material or different materials. Specifically, the first buffer layer 1312 can be made of a material having an etching rate greater than the etching rate of the dielectric layer 12, or a material having an etching rate less than or equal to the etching rate of the dielectric layer 12. The material of the second buffer layer 1322 is a material having an etching rate less than the etching rate of the dielectric layer 12. Preferably, the first buffer layer 1312 and the second buffer layer 1322 are formed by depositing the same material, for example, the first buffer layer 1312 and the second buffer layer 1322 are both made of silicon nitride. Optionally, the thickness h2 of the second buffer layer 1322 is greater than the thickness h1 of the first buffer layer 1312. Further, the thickness h1 of the first buffer layer 1312 is less than 30 nm, for example, it can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm or other suitable values, and the thickness h2 of the second buffer layer 1322 is 40 nm to 60 nm, for example, it can be 40 nm, 45 nm, 50 nm, 55 nm, 60 nm or other suitable values. By controlling the thickness of the first buffer layer 1312 and the second buffer layer 1322, and making the thickness of the second buffer layer 1322 greater than the thickness of the first buffer layer 1312, the controllability of the etching time of the first contact hole 1211 and the second contact hole 1221 in practical applications can be enhanced, so that the actual effect is easier to meet the design requirements, the etching difficulty is reduced, and the degree of freedom of design of the field plate height of the device is improved.

[0070] In an optional embodiment, the first field plate region 131 includes a first field plate layer 1311 and a first buffer layer 1312, the second field plate region 132 includes a second field plate layer 1321 and a second buffer layer 1322, the etching rates of the dielectric layer 12, the first buffer layer 1312, and the second buffer layer 1322 are respectively recorded as v0, v1, and v2, the thickness of the second field plate region 132 is recorded as h2, and the distance between the first field plate region 131 and the second field plate region 132 along the first direction is recorded as L 12 , the thickness of the first buffer layer 1312 is recorded as d1, and the thickness of the second buffer layer 1322 is d2, which satisfies the following formula: d2 / v2-d1 / v1=(h2+L 12 ) / v0.

[0071] It can be understood that the semiconductor device of this embodiment may also include other structures. For example, the semiconductor device also includes a metal interconnection layer, a passivation layer, a lead electrode, a gate electrode, a drain electrode, a source electrode and other structures. Through holes and contact holes are opened in the dielectric layer 12 and the passivation layer. The through holes and contact holes can be used to achieve electrode interconnection and electrical lead-out. Please refer to the prior art for the specific settings, which will not be repeated in this embodiment.

[0072] The semiconductor device of this embodiment, by setting a first buffer layer 1312 and a second buffer layer 1322 and controlling the thickness of the first buffer layer 1312 and the second buffer layer 1322, can compensate for the etching time of contact holes with different heights on the field plate structure 13, effectively prevent the occurrence of over-etching or under-etching problems of the field plate structure 13, improve the controllability of the contact hole etching time in practical applications, make the etching effect easier to meet the design requirements, reduce the difficulty of etching, reduce the contact resistance, and improve the device performance and the degree of freedom of device field plate height design.

[0073] Embodiment 2

[0074] This embodiment provides another semiconductor device, which also includes a semiconductor substrate 11, a dielectric layer 12 and a field plate structure 13 disposed in the dielectric. The same points as those in the first embodiment are not repeated here. Figure 3 , the difference is that the field plate structure 13 is a multi-layer structure, and also includes a third field plate region 133 to an Nth field plate region, wherein N is a positive integer greater than 3.

[0075] In this embodiment, the dielectric layer 12 also includes a fourth dielectric layer 124 to an N+1th dielectric layer, and the fourth dielectric layer 124 to the N+1th dielectric layer are sequentially stacked on the third dielectric layer 123 along the first direction. Specifically, the dielectric layer 12 includes a first dielectric layer 121 to an N+1th dielectric layer sequentially stacked on the base layer 112 along the first direction.

[0076] The field plate structure 13 also includes a third field plate region 133 to an Nth field plate region. Specifically, in the present embodiment, the field plate structure 13 includes a first field plate region 131 to an Nth field plate region. Among the N field plate regions, the i-th field plate region is formed on the i-th dielectric layer, and the i+1-th dielectric layer covers the i-th field plate region, wherein i is a positive integer greater than 2 and less than N+1; optionally, in the main view of the semiconductor device, the first field plate region 131 to the N-th field plate region are sequentially arranged in intervals along the first direction. Among them, the i-th field plate region includes an i-th field plate layer and an i-th buffer layer, and the i-th buffer layer is formed on the i-th field plate layer and is located between the i-th field plate layer and the i+1-th dielectric layer. The dielectric layer 12 is also provided with a third contact hole 1231 to an N-th contact hole, and among the N contact holes, the i-th contact hole penetrates the i+1-th dielectric layer to the N+1-th dielectric layer and the i-th buffer layer and exposes the i-th field plate layer.

[0077] In an alternative embodiment, reference Figure 3 , N is 3, the dielectric layer 12 includes a first dielectric layer 121, a second dielectric layer 122, a third dielectric layer 123 and a fourth dielectric layer 124 stacked in sequence along a first direction, the field plate structure 13 includes a first field plate region 131, a second field plate region 132 and a third field plate region 133, the third field plate region 133 is formed on the third dielectric layer 123, the fourth dielectric layer 124 covers the third field plate region 133, the third field plate region 133 includes a third field plate layer 1331 and a third buffer layer 1332, the third buffer Layer 1332 is formed on the third field plate layer 1331, and a third contact hole 1231 is also provided in the dielectric layer 12. The first contact hole 122 penetrates the second dielectric layer 122 to the fourth dielectric layer 124 and exposes the first field plate layer 1311. The second contact hole 1221 penetrates the fourth dielectric layer 124, the third dielectric layer 123 and the second buffer layer 1322 and exposes the second field plate layer 1321. The third contact hole 1231 penetrates the fourth dielectric layer 124 and the third buffer layer 1332 and exposes the third field plate layer 1331.

[0078] In the field plate structure 13 of the semiconductor device provided in this embodiment, the thickness of the i-th buffer layer is greater than or equal to the thickness of the i-1-th buffer layer. Each buffer layer can be made of different materials or the same material. Preferably, each buffer layer is made of the same material. By controlling the thickness of each buffer layer, the controllability of the etching time of each contact hole in practical applications can be enhanced. While avoiding the problem of over-etching or under-etching of the field plate structure 13, the etching difficulty is reduced, making it easier to achieve the design requirements. Optionally, the etching rate of the i-th buffer layer is less than or equal to the etching rate of the i-1-th buffer layer. As the i value increases, the thickness of the buffer layer can be reduced by gradually reducing the etching rate, thereby improving the freedom and feasibility of the device field plate height design.

[0079] In an optional embodiment, the first field plate region 131 includes a first field plate layer 1311, and the etching rate of the i-th buffer layer is recorded as v i , let the thickness of the i-th field plate region be h i , the distance between the first field plate region 131 and the i-th field plate region along the first direction is recorded as L 1i , the thickness of the i-th buffer layer d i Satisfy i / v i =(h i +L 1i ) / v0. Optionally, N is 3, and the thickness d3 of the third buffer layer 1332 satisfies d3 / v3=(h3+L 13 ) / v0.

[0080] In an optional embodiment, the first field plate region 131 includes a first field plate layer 1311 and a first buffer layer 1312. The etching rate of the first buffer layer 1312 is recorded as v1, and the thickness d of the i-th buffer layer is i Satisfies the following formula: d i / v i —d1 / v1=(h i +L 1i ) / v0. Optionally, N is 3, and the thickness d3 of the third buffer layer 1332 satisfies the following formula: d3 / v3-d1 / v1=(h3+L 13 ) / v0.

[0081] In an optional embodiment, N is taken as 3, the first field plate region 131 includes a first field plate layer 1311 and a first buffer layer 1312, the thickness of the first field plate layer 1311 is, for example, 100 nm, the thickness of the first buffer layer 1312 is set to 20 nm, the thickness of the second buffer layer 1322 is set to 50 nm, and the thickness of the third buffer layer 1332 is set to 100 nm.

[0082] The semiconductor device provided in this embodiment includes the semiconductor substrate 11, dielectric layer 12 and field plate structure 13 described in Embodiment 1, and thus has the same beneficial effects as Embodiment 1. In addition, the field plate structure 13 in this embodiment includes multiple field plate regions, which further improves the voltage resistance of the device, and enhances the controllability of the etching time of each contact hole by adjusting the thickness of each buffer layer, thereby avoiding the problem of over-etching or under-etching the field plate structure 13, and reducing the etching difficulty, so that the etching effect is easier to meet the design requirements.

[0083] Embodiment 3

[0084] This embodiment provides a method for manufacturing a semiconductor device, which is used to manufacture any semiconductor device in the aforementioned embodiments. Figure 4, the preparation method includes steps S01 to S07.

[0085] Step S01: providing a semiconductor substrate 11 .

[0086] Specifically, refer to Figure 5 The semiconductor substrate 11 includes a substrate 111, a base layer 112 stacked on the substrate 111 along a first direction, and a gate region 113 formed on the base layer 112. Optionally, a drain region 114 and a source region 115 are also formed on the base layer 112.

[0087] Step S02 : forming a first dielectric layer 121 on the base layer 112 .

[0088] Specifically, refer to Figure 6 A layer of first dielectric material is deposited on the base layer 112 by a deposition process to form a first dielectric layer 121, and the first dielectric layer 121 covers the gate region 113. Optionally, the first dielectric material may be silicon dioxide or other suitable materials.

[0089] The deposition process may be physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) and other suitable deposition processes, but the present embodiment is not limited thereto.

[0090] Step S03 : depositing a first field plate layer 1311 on the surface of the first dielectric layer 121 and performing photolithography.

[0091] In this embodiment, refer to Figure 7 The first field plate layer 1311 is deposited on the surface of the first dielectric layer 121 through a deposition process, and the deposited first field plate layer 1311 is subjected to photolithography processes such as coating, developing, exposing and etching to form the first field plate layer 1311 with a specific pattern.

[0092] In an alternative embodiment, reference Figure 8, the first field plate region 131 also includes a first buffer layer 1312, and after the first field plate layer 1311 is deposited on the surface of the first dielectric layer 121 to form the first field plate layer 1311, the following steps are further included: depositing the first buffer layer 1312 on the first field plate layer 1311. Specifically, after the first field plate layer 1311 is deposited by a deposition process, silicon nitride, aluminum oxide, titanium, titanium nitride or other suitable materials are deposited on the first field plate layer 1311 to form the first buffer layer 1312, and then the first field plate region 131 is subjected to a photolithography process to form the first field plate region 131 with a specific pattern. Among them, the etching rate of the first buffer layer 1312 can be less than the etching rate of the dielectric layer 12, and can also be greater than or equal to the etching rate of the dielectric layer 12. The etching rate in this application refers to the etching rate of the corresponding material layer when performing the contact hole etching process.

[0093] Step S04 : forming a second dielectric layer 122 covering the first field plate layer 1311 on the first dielectric layer 121 .

[0094] In this embodiment, refer to Fig. 9 , a layer of second dielectric material is deposited on the first dielectric layer 121 to form a second dielectric layer 122. Optionally, the second dielectric material can be the same material as the first dielectric layer 121, or other suitable materials.

[0095] In an optional embodiment, after forming the second dielectric layer 122, the following steps are further included: performing a photolithography process on the second dielectric layer 122 to form a vertical through hole 1222, and making the vertical through hole 1222 expose the gate region 113. Optionally, the vertical through hole 1222 is located directly above the gate region 113 along the first direction, and performing a photolithography process on the second dielectric layer 122 and etching the second dielectric layer 122 and the first dielectric layer 121 to expose the gate region 113.

[0096] Step S05 : depositing a second field plate layer 1321 and a second buffer layer 1322 in sequence on the surface of the second dielectric layer 122 and performing photolithography molding.

[0097] Specifically, refer to Fig.10 , using a deposition process, a second field plate layer 1321 is deposited on the surface of the second dielectric layer 122, after the second field plate layer 1321 is formed, a second buffer layer 1322 is deposited on the surface of the second field plate layer 1321, and the second buffer layer 1322 and the second field plate layer 1321 are etched by a photolithography process to form a second field plate region 132 with a specific pattern. Optionally, the second field plate layer 1321 covers the sidewall and bottom surface of the vertical through hole 1222 and contacts the gate region 113 to achieve the extraction of the gate, and cooperates with the remaining field plate layers to facilitate the uniform distribution of the electric field. Further, the second field plate layer 1321 forms a field plate groove directly above the gate region 113 along the first direction.

[0098] In an optional embodiment, the thickness of the second buffer layer 1322 is greater than the thickness of the first buffer layer 1312, the etching rate of the second buffer layer 1322 is less than or equal to the etching rate of the first buffer layer 1312, and the etching rate of the second buffer layer 1322 is less than the etching rate of the dielectric layer 12. Optionally, the second buffer layer 1322 can be made of the same material as the first buffer layer 1312, for example, the first buffer layer 1312 and the second buffer layer 1322 are both made of silicon nitride.

[0099] In an optional embodiment, the thickness d2 of the second buffer layer 1322 satisfies the following formula: d2 / v2-d1 / v1=(h2+L 12 ) / v0; wherein v0, v1, and v2 are the etching rates of the dielectric layer 12, the first buffer layer 1312, and the second buffer layer 1322, respectively; h2 is the thickness of the second field plate region 132; L 12 is the distance between the first field plate region 131 and the second field plate region 132 along the first direction, d1 is the thickness of the first buffer layer 1312 , and d1 can be 0, which means that the first field plate region 131 only includes the first field plate layer 1311 .

[0100] Step S06 : forming a third dielectric layer 123 on the second dielectric layer 122 and covering the second buffer layer 1322 .

[0101] Specifically, refer to Fig.11 , a layer of third dielectric material is deposited on the second dielectric layer 122 to form a third dielectric layer 123, and the third dielectric layer 123 covers the second buffer layer 1322 and the second field plate layer 1321. Optionally, the third dielectric material can be the same material as the first dielectric layer 121, or other suitable materials, for example, the third dielectric material is also silicon dioxide.

[0102] Step S07 : etching the dielectric layer 12 to form a first contact hole 1211 exposing the first field plate layer 1311 and a second contact hole 1221 exposing the second field plate layer 1321 .

[0103] Specifically, refer to Figure 2 , the dielectric layer 12 is etched by a photolithography process to form a first contact hole 1211 and a second contact hole 1221, respectively, wherein the first contact hole 1211 penetrates the third dielectric layer 123 and the second dielectric layer 122 and exposes the first field plate layer 1311, and the second contact hole penetrates the third dielectric layer 123 and the second buffer layer 1322 and exposes the second field plate layer 1321.

[0104] In this embodiment, CF4, C4F8 or other acceptable etchants may be used for etching, and the etching pressure may be set to, for example, 5 mT to 15 mT.

[0105] In an alternative embodiment, reference Fig.12 After forming the third dielectric layer 123 covering the second buffer layer 1322 on the second dielectric layer 122 , the method may further include steps S61 to S64 to form a semiconductor device having a plurality of field plate layers.

[0106] S61: depositing the i-th field plate layer and the i-th buffer layer on the surface of the i-th dielectric layer in sequence and performing photolithography. Specifically, using a deposition process, depositing the i-th field plate layer on the surface of the i-th dielectric layer and depositing the i-th buffer layer on the surface of the i-th field plate layer.

[0107] S62; forming an i+1th dielectric layer covering the i-th buffer layer on the i-th dielectric layer; specifically, using a deposition process to deposit corresponding dielectric materials on the surface of the i-th dielectric layer and the surface of the i-th buffer layer to form an i+1th dielectric layer covering the i-th dielectric layer, the i-th buffer layer and the i-th field plate layer.

[0108] S63: i is sequentially set to a positive integer from 3 to N, and the above steps are repeated until the N+1th dielectric layer is formed.

[0109] In this embodiment, the initial value of i is set to 3, a third field plate layer and a third buffer layer are formed on the surface of the third dielectric layer 12, and a fourth dielectric layer 124 is formed on the third dielectric layer 123. The value of i is increased from small to large and the above steps are repeated until the N+1th dielectric layer is formed, where N is a positive integer greater than 3.

[0110] S64: Etching the dielectric layer 12 to form the third to Nth contact holes, respectively. Optionally, the etching rate of the i-th buffer layer is less than or equal to the etching rate of the i-1th buffer layer, and less than the etching rate of the dielectric layer 12, and the thickness of the i-th buffer layer is greater than or equal to the thickness of the i-1th buffer layer. Further, referring to the second embodiment, the thickness d of the i-th buffer layer can be i Set to satisfy the following formula: d i / v i —d1 / v1=(h i +L 1i ) / v0.

[0111] In a specific embodiment, referring to Fig.13 , Fig.14 and Figure 3, N is, for example, 3. After forming the third dielectric layer 123 covering the second buffer layer 1322 on the second dielectric layer 122, the following steps are also included: depositing a third field plate layer 1331 and a third buffer layer 1332 on the surface of the third dielectric layer 123 in sequence; forming a fourth dielectric layer 124 covering the third buffer layer 1332 on the third dielectric layer 123; etching the dielectric layer 12 to form the first contact hole 1211 to the third contact hole 1231.

[0112] It can be understood that the preparation method of the semiconductor device provided in this embodiment can also include the steps of forming metal interconnection layers, passivation layers, gate electrodes, drain electrodes, source electrodes and other structures, as well as the steps of forming conductive holes and contact holes. Please refer to the prior art for details, which will not be repeated in this embodiment.

[0113] The method for preparing a semiconductor device provided in this embodiment is used to manufacture any one of the semiconductor devices in Embodiment 1 and Embodiment 2, and therefore also has the beneficial effects of Embodiment 1 and Embodiment 2.

[0114] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify, change or combine the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate, comprising a substrate, a base layer stacked on the substrate along a first direction, and a gate region formed on the base layer; a dielectric layer, formed on the base layer, comprising a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence along the first direction, wherein the first dielectric layer covers the gate region, and a vertical through hole, a first contact hole and a second contact hole are provided in the dielectric layer, wherein the vertical through hole penetrates the first dielectric layer and the second dielectric layer and exposes the gate region; The field plate structure is located in the dielectric layer and includes a first field plate region and a second field plate region; wherein, The first field plate region is formed on the first dielectric layer, the second dielectric layer covers the first field plate region, the first field plate region includes a first field plate layer, and the first contact hole penetrates the second dielectric layer and the third dielectric layer and exposes the first field plate layer; The second field plate region is formed on the second dielectric layer and is located on a side of the first field plate region away from the semiconductor substrate, and includes a second field plate layer and a second buffer layer. The second field plate layer contacts the gate region through the vertical through hole, the second buffer layer is located between the second field plate layer and the third dielectric layer, and the second contact hole penetrates the third dielectric layer and the second buffer layer to expose the second field plate layer.

2. The semiconductor device according to claim 1, wherein: The thickness d2 of the second buffer layer satisfies the following relationship: d2 / v2=(h2+L 12 ) / v0; Wherein, v0 and v2 are the etching rates of the dielectric layer and the second buffer layer respectively, h2 is the thickness of the second field plate region, L 12 is the distance between the first field plate region and the second field plate region along the first direction.

3. The semiconductor device according to claim 1, wherein: The first field plate region also includes a first buffer layer, which is located between the first field plate layer and the second dielectric layer. The first contact hole penetrates the third dielectric layer, the second dielectric layer and the first buffer layer to expose the first field plate layer, and the thickness of the second buffer layer is greater than that of the first buffer layer.

4. The semiconductor device according to claim 3, characterized in that The thickness of the first buffer layer is less than 30 nm, and the thickness of the second buffer layer is 40 nm to 60 nm.

5. The semiconductor device according to claim 1, wherein: The dielectric layer further includes fourth to N+1th dielectric layers formed on the third dielectric layer and sequentially stacked along the first direction; wherein N is a positive integer greater than 3; The field plate structure further includes third to Nth field plate regions, wherein in the third to Nth field plate regions, the i-th field plate region is formed on the i-th dielectric layer, and the i+1-th dielectric layer covers the i-th field plate region, wherein i is a positive integer greater than 2 and less than N+1; The i-th field plate region includes an i-th field plate layer and an i-th buffer layer, and the i-th buffer layer is located between the i+1-th dielectric layer and the i-th field plate layer; The dielectric layer is also provided with third to Nth contact holes, wherein the i-th contact hole penetrates the i-th buffer layer and the i+1-th to N+1-th dielectric layers and exposes the i-th field plate layer.

6. The semiconductor device according to claim 5, characterized in that The thickness of the i-th buffer layer is greater than or equal to the thickness of the (i-1)-th buffer layer.

7. The semiconductor device according to claim 1, wherein: The semiconductor substrate also includes a drain region and a source region formed on the substrate layer, the gate region is located between the source region and the drain region, and when the semiconductor device is viewed from above along the first direction, the field plate structure is located between the gate region and the drain region.

8. A method for manufacturing a semiconductor device, for manufacturing the semiconductor device according to any one of claims 1 to 7, characterized in that: The following steps are involved: Providing a semiconductor substrate, the semiconductor substrate comprising a substrate, a base layer stacked on the substrate along a first direction, and a gate region formed on the base layer; forming a first dielectric layer on the base layer; wherein the first dielectric layer covers the gate region; Depositing a first field plate layer on the surface of the first dielectric layer, and performing photolithography molding; forming a second dielectric layer covering the first field plate layer on the first dielectric layer, and etching the second dielectric layer to form a vertical through hole exposing the gate region; A second field plate layer and a second buffer layer are sequentially deposited on the surface of the second dielectric layer, and photolithography is performed, and the second field plate layer is in contact with the gate region through the vertical through hole; forming a third dielectric layer on the second dielectric layer and covering the second buffer layer; The dielectric layer is etched to form a first contact hole exposing the first field plate layer and a second contact hole exposing the second field plate layer.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: After the first field plate layer is deposited on the surface of the first dielectric layer, the following steps are also included: A first buffer layer is deposited on the first field plate layer; wherein the thickness of the second buffer layer is greater than the thickness of the first buffer layer, and the etching rate of the second buffer layer is less than the etching rate of the dielectric layer, and is less than or equal to the etching rate of the first buffer layer.

10. The method for preparing a semiconductor device according to claim 8, characterized in that: After forming a third dielectric layer covering the second buffer layer on the second dielectric layer, the method further includes the following steps: Depositing the i-th field plate layer and the i-th buffer layer on the surface of the i-th dielectric layer in sequence, and performing photolithography molding; forming an (i+1)th dielectric layer covering the (i)th buffer layer on the (i)th dielectric layer; i is sequentially set to a positive integer from 3 to N+1, and the above steps are repeated until the N+1th dielectric layer is formed; Etching the dielectric layer to form third to Nth contact holes respectively; Wherein, N is a positive integer greater than 3, and the i-th contact hole exposes the i-th field plate layer, and the etching rate of the i-th buffer layer is less than or equal to the etching rate of the i-1-th buffer layer.

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