Semiconductor die with silicon carbide substrate

Abstract

A semiconductor die having a silicon carbide substrate is disclosed. The present disclosure relates to a semiconductor die (1) having a semiconductor device (100) in a semiconductor body (10), the semiconductor body (10) comprising: a silicon carbide substrate (11); an epitaxial silicon carbide layer system (12) on a first side (11.1) of the silicon carbide substrate (11); an intermediate layer (13); wherein the intermediate layer (13) is embedded in the silicon carbide substrate (11) or in the epitaxial silicon carbide layer system (12), in each case, the intermediate layer (13) is embedded at a vertical distance (20) from a first side (11.1) of the silicon carbide substrate (11).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor die having a semiconductor device in a semiconductor body including a silicon carbide substrate. Background Art

[0002] Silicon carbide (SiC) has a relatively wide bandgap, for example compared to silicon. This may, for example, facilitate high voltage and / or high current capabilities and is of particular interest for power semiconductor devices. These have applications in various fields, such as high voltage DC transmission in, for example, offshore wind farms. Summary of the invention

[0003] Examples of the present application relate to advantageous semiconductor dies having silicon carbide substrates.

[0004] In an embodiment, the semiconductor die comprises a semiconductor device in a semiconductor body. In addition to a silicon carbide (SiC) substrate, the semiconductor body comprises an epitaxial SiC layer system and a break layer. The epitaxial SiC layer system is arranged on a first side of the SiC substrate. The break layer is embedded in the SiC substrate or in the epitaxial SiC layer system, in each case at a certain vertical distance from the first side of the SiC substrate. In other words, the break layer can be arranged in the SiC substrate below the first side or in the epitaxial SiC layer system above the first side, but in each case it is vertically spaced apart from the first side.

[0005] The interruption layer can be an amorphous and / or porous layer as well as a highly doped layer. It can form or act as an "interruption" in the crystal structure or "interrupt" (e.g. strongly reduce) electron-hole (eh) recombination, for example shielding the interface between substrate and epitaxial layer system from eh recombination. The so-called transition point can be located in particular at this interface between SiC substrate and epitaxial SiC layer system ("first side" of the SiC substrate), which can result from the transition from a basal plane dislocation (BPD) in the substrate to a threading edge dislocation (TED) in the epitaxial layer system.

[0006] Although TED may be less important, stacking fault growth may occur once eh recombination reaches a switching point. Although this bipolar degradation occurs in bipolar mode, the resulting stacking faults remain in unipolar mode and may, for example, affect the electrical properties of the device. Interrupt layers embedded in the substrate or epitaxial layer system may, for example, physically stop or reduce stacking fault growth by "interrupting" the crystal structure and / or "interrupting" (e.g., strongly reducing) eh recombination over the interface.

[0007] Specific embodiments and features are provided in the present description and the figures, as well as in the dependent claims. Where individual features are to be disclosed independently of a specific claim category, the present disclosure relates to apparatus and device aspects, but also to method and use aspects. If, for example, a die manufactured in a specific manner is described, this also discloses the corresponding manufacturing process, and vice versa. In general, the method of the present application is to introduce a discontinuity layer into a semiconductor body having a SiC substrate and an epitaxial SiC layer system, in particular at a certain vertical distance from the interface between the substrate and the epitaxial layer system.

[0008] The SiC substrate may have a main extension plane spanning in a lateral direction (also referred to as a "horizontal direction"). The vertical direction may run essentially perpendicular to the lateral direction and the extension of the SiC substrate in the vertical direction may be small compared to the extension of the SiC substrate in the lateral direction. In some examples, the SiC substrate may include or be essentially composed of 2H-SiC (2H polytype SiC), 6H-SiC, 3C-SiC or 15R-SiC. According to an example, the semiconductor material is hexagonal 4H polytype silicon carbide (4H-SiC). The off-axis angle of the SiC substrate may be in the range from 2° to 8°, typically 4°. The first side of the SiC substrate may then be ribbed so that a section of the first side may be tilted with respect to the lateral direction and / or the horizontal direction. For example, the main crystal axis of the SiC substrate (e.g., <0001> axis) can form an angle with the vertical direction (e.g., an off-axis angle).

[0009] Since the interruption layer is a "layer", it may have a lateral extension that is greater than its thickness, e.g. a greater extension in each lateral direction than in the vertical direction. Relating to the area of ​​the die, the interruption layer may, e.g., extend over at least 50%, 70% or 90% of the area of ​​the die. In an embodiment, the interruption layer extends over the entire area of ​​the die.

[0010] The "vertical distance" is taken in the vertical direction. In detail, it is taken as the minimum distance, i.e. the gap (not the center-to-center distance). By definition, all layers or layer systems of the semiconductor body have a first side and a second side opposite in the vertical direction, the first side being respectively oriented in the same vertical upward direction and the second side being respectively oriented in the same vertical downward direction. For example, the first side of the epitaxial SiC layer system faces away from the SiC substrate and / or the second side of the SiC substrate faces away from the epitaxial SiC layer system. "Above" means closer to the first side of the semiconductor body and "below" means closer to the second side of the semiconductor body.

[0011] The epitaxial SiC layer system comprises at least one epitaxial SiC layer. In particular, it may comprise a plurality of stacked layers, for example one or more device layers, in particular with a buffer layer underneath. In the device layer(s), one or more active regions of the device may be arranged. Instead of or in addition to an n-region, the device may in particular comprise a p-region, for example, depending on the device type, an anode contact in the case of a diode or a body region in the case of an nFET.

[0012] As discussed above, the interrupt layer is embedded in a SiC substrate or in an epitaxial SiC layer system. "Embedded" can refer to a vertical direction, so that, for example, in the case of a SiC substrate, the upper end (first side) of the interrupt layer can be arranged below the first side of the SiC substrate and the lower end (second side) of the interrupt layer can be arranged above the second side of the SiC substrate. For example, in the case of an epitaxial SiC layer system, the upper end (first side) of the interrupt layer can be arranged below the first side of the SiC epitaxial layer system and the lower end (second side) of the interrupt layer can be arranged above the second side of the epitaxial SiC layer system. In other words, when embedded in a SiC substrate, the corresponding parts of the SiC substrate are correspondingly arranged above and above the interrupt layer. When embedded in an epitaxial SiC layer system, the corresponding parts of the epitaxial SiC layer system are correspondingly arranged above and above the interrupt layer.

[0013] In general, the semiconductor body may include additional ("second") interrupt layers in addition to the ("first") interrupt layer discussed so far. For example, one interrupt layer may be embedded in the SiC substrate and the other may be embedded in the epitaxial SiC layer system. Alternatively, the semiconductor body may include only a single interrupt layer, and the present disclosure shall cover both options unless otherwise indicated. In other words, the "interrupt layer" may be the only interrupt layer in the semiconductor body or may be a first interrupt layer combined with a second interrupt layer.

[0014] In an embodiment, the vertical distance between the first side of the SiC substrate and the interruption layer is at least 0.1 μm, in particular at least 0.2 μm. The upper limit of the vertical distance may be, for example, 1 μm, 0.7 μm or 0.5 μm. The interruption layer is arranged at a vertical distance, but not too far from the interface / first side of the SiC substrate.

[0015] In an embodiment, the interruption layer has a vertical thickness of at least 0.1 μm (or at least 0.2 μm or at least 0.3 μm or at least 0.5 μm) and / or no more than 5 μm. With respect to the vertical distance, the thickness is taken in the vertical direction. The limitation of the thickness may, for example, have economic advantages, for example depending on the specific interruption layer type and its manufacture.

[0016] In an embodiment, the interrupt layer is a highly doped layer. In the case of an epitaxial SiC layer system including a buffer layer, the highly doped interrupt layer can in particular have a higher doping concentration than the buffer layer. When arranged above an interface, i.e. embedded in the epitaxial SiC layer system, the shielding properties of the highly doped interrupt layer can strongly reduce the eh recombination above the interface by means of a transition point. Alternatively or in addition, the high-dose implantation can destroy the crystal structure. Therefore, high-dose implantation can also be a way to produce amorphous and / or porous layers, which are applied due to the physical interruption of the crystal structure (for this reason alone or in combination with the shielding properties).

[0017] In an embodiment, the interruption layer is an amorphous and / or porous layer. When embedded in the epitaxial SiC layer system, the amorphous / porous interruption layer can, for example, stop or interrupt the dislocation itself, i.e. the stacking fault growth from the interface towards the first side of the semiconductor body. However, when the amorphous / porous interruption layer is embedded in the SiC substrate, this growth towards the first side can also be interrupted, see the detailed description below. As an alternative to high-dose implantation, the amorphous / porous layer can be formed, for example, by laser irradiation and / or porosification.

[0018] In an embodiment, the epitaxial SiC layer system comprises a device layer and a buffer layer, the buffer layer being arranged between the device layer and the SiC substrate. In particular, the buffer layer may be directly adjacent to a first side of the SiC substrate and / or the device layer may be directly adjacent to a first side of the buffer layer. The doping concentration of the buffer layer may be higher than in the device layer, for example higher than in a region of the device layer directly adjacent to the buffer layer. In other words, the doping concentration in the buffer layer may be, for example, higher than in a drift region formed in the device layer. With respect to the highly doped interrupt layer, its doping concentration may be higher than the doping concentration of the buffer layer.

[0019] Independent of these details, a buffer layer arranged above the interface can, for example, shield the switching point from the device layer. The hole density can become particularly high in the drift region, for example, as the holes reach the switching point with increasing current density. Although this can be offset by increasing the thickness and doping concentration of the buffer layer, there may be limitations for economic and technical reasons. In this regard, the method of the present application is to combine the buffer layer with the interruption layer.

[0020] In an embodiment, the interruption layer is embedded in the buffer layer so that the lower part of the buffer layer is arranged below the interruption layer and the upper part of the buffer layer is arranged above the interruption layer. In the case of an amorphous / porous interruption layer, the interruption of the crystal structure can, for example, stop the further growth of dislocations or stacking faults when eh-recombination reaches a switching point despite the presence of the buffer layer. Alternatively or in addition, when the interruption layer has a higher doping concentration than the buffer layer, it can, for example, provide a certain separation of the switching point and eh-recombination at the interface, for example thereby strongly reducing eh-recombination and dislocation growth.

[0021] In embodiments involving an amorphous and / or porous interruption layer, it is embedded in the SiC substrate. In other words, the interruption layer is arranged at a certain vertical distance below the first side of the interface / substrate. For example, for geometric reasons, dislocation growth upwards from the interface may cause or require a "mirror dislocation" traveling downwards in the substrate. The latter may be stopped by an amorphous / porous layer embedded in the substrate, which may also stop the upward growth vice versa.

[0022] In an embodiment, the metallization layer is arranged on the second side of the SiC substrate, which is the second side of the semiconductor body. In other words, the die has a backside metallization, for example in combination with a frontside metallization on the first side of the semiconductor body. The metallization layer on the backside can, for example, be used to mount the die in a package and / or in particular as an electrical contact for the device. This applies in particular to vertical devices having their load contacts at the opposite side of the semiconductor body.

[0023] In an embodiment, the device is a FET having a source region and a drain region. In particular, it may be a vertical FET having its source region and drain region at opposite sides of the semiconductor body, for example the source region at a first side and the drain region at a second side. Then, the backside metallization may in particular be or may consist of the drain metallization of the vertical FET.

[0024] In an embodiment, the die comprises an additional ("second") interrupt layer, which may in particular be arranged to be "complementary" to the first interrupt layer. For example, one interrupt layer may be embedded in the SiC substrate and the other interrupt layer in the epitaxial SiC layer system. The additional or "second" interrupt layer is not necessarily arranged at a certain vertical distance from the interface between the substrate and the epitaxial layer system, but may generally be directly adjacent to the interface. Such an interrupt layer, in particular, which is disposed between the SiC substrate and the buffer layer (see above), should also be disclosed independently of the vertical distance from the interface and independently of whether there is only one interrupt layer or two interrupt layers. In other words, a semiconductor die having a semiconductor device in a semiconductor body should be disclosed, the semiconductor body comprising: a silicon carbide substrate; an epitaxial silicon carbide layer system on a first side of the silicon carbide substrate; an interrupt layer; wherein the epitaxial silicon carbide layer system comprises a buffer layer, and wherein the interrupt layer is arranged on the first side of the silicon carbide substrate between the silicon carbide substrate and the buffer layer. In particular, the interrupt layer may be directly adjacent to the first side of the SiC substrate.

[0025] The present application also relates to a package comprising a semiconductor die and a housing in which the die is mounted and electrically contacted. In particular, the backside metallization of the die (see above) can be contacted in the housing, for example connected to a pin of the package. In the example just given, this can be a drain pin of the package.

[0026] The present application further relates to a method of manufacturing a semiconductor die or a package. In addition to epitaxially depositing the epitaxial SiC layer system onto the SiC substrate, the method further comprises forming an interruption layer.

[0027] The interruption layer can be formed in particular by high-dose implantation ("highly doped layer", see above), which can be applied due to the shielding properties and / or the accompanying destruction of the crystal structure. Alternatively, the amorphous / porous layer can be formed by laser irradiation, wherein the SiC can be split into Si and C, for example, in the focus of the laser. In particular, the focal plane of the laser can be chosen slightly below the irradiation surface, for example slightly below the first side of the SiC substrate, in order to embed the interruption layer therein (or slightly below the first side of the buffer layer in order to embed the interruption layer therein).

[0028] Alternatively, the amorphous / porous layer can be formed by porosification, i.e. by an etching process. These different manufacturing methods can be combined or applied as an alternative. Depending on the location of the interruption layer, its formation can be achieved at different steps of the process flow. For example, an interruption layer embedded in the SiC substrate can be formed before depositing the epitaxial SiC layer system.

[0029] Vice versa, the formation of a break layer embedded in the epitaxial SiC layer system can be integrated into its deposition. In particular, the break layer can be formed after the deposition of the buffer layer, for example at least after the deposition of its lower part and before the deposition of the device layer. In an embodiment, the break layer is made after the deposition of the lower part of the buffer layer and before the deposition of the upper part of the buffer layer. In particular, a high-dose implantation step can be implemented in between to form a highly doped break layer embedded in the buffer layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The die and further embodiments are discussed in further detail below with the aid of exemplary embodiments, wherein individual features may also be associated in different combinations.

[0031] Figure 1 shows a die having an epitaxial SiC layer system on a SiC substrate, into which the interruption layer is embedded;

[0032] Figure 2 shows a die having a SiC substrate and an epitaxial SiC layer system into which a break layer is embedded;

[0033] Figure 3 shows a cross-sectional view of a device formed in a die;

[0034] Figures 4a to 4c Schematic illustrations of different possibilities for producing interruption layers are shown;

[0035] Figure 5 shows a cross section through a package with a die;

[0036] Figure 6 Some manufacturing steps are shown in a flow chart. DETAILED DESCRIPTION

[0037] Figure 1 A schematic cross section through a semiconductor die 1 having a semiconductor body 10 is shown. The semiconductor body 10 comprises a silicon carbide (SiC) substrate 11 and an epitaxial SiC layer system 12. The epitaxial SiC layer system 12 is epitaxially deposited onto a first side 11.1 of the SiC substrate 11 and comprises, in the example shown, a device layer 16 and an underlying buffer layer 15. A metallization layer 30 is arranged on a second side 11.2 of the SiC substrate 11 (which is the second side 10.2 of the semiconductor body 10), see for further details Figure 3 and Figure 5 .

[0038] Furthermore, the semiconductor body 10 comprises a discontinuity layer 13. Figure 1In an embodiment of the present invention, it is embedded in the SiC substrate 11, i.e. arranged at a certain vertical distance 20 from the first side 11.1, which is the interface between the SiC substrate 11 and the epitaxial SiC layer system 12. A transition point 40 (only one is shown for the sake of clarity) can be located at the interface, which can be a starting point for the growth of dislocations or stacking faults 41, for example in bipolar mode. The interruption layer 13 provided as an amorphous / porous layer can interrupt the crystal structure and can stop the mirror image stacking fault 42. Therefore, it can also interrupt the further upward propagation of the stacking fault 41.

[0039] By way of example, the interruption layer 13 may have a vertical thickness 25 of approximately 2.5 μm. The vertical distance 20 may be approximately 0.5 μm, for example. The interruption layer 13 may be produced before depositing the epitaxial SiC layer system, for example by laser irradiation through the first side 11 . 1 , wherein the focal plane is slightly shifted downwards, see below for details.

[0040] exist Figure 2 In the embodiment of the present invention, the interrupt layer 13 is embedded in the buffer layer 15. The lower part 15.1 of the buffer layer is arranged below the interrupt layer 13 and the upper part 15.2 is arranged above the interrupt layer 13, i.e. between the interrupt layer 13 and the device layer 16. Again, the interrupt layer 13 is spaced apart from the interface between the SiC substrate 11 and the epitaxial SiC layer system 12.

[0041] On the other hand, in the case of an amorphous / porous interruption layer 13, the interruption of the crystal structure can physically stop the stacking fault 41 growth, as schematically illustrated. Alternatively or in addition, the interruption layer 13 can be highly doped and provide shielding from the interface from eh recombination, for example in addition to shielding by the buffer layer 15. In summary, the interruption layer 13 can reduce eh recombination (which triggers stacking fault growth) and / or can stop growth once initiated due to the interrupted crystal structure.

[0042] To manufacture Figure 2 For example, the interruption layer 13 can be formed after depositing the lower part 15.1 of the buffer layer 15 and before depositing the upper part 15.2 thereof, for example by high-dose implantation therebetween. Alternatively, the buffer layer 15 can be deposited in one step, after which the interruption layer 13 is formed, for example by laser irradiation.

[0043] Figure 3 A schematic cross section of a die 1 is shown and a semiconductor device 100 is illustrated, in the example shown a vertical transistor device 100. Generally, in the present disclosure, the same reference numerals refer to the same elements or elements having the same function, and reference is also always made to the corresponding description of the other figures. Of course, any measurements or ratios in the schematic drawings are not to scale.

[0044] The vertical transistor device 101 comprises a source region 110 at a first side 10.1 of the semiconductor body 10 and a drain region 113 at a second side 10.2 opposite in the vertical direction. Arranged therebetween is its main region 111 and a drift region 112. The drift region 112 is made of the same doping type but with a lower doping concentration than the drain region 113. In the case of an nFET, the source region 110, the drift region 112 and the drain region 113 are n-doped, while the main region 111 is p-doped.

[0045] The gate region 120 is arranged in a trench 121 laterally next to the body region 111. It comprises a gate electrode 122 and a gate dielectric 123, which capacitively couples the gate electrode 122 to the body region 111. On the first side 10.1 an insulating layer 130 is arranged, on top of which there is a front side metallization layer 135. The front side metallization layer 135 is a source contact, which is connected to the source region 110 and the body region 111 via a contact plug 136. The metallization layer 30 on the second side 10.2 is connected to the drain region 113 and is used as a drain contact.

[0046] A source region 110, a body region 111 and a drift region 112 are formed in the device layer 16. A buffer layer 15 is arranged below the device layer 16 to shield the interface to some extent from the effects of eh recombination, see above. In the example shown, the interruption layer 13 is embedded in the SiC substrate, as shown in FIG. Figure 1 As explained above, the interruption layer can also be embedded in the buffer layer 15, as in Figure 2 As shown in the figure.

[0047] Figures 4a to 4c Different options for producing the interruption layer 13 are illustrated. Figure 4a Shown is a laser irradiation 150, ie a laser beam 151 which is focused into a focal plane 125 below the first side 11.1 of the SiC substrate 11. In the focal plane 125 the crystal structure is locally destroyed which gives an amorphous and / or porous layer 13a.

[0048] Figure 4b The interruption layer formation by porosification 160 , ie by an etchant 161 , is shown. Figure 4c A high dose implant 170 is illustrated. In this case, the interruption layer should be embedded in the buffer layer 15 and the dopant 171 for the high dose implant 170 is introduced after depositing the lower part 15.1 of the buffer layer 15 and before depositing the upper part 15.2 of the buffer layer 15.

[0049] Figure 5A package 200 is shown, comprising a housing 201 in which a semiconductor die 1 is mounted. In detail, the die 1 is placed on a heat sink 202, wherein a metallization layer (not shown here) arranged on the second side, i.e. the drain metallization of the die 1, is electrically connected to the heat sink 202. The drain contact may be connected via a corresponding pin 203. The die 1 is embedded in a molding compound 204, wherein further connection details are not shown here.

[0050] Figure 6 Some manufacturing steps are summarized. After providing 210 the SiC substrate, different options are possible. Alternatively, the formation 211 of the interruption layer can be done before epitaxially depositing 212 the epitaxial SiC layer system. Alternatively, as illustrated in the lower path, the formation 211 of the interruption layer can be embedded between the deposition steps 212.1, 212.2, see also Figure 4c .

Claims

1. A semiconductor die (1) having A semiconductor device (100) in a semiconductor body (10), A semiconductor body (10) comprising Silicon carbide substrate (11); An epitaxial silicon carbide layer system (12) on a first side (11.1) of a silicon carbide substrate (11); Interrupt layer (13); wherein the interruption layer (13) is embedded in the silicon carbide substrate (11) or in the epitaxial silicon carbide layer system (12), In each case, the interruption layer (13) is embedded at a vertical distance (20) from the first side (11.1) of the silicon carbide substrate (11).

2. The semiconductor die (1) according to claim 1, wherein a vertical distance (20) between the first side (11.1) of the silicon carbide substrate (11) and the interruption layer (13) is at least 0.1 μm but not more than 1 μm.

3. The semiconductor die (1) according to claim 1 or 2, wherein the interruption layer (13) has a vertical thickness (25) of at least 0.1 μm but not more than 5 μm.

4. The semiconductor die (1) according to any of the preceding claims, wherein the interruption layer (13) is a highly doped layer (13b).

5. The semiconductor die (1) according to any one of the preceding claims, wherein the interruption layer (13) is an amorphous and / or porous layer (13a).

6. A semiconductor die (1) according to any of the preceding claims, wherein the epitaxial silicon carbide layer system (12) comprises a device layer (16) and a buffer layer (15), the buffer layer (15) being arranged between the device layer (16) and the silicon carbide substrate (11) and being doped with a higher doping concentration than the device layer (16).

7. A semiconductor die (1) according to claim 6, wherein the interruption layer (13) is embedded in the buffer layer (15), the lower part (15.1) of the buffer layer (15) is arranged between the interruption layer (13) and the silicon carbide substrate (11), and the upper part (15.2) of the buffer layer (15) is arranged between the device layer (16) and the interruption layer (13).

8. The semiconductor die (1) according to claim 5, optionally also in combination with claim 6, wherein the amorphous and / or porous layer (13a) is embedded in a silicon carbide substrate (11).

9. The semiconductor die (1) according to any of the preceding claims, comprising a metallization layer (30) arranged on a second side (11.2) of the silicon carbide substrate (11) vertically opposite to the first side (11.1).

10. The semiconductor die (1) of claim 9, wherein the semiconductor device (100) is a vertical transistor device (101) having a source region (110) and a drain region (113) at opposite sides (10.1, 10.2) of the semiconductor body (10).

11. The semiconductor die (1) according to any one of the preceding claims, comprising an additional interruption layer, which is vertically spaced apart from the interruption layer (13).

12. A package (200), comprising: A semiconductor die (1) as claimed in any one of the preceding claims, and Housing (201), A semiconductor die (1) is mounted in the housing (201) and electrically contacted.

13. A method of manufacturing a semiconductor die (1) according to any one of claims 1 to 11 or a package (200) according to claim 12, comprising the following steps: i) providing a silicon carbide substrate (11); ii) epitaxially depositing an epitaxial silicon carbide layer system (12) on the first side (11.1) of the silicon carbide substrate (11); iii) Formation of a break layer (13).

14. The method according to claim 13, for producing the semiconductor die (1) according to claim 5, wherein the interruption layer (13) is formed by laser irradiation (150) and / or porosification (160) and / or high-dose implantation (170).

15. The method according to claim 14, for manufacturing a semiconductor die (1) according to claim 8, wherein step iii) is performed before step ii).

16. A method according to claim 13 for manufacturing a semiconductor die (1) as claimed in claims 4 and 7, wherein the highly doped layer (13b) is produced by performing a high-dose implantation (170) between a lower part (15.1) of a deposited buffer layer (15) and an upper part (15.2) of the deposited buffer layer (15).

Images