Semiconductor device and method

Abstract

The invention relates to a semiconductor device and a method. A semiconductor device and a method of forming the same are provided. The semiconductor device may include a first plurality of nanostructures and a second plurality of nanostructures over a substrate; a first gate stack and a second gate stack, the first gate stack extending between nanostructures in the first plurality of nanostructures and the second gate stack extending between nanostructures in the second plurality of nanostructures; a first source / drain region in contact with a first nanostructure of the first plurality of nanostructures; a second source / drain region in contact with a first nanostructure of the second plurality of nanostructures, where the second source / drain region may be separated from the first source / drain region; a silicide layer between the first source / drain region and the second source / drain region; and an isolation layer between the silicide layer and the substrate.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a first plurality of nanostructures and a second plurality of nanostructures, on a substrate; a first gate stack and a second gate stack, the first gate stack extending between nanostructures in the first plurality of nanostructures, and the second gate stack extending between nanostructures in the second plurality of nanostructures; a first source / drain region in contact with a first nanostructure in the first plurality of nanostructures; a second source / drain region in contact with a first nanostructure in the second plurality of nanostructures, wherein the second source / drain region is separated from the first source / drain region; a silicide layer located between the first source / drain region and the second source / drain region; and an isolation layer located between the silicide layer and the substrate.

[0005] According to one embodiment of the present disclosure, a semiconductor device is provided, including: a first plurality of nanostructures and a second plurality of nanostructures, on a substrate; a first gate stack and a second gate stack, the first gate stack extending between nanostructures in the first plurality of nanostructures, and the second gate stack extending between nanostructures in the second plurality of nanostructures; a first source / drain region along a sidewall of a first nanostructure in the first plurality of nanostructures; a second source / drain region along a sidewall of a first nanostructure in the second plurality of nanostructures; a silicide layer located between the first source / drain region and the second source / drain region; and a material layer located between the silicide layer and the substrate.

[0006] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a first plurality of nanostructures and a second plurality of nanostructures on a substrate; forming a first source / drain region on a sidewall of a first nanostructure in the first plurality of nanostructures, and forming a second source / drain region on a sidewall of a first nanostructure in the second plurality of nanostructures; forming a material layer on the first source / drain region and the second source / drain region; removing at least a portion of the material layer to form an opening; forming a metal layer in the opening; and performing annealing to form a silicide layer from the metal layer, the first source / drain region, and the second source / drain region, and wherein the silicide layer is located between the first source / drain region and the second source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An example of a nanostructured field effect transistor (nano-FET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C , Fig. 9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig.18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A , Fig. 21B , Fig. 21C , Fig.22A , Fig. 22B , Fig. 22C , Fig.23A , Fig. 23B , Fig.23C , Fig.23D , Fig.23E , Fig.23F , Figure 23G , Fig.23H and Fig.23I is a diagram of an intermediate stage in the fabrication of a semiconductor device including a nanostructure FET, according to some embodiments.

[0010] Fig.24A , Fig. 24B and Fig.24C is a diagram of a semiconductor device including a nanostructure FET according to some embodiments.

[0011] Fig.25A , Fig.25B and Fig.25C is a diagram of a semiconductor device including a nanostructure FET according to some embodiments.

[0012] Fig.26A , Fig.26B and Fig.26C is a diagram of a semiconductor device including a nanostructure FET according to some embodiments.

[0013] Fig.27A , Fig.27B , Fig.27C and Fig.27D is a diagram of a semiconductor device including a nanostructure FET according to some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] Various embodiments provide semiconductor devices with larger contact areas. For example, some embodiments provide nanostructured FETs including epitaxial source / drain regions and silicide layers formed on the epitaxial source / drain regions, wherein the contact area between the epitaxial source / drain regions and the silicide layer is larger. By increasing the contact area between the epitaxial source / drain regions and the silicide layer, the resistance between the epitaxial source / drain regions and the silicide layer can be reduced. Therefore, the resistance between the epitaxial source / drain regions and the source / drain contacts can be reduced, thereby improving the performance of the semiconductor device.

[0017] Some embodiments discussed herein are described in the context of semiconductor devices including nanostructured FETs. However, various embodiments may be applied to dies that include other types of transistors (e.g., fin field effect transistors (FinFETs), vertical field effect transistors (VFETs), complementary field effect transistors (CFETs), planar transistors, etc.) instead of or in combination with nanostructured FETs.

[0018] Figure 1An example of a nanostructure FET (e.g., a nanowire FET, a nanosheet FET, etc.) is shown in a three-dimensional view. The nanostructure FET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) located on a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 is used as a channel region of the nanostructure FET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. A shallow trench isolation (STI) region 68 is disposed between adjacent fins 66, which may protrude above the STI region 68 and protrude from between adjacent STI regions 68. Although the STI region 68 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate, or a combination of a semiconductor substrate and an STI region. In addition, although the bottom portion of the fin 66 is shown as a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 66 refers to a portion extending between adjacent STI regions 68. The gate dielectric layer 100 is over the top surface of the fin 66 and along the top surface, sidewalls and bottom surface of the nanostructure 55. The gate electrode 102 is over the gate dielectric layer 100. The epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0019] Figure 1 Reference cross sections used in subsequent figures are further shown. Reference cross section AA' is along the longitudinal axis of the gate electrode 102 and in a direction perpendicular to the direction of current flow between, for example, the epitaxial source / drain regions 92 of the nanostructured FET. Reference cross section BB' is parallel to reference cross section AA' and extends through the epitaxial source / drain regions 92 of multiple nanostructured FETs. Reference cross section CC' is perpendicular to reference cross section AA' and parallel to the longitudinal axis of the fin 66 of the nanostructured FET and in the direction of current flow between, for example, the epitaxial source / drain regions 92 of the nanostructured FET. For clarity, subsequent figures refer to these reference cross sections. Some embodiments discussed herein are discussed in the context of nanostructured FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments consider aspects used in planar devices (e.g., planar FETs) or in FinFETs.

[0020] Figures 2 to 23C is a diagram of an intermediate stage in the fabrication of a semiconductor device including a nanostructure FET, according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A and Fig.23A Shown along Figure 1 A cross-sectional view with reference to section AA' is shown. Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig.12D , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B and Fig. 23B Shown along Figure 1 A cross-sectional view with reference to section BB' is shown. Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig.11D , Fig.11E , Fig. 12C , Fig.12E , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C , Fig.19C , Fig. 20C , Fig. 21C , Fig. 22C , Fig.23C , Fig.23D , Fig.23E , Fig.23F , Figure 23G , Fig.23H and Fig.23I Shown along Figure 1 A cross-sectional view of reference section CC' is shown.

[0021] exist Figure 2 In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (for example, with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, for example, a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, for example, a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0022] The substrate 50 has a region n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, for example, an NMOS transistor, such as an n-type nanostructure FET, and the p-type region 50P can be used to form a p-type device, for example, a PMOS transistor, such as a p-type nanostructure FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0023] Further in Figure 2In the embodiment of the present invention, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustration purposes and as discussed in more detail below, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form a channel region of the nanostructure FET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanostructure FET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanostructure FET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanostructure FET in the n-type region 50N, and the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanostructure FET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanostructure FET in the n-type region 50N and the p-type region 50P.

[0024] For illustrative purposes, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of the first semiconductor layer 51 and the second semiconductor layer 53. Each layer of the multilayer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material different from the first semiconductor material, such as silicon, carbon-doped silicon, etc.

[0025] The first semiconductor material and the second semiconductor material may be materials having high etching selectivity relative to each other. In this way, the first semiconductor layer 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form a channel region of the nanostructure FET. Similarly, in an embodiment where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region, the second semiconductor layer 53 of the second semiconductor material may be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form a channel region of the nanostructure FET.

[0026] exist Figure 3 In some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching grooves in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, for example, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching can be anisotropic. Forming nanostructure 55 by etching multilayer stack 64 can further define first nanostructures 52A-52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and define second nanostructures 54A-54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructure 52 and second nanostructure 54 can be collectively referred to as nanostructure 55.

[0027] The fins 66 and nanostructures 55 may be patterned by any suitable method. For example, one or more photolithography processes may be used to pattern the fins 66 and nanostructures 55, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines a photolithography process and a self-alignment process, allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A spacer is formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 66.

[0028] For illustrative purposes, Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are shown as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater or thinner than the width of the fins 66 in the p-type region 50P. In addition, although each of the fins 66 and the nanostructures 55 are shown as having a consistent width throughout, in other embodiments, the fins 66 and / or the nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or the nanostructures 55 increases continuously in a direction toward the substrate 50. In such an embodiment, each nanostructure 55 may have a different width and be trapezoidal.

[0029] exist Figure 4In the embodiment, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, the fin 66 and the nanostructure 55 and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that an excess of insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 50, the fin 66 and the nanostructure 55. Thereafter, a filling material such as described above may be formed over the liner.

[0030] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be employed. The planarization process exposes the nanostructures 55 so that after the planarization process is completed, the top surfaces of the nanostructures 55 and the insulating material may be substantially coplanar or flush.

[0031] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 can have a flat surface (as shown), a convex surface, a concave surface (e.g., a dished shape), or a combination thereof. The top surface of the STI region 68 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fin 66 and the nanostructure 55). For example, oxide removal using an acid such as dilute hydrofluoric acid (dHF) can be used.

[0032] Above about Figures 2 to 4The process described is an example of how the fin 66 and the nanostructure 55 can be formed. In some embodiments, the fin 66 and / or the nanostructure 55 can be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 66 and / or the nanostructure 55. The epitaxial structure may include alternating semiconductor materials described above, for example, a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxially grown material can be doped in situ during growth, which can avoid previous and / or subsequent implantation, but in situ doping and implantation doping can be used together.

[0033] In addition, for illustrative purposes, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as including the same material in the p-type region 50P and the n-type region 50N. In some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region 50P and the n-type region 50N, or may be formed in a different order.

[0034] Further in Figure 4 In the embodiment having different well types, a photoresist or other mask (not shown separately) may be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist may be formed over the fins 66 and the STI region 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P and the photoresist may be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0035] After or before the implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., which is implanted into the region at a concentration of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process. After implantation of the n-type region 50N and the p-type region 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0036] exist Figure 5In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials with high etch selectivity relative to the etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. Note that for illustrative purposes, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited so that the dummy dielectric layer 70 covers the STI region 68, so that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0037] FIG. 6A to FIG. 23I Various additional steps in fabricating nanostructured FEI devices according to some embodiments are shown. FIG. 6A to FIG. 23I Features in either or both of the n-type region 50N or the p-type region 50P are shown. FIG. 6A to FIG. 6C In the embodiment, the mask layer 74 may be patterned using acceptable photolithography and etching techniques (see Figure 5 ) to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from an adjacent dummy gate 76. The dummy gate 76 can also have a length direction that is substantially perpendicular to the length direction of the corresponding fin 66.

[0038] exist FIG. 7A to FIG. 7C in FIG. 6A to FIG. 6C A first spacer layer 80 and a second spacer layer 82 are formed over the structure shown. The first spacer layer 80 and the second spacer layer 82 will subsequently be patterned to act as spacers for forming self-aligned source / drain regions. FIG. 7A to FIG. 7C, a first spacer layer 80 is formed on: the top surface of the STI region 68; the top surface and sidewalls of the fin 66, the nanostructure 55, and the mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a technique such as thermal oxidation, or deposited by CVD, ALD, etc. The second spacer layer 82 can be formed of a material having a different etch rate from the material of the first spacer layer 80, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc.

[0039] After forming the first spacer layer 80 and before forming the second spacer layer 82, an implant for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above, Figure 4 As discussed in the implantation, a mask such as a photoresist may be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of an appropriate type (e.g., p-type) may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of an appropriate type (e.g., n-type) may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the previously discussed n-type impurities, and the p-type impurity may be any of the previously discussed p-type impurities. The lightly doped source / drain regions may have a density of approximately 1×10 15 Atom / cm 3 About 1×10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0040] exist FIG. 8A to FIG. 8C, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source / drain regions, and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, for example, an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, so that the first spacer layer 80 can be used as an etch stop layer when patterning the second spacer layer 82, and so that the second spacer layer 82 can be used as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 is used as an etch stop layer, and wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, such as Figure 8B Thereafter, the second spacer 83 is used as a mask when etching the exposed portion of the first spacer layer 80, thereby forming the first spacer 81, as shown in FIG. Figure 8B and Figure 8C shown.

[0041] like Figure 8B As shown, some portions of the first spacer 81 and the second spacer 83 may remain disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8C As shown, in some embodiments, the second spacer layer 82 may be removed from the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain on the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0042] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), additional spacers may be formed and removed, etc. In addition, different structures and steps may be used to form n-type devices and p-type devices.

[0043] exist 9A to 9CIn some embodiments, a recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region will be formed in the recess 86. The recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and extend into the substrate 50. Fig. 9B As shown, the top surface of STI region 68 may be flush with the bottom surface of recess 86. Fig. 9C As shown, the recess 86 may have a width D1 between the stacks of two adjacent second nanostructures 54, which may correspond to the width of the subsequently formed epitaxial source / drain region, as described in more detail below. In some embodiments, the width D1 may be in the range between about 15nm and about 25nm. In various embodiments, the fin 66 may be etched so that the bottom surface of the recess 86 is disposed below the top surface of the STI region 68, etc. The recess 86 may be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, etc. The first spacer 81, the second spacer 83, and the mask 78 mask some portions of the fin 66, the nanostructure 55, and the substrate 50 during the etching process for forming the recess 86. Each layer in the nanostructure 55 and / or the fin 66 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching after the recess 86 reaches the desired depth.

[0044] exist FIG. 10A to FIG. 10C In FIG. 8 , the portion of the sidewall of the first nanostructure 52 exposed by the recess 86 is etched to form a sidewall recess 88. Fig. 10C The sidewalls of the first nanostructure 52 adjacent to the sidewall recess 88 are shown as concave, but the sidewalls may be straight or convex. The sidewalls may be etched using an isotropic etching process (e.g., wet etching, etc.). In embodiments where the first nanostructure 52 includes silicon germanium, etc. and the second nanostructure 54 includes silicon, silicon carbide, etc., the sidewalls of the first nanostructure 52 may be etched using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0045] exist FIG. 11A to FIG. 11E, a first internal spacer 90 is formed in the sidewall recess 88. As will be discussed in more detail below, an epitaxial source / drain region will be formed in the recess 86, and the first nanostructure 52 will be replaced by a corresponding gate structure. The first internal spacer 90 can be used as an isolation feature to prevent the subsequently formed source / drain region from being damaged by a subsequent etching process used to form the gate structure. The first internal spacer 90 can be formed by first depositing an internal spacer layer (not shown separately) via a deposition process (e.g., CVD, ALD, etc.). The internal spacer layer may include a low dielectric constant (low-k) material having a k value of less than about 3.5, such as silicon nitride, silicon oxide, etc. The internal spacer layer can then be etched by an anisotropic etching process (e.g., RIE, NBE, etc.) to form the first internal spacer 90.

[0046] Although the outer sidewalls of the first inner spacer 90 are shown as being flush with the sidewalls of the second nanostructure 54, the outer sidewalls of the first inner spacer 90 may extend beyond or be recessed from the sidewalls of the second nanostructure 54. Fig. 11C The outer sidewall of the first interior partition 90 is shown as being straight, but the outer sidewall of the first interior partition 90 may be concave or convex. Fig.11D An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave and the outer sidewalls of the first inner spacer 90 are concave. Fig.11E An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave and the outer sidewalls of the first inner spacer 90 are convex.

[0047] exist FIG. 12A to FIG. 12C In the embodiment, the semiconductor layer 91, the isolation layer 93, the epitaxial source / drain region 92 and the sacrificial layer 95 are formed in the recess 86 ( Fig. 11B and Fig. 11C ). The sacrificial layer 95 may also be referred to as a material layer, and at least a portion of each sacrificial layer 95 may be removed in a subsequent etching process, as described in more detail below. A semiconductor layer 91 may be formed on the fin 66. The semiconductor layer 91 may be formed of a semiconductor material selected from a candidate semiconductor material of the substrate 50, which may be formed by an epitaxial growth process such as VPE, MBE, etc. The materials of the semiconductor layer 91 and the substrate 50 may be the same or different. A timed epitaxial growth process may be used to grow the semiconductor layer 91 to a certain height. The semiconductor layer 91 may be separated from the second nanostructure 54.

[0048] The isolation layer 93 is formed on the semiconductor layer 91. The isolation layer 93 may be in contact with the first inner spacer 90 on the first nanostructure 52A. The top surface of the isolation layer 93 may be disposed below the top surface of the first inner spacer 90 on the first nanostructure 52A (e.g., the bottom nanostructure of the first nanostructure 52). The isolation layer 93 may be separated from the second nanostructure 54. The isolation layer 93 may be formed by forming one or more dielectric materials on the semiconductor layer 91 via a deposition process (e.g., CVD, ALD, etc.). Acceptable dielectric materials may include silicon nitride, silicon oxynitride, silicon oxycarbon nitride, silicon oxycarbide, silicon carbon nitride, silicon oxide, aluminum oxide, hafnium oxide, etc. Fig. 12C Isolation layer 93 is shown as being above the top surface of fin 66 as an example, isolation layer 93 may be disposed at other locations, such as below the top surface of fin 66 .

[0049] The epitaxial source / drain regions 92 and the sacrificial layer 95 are sequentially formed in the n-type region 50N (e.g., NMOS region) and the p-type region 50P (e.g., PMOS region). For example, when the epitaxial source / drain regions 92 and the sacrificial layer 95 are formed in the n-type region 50N, the p-type region 50P may be masked, and when the epitaxial source / drain regions 92 and the sacrificial layer 95 are formed in the p-type region 50P, the n-type region 50N may be masked.

[0050] Epitaxial source / drain regions 92 are formed on the second nanostructure 54. The epitaxial source / drain regions 92 may be formed by an epitaxial growth process (e.g., VPE, MBE, etc.). Process conditions (e.g., temperature, pressure, and processing time) may affect the shape of the epitaxial source / drain regions 92, as described in more detail below. In some embodiments, the epitaxial source / drain regions 92 may apply stress to the second nanostructure 54, thereby improving the performance of a subsequently formed semiconductor device. Fig. 12C As shown, epitaxial source / drain regions 92 may be formed on both sides of the second nanostructure 54, and the epitaxial source / drain regions 92 on each second nanostructure 54 are separated from the epitaxial source / drain regions 92 on another second nanostructure 54, which may increase the contact area between the epitaxial source / drain regions 92 and the subsequently formed silicide layer, as described in more detail below. The epitaxial source / drain regions 92 may contact the first spacer 81 and the first internal spacer 90. The first spacer 81 may separate the epitaxial source / drain regions 92 from the dummy gate 76, and the first internal spacer 90 may separate the epitaxial source / drain regions 92 from the first nanostructure 52, so that the epitaxial source / drain regions 92 are not short-circuited with the subsequently formed gate electrode.

[0051] The epitaxial source / drain regions 92 in the p-type region 50P may include any acceptable material suitable for a p-type nanostructure FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 may include a material that applies compressive strain to the second nanostructure 54, such as silicon germanium, germanium, germanium tin, etc. In some embodiments, the epitaxial source / drain regions 92 in the p-type region 50P include silicon germanium, and its first germanium concentration is in the range of about 0% to about 80%, for example, in the range of about 40% to about 60%. The epitaxial source / drain regions 92 in the p-type region 50P may be formed using a precursor, such as dichlorosilane, silane, disilane, germanium, germanium tetrachloride, hydrochloric acid, chlorine, etc. The epitaxial source / drain regions 92 in the p-type region 50P may be formed at a temperature in the range of about 520° C. to about 680° C. and a pressure in the range of about 20 torr to about 80 torr.

[0052] The epitaxial source / drain regions 92 in the n-type region 50N may include any acceptable material suitable for an n-type nanostructure FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 may include a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, etc. The epitaxial source / drain regions 92 in the n-type region 50N may be formed using a precursor, such as dichlorosilane, silane, disilane, hydrochloric acid, chlorine, etc. The epitaxial source / drain regions 92 in the n-type region 50N may be formed at a temperature in the range of about 600° C. to about 750° C. and a pressure in the range of about 100 Torr to about 300 Torr.

[0053] The epitaxial source / drain regions 92 may be implanted with dopants by an implantation process similar to that discussed above with respect to forming the LDD regions. In some embodiments, the dopants for the epitaxial source / drain regions 92 in the p-type region 50P include boron, gallium, etc., at a concentration of about 5×10 19 Atom / cm 3 About 5×10 21 Atom / cm 3 In some embodiments, the dopant for the epitaxial source / drain regions 92 in the n-type region 50N includes phosphorus, arsenic, antimony, etc., with a concentration of about 5×10 19 Atom / cm 3 About 5×10 21 Atom / cm 3 In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth, wherein diborane, boron trichloride, trimethyl gallium, etc. may be used as dopant precursors in the p-type region 50P, and phosphine, arsine, etc. may be used as dopant precursors in the n-type region 50N.

[0054] A sacrificial layer 95 is then formed on the epitaxial source / drain regions 92. The sacrificial layer 95 may fill the remaining portion of the recess 86. Fig. 12C As shown, the sacrificial layer 95 may be disposed between adjacent epitaxial source / drain domains 92, and between the epitaxial source / drain domains 92 and the isolation layer 93. The sacrificial layer 95 may be in contact with the first spacer 81, the second spacer 83, and the first inner spacer 90. The top of the sacrificial layer 95 may be higher than the corresponding top surface of the nanostructure 55, and the top of the sacrificial layer 95 may have facets, such as Fig. 12B and Fig. 12C shown.

[0055] The sacrificial layer 95 may include a material having an etch selectivity to the epitaxial source / drain region 92. The sacrificial layer 95 in the p-type region 50P may include any acceptable material suitable for a p-type nanostructure FET, for example, silicon germanium, germanium, germanium tin, etc., formed by an epitaxial growth process (e.g., VPE, MBE, etc.). In some embodiments, the sacrificial layer 95 in the p-type region 50P includes silicon germanium having a second germanium concentration in the range of about 40% to about 80%, for example, in the range of about 50% to about 60%. The second germanium concentration of the sacrificial layer 95 may be higher than the first germanium concentration of the epitaxial source / drain region 92, which may result in an etch selectivity between the epitaxial source / drain region 92 and the sacrificial layer 95 in the p-type region 50P during a subsequent etching process, as described in more detail below. The sacrificial layer 95 in the p-type region 50P may be formed at a temperature in the range of about 520° C. to about 680° C., and a pressure in the range of about 20 Torr to about 80 Torr. The sacrificial layer 95 in the n-type region 50N may include any acceptable material suitable for an n-type nanostructure FET, such as silicon, silicon carbide, silicon phosphide, etc., formed by an epitaxial growth process (e.g., VPE, MBE, etc.). The sacrificial layer 95 in the n-type region 50N may be formed at a temperature in the range of about 600° C. to about 750° C. and a pressure in the range of about 100 Torr to about 300 Torr.

[0056] The sacrificial layer 95 may be implanted with dopants by an implantation process similar to that discussed above with respect to forming the LDD region. In some embodiments, the dopant for the sacrificial layer 95 in the p-type region 50P includes boron, gallium, etc., with a concentration of about 5×10 19 Atom / cm 3 About 5×10 21 Atom / cm 3 In some embodiments, the dopant for the sacrificial layer 95 in the n-type region 50N includes phosphorus, arsenic, antimony, etc., with a concentration of about 5×10 19 Atom / cm 3 About 5×10 21 Atom / cm 3In some embodiments, in the n-type region 50N, the dopant for the epitaxial source / drain region 92 includes arsenic and the dopant for the sacrificial layer 95 includes phosphorus, which can produce an etch selectivity between the epitaxial source / drain region 92 and the sacrificial layer 95 in the n-type region 50N during a subsequent etching process, as described in more detail below. In some embodiments, the sacrificial layer 95 can be doped in situ during growth.

[0057] As a result of the epitaxial process used to form the sacrificial layer 95 in the n-type region 50N and the p-type region 50P, the top of the sacrificial layer 95 may have facets that extend laterally outward beyond the first spacer 81 and the second spacer 83. In some embodiments, these facets cause the tops of adjacent sacrificial layers 95 to merge, such as Fig. 12B In some embodiments, the tops of adjacent sacrificial layers 95 remain separated after the epitaxial process is completed, as shown in FIG. Fig.12D The first spacer 81 and the second spacer 83 may be located on the upper surface of the STI region 68 and block the lateral expansion of the bottom of the sacrificial layer 95 .

[0058] In some embodiments, the sacrificial layer 95 includes a dielectric material, such as silicon oxycarbon nitride, etc. In some embodiments, the silicon oxycarbon nitride in the sacrificial layer 95 includes 20% to 80% oxygen, 0% to 20% carbon, and 0% to 40% nitrogen. In these embodiments, the sacrificial layer 95 is formed by a deposition process (e.g., CVD, ALD, etc.), and excess dielectric material can be removed after the deposition process. Fig. 12B and Fig. 12C Unlike the illustrated embodiment, the sacrificial layer 95 comprising a dielectric material may not have facets (not separately shown).

[0059] In some embodiments, the second nanostructure 54 may be recessed on both sides by a suitable etching process before forming the epitaxial source / drain regions 92. Thus, the epitaxial source / drain regions 92 may extend into the recess and extend beyond the outer sidewalls of the first inner spacer 90 toward the second nanostructure 54 by a distance D2, as shown in FIG. Fig.12E As shown. The distance D2 may be in a range between about 1 nm and about 5 nm. The distance D2 may be referred to as a push-in distance of the epitaxial source / drain regions 92 .

[0060] exist FIG. 13A to FIG. 13C in FIG. 12A to FIG. 12CA first interlayer dielectric (ILD) 96 is deposited over the structure shown. The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the sacrificial layer 95, the mask 78, and the first spacer 81. The CESL 94 may include a dielectric material having an etch rate different from that of the material of the overlying first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0061] exist FIG. 14A to FIG. 14C In the process, a planarization process such as a CMP process may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 may be substantially coplanar or flush. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0062] exist FIG. 15A to FIG. 15C In one embodiment, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps, thereby forming a recess 98. The portion of the dummy gate dielectric 71 in the recess 98 is also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each recess 98 exposes and / or overlies a portion of the nanostructure 55 that is used as a channel region in a subsequently completed nanostructure FET. The portion of the nanostructure 55 that is used as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer when the dummy gate 76 is etched. The dummy gate dielectric 71 can then be removed after the dummy gate 76 is removed.

[0063] exist FIG. 16A to FIG. 16C, the first nanostructure 52 is removed, expanding the recess 98. The first nanostructure 52 may be removed by performing an isotropic etching process such as a wet etch or the like using an etchant that is selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 includes silicon germanium or the like and the second nanostructure 54 includes silicon, silicon carbide or the like, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the first nanostructure 52.

[0064] exist 17A to 17C , a gate dielectric layer 100 and a gate electrode 102 are formed for replacing the gate. The gate dielectric layer 100 is conformally deposited in the recess 98. The gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, and the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 may also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68, and on the sidewalls of the first spacer 81 and the first inner spacer 90.

[0065] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or a combination thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer located above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant (k) value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0066] The gate electrode 102 is deposited on the gate dielectric layer 100 and fills the remaining portion of the recess 98. The gate electrode 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. Fig.17A and Fig. 17C, a single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filling materials. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 and between the second nanostructures 54A and the substrate 50 in the n-type region 50N, and may be deposited between adjacent first nanostructures 52 in the p-type region 50P.

[0067] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by a different process, such that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by a different process, such that the gate electrode 102 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0068] After filling the recess 98, a planarization process such as a CMP process may be performed to remove the material of the gate electrode 102 and the excess portions of the gate dielectric layer 100 that are above the top surface of the first ILD 96. After the planarization process, the surfaces of the first ILD 96, the gate electrode 102, and the gate dielectric layer 100 may be substantially coplanar or flush. The material of the gate electrode 102 and the remaining portions of the gate dielectric layer 100 thus form a replacement gate structure of the resulting nanostructure FET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a gate structure.

[0069] exist 18A to 18C In the embodiment of the present invention, a recess 99 is formed through the first ILD 96 and the CESL 94 to expose the top surface of the sacrificial layer 95. The recess 99 can be formed by one or more etching processes, such as RIE, NBE, etc. In some embodiments, the recess 99 can be formed by etching through the first ILD 96 using a first etching process and etching through the CESL 94 using a second etching process. A mask (e.g., a patterned photoresist) can be formed before the etching process and removed after the etching process.

[0070] exist FIG. 19A to FIG. 19CIn the embodiment of the present invention, the recess 99 is expanded by removing at least a portion of the sacrificial layer 95 to expose the surface of at least some of the epitaxial source / drain regions 92. At least some of the sidewalls of the first spacer 81 and the first internal spacer 90 may also be exposed. In some embodiments, a portion of the sacrificial layer 95 is retained along the bottom of the recess 99. The remaining sacrificial layer 95 may have a concave top surface and may be located on the top surface of the corresponding isolation layer 93 and on the surface of some corresponding epitaxial source / drain regions 92 adjacent to the isolation layer 93. The sacrificial layer 95 may be removed by one or more etching processes (e.g., a dry etching process, etc.). After the etching process, the epitaxial source / drain regions 92 may be substantially intact.

[0071] The sacrificial layer 95 may be removed in the n-type region 50N and the p-type region 50P in sequence. For example, when the sacrificial layer 95 is removed in the n-type region 50, the p-type region 50P may be masked, and when the sacrificial layer 95 is removed in the p-type region 50P, the n-type region 50N may be masked. The etchant used to remove the sacrificial layer 95 in the p-type region 50P may be different from the etchant used to remove the sacrificial layer 95 in the n-type region 50N. During the etching process, the etching rate of the sacrificial layer 95 may be greater than the epitaxial source / drain region 92. In the p-type region 50P, this etching selectivity may be due to the second germanium concentration of the sacrificial layer 95 being higher than the first germanium concentration of the epitaxial source / drain region 92. In the n-type region 50N, this etching selectivity may be due to the dopant (e.g., arsenic) in the epitaxial source / drain region 92 being different from the dopant (e.g., phosphorus) in the sacrificial layer 95.

[0072] exist FIG. 20A to FIG. 20C In the embodiment of the present invention, a metal layer 101 is formed in the recess 99. The metal layer 101 may fill the recess 99. The metal layer 101 may include titanium, nickel, cobalt, platinum, etc., and may be formed by electroplating, PVD, etc. A planarization process, such as a CMP process, may be performed after the metal layer 101 is formed to remove excess material from the surfaces of the first ILD 96, the CESL 94, and the gate electrode 102. After the planarization process, the surfaces of the first ILD 96, the CESL 94, the gate electrode 102, and the metal layer 101 may be substantially coplanar or flush.

[0073] exist FIG. 21A to FIG. 21CIn the embodiment of the present invention, a silicide layer 103 is formed on the epitaxial source / drain region 92. The silicide layer 103 can electrically connect the epitaxial source / drain region 92 to the remaining metal layer 101. In some embodiments, the silicide layer 103 is also formed on the remaining portion of the sacrificial layer 95. In some embodiments, the silicide layer 103 extends continuously between adjacent epitaxial source / drain regions 92 and completely fills the gap between adjacent epitaxial source / drain regions 92 on the same second nanostructure 54 stack or on adjacent second nanostructure 54 stacks. Due to the shape of the epitaxial source / drain region 92 and the silicide layer 103, the contact area between the epitaxial source / drain region 92 and the silicide layer 103 can be increased, which can reduce the resistance between the epitaxial source / drain region 92 and the silicide layer 103, thereby reducing the resistance between the epitaxial source / drain region 92 and the source / drain contact subsequently formed on the remaining metal layer 101, as described in more detail below.

[0074] The silicide layer 103 may be formed by performing a thermal annealing process to induce a reaction between the metal layer 101 and the epitaxial source / drain region 92. In an embodiment where the sacrificial layer 95 includes a semiconductor material, the thermal annealing process may further induce a reaction between the metal layer 101 and the sacrificial layer 95. Therefore, some portions of the metal layer 101, the epitaxial source / drain region 92, and the sacrificial layer 95 may become the silicide layer 103. The portion of the epitaxial source / drain region 92 in contact with the sacrificial layer 95 may remain intact after the thermal annealing process. The thermal annealing process may be performed at a temperature in a range of about 450° C. to about 850° C. for a time period in a range of about 1 second to about 3 minutes. Between two adjacent second nanostructure 54 stacks, the corresponding semiconductor layer 91, the corresponding isolation layer 93, the corresponding epitaxial source / drain region 92, the corresponding sacrificial layer 95, and the corresponding silicide layer 103 may be collectively referred to as a region 97.

[0075] exist FIG. 22A to FIG. 22C In the embodiment of the present invention, the gate structure (including the gate dielectric layer 100 and the corresponding gate electrode 102 thereon) is recessed so that a recess is formed directly above the gate structure and between the opposing portions of the first spacer 81. A gate mask 104 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the recess, and then a planarization process is performed to remove excess portions of the dielectric material extending above the first ILD 96. A gate contact formed subsequently may pass through the gate mask 104 and contact the top surface of the recessed gate electrode 102.

[0076] like FIG. 22A to FIG. 22CAs further shown, the second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0077] exist FIG. 23A to FIG. 23C In the embodiment, source / drain contacts 112 are formed through the second ILD 106 to contact the metal layer 101 , and a gate contact 114 is formed through the second ILD 106 and the gate mask 104 to contact the gate electrode 102 . FIG. 23A to FIG. 23C The structure shown may be referred to as semiconductor device 200. Source / drain contacts 112 may be electrically connected to epitaxial source / drain regions 92, and gate contacts 114 may be electrically connected to gate electrode 102. Source / drain contacts 112 and gate contacts 114 may also be referred to as conductive contacts. FIG. 21A to FIG. 21C The resistance between the epitaxial source / drain region 92 and the silicide layer 103 is reduced, and the resistance between the epitaxial source / drain region 92 and the source / drain contact 112 can also be reduced, thereby improving the performance of the semiconductor device 200 .

[0078] The source / drain contacts 112 and the gate contacts 114 may each include one or more layers, for example, a barrier layer, a diffusion layer, and a filling material. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, ruthenium, molybdenum, etc. The source / drain contacts 112 and the gate contacts 114 may be formed by electroplating, PVD, etc. A planarization process, for example, a CMP process, may be performed after forming the source / drain contacts 112 and the gate contacts 114 to remove excess material from the surface of the second ILD 106. After the planarization process, the surfaces of the source / drain contacts 112, the gate contacts 114, and the second ILD 106 may be substantially coplanar or flush.

[0079] Fig.23D Shows Fig.23C FIG. 2 is an enlarged view of region 97 of semiconductor device 200. Fig.23D In the illustrated embodiment, the epitaxial source / drain region 92 may have an arch shape, which may be aligned with the second nanostructure 54 ( Fig.23CThe epitaxial source / drain region 92 may be in contact with the corresponding second nanostructure 54 in FIG. 1 . The height H1 of the epitaxial source / drain region 92 from the second nanostructure 54 may be in the range of about 1 nm to about 8 nm, and the width W1 may be in the range of about 1 nm to about 30 nm. The width W2 of the silicide layer 103 may correspond to the distance between two opposing epitaxial source / drain regions 92 on the adjacent second nanostructure 54 stack. The width W2 may be in the range of about 3 nm to about 20 nm. The thickness T1 of the sacrificial layer 95 may be in the range of about 1 nm to about 60 nm. The thickness T1 may be the minimum thickness of the sacrificial layer 95. The width of region 97 may be about Fig. 9C The width D1 of the recess 86 corresponds to this.

[0080] Fig.23E Shown with Fig.23D An example of a similar region 97 is shown, wherein like reference numerals refer to like features. Fig.23E In the illustrated embodiment, the epitaxial source / drain region 92 may have a rectangular shape, which may be aligned with a second nanostructure 54 ( Fig.23C The height H3 of the epitaxial source / drain region 92 may be in the range of about 1 nm to about 8 nm, and the width W3 may be in the range of about 1 nm to about 30 nm. The width W1 of the silicide layer 103 may correspond to the distance between two opposing epitaxial source / drain regions 92 on the adjacent second nanostructure 54 stack.

[0081] Fig.23F Shown with Fig.23D An example of a similar region 97 is shown, wherein like reference numerals refer to like features. Fig.23F In the illustrated embodiment, the epitaxial source / drain region 92 may have a triangular shape, which may be aligned with a second nanostructure 54 ( Fig.23C The height H5 of the epitaxial source / drain region 92 may be in the range of about 1 nm to about 8 nm, the width W5 may be in the range of about 1 nm to about 30 nm, and the inner angle θ1 may be in the range of about 20° to about 60°, for example, 35° and 54°. The width W1 of the silicide layer 103 may correspond to the distance between two opposing epitaxial source / drain regions 92 on the adjacent second nanostructure 54 stack.

[0082] Figure 23G Shown with Fig.23D An example of a similar region 97 is shown, wherein like reference numerals refer to like features. Figure 23G In the illustrated embodiment, some of the epitaxial source / drain regions 92 may have an arched shape, which may be aligned with a second nanostructure 54 ( Fig.23CThe height H7 of such epitaxial source / drain region 92 may be in the range of about 1 nm to about 8 nm, and the width W7 may be in the range of about 1 nm to about 30 nm. Some epitaxial source / drain regions 92 may have a merged arch shape with a wavy surface, which may be in contact with two second nanostructures 54 and extend continuously from one second nanostructure 54 to another second nanostructure 54. The height H7 of such epitaxial source / drain region 92 may be in the range of about 1 nm to about 8 nm, the height H8 is less than the height H7, and the width W8 may be in the range of about 1 nm to about 60 nm. The height H7 may be the maximum height of the corresponding epitaxial source / drain region 92, and the height H8 may be the minimum height of the corresponding epitaxial source / drain region 92. The width W1 of the silicide layer 103 may correspond to the distance between two opposing epitaxial source / drain regions 92 on the adjacent second nanostructure 54 stack.

[0083] Fig.23H Shown with Fig.23D An example of a similar region 97 is shown, wherein like reference numerals refer to like features. Fig.23H In the illustrated embodiment, the epitaxial source / drain region 92 may have a combined arched shape with a wavy surface, which may be combined with the three second nanostructures 54 ( Fig.23C The epitaxial source / drain region 92 may be in contact with the epitaxial source / drain region 92 (as shown) and extend continuously from between the three second nanostructures 54. The height H9 of the epitaxial source / drain region 92 may be in the range of about 1 nm to about 8 nm, the height H10 may be less than the height H9, and the width W9 may be in the range of about 1 nm to about 90 nm. The height H9 may be the maximum height of the epitaxial source / drain region 92, and the height H10 may be the minimum height of the epitaxial source / drain region 92. The width W1 of the silicide layer 103 may correspond to the distance between two opposing epitaxial source / drain regions 92 on the adjacent second nanostructure 54 stack.

[0084] Fig.23I Shown with Fig.23D An example of a similar region 97 is shown, wherein like reference numerals refer to like features. Fig.23I In the illustrated embodiment, the epitaxial source / drain region 92 may have an arch shape, which may be aligned with the three second nanostructures 54 ( Fig.23C The epitaxial source / drain regions 92 may have a height H11 in the range of about 1 nm to about 8 nm, and a width W11 in the range of about 1 nm to about 90 nm. The width W1 of the silicide layer 103 may correspond to the distance between two opposing epitaxial source / drain regions 92 on the adjacent second nanostructure 54 stack.

[0085] Fig.24A , Fig. 24B and Fig.24C The following are respectively shown according to some embodiments and Fig.23A , Fig. 23B and Fig.23C The cross-section of semiconductor device 200 shown is similar to a different cross-section of semiconductor device 202, where like reference numbers refer to like features. Fig.24A , Fig. 24B and Fig.24C In the illustrated embodiment, a portion of the metal layer 101 remains between opposing epitaxial source / drain regions 92 on adjacent second nanostructure 54 stacks in at least one region 97. The silicide layer 103 may extend continuously over the surfaces of the epitaxial source / drain regions 92 and the sacrificial layer 95.

[0086] Fig.25A , Fig.25B and Fig.25C The following are respectively shown according to some embodiments and Fig.23A , Fig. 23B and Fig.23C The cross-section of semiconductor device 200 shown is similar to a different cross-section of semiconductor device 204, where like reference numbers refer to like features. Fig.25A , Fig.25B and Fig.25C In the illustrated embodiment, the sacrificial layer 95 is completely removed in at least one region 97. The silicide layer 103 may contact the top surface of the isolation layer 93 and may fill the gap between the epitaxial source / drain region 92 and the isolation layer 93. Due to the shape of the silicide layer 103, the contact area between the epitaxial source / drain region 92 and the silicide layer 103 in the semiconductor device 204 may be further increased compared to the semiconductor device 200, which may further reduce the resistance between the epitaxial source / drain region 92 and the source / drain contact 112, thereby further improving the performance of the semiconductor device 204.

[0087] Fig.26A , Fig.26B and Fig.26C The following are respectively shown according to some embodiments and Fig.23A , Fig. 23B and Fig.23C The cross-section of semiconductor device 200 shown is similar to a different cross-section of semiconductor device 206, where like reference numbers refer to like features. Fig.26A , Fig.26B and Fig.26CIn the illustrated embodiment, an etch stop layer 105 is formed on each epitaxial source / drain region 92 before forming the sacrificial layer 95. The etch stop layer 105 can separate the epitaxial source / drain region 92 from the sacrificial layer 95 and the silicide layer 103. During the thermal annealing process, the metal layer 101 and the etch stop layer 105 can react. Therefore, the portion of the etch stop layer 105 in contact with the metal layer 101 can become the silicide layer 103. The portion of the etch stop layer 105 in contact with the sacrificial layer 95 can remain intact after the thermal annealing process. The silicide layer 103 can be electrically connected to the epitaxial source / drain region 92 through the etch stop layer 105. The etch stop layer 105 can be formed by a process similar to the epitaxial source / drain region 92 and under similar conditions. The etch stop layer 105 can be subjected to an oxidation process to form an oxide layer (not shown separately) having a thickness ranging between about 0.5 nm and about 2 nm. During the etching process, the oxide layer can improve the etching selectivity between the etch stop layer 105 and the sacrificial layer 95, as described in more detail below. The oxide layer can be removed before forming the metal layer 101.

[0088] The etch stop layer 105 in the p-type region 50P may include silicon germanium, germanium, germanium tin, silicon, etc. In some embodiments, the etch stop layer 105 in the p-type region 50P includes silicon germanium having a third germanium concentration in a range of about 0% to about 30% (e.g., in a range of about 5% to about 15%), and a concentration of about 5×10 19 Atom / cm 3 About 5×10 21 Atom / cm 3 The third germanium concentration of the etch stop layer 105 may be lower than the first germanium concentration of the epitaxial source / drain regions 92 and the second germanium concentration of the sacrificial layer 95, which may result in an etch selectivity between the etch stop layer 105 and the sacrificial layer 95 in the p-type region 50P during an etching process (e.g., an etching rate of the sacrificial layer 95 is greater than an etching rate of the etch stop layer 105), the etching process removing at least a portion of each sacrificial layer 95. In some embodiments, the etch stop layer 105 in the p-type region 50P includes silicon and a dopant (e.g., boron, etc.) having a concentration of about 5×10 20 Atom / cm 3 About 5×10 22 Atom / cm 3 During the etching process, such an etching stop layer 105 also has the above-mentioned etching selectivity to the sacrificial layer 95 in the p-type region 50P. Therefore, the epitaxial source / drain region 92 is protected by the etching stop layer 105 in the p-type region 50P during the etching process.

[0089] The etch stop layer 105 in the n-type region 50N may include silicon, silicon carbide, etc. In some embodiments, the etch stop layer 105 in the n-type region 50N includes silicon doped with phosphorus, arsenic, antimony, etc., with a concentration of about 5×10 19 Atom / cm 3 About 1×10 21 Atom / cm 3 In some embodiments, in the n-type region 50N, the dopant in the sacrificial layer 95 includes phosphorus and the dopant in the etch stop layer 105 includes arsenic, which can produce an etching selectivity between the sacrificial layer 95 and the etch stop layer 105 in the n-type region 50N during the etching process of the sacrificial layer 95 (for example, the etching rate of the sacrificial layer 95 is greater than the etching rate of the etch stop layer 105). Therefore, the epitaxial source / drain region 92 is protected by the etch stop layer 105 in the n-type region 50N during the etching process.

[0090] Fig.27A , Fig.27B , Fig.27C and Fig.27D The following are respectively shown according to some embodiments and Fig.23A , Fig. 23B and Fig.23C The cross-section of semiconductor device 200 shown is similar to a different cross-section of semiconductor device 208, where like reference numbers refer to like features. Fig.27A , Fig.27B , Fig.27C and Fig.27D In the illustrated embodiment, in at least one region 97, a semiconductor layer 107 is formed on the fin 66 and a sacrificial layer 95 is formed on the semiconductor layer 107. The semiconductor layer 107 and the epitaxial source / drain region 92 may be formed during the same process, and the semiconductor layer 107 may include the same or similar material as the epitaxial source / drain region 92. The semiconductor layer 107 may be U-shaped and contact the sacrificial layer 95, the first inner spacer 90, and the fin 66. The height H13 of the semiconductor layer 107 may be in the range of about 1 nm to about 30 nm, the bottom surface is flat, and the width W13 may be in the range of about 1 nm to about 30 nm. The thickness T2 of the sacrificial layer 95 may be in the range of about 1 nm to about 60 nm. The semiconductor layer 107 in the p-type region 50P may induce strain on the adjacent second nanostructure 54, which may improve the performance of the semiconductor device 208.

[0091] The embodiments of the present disclosure have some advantageous features. By increasing the contact area between the epitaxial source / drain region 92 and the silicide layer 103 , the resistance between the epitaxial source / drain region 92 and the source / drain contact 112 can be reduced, thereby improving the performance of the semiconductor devices 200 , 202 , 204 , 206 , and 208 .

[0092] In one embodiment, a semiconductor device includes: a first plurality of nanostructures and a second plurality of nanostructures, on a substrate; a first gate stack and a second gate stack, the first gate stack extending between nanostructures in the first plurality of nanostructures, and the second gate stack extending between nanostructures in the second plurality of nanostructures; a first source / drain region in contact with a first nanostructure in the first plurality of nanostructures; a second source / drain region in contact with a first nanostructure in the second plurality of nanostructures, wherein the second source / drain region is separated from the first source / drain region; a silicide layer between the first source / drain region and the second source / drain region; and an isolation layer between the silicide layer and the substrate. In one embodiment, the semiconductor device further includes: a material layer between the silicide layer and the isolation layer, wherein the material layer is in contact with the silicide layer and the isolation layer. In one embodiment, the material layer has a higher germanium concentration than the first source / drain region and the second source / drain region. In one embodiment, the material layer is doped with phosphorus, and wherein the first source / drain region and the second source / drain region are doped with arsenic. In one embodiment, the first source / drain region contacts a second nanostructure in the first plurality of nanostructures, wherein the first source / drain region extends continuously from the first nanostructure to the second nanostructure, and wherein the first nanostructure and the second nanostructure are separated by a first gate stack. In one embodiment, the silicide layer includes a first portion in contact with the first source / drain region and a second portion in contact with the second source / drain region, wherein the metal layer is located between the first portion and the second portion. In one embodiment, the semiconductor device further includes a first etch stop layer in contact with the first source / drain region and a second etch stop layer in contact with the second source / drain region, wherein the first etch stop layer is located between the first source / drain region and the silicide layer, and the second etch stop layer is located between the second source / drain region and the silicide layer. In one embodiment, the first etch stop layer has a lower germanium concentration than the first source / drain region, and the second etch stop layer has a lower germanium concentration than the second source / drain region.

[0093] In one embodiment, a semiconductor device includes: a first plurality of nanostructures and a second plurality of nanostructures on a substrate; a first gate stack and a second gate stack, the first gate stack extending between nanostructures in the first plurality of nanostructures, and the second gate stack extending between nanostructures in the second plurality of nanostructures; a first source / drain region along a sidewall of a first nanostructure in the first plurality of nanostructures; a second source / drain region along a sidewall of a first nanostructure in the second plurality of nanostructures; a silicide layer between the first source / drain region and the second source / drain region; and a material layer between the silicide layer and the substrate. In one embodiment, the material layer has a higher germanium concentration than the first source / drain region and the second source / drain region. In one embodiment, the semiconductor device further includes: a third source / drain region along a sidewall of a second nanostructure in the first plurality of nanostructures, wherein the silicide layer is between the first source / drain region and the third source / drain region. In one embodiment, the semiconductor device further includes: a semiconductor layer between the material layer and the substrate, wherein the material layer is between the first source / drain region and the semiconductor layer, and wherein the semiconductor layer includes a material different from the substrate. In one embodiment, the semiconductor device further includes: an isolation layer located between the material layer and the substrate.

[0094] In one embodiment, a method of forming a semiconductor device includes: forming a first plurality of nanostructures and a second plurality of nanostructures on a substrate; forming a first source / drain region on a sidewall of a first nanostructure in the first plurality of nanostructures, and forming a second source / drain region on a sidewall of the first nanostructure in the second plurality of nanostructures; forming a material layer on the first source / drain region and the second source / drain region; removing at least a portion of the material layer to form an opening; forming a metal layer in the opening; and annealing to form a silicide layer from the metal layer, the first source / drain region, and the second source / drain region, wherein the silicide layer is located between the first source / drain region and the second source / drain region. In one embodiment, removing at least a portion of the material layer completely removes the material layer. In one embodiment, the material layer includes a semiconductor material, and wherein the germanium concentration of the material layer is higher than that of the first source / drain region and the second source / drain region. In one embodiment, the material layer includes a dielectric material. In one embodiment, the method further includes: before forming the material layer, forming a first etch stop layer on the first source / drain region, and forming a second etch stop layer on the second source / drain region. In one embodiment, the method further comprises: performing an oxidation process on the first etch stop layer and the second etch stop layer before forming the material layer. In one embodiment, the method further comprises: forming a dielectric layer on the substrate before forming the first source / drain region and the second source / drain region, wherein the material layer is located between the dielectric layer and the silicide layer.

[0095] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0096] Example 1 is a semiconductor device, comprising: a first plurality of nanostructures and a second plurality of nanostructures, on a substrate; a first gate stack and a second gate stack, the first gate stack extending between nanostructures in the first plurality of nanostructures, and the second gate stack extending between nanostructures in the second plurality of nanostructures; a first source / drain region in contact with a first nanostructure in the first plurality of nanostructures; a second source / drain region in contact with a first nanostructure in the second plurality of nanostructures, wherein the second source / drain region is separated from the first source / drain region; a silicide layer located between the first source / drain region and the second source / drain region; and an isolation layer located between the silicide layer and the substrate.

[0097] Example 2 is the semiconductor device described in Example 1, further comprising: a material layer located between the silicide layer and the isolation layer, wherein the material layer is in contact with the silicide layer and the isolation layer.

[0098] Example 3 is the semiconductor device of Example 2, wherein the germanium concentration of the material layer is higher than that of the first source / drain region and the second source / drain region.

[0099] Example 4 is the semiconductor device of Example 2, wherein the material layer is doped with phosphorus, and wherein the first source / drain region and the second source / drain region are doped with arsenic.

[0100] Example 5 is a semiconductor device described in Example 1, wherein the first source / drain region contacts a second nanostructure of the first plurality of nanostructures, wherein the first source / drain region extends continuously from the first nanostructure to the second nanostructure, and wherein the first nanostructure and the second nanostructure are separated by the first gate stack.

[0101] Example 6 is a semiconductor device as described in Example 1, wherein the silicide layer includes a first portion in contact with the first source / drain region and a second portion in contact with the second source / drain region, and wherein a metal layer is located between the first portion and the second portion.

[0102] Example 7 is a semiconductor device described in Example 1, further comprising: a first etch stop layer in contact with the first source / drain region and a second etch stop layer in contact with the second source / drain region, wherein the first etch stop layer is located between the first source / drain region and the silicide layer, and the second etch stop layer is located between the second source / drain region and the silicide layer.

[0103] Example 8 is the semiconductor device of Example 7, wherein the germanium concentration of the first etch stop layer is lower than that of the first source / drain region, and the germanium concentration of the second etch stop layer is lower than that of the second source / drain region.

[0104] Example 9 is a semiconductor device comprising: a first plurality of nanostructures and a second plurality of nanostructures on a substrate; a first gate stack and a second gate stack, the first gate stack extending between nanostructures in the first plurality of nanostructures, and the second gate stack extending between nanostructures in the second plurality of nanostructures; a first source / drain region along a sidewall of a first nanostructure in the first plurality of nanostructures; a second source / drain region along a sidewall of a first nanostructure in the second plurality of nanostructures; a silicide layer between the first source / drain region and the second source / drain region; and a material layer between the silicide layer and the substrate.

[0105] Example 10 is the semiconductor device of Example 9, wherein the germanium concentration of the material layer is higher than that of the first source / drain region and the second source / drain region.

[0106] Example 11 is the semiconductor device described in Example 9, further comprising: a third source / drain region along a sidewall of a second nanostructure in the first plurality of nanostructures, wherein the silicide layer is located between the first source / drain region and the third source / drain region.

[0107] Example 12 is the semiconductor device described in Example 9, further comprising: a semiconductor layer located between the material layer and the substrate, wherein the material layer is located between the first source / drain region and the semiconductor layer, and wherein the semiconductor layer includes a material different from that of the substrate.

[0108] Example 13 is the semiconductor device described in Example 9, further comprising: an isolation layer located between the material layer and the substrate.

[0109] Example 14 is a method for forming a semiconductor device, the method comprising: forming a first plurality of nanostructures and a second plurality of nanostructures above a substrate; forming a first source / drain region on a sidewall of a first nanostructure in the first plurality of nanostructures, and forming a second source / drain region on a sidewall of a first nanostructure in the second plurality of nanostructures; forming a material layer on the first source / drain region and the second source / drain region; removing at least a portion of the material layer to form an opening; forming a metal layer in the opening; and annealing to form a silicide layer from the metal layer, the first source / drain region, and the second source / drain region, and wherein the silicide layer is located between the first source / drain region and the second source / drain region.

[0110] Example 15 is the method described in Example 14, wherein removing at least a portion of the material layer completely removes the material layer.

[0111] Example 16 is the method of Example 14, wherein the material layer includes a semiconductor material, and wherein a germanium concentration of the material layer is higher than that of the first source / drain region and the second source / drain region.

[0112] Example 17 is the method of Example 14, wherein the material layer includes a dielectric material.

[0113] Example 18 is the method described in Example 14, further comprising: before forming the material layer, forming a first etch stop layer on the first source / drain region, and forming a second etch stop layer on the second source / drain region.

[0114] Example 19 is the method described in Example 18, further comprising: performing an oxidation treatment on the first etch stop layer and the second etch stop layer before forming the material layer.

[0115] Example 20 is the method described in Example 14, further comprising: forming a dielectric layer on the substrate before forming the first source / drain region and the second source / drain region, wherein the material layer is located between the dielectric layer and the silicide layer.

Claims

1. A semiconductor device, comprising: a first plurality of nanostructures and a second plurality of nanostructures over a substrate; a first gate stack extending between nanostructures in the first plurality of nanostructures and a second gate stack extending between nanostructures in the second plurality of nanostructures; a first source / drain region in contact with a first nanostructure of the first plurality of nanostructures; a second source / drain region in contact with a first nanostructure of the second plurality of nanostructures, wherein the second source / drain region is separated from the first source / drain region; a silicide layer located between the first source / drain region and the second source / drain region; and An isolation layer is located between the silicide layer and the substrate.

2. The semiconductor device according to claim 1, further comprising: A material layer is located between the silicide layer and the isolation layer, wherein the material layer is in contact with the silicide layer and the isolation layer.

3. The semiconductor device according to claim 2, wherein: The germanium concentration of the material layer is higher than that of the first source / drain region and the second source / drain region.

4. The semiconductor device according to claim 2, wherein: The material layer is doped with phosphorus, and wherein the first source / drain region and the second source / drain region are doped with arsenic.

5. The semiconductor device according to claim 1, wherein The first source / drain region contacts a second nanostructure of the first plurality of nanostructures, wherein the first source / drain region extends continuously from the first nanostructure to the second nanostructure, and wherein the first nanostructure and the second nanostructure are separated by the first gate stack.

6. The semiconductor device according to claim 1, wherein The silicide layer includes a first portion in contact with the first source / drain region and a second portion in contact with the second source / drain region, and wherein a metal layer is located between the first portion and the second portion.

7. The semiconductor device according to claim 1, further comprising: A first etch stop layer in contact with the first source / drain region and a second etch stop layer in contact with the second source / drain region, wherein the first etch stop layer is located between the first source / drain region and the silicide layer, and the second etch stop layer is located between the second source / drain region and the silicide layer.

8. The semiconductor device according to claim 7, wherein: The germanium concentration of the first etch stop layer is lower than that of the first source / drain region, and the germanium concentration of the second etch stop layer is lower than that of the second source / drain region.

9. A semiconductor device comprising: a first plurality of nanostructures and a second plurality of nanostructures over a substrate; a first gate stack extending between nanostructures in the first plurality of nanostructures and a second gate stack extending between nanostructures in the second plurality of nanostructures; a first source / drain region along a sidewall of a first nanostructure of the first plurality of nanostructures; a second source / drain region along a sidewall of a first nanostructure in the second plurality of nanostructures; a silicide layer, located between the first source / drain region and the second source / drain region; as well as A material layer is located between the silicide layer and the substrate.

10. A method for forming a semiconductor device, the method comprising: forming a first plurality of nanostructures and a second plurality of nanostructures over a substrate; forming a first source / drain region on a sidewall of a first nanostructure in the first plurality of nanostructures, and forming a second source / drain region on a sidewall of a first nanostructure in the second plurality of nanostructures; forming a material layer on the first source / drain region and the second source / drain region; removing at least a portion of the material layer to form an opening; forming a metal layer in the opening; as well as Annealing is performed to form a silicide layer from the metal layer, the first source / drain region, and the second source / drain region, and wherein the silicide layer is located between the first source / drain region and the second source / drain region.

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