Semiconductor structure and forming method thereof

Abstract

Methods to form low contact resistance contacts to source / drain features are provided. A method of the present disclosure includes receiving a workpiece including an opening exposing a surface of an n-type source / drain feature and a surface of a p-type source / drain feature; selectively depositing a first silicide layer on a surface of the p-type source / drain feature while a surface of the n-type source / drain feature is substantially free of the first silicide layer; depositing a metal layer on the surfaces of the first silicide layer and the n-type source / drain feature; a second silicide layer is deposited over the metal layer. The selective deposition includes: passivating a surface of the n-type source / drain feature by a self-assembled layer; depositing a first silicide layer on a surface of the p-type source / drain feature; and removing the self-assembly layer. According to an embodiment of the invention, a semiconductor structure and a forming method thereof are provided.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous one. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or wire) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., a gate wraps around the top and sidewalls of a "fin" of a semiconductor material extending from a substrate). The gate structure of an MBC transistor may extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, an MBC transistor may also be referred to as a gate-around transistor (SGT) or a gate-all-around (GAA) transistor. The channel region of the MBC transistor may be formed of nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also provides alternative names for the MBC transistor, such as nanosheet transistor or nanowire transistor.

[0004] As the semiconductor industry continues to advance in pursuit of higher device density, higher performance, and lower cost, challenges posed by manufacturing and design issues have led to stacked device structure configurations, such as complementary field effect transistors (C-FETs). Although existing C-FET structures are generally adequate for their intended purposes, they are not satisfactory in all aspects. Summary of the invention

[0005] According to one embodiment of the present application, a semiconductor structure is provided, including: a fin structure generated from a substrate; an isolation component surrounding the fin structure; a first type epitaxial component disposed above the fin structure; a first contact etch stop layer disposed on the first type epitaxial component and the isolation component; a first dielectric layer disposed above the first contact etch stop layer; a second type epitaxial component disposed on the first dielectric layer; a second contact etch stop layer disposed on the first dielectric layer and the second type epitaxial component; a second dielectric layer disposed above the second contact etch stop layer; and a contact structure. The contact structure includes: a top portion extending through the second dielectric layer and the second contact etch stop layer, and contacting the second type epitaxial component through a first metal silicide layer and a dipole layer; and a bottom portion disposed below the top portion, the bottom portion extending through the second type epitaxial component, the first dielectric layer, and the first contact etch stop layer, and contacting the first type epitaxial component through the first metal silicide layer, the dipole layer, and the second metal silicide layer, wherein the first metal silicide layer and the second metal silicide layer have different metal compositions.

[0006] According to another embodiment of the present application, a semiconductor structure is provided, including: a first plurality of nanostructures extending between a first p-type source / drain component and a second p-type source / drain component; a second plurality of nanostructures arranged above the first plurality of nanostructures, the second plurality of nanostructures extending between a first n-type source / drain component and a second n-type source / drain component; a first contact contacting a top surface of the first n-type source / drain component through a first metal silicide layer and an n-type dipole layer; and a second contact contacting a top surface of the second p-type source / drain component through the first metal silicide layer, the n-type dipole layer, and the second metal silicide layer, wherein the first metal silicide layer and the second metal silicide layer have different metal compositions.

[0007] According to another embodiment of the present application, a method for forming a semiconductor structure is provided, comprising: receiving a workpiece including an opening exposing a surface of an n-type source / drain component and a surface of a p-type source / drain component; selectively depositing a first silicide layer on the surface of the p-type source / drain component, while the surface of the n-type source / drain component is substantially free of the first silicide layer; after the selective deposition, depositing a metal layer on the first silicide layer and the surface of the n-type source / drain component; depositing a second silicide layer over the metal layer; and depositing a metal filling layer over the second silicide layer, wherein the selective deposition comprises: passivating the surface of the n-type source / drain component by a self-assembled layer, depositing the first silicide layer on the surface of the p-type source / drain component after the passivation, and removing the self-assembled layer after the selective deposition of the first silicide layer.

[0008] Embodiments of the present application relate to stacked multi-gate devices with reduced contact resistance and methods of forming the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0010] Figure 1 A flow chart illustrating a method for forming low resistance source / drain contacts for a C-FET structure according to one or more aspects of the present disclosure;

[0011] Figure 2-Figure 15 According to one or more aspects of the present disclosure, Figure 1 A partial cross-sectional view of a workpiece undergoing various manufacturing processes in a method;

[0012] Fig.16 A mechanism for selectively depositing a first silicide layer on a p-type source / drain feature according to one or more aspects of the present disclosure is shown;

[0013] Figure 17-Figure 19 An alternative mechanism for selectively depositing a first silicide layer on p-type source / drain features in accordance with one or more aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] For ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] In addition, when "about," "approximately," etc. are used to describe a number or a range of numbers, the term is intended to encompass numbers within a reasonable range that take into account variations inherently caused during manufacturing as understood by a person of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing a component having the features associated with the number, the number or range of numbers encompasses a reasonable range that includes the described number, for example, within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" may encompass a size range from 4.25 nm to 5.75 nm, where a person of ordinary skill in the art knows that the manufacturing tolerance associated with depositing material layers is + / - 15%.

[0017] A stacked multi-gate device refers to a semiconductor device comprising a first multi-gate device and a second multi-gate device stacked above the first multi-gate device. When the first multi-gate device and the second multi-gate device have different conductivity types, the stacked multi-gate device can be a complementary field effect transistor (C-FET). The multi-gate device in the C-FET can be a FinFET or an MBC transistor. Vertical stacking poses challenges to the formation of source / drain components. In some cases, the contact component can extend through the top source / drain component to contact the bottom source / drain component. This raises concerns about increased contact resistance because longer source / drain contact components and smaller contact areas may increase contact resistance. In some existing schemes, the source / drain contact is interfaced with the n-type and p-type source / drain components through the same type of metal silicide components. It is hoped that the contact resistance with the source / drain component will be further reduced.

[0018] The present disclosure provides a process for selectively depositing a first silicide layer on a p-type source / drain component to reduce contact resistance. The n-type source / drain component may include silicon and an n-type dopant, and the p-type source / drain component may include silicon germanium and a p-type dopant. In one embodiment, a metal precursor selective to a silicon germanium surface is used to selectively deposit a first silicide layer on a p-type source / drain component. In another embodiment, before the first silicide layer is deposited on the p-type source / drain component, a self-assembled monolayer (SAM) barrier layer is selectively deposited on a germanium-free surface. After the selective deposition of the first silicide layer, an n-type dipole layer is deposited on the first silicide layer and the n-type source / drain component in the entire region. Then a second silicide layer is deposited on the n-type dipole layer. The interface between the first silicide layer reduces the contact resistance between the p-type source / drain component, and the interface between the n-type dipole layer reduces the contact resistance between the n-type source-drain component. In some cases, by using the disclosed process, the contact resistance to both p-type and n-type source / drain features can be reduced to less than 1×10 -9 ohm-cm2 .

[0019] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 1 is a flow chart illustrating a method 100 for forming low resistance source / drain contacts in a stacked multi-gate structure. The method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly described in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, removed, or relocated for additional embodiments of the method. For simplicity, not all steps are described in detail. Figure 2-Figure 15 Describing method 100, Figure 2-Figure 15 are partial cross-sectional views of a workpiece 200 at various stages of manufacture according to an embodiment of the method 100 . Figure 16-Figure 19 Two exemplary mechanisms for selectively depositing a silicide layer on a p-type source / drain feature are shown. Since the workpiece 200 will be manufactured into a semiconductor structure 200 at the end of the manufacturing process, the workpiece 200 may be referred to as a semiconductor structure 200 as the context requires. In addition, throughout this application, the same reference numerals denote the same components unless otherwise specified.

[0020] refer to Figure 1 , Figure 2 ,and Figure 3 , the method 100 includes a block 102, wherein a workpiece 200 is provided. Figure 2 and Figure 3As shown, the workpiece 200 includes a stacked multi-gate device structure formed on a substrate 202. In the described embodiment, the stacked multi-gate device structure is a C-FET structure. The substrate 202 may include: elemental (single element) semiconductors, such as silicon (Si), germanium (Ge), and / or other suitable materials; compound semiconductors (i.e., alloy semiconductors), such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), and / or other suitable materials. The substrate 202 may be a single layer of material having a uniform composition. Alternatively, the substrate may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, the substrate can be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a buried silicon oxide (BOX) layer. In some embodiments, the substrate includes various doped regions, such as an n-type well or a p-type well. Depending on the design requirements, the doped regions can be doped with n-type dopants such as phosphorus (P) or arsenic (As), and / or p-type dopants such as boron (B) or BF2. The doped regions can be formed by implantation of doping atoms, in-situ doping epitaxial growth, and / or other suitable techniques. In the described embodiments, the substrate 202 includes silicon (Si).

[0021] refer to Figure 2 and Figure 3 The workpiece 200 includes an active region extending longitudinally along the X direction, and a gate structure (including an upper gate structure 240N and a lower gate structure 240P) extending longitudinally along the Y direction. Figure 3 Cut along the Y direction, and Figure 2 Along Figure 3 The A-A' line is cut along the X direction. Figure 2 and Figure 3, a portion of the substrate 202 is patterned into a fin structure 205. The fin structure 205 rises continuously from the substrate 202 and is surrounded by an isolation component 207. The isolation component 207 may include silicon oxide. A plurality of channel members 2080 are disposed above the channel region of the fin structure 205. The active region includes a plurality of channel members 2080, including a lower channel member 2080L, an intermediate channel member 2080M, and an upper channel member 2080U. Similar to the fin structure 205, the plurality of channel members 2080 extend along the X direction. The fin structure 205 and the channel member 2080 may be collectively referred to as an active region. Along the Z direction, the plurality of channel members 2080 are interlaced by an internal spacer component 216. In some embodiments, the internal spacer component 216 includes silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a combination thereof. Channel member 2080 may also be referred to as a nanostructure, nanosheet, or nanowire, depending on size and shape. In the described embodiment, lower channel member 2080L is used as a channel for a bottom multi-gate device, and upper channel member 2080U is used as a channel for a top multi-gate device. Intermediate channel member 2080M is vertically spaced apart by intermediate dielectric layer 211 and, as described below, is disabled.

[0022] exist Figure 2 In some embodiments represented, the active area can be divided into multiple sections along the X direction by multiple dielectric components 209. In the described embodiment, each dielectric component 209 includes an outer layer 204 and an inner layer 206. In some embodiments, the dielectric constant of the outer layer 204 is greater than the dielectric constant of the inner layer 206. The outer layer 206 is more etch-resistant than the inner layer 204. In some embodiments, the outer layer 204 includes a nitrogen-containing dielectric material, such as silicon nitride, silicon carbonitride, silicon oxynitride, or silicon oxycarbonitride. The inner layer 204 may include an oxygen-containing dielectric material, such as silicon oxide.

[0023] exist Figure 3 In some of the embodiments represented, the active region may be separated from adjacent active regions by dielectric fins 215. Figure 3 As shown, the dielectric fin 215 may extend at least partially into the isolation feature 207. In some embodiments, the dielectric fin 215 may include silicon nitride, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride.

[0024] The workpiece 200 also includes a lower gate structure 240P and an upper gate structure 240N. Figure 2As shown, the lower gate structure 240P wraps around the lower channel member 2080L, and the upper gate structure 240N wraps around the upper channel member 2080U. Each of the lower gate structure 240P and the upper gate structure 240N includes an interface layer 212 intersecting the channel member, a gate dielectric layer 213 located above the interface layer 212, and at least one work function layer. In some embodiments, the interface layer 212 includes silicon oxide and can be formed on a semiconductor surface (e.g., a silicon surface) in a pre-cleaning process. An exemplary pre-cleaning process may include using RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The gate dielectric layer 213 can be formed by a high-k dielectric material. As used and described herein, a high-k dielectric material includes a dielectric material having a high dielectric constant, for example, a dielectric constant greater than that of thermal silicon oxide (~3.9). In one embodiment, the gate dielectric layer 213 includes hafnium oxide. Alternatively, the gate dielectric layer 213 may include other high-K dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium oxide silicide (HfSiO4), zirconium dioxide (ZrO2), zirconium oxide silicide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum oxide silicide (LaSiO), aluminum oxide silicide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. In some embodiments, the intermediate dielectric layer 211 is formed together with the inner spacer component 216 and shares the same composition as the inner spacer component 216. It should be noted that due to the presence of the intermediate dielectric layer 211 and the isolation layer disposed between the lower gate structure 240P and the upper gate structure 240N, neither the lower gate structure 240P nor the upper gate structure 240N extends between the two middle channel components 2080M. The sidewalls of the portion of the upper gate structure 240N above the upper channel component 2080U are lined with gate spacers 214. The gate spacers 214 can be a single layer or multiple layers. Figure 2 In the depicted embodiment, gate spacer 214 may include a first spacer in contact with upper gate structure 240N and a second spacer spaced apart from upper gate structure 240N by the first spacer. In some cases, gate spacer 214 includes silicon nitride, silicon oxycarbonitride, silicon oxynitride, or silicon carbonitride.

[0025] In the described embodiments, the lower gate structure 240P is a p-type gate structure and the upper gate structure 240N is an n-type gate structure. In these embodiments, the lower gate structure 240P and the upper gate structure 240N have different work function layer compositions. In some embodiments, the lower gate structure 240P includes at least one p-type work function layer and the upper gate structure 240N includes at least one n-type work function layer. Exemplary p-type work function layer materials include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN), zirconium silicide (ZrSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), nickel silicide (NiSi2), other p-type work function materials, or combinations thereof. Exemplary n-type work function layer materials include titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum nitride (TaSiN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), other n-type work function materials, or combinations thereof. In some embodiments, a metal gate cap layer may be deposited over the upper gate structure 240N. The metal gate cap layer may include tungsten (W). In some alternative embodiments, the lower gate structure 240P and the upper gate structure 240N may share the same composition except for the metal gate cap layer found only in the upper gate structure 240N.

[0026] The lower channel member 2080L extends between the two p-type source / drain features 220P along the X direction. The upper channel member 2080U extends between the two n-type source / drain features 220N along the X direction. Due to their relative positions, the p-type source / drain feature 220P may be referred to as a bottom source / drain feature 220P, and the n-type source / drain feature 220N may be referred to as a top source / drain feature 220N. In some embodiments, the p-type source / drain feature 220P includes silicon germanium (SiGe) and a p-type dopant such as boron (B) or boron difluoride (BF2), while the n-type source / drain feature 220N includes silicon (Si) and an n-type dopant such as phosphorus (p). The p-type source / drain feature 220P and the n-type source / drain feature 220N are deposited using an epitaxial deposition method such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), or molecular beam epitaxy (MBE). For this reason, the p-type source / drain feature 220P may be referred to as a p-type epitaxial feature, and the n-type source / drain feature 220N may be referred to as an n-type epitaxial feature. The p-type source / drain feature 220P and the n-type source / drain feature 220N disposed just above are disposed between two adjacent dielectric fins 215.

[0027] In the described embodiment, the p-type source / drain component 220P is not directly deposited on the substrate 202 to reduce body leakage. Instead, the p-type source / drain component 220P is spaced apart from the substrate by means of a leakage barrier layer (not shown). In some embodiments, the leakage barrier layer may include an undoped semiconductor material, such as undoped silicon, undoped germanium, or undoped silicon germanium. In some other embodiments, the leakage barrier layer includes a dielectric material, such as silicon oxide or silicon nitride. When the leakage barrier layer is formed of a semiconductor material, it can be deposited using an epitaxial deposition method such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), and molecular beam epitaxy (MBE). When the leakage barrier layer is formed of a dielectric material, it can be deposited using chemical vapor deposition (CVD) deposition or a suitable deposition method.

[0028] like Figure 2 As shown, each p-type source / drain component 220P and each n-type source / drain component 220N may include more than one epitaxial layer. In some embodiments, the p-type source / drain component 220P may include a first epitaxial layer 221 in contact with the sidewall of the lower channel member 2080L, and a second epitaxial layer 222 located above the first epitaxial layer 211. The second epitaxial layer 222 may include a greater germanium content and a greater p-type dopant concentration than the first epitaxial layer 221 to reduce defects caused by lattice mismatch. In some embodiments, the n-type source / drain component 220N may include a third epitaxial layer 223 in contact with the sidewall of the upper channel member 2080U, and a fourth epitaxial layer 224 located above the third epitaxial layer 223. The fourth epitaxial layer 224 may include a greater N-type dopant concentration than the third epitaxial layer 223 to reduce contact resistance.

[0029] Still reference Figure 2 and Figure 3 The workpiece 200 includes a lower contact etch stop layer (CESL) 232 and a lower interlayer dielectric (ILD) layer 234 located above the p-type source / drain features 220P. The workpiece 200 also includes an upper CESL 236 located above the n-type source / drain features 220N, and an upper ILD layer 238 located above the upper CESL 236. In some embodiments, the lower CESL 232 and the upper CESL 236 include silicon nitride or silicon oxynitride, and the lower ILD layer 234 and the upper ILD layer 238 include silicon oxide. Figure 3As shown, the lower CESL 232 conformally covers the top surface of the isolation feature 207, the sidewalls (or portions thereof) of the gate spacer 214 disposed along the sidewalls of the fin structure 205, and the exposed surfaces of the p-type source / drain feature 220P. The lower ILD layer 234 fills the gap left by the lower CESL 232. The upper CESL 236 conformally covers the top surface of the lower ILD layer 234 and the exposed surfaces of the n-type source / drain feature 220N.

[0030] Still reference Figure 2 and Figure 3 As a result of the planarization process, top surfaces of the gate spacer 214, the upper gate structure 240N, the upper CESL 236, and the upper ILD layer 238 are all coplanar. The workpiece 200 also includes an etch stop layer (ESL) 242 located on the upper ILD layer 238, the upper CESL 236, the gate spacer 214, the dielectric feature 209, and the upper gate structure 240N, and an ILD layer 244 located on the ESL 242. In some embodiments, the ESL 242 may include silicon nitride or silicon oxynitride, and the ILD layer 244 may include silicon oxide.

[0031] refer to Figure 1 and Figure 4-Figure 7 , method 100 includes block 104, where source / drain contact openings are formed. The operations at block 104 include forming a patterned mask, forming source / drain contact openings to expose n-type source / drain features 220N, selectively extending at least one source / drain contact opening to reach p-type source / drain features 220P, and removing the hard mask layer. It should be noted that Figure 4 , Figure 6 ,and Figure 8 shows a cross-sectional view along the X direction, and Figure 5 and Figure 7 A cross-sectional view along the Y direction is shown. Figure 4 , Figure 6 , Figure 8 ,and Fig.12 The p-type source / drain feature 220P and the n-type source / drain feature 220N shown on the right-hand side of the Figure 5 and Figure 7 The counterpart shown on the right-hand side is different.

[0032] First, one or more hard mask layers are deposited above the ILD layer 244. One or more hard mask layers can be tungsten carbide (WC), silicon oxide, amorphous silicon (a-Si), or silicon nitride. Each hard mask layer can be deposited using physical vapor deposition (PVD), CVD, ALD, or a suitable deposition method. Photolithography can be used to pattern one or more hard mask layers. In an exemplary process, a photoresist layer is deposited above the workpiece 200, including one or more hard mask layers. The photoresist layer is patterned using a photolithography process. The photolithography process can include soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. Then, the patterned photoresist layer is applied as an etching mask to etch one or more hard mask layers below to form a patterned hard mask. The etching process can include dry etching (e.g., RIE etching) or other etching methods.

[0033] Then refer to Figure 4 and Figure 5 , the patterned hard mask layer is applied as an etching mask to etch through the ILD layer 244, the ESL 242, the upper ILD layer 238, and the upper CESL 236 to form a first contact opening 260, a second contact opening 262, and a third contact opening 264. An anisotropic etching process may be used. For example, the anisotropic etching process may be a reactive ion etching (RIE) process including using a bromine-containing gas (e.g., HBr and / or CHBr3), a fluorine-containing gas (e.g., CF4, SF6, NF3, CH2F2, CHF3, and / or C2F6), a carbon-containing gas (e.g., CH4 or C2H6), other suitable gases, or combinations thereof. Each of the first contact opening 260, the second contact opening 262, and the third contact opening 264 exposes a portion of the n-type source / drain feature 220N.

[0034] Reference now Figure 6 and Figure 7The second contact opening 262 partially extends further toward the substrate 202 to form a first extension opening 272. The third contact opening 264 partially extends further toward the substrate 202 to form a second extension opening 274. Each of the first extension opening 272 and the second extension opening 274 exposes the p-type source / drain feature 220P and the n-type source / drain feature 220N thereon. To form the first extension opening 272 and the second extension opening 274, a bottom anti-reflective coating (BARC) layer may be deposited over the workpiece 200 to protect the contact openings that do not extend further toward the substrate 202. After the BARC layer is deposited, a photolithography process and an etching process are then performed to form the first extension opening 272 and the second extension opening 274. Each of the first extension opening 272 and the second extension opening 274 extends through the n-type source / drain feature 220N, the lower ILD layer 234, and the lower CESL 232 to expose the p-type source / drain feature 220P.

[0035] refer to Figure 1 and Figure 8-Figure 11 , the method 100 includes block 106, in which a first silicide layer 280 is selectively deposited on the exposed p-type source / drain feature 220P. The operations at block 106 may include conformal deposition of the sidewall liner 269, anisotropic etching to remove a portion of the sidewall liner 269 to expose the p-type source / drain feature 220P and the n-type source / drain feature 220N, and selectively depositing the first silicide layer 280. Figure 8 and Fig. 9 , using chemical vapor deposition (CVD), a sidewall liner 269 is conformally deposited over the first contact opening 260, the first extension opening 272, and the second extension opening 274. In some cases, the sidewall liner 269 includes silicon nitride. Then refer to Fig.10 and Fig.11 , anisotropic etching is performed to remove the sidewall liner 269 deposited on the top-facing surface. The anisotropic etching exposes the n-type source / drain feature 220N in the first contact opening 260, the n-type source / drain feature 220N and the p-type source / drain feature 220P in the first extension opening 272, and the n-type source / drain feature 220N and the p-type source / drain feature 220P in the second extension opening 274. Still referring to Fig.10 and Fig.11 , the first silicide layer 280 is selectively deposited on the exposed surface of the p-type source / drain feature 220P, but is substantially not deposited on other surfaces formed of silicon or dielectric materials. For example, the present disclosure provides two mechanisms for selectively depositing the first silicide layer 280 on the p-type source / drain feature 220P. Fig.16A first mechanism is shown, where the precursor of the first silicide layer 280 is more likely to react with a silicon germanium surface (or germanium-containing surface) due to a lower energy barrier. Figure 17-Figure 19 A second mechanism is shown where a surface passivation layer 300 (or surface barrier layer 300 ) is deposited on a germanium-free surface, such as a silicon, silicon oxide, or silicon nitride surface, prior to depositing the first silicide layer 280 .

[0036] It should be noted that the first mechanism and the second mechanism can be implemented separately or sequentially. In one embodiment, the first mechanism can be used to selectively deposit the first silicide layer on the p-type source / drain component 220P. In some embodiments not explicitly shown, when the first mechanism is used, any unintentional deposition of the first silicide layer 280 on the n-type source / drain component 220N can be removed by a cleaning or selective etching process. In another embodiment, the second mechanism can be used to selectively deposit the first silicide layer on the p-type source / drain component 220P by first forming a surface passivation layer 300 on a germanium-free surface. In yet another embodiment, both the first mechanism and the second mechanism can be used together. The surface passivation layer 300 is first formed on the germanium-free surface, and then the first silicide layer 280 is deposited on the p-type source / drain component 220P.

[0037] First reference Fig.16 . Fig.16 Surfaces exposed when depositing the first silicide layer 280 are schematically shown. For example, the ILD layer 244 may include silicon oxide, the ESL 242 may include silicon nitride, the sidewall liner 269 may include silicon nitride, the lower ILD layer 234 may include silicon oxide, the lower CESL 232 may include silicon nitride, and the n-type source / drain feature 220N may include silicon. Fig.16 In the first mechanism shown, a precursor with a lower energy barrier is used to react with germanium on the p-type source / drain feature 220P to deposit the first silicide layer 280. In some embodiments, the first silicide layer 280 includes tungsten (W), molybdenum (Mo), ruthenium (Ru), nickel (Ni), or cobalt (Co). In these embodiments, the precursor may include tungsten chloride (WCl5), molybdenum chloride (MoCl5), diazadiene-nickel-butadiene compound (Ni(DAD)2), diazadiene-cobalt-butadiene compound (Co(DAD)2), ruthenium (II) complex (e.g., C 10 H 14 R6H 10 , C 16 H 22O6Ru, or Ru(C5H4C2H5)2), or a metal organic precursor including tungsten (W), molybdenum (Mo), ruthenium (Ru), nickel (Ni), or cobalt (Co). Among these examples, it can be considered that diazadiene-nickel-butadiene compound (Ni(DAD)2), diazadiene-cobalt-butadiene compound (Co(DAD)2), ruthenium (II) complex (e.g., C 10 H 14 R6H 10 , C 16 H 22 O6Ru, or Ru(C5H4C2H5)2) is a metal organic precursor. In some embodiments, the precursor can be selectively deposited on the exposed surface of the p-type source / drain component 220P using ALD, plasma enhanced ALD (PEALD), CVD, plasma enhanced CVD (PECVD), or PVD. In one embodiment, the first silicide layer 280 is deposited using ALD or PEALD. In some cases, the deposition can be performed at a temperature between about 250°C and about 450°C (including about 350°C and about 450°C) and at a pressure between about 10mTorr to about 760mTorr. Within the aforementioned temperature range, the metal precursor reacts with the silicon and germanium in the p-type source / drain component 220P to form the first silicide layer 280. In one embodiment in which the precursor includes molybdenum, the first silicide layer 280 includes molybdenum germanium silicon (or molybdenum germanium silicon).

[0038] exist Fig.16In the illustrated embodiment, the first silicide layer 280 may be deposited to have a thickness between about 3 nm and about 6.5 nm, while no substantial growth of the first silicide layer 280 is observed on the silicon oxide, silicon nitride, or silicon surface. This thickness range is not insignificant. According to the present disclosure, the first silicide layer 280 also serves as a diffusion barrier to block the n-type dipole layer 282 (described in detail below) from diffusing into the p-type source / drain feature 220P. Since the interdiffusion of metals at the process temperatures described herein may result in a diffusion depth of about 2 nm, when the first silicide layer 280 is thinner than 3 nm, the metal in the n-type dipole layer 282 may diffuse into the p-type source / drain feature 220P. When this occurs, the contact resistance to the p-type source / drain feature 220P will increase, thereby compromising the overall effort to selectively deposit the first silicide layer 280 in the first location. When the thickness of the first silicide layer 280 is greater than 6.5 nm, excessive first silicide layer 280 may be deposited on the n-type source / drain features 220N, which may increase the contact resistance to the n-type source / drain features, although this is unintentional. When the first mechanism is adopted, impurities in the precursor may remain in the first silicide layer 280. Exemplary impurity compositions may include chlorine (Cl), carbon (C), nitrogen (N), or fluorine (F).

[0039] Reference now Figure 17-Figure 19 .and Fig.16 similar, Fig.17Schematically showing the surfaces exposed when the first silicide layer 280 is deposited, including silicon oxide surface, silicon nitride surface, silicon surface (n-type source / drain component 220N), and silicon germanium surface (p-type source / drain component 220P). Different from the first mechanism, a self-assembled monolayer (SAM) layer is selectively formed on a germanium-free surface, such as a silicon oxide surface, a silicon nitride surface, or a silicon surface, to form a surface passivation layer 300. The SAM layer may include polymer chains and functional groups that react with dangling hydroxyl bonds on the germanium-free surface, but are unlikely to react with germanium or germanium oxide surfaces. Germanium is easily oxidized, which is why germanium oxide is often present on the germanium surface. For example, the SAM layer may include dithiothreitol, 3-(trimethoxysilyl) propanethiol, or other functional groups containing thiol. The surface passivation layer 300 formed by the SAM layer may serve as an inhibitor of the precursor of the first silicide layer 280. Once the surface passivation layer 300 is formed on the silicon oxide surface, the silicon nitride surface, and the silicon surface, the first silicide layer 280 may be deposited using the above-mentioned precursors or ALD deposition process, the ALD deposition process including using a metal-containing precursor (e.g., molybdenum chloride (MoCl5)), a silicon-containing precursor (e.g., silane (SiH4), disilane (Si2H6), or dichlorosilane (SiCl2H2)), and / or a germanium-containing precursor (e.g., germanium (GeH4)). Due to the formation of the surface passivation layer 300, the first silicide layer 280 may be selectively formed on the exposed surface of the p-type source / drain feature 220P, such as Fig.18 After depositing the first silicide layer 280, the surface passivation layer 300 may be removed by ashing, as shown in FIG. Fig.19 Exemplary ashing processes include treatment using argon (Ar), helium (He), nitrogen (N2), or hydrogen (H2) plasma.

[0040] refer to Figure 1 , Fig.12 ,and Fig.13, the method 100 includes block 108, where an n-type dipole layer 282 is globally deposited over the workpiece 200. In some embodiments, the n-type dipole layer 282 includes zirconium (Zr), hafnium (Hf), antimony (Sb), cerium (Ce), scandium (Sc), yttrium (Y), ytterbium (Yb), erbium (Er), or lanthanum (La). The n-type dipole layer 282 can be deposited using ALD or PEALD at a temperature between about 50° C. and about 450° C. and a pressure between 10 mTorr and about 760 mTorr. The precursor for depositing the n-type dipole layer 282 may include zirconium chloride (ZrCl), hafnium chloride (HfCl), antimony chloride (SbCl), tris(dimethylamino)antimony, tris(ethylsilyl)antimony, tris(trimethylsilyl)antimony, or an organic precursor of cerium (Ce), scandium (Sc), yttrium (Y), ytterbium (Yb), erbium (Er), or lanthanum (La). In some embodiments, the n-type dipole layer 282 may be formed to a thickness between 0.5 nm and 1.5 nm to completely cover the surface of the contact opening, the exposed surface of the n-type source / drain feature 220N, and the first silicide layer 280. The above-mentioned precursors may introduce impurities into the n-type dipole layer 282. For example, the n-type dipole layer 282 may include chlorine (Cl), carbon (C), oxygen (O), nitrogen (N), or fluorine (F).

[0041] refer to Figure 1 , Fig.14 ,and Fig.15 , the method 100 includes a frame 110, wherein a second silicide layer 284 is deposited globally over the workpiece 200. The second silicide layer 284 has a different metal composition than the first silicide layer 280 or the n-type dipole layer 282. In other words, the second silicide layer 284 is formed of a metal that is not present in the first silicide layer 280 or the n-type dipole layer 282. In some embodiments, the second silicide layer 284 includes titanium (Ti) and is deposited using ALD, PEALD, CVD, PECVD, or a suitable deposition method. The precursors used to deposit the second silicide layer 284 may include a titanium-containing precursor (e.g., titanium tetrachloride) and a silicon-containing precursor (e.g., silane (SiH4), disilane (Si2H6), or dichlorosilane (SiCl2H2)). The second silicide layer 284 may be deposited at a temperature between about 250° C. and about 450° C., inclusive, and at a pressure between about 10 mTorr and about 760 mTorr.

[0042] refer to Figure 1 , Fig.14 ,and Fig.15, the method 100 includes a block 112, in which a metal fill layer 286 is deposited over the workpiece 200. In some embodiments, the metal fill layer 286 may include tungsten (W), molybdenum (Mo), ruthenium (Ru), nickel (Ni), or cobalt (Co). In one embodiment, the metal fill layer 286 includes cobalt (Co). The metal fill layer 286 may be deposited using ALD, PVD, CVD, electroplating, or chemical plating. After depositing the metal fill layer 286, the workpiece 200 is planarized to remove excess material. Planarization may include using a chemical mechanical polishing (CMP) process. As Fig.14 and Fig.15 As shown, after planarization, a first source / drain contact 2862 , a second source / drain contact 2864 , and a third source / drain contact 2866 are formed.

[0043] When viewed along the Y direction, Fig.14 As shown, the first source / drain contact 2862, the second source / drain contact 2864, and the third source / drain contact 2866 ( Fig.14 (not shown) have substantially the same width along the X direction. When viewed along the X direction, Fig.15 As shown, the first source / drain contact 2862 and the third source / drain contact 2866 may be divided into a bottom portion and a top portion located above the bottom portion. Fig.15 , the bottom of the third source / drain contact 2866 has a first width W1 along the Y direction, and the top of the third source / drain contact 2868 has a second width W2 along the Y direction. The second width W2 is greater than the first width W1, so that the third source / drain contact 2866 does not substantially damage the n-type source / drain feature 220N it penetrates. The ratio of the second width W2 to the first width W1 can be between about 1.5 and about 3. Fig.15 As shown, when the bottom and top of the third source / drain contact 2866 share the same width, it will eliminate most of the n-type source / drain component 220N. The bottom surface of the top of the third source / drain contact 2866 is bounded by the second silicide layer 284 and the n-type dipole layer 282, and the top surface of the n-type source / drain component 220N. The bottom terminal of the third source / drain contact 2866 is bounded by the second silicide layer 284, the n-type dipole layer 282, and the first silicide layer 280, and the p-type source / drain component 220P. Although not explicitly shown in the figure, the second source / drain contact 2864 can have a width similar to that of the n-type source / drain component 220N. Fig.15 A similar X-direction profile of the third source / drain contact 2866 is shown in FIG.

[0044] Still reference Fig.14 and Fig.15. The first source / drain contact 2862, the second source / drain contact 2864, and the third source / drain contact 2866 interface with the n-type source / drain feature 220N through the n-type dipole layer 282. The second source / drain contact 2864 and the third source / drain contact 2866 interface with the p-type source / drain feature 220P through the first silicide layer 280. The n-type dipole layer 282 reduces the contact resistance to the n-type source / drain feature 220N, and the first silicide layer 280 reduces the contact resistance to the p-type source / drain feature 220P. It can be seen that the selective deposition of the first silicide layer 280 on the p-type source / drain feature 220P according to the present disclosure allows for optimized contact resistance reduction for both the n-type source / drain feature 220N and the p-type source / drain feature 220P. The interfaces of these layers can be observed using transmission electron microscopy (TEM) or energy dispersive X-ray spectroscopy (EDS).

[0045] In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a fin structure generated from a substrate; an isolation component surrounding the fin structure; a first type epitaxial component disposed above the fin structure; a first contact etch stop layer (CESL) disposed on the first type epitaxial component and the isolation component; a first dielectric layer disposed above the first CESL; a second type epitaxial component disposed on the first dielectric layer; a second CESL disposed on the first dielectric layer and the second type epitaxial component; a second dielectric layer disposed above the second CESL; and a contact structure including: a top portion extending through the second dielectric layer and the second CESL, and contacting the second type epitaxial component through a first metal silicide layer and a dipole layer; and a bottom portion disposed below the top portion, the bottom portion extending through the second type epitaxial component, the first dielectric layer, and the first CESL, and contacting the first type epitaxial component through the first metal silicide layer, the dipole layer, and the second metal silicide layer. The first metal silicide layer and the second metal silicide layer have different metal compositions.

[0046] In some embodiments, the first metal silicide layer includes Ti. In some embodiments, the second metal silicide layer includes Mo, Ru, Ni, or Co. In some embodiments, the dipole layer includes Zr, Hf, Sb, Ce, Sc, Y, Yb, or Er. In some cases, the fin structure extends longitudinally along a first direction, the top of the contact structure includes a first width along a second direction perpendicular to the first direction, the bottom of the contact structure includes a second width along the second direction, and the first width is greater than the second width. In some embodiments, the second metal silicide layer includes a thickness between about 3nm and about 6.5nm. In some embodiments, the sidewalls of the contact structure are separated from the first CESL, the first dielectric layer, the second type epitaxial component, the second CESL, and the second dielectric layer by a dielectric liner. In some cases, the dielectric liner includes silicon nitride. In some embodiments, the first type epitaxial component and the second type epitaxial component are disposed between two dielectric fins.

[0047] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a first plurality of nanostructures extending between a first p-type source / drain component and a second p-type source / drain component; a second plurality of nanostructures disposed above the first plurality of nanostructures, the second plurality of nanostructures extending between a first n-type source / drain component and a second n-type source / drain component; a first contact contacting a top surface of the first n-type source / drain component through a first metal silicide layer and an n-type dipole layer; and a second contact contacting a top surface of the second p-type source / drain component through the first metal silicide layer, the n-type dipole layer, and the second metal silicide layer. The first metal silicide layer and the second metal silicide layer have different metal compositions.

[0048] In some embodiments, the first metal silicide layer comprises Ti. In some embodiments, the second metal silicide layer comprises Mo, Ru, Ni, or Co. In some embodiments, the n-type dipole layer comprises Zr, Hf, Sb, Ce, Sc, Y, Yb, or Er. In some embodiments, the first contact and the second contact comprise Mo, Ru, Ni, or Co. In some embodiments, the second metal silicide layer comprises chlorine, carbon, oxygen, nitrogen, or fluorine.

[0049] In another exemplary aspect, the present disclosure relates to a method. The method includes: receiving a workpiece including an opening exposing a surface of an n-type source / drain component and a surface of a p-type source / drain component; selectively depositing a first silicide layer on the surface of the p-type source / drain component, while the surface of the n-type source / drain component is substantially free of the first silicide layer; after the selective deposition, depositing a metal layer on the first silicide layer and the surface of the n-type source / drain component; depositing a second silicide layer over the metal layer; and depositing a metal filling layer over the second silicide layer. The selective deposition includes: passivating the surface of the n-type source / drain component by a self-assembled layer; after the passivation, depositing a first silicide layer on the surface of the p-type source / drain component; and after the selective deposition of the first silicide layer, removing the self-assembled layer.

[0050] In some embodiments, the self-assembled layer comprises dithiothreitol or 3-(trimethoxysilyl) propanethiol. In some embodiments, the selective deposition of the first silicide layer comprises a temperature between about 250°C and about 400°C. In some embodiments, the removal of the self-assembled layer comprises treatment with a plasma comprising argon, helium, nitrogen, or hydrogen. In some embodiments, the first silicide layer comprises Mo, Ru, Ni, or Co.

[0051] According to another embodiment of the present application, a method for forming a semiconductor structure is provided, comprising: receiving a workpiece including an opening exposing a surface of an n-type source / drain component and a surface of a p-type source / drain component; selectively depositing a first silicide layer on the surface of the p-type source / drain component, while the surface of the n-type source / drain component is substantially free of the first silicide layer; after the selective deposition, depositing a metal layer on the surface of the first silicide layer and the n-type source / drain component; depositing a second silicide layer over the metal layer; and depositing a metal fill layer over the second silicide layer, wherein the selective deposition comprises: passivating the surface of the n-type source / drain component by a self-assembled layer, depositing the first silicide layer on the surface of the p-type source / drain component after the passivation, and removing the self-assembled layer after the selective deposition of the first silicide layer. In some embodiments, the self-assembled layer comprises dithiothreitol or 3-(trimethoxysilyl)propanethiol. In some embodiments, the selective deposition of the first silicide layer comprises a temperature between about 250° C. and about 400° C. In some embodiments, the removal of the self-assembled layer comprises treatment with a plasma comprising argon, helium, nitrogen, or hydrogen. In some embodiments, the first silicide layer comprises Mo, Ru, Ni, or Co.

[0052] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: The fin structure is generated from the substrate; an isolation member surrounding the fin structure; A first type epitaxial component disposed above the fin structure; a first contact etch stop layer, disposed on the first type epitaxial component and the isolation component; a first dielectric layer disposed above the first contact etch stop layer; A second type epitaxial component is disposed on the first dielectric layer; a second contact etch stop layer, disposed on the first dielectric layer and the second type epitaxial component; a second dielectric layer disposed above the second contact etch stop layer; as well as Contact structure, including: a top portion extending through the second dielectric layer and the second contact etch stop layer and contacting the second type epitaxial feature through the first metal silicide layer and the dipole layer; and A bottom portion is disposed below the top portion, the bottom portion extending through the second type epitaxial component, the first dielectric layer, and the first contact etch stop layer, and contacting the first type epitaxial component through the first metal silicide layer, the dipole layer, and the second metal silicide layer, wherein the first metal silicide layer and the second metal silicide layer have different metal compositions.

2. The semiconductor structure according to claim 1, wherein: The first metal silicide layer includes Ti.

3. The semiconductor structure according to claim 2, wherein: The second metal silicide layer includes Mo, Ru, Ni, or Co.

4. The semiconductor structure according to claim 3, wherein: The dipole layer includes Zr, Hf, Sb, Ce, Sc, Y, Yb, or Er.

5. The semiconductor structure according to claim 1, in, The fin structure extends longitudinally along a first direction, wherein the top of the contact structure comprises a first width along a second direction perpendicular to the first direction, wherein the bottom of the contact structure comprises a second width along the second direction, Wherein, the first width is greater than the second width.

6. The semiconductor structure according to claim 1, wherein: The second metal silicide layer includes a thickness between about 3 nm and about 6.5 nm.

7. The semiconductor structure according to claim 1, wherein: A sidewall of the contact structure is spaced apart from the first contact etch stop layer, the first dielectric layer, the second type epitaxial feature, the second contact etch stop layer, and the second dielectric layer by a dielectric liner.

8. The semiconductor structure according to claim 7, wherein: The dielectric liner includes silicon nitride.

9. A semiconductor structure comprising: a first plurality of nanostructures extending between the first p-type source / drain feature and the second p-type source / drain feature; a second plurality of nanostructures disposed above the first plurality of nanostructures, the second plurality of nanostructures extending between the first n-type source / drain feature and the second n-type source / drain feature; a first contact, contacting a top surface of the first n-type source / drain component through the first metal silicide layer and the n-type dipole layer; as well as a second contact, contacting a top surface of the second p-type source / drain component through the first metal silicide layer, the n-type dipole layer, and the second metal silicide layer, The first metal silicide layer and the second metal silicide layer have different metal compositions.

10. A method of forming a semiconductor structure, comprising: receiving a workpiece including an opening exposing a surface of an n-type source / drain feature and a surface of a p-type source / drain feature; selectively depositing a first silicide layer on the surface of the p-type source / drain feature, while the surface of the n-type source / drain feature is substantially free of the first silicide layer; depositing a metal layer on the surfaces of the first silicide layer and the n-type source / drain features after the selective deposition; depositing a second silicide layer over the metal layer; as well as depositing a metal filling layer on the second silicide layer, Wherein, the selective deposition comprises: passivating said surface of said n-type source / drain features by a self-assembled layer, depositing the first silicide layer on the surface of the p-type source / drain feature after the passivation, and After the selective deposition of the first silicide layer, the self-assembled layer is removed.

Images