Shielded gate type image sensing device with piezoresistive sensing function and method of manufacturing the same

Abstract

The application relates to the technical field of image sensing devices, in particular to a shielded gate type image sensing device loaded with a piezoresistive sensing function and a preparation method thereof. The shielded gate type image sensing device loaded with the piezoresistive sensing function comprises a plurality of pixels, each of which comprises a red image sensing sub-pixel R, a green image sensing sub-pixel G, a blue image sensing sub-pixel B and a pressure sensing sub-pixel S; a driving back plate is provided with a plurality of regularly arranged through holes, the driving back plate carries the plurality of pixels, and drives the red image sensing sub-pixel R, the green image sensing sub-pixel G and the light-emitting sub-pixel B to receive image information and drives the pressure sensing sub-pixel S to receive pressure information. The shielded gate type sensing module prepared by using a semiconductor process can efficiently receive external pressure and image information, and provides a feasible scheme for interactive single-chip integration.

Description

Technical Field

[0001] This invention relates to the field of image sensing device technology, and in particular to a shielded grid-type image sensing device with piezoresistive sensing function and its manufacturing method. Background Technology

[0002] The performance of an image sensor depends not only on its pixel count but also on factors such as pixel size, sensor dimensions, and signal-to-noise ratio. With technological advancements, image sensors are evolving towards higher resolution, miniaturization, lower power consumption, and lower cost to meet growing market demands. However, current image sensors require additional pressure sensing devices to receive real-time external pressure information, and the pixel arrangement of existing sensors needs optimization.

[0003] If the piezoresistive sensor is incorporated into the image sensor fabrication process, a practical solution can be provided for single-chip integration of interactive displays. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a shielded grid image sensing device with piezoresistive sensing function in order to solve the problems existing in the prior art mentioned above.

[0005] The technical solution adopted by this invention to solve its technical problem is: a shielded grid-type image sensing device equipped with piezoresistive sensing function, comprising:

[0006] Multiple pixels, each of which includes a red image sensing sub-pixel R, a green image sensing sub-pixel G, a blue image sensing sub-pixel B, and a pressure sensing sub-pixel S;

[0007] A driving backplate is provided with a plurality of regularly arranged vias. The red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B, or the pressure sensing sub-pixel S covers at least one via. The driving backplate carries multiple pixels and drives the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the light-emitting sub-pixel B to receive image information and drives the pressure sensing sub-pixel S to receive pressure information, respectively.

[0008] The red image sensing sub-pixel R, green image sensing sub-pixel G, blue image sensing sub-pixel B, and pressure sensing sub-pixel S each include an anode, a semiconductor device, and an ITO thin film layer. The anode is disposed on the driving backplate and covers at least one via. The semiconductor device is located on the side of the anode away from the driving backplate, and the ITO thin film layer is located on the side of the semiconductor device away from the driving backplate.

[0009] The semiconductor device includes a P-type collector region, an N-type buffer layer, an N-type drift layer, a P-type base region, a gate, a metal shielding layer, an N+ region, and an emitter region.

[0010] Furthermore, the P-type collector region is located on the side of the anode away from the driving backplane. An N-type buffer layer and an N-type drift layer are sequentially formed on the P-type collector region. A P-type base region is formed on the N-type drift layer. A gate is provided from the upper surface of the P-type base region to the upper part of the N-type drift layer. A metal shielding layer is provided on the outside of the gate. An N+ region is provided inside the N-type drift layer. An emitter region is provided on the metal shielding layer.

[0011] Furthermore, the pressure sensing sub-pixel S has an ITO thin film layer, a Si layer with a hollow structure, a SiO2 layer on the Si layer, a P-type silicon layer on the SiO2 layer, a P-type single crystal silicon sensing film with a piezoresistive electrode connected to the P-type silicon, and a through hole from the upper surface of the P-type silicon to the lower surface of the Si layer, with tungsten connecting the P-type single crystal silicon sensing film and the ITO thin film layer inside the through hole.

[0012] Furthermore, it also includes an interlayer dielectric layer and a common cathode. The interlayer dielectric layer is filled between the red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B, and the pressure sensing sub-pixel S. Electrode grooves are formed on the interlayer dielectric layers corresponding to the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B. The common cathode is located on the side of the interlayer dielectric layer away from the driving backplate and covers the electrode grooves. The common cathode is in contact with the upper surfaces of the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B through the electrode grooves. In the pressure sensing sub-pixel S, the P-type silicon is connected to the piezoresistive electrode of the P-type single-crystal silicon sensing film.

[0013] Furthermore, it also includes an encapsulation layer located on the side of the common cathode away from the drive backplane and covering the common cathode.

[0014] Furthermore, it also includes an RGB filter layer, microlenses, and a thin-film encapsulation layer. The RGB filter layer is disposed on the side of the encapsulation layer away from the driving backplane. The RGB filter layer includes a red filter unit R, a green filter unit G, a blue filter unit B, and a black matrix. The red filter unit R, green filter unit G, and blue filter unit B are arranged sequentially at intervals on the upper surface of the encapsulation layer. The black matrix is ​​disposed around the periphery of the red filter unit R, green filter unit G, and blue filter unit B. Microlenses are provided on the side of the red filter unit R, green filter unit G, and blue filter unit B away from the driving backplane. The thin-film encapsulation layer is disposed above the microlenses and covers the microlenses and the RGB filter layer.

[0015] The text also mentions a method for fabricating a shielded grid-type image sensing device with piezoresistive sensing function, comprising the following steps:

[0016] S1. Form several regularly arranged vias on the drive backplane and fill the vias with conductive material. Then form several anodes on the upper surface of the drive backplane, with each anode covering at least one via.

[0017] S2. A P-type collector region, an N-type buffer layer, and an N-type drift layer are sequentially grown on the driving backplate and the anode to form a semiconductor layer.

[0018] S3, patterned semiconductor layer, the part removed by filling the interlayer dielectric layer, and the interlayer dielectric layer is smoothed by chemical mechanical grinding process, so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the N-type drift layer.

[0019] S4, ion implantation on the upper surface of the N-type drift layer forms a P-type base region;

[0020] S5. A trench with an arc-shaped cross section is etched from the upper surface of the P-type base region to the upper part of the N-type drift layer, and a gate oxide layer is grown on the trench surface.

[0021] S6. A polysilicon gate is grown in a trench with a gate oxide layer on the surface. At the same time, a deep trench is dug on the outside of the polysilicon gate and a metal shielding layer is deposited. A SiO2 passivation protection layer is grown on the outer surface of the metal shielding layer, the polysilicon gate and the P-type base region.

[0022] S7. Patterned SiO2 passivation protective layer, forming a through hole in the middle section of the SiO2 passivation protective layer, implanting N+ regions into the P-type base region through the through hole, and growing the emitter region on the SiO2 passivation protective layer.

[0023] S8. Deposit an ITO thin film layer on the emitter region, grow a filling interlayer dielectric layer, and use a chemical mechanical polishing process to polish the interlayer dielectric layer so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the ITO thin film layer.

[0024] S9. A Si layer is deposited on the ITO thin film layer of the pressure sensing sub-pixel S and patterned to form a hollow structure. A thin SiO2 layer and a P-type silicon are grown sequentially on the top of the Si layer of the hollow structure. After deep silicon etching and drilling, tungsten is deposited in the hole using CVD process. Then, a P-type single crystal silicon sensing film with piezoresistive electrode is bonded by bonding process.

[0025] S10. Set a common cathode and grow and pattern the encapsulation layer;

[0026] S11. An RGB filter layer is fabricated on the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B using a photoluminescence process. Microlenses are then fabricated on the red filter unit R, the green filter unit G, and the blue filter unit B of the RGB filter layer. Finally, a thin film encapsulation layer is fabricated on the RGB filter layer and the microlenses.

[0027] It also mentions another method for fabricating a shielded grid-type image sensor with piezoresistive sensing function, including the following steps:

[0028] Sa, Several regularly arranged vias are formed on the drive backplane, and conductive material is filled in the vias. Then several anodes are formed on the upper surface of the drive backplane, and each anode covers at least one via.

[0029] Sb, a P-type collector region, an N-type buffer layer and an N-type drift layer are sequentially grown on the driving backplane and the anode to form a semiconductor layer;

[0030] Sc, patterned semiconductor layer, the part removed by filling the interlayer dielectric layer, and the interlayer dielectric layer is smoothed by chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the N-type drift layer;

[0031] Ion implantation on the upper surface of Sd and N-type drift layers forms a P-type base region;

[0032] Se, a rectangular trench with a stepped bottom is etched from the upper surface of the P-type base region to the lower part of the N-type drift layer, and a gate oxide layer is grown on the surface of the trench;

[0033] Sf, a polysilicon gate and a metal shielding layer are grown on two step surfaces respectively. At the same time, a SiO2 passivation protection layer is grown on the outer surface of the metal shielding layer, the polysilicon gate and the P-type base region.

[0034] Sg, patterned SiO2 passivation protective layer, through hole formed in the middle section of SiO2 passivation protective layer, ion implantation into P-type base region through through hole to form N+ region, and emitter region grown on SiO2 passivation protective layer;

[0035] Sh, deposit an ITO thin film layer on the emitter region, grow a filling interlayer dielectric layer, and use a chemical mechanical polishing process to polish the interlayer dielectric layer so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the ITO thin film layer.

[0036] Si, deposit a Si layer on the ITO thin film layer of the pressure sensing sub-pixel S and pattern it to form a hollow structure. On the top of the Si layer of the hollow structure, grow a thin SiO2 layer and P-type silicon in sequence. Then, perform deep silicon etching to drill holes and use CVD process to deposit tungsten in the holes. Then, use bonding process to bind the P-type single crystal silicon sensing film with piezoresistive electrode.

[0037] Sj, Set up a common cathode, grow and pattern the encapsulation layer;

[0038] Sk is prepared by using a photoluminescence process to fabricate RGB filter layers on red image sensing sub-pixels R, green image sensing sub-pixels G, and blue image sensing sub-pixels B. Microlenses are then fabricated on the red filter unit R, green filter unit G, and blue filter unit B of the RGB filter layers. Finally, a thin film encapsulation layer is fabricated on the RGB filter layers and microlenses.

[0039] The beneficial effects of this invention are as follows: The shielded gate sensing module fabricated using semiconductor technology can efficiently receive external pressure and image information, providing a practical solution for interactive single-chip integration. Attached Figure Description

[0040] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0041] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention.

[0042] Figure 2 This is a schematic diagram of step 1 in Embodiment 1 of the present invention.

[0043] Figure 3 This is a schematic diagram of step 2 in Embodiment 1 of the present invention.

[0044] Figure 4 This is a schematic diagram of step 3 in Embodiment 1 of the present invention.

[0045] Figure 5 This is a schematic diagram of step 4 in Embodiment 1 of the present invention.

[0046] Figure 6 This is a schematic diagram of step 5 in Embodiment 1 of the present invention.

[0047] Figure 7 This is a schematic diagram of step 6 in Embodiment 1 of the present invention.

[0048] Figure 8 This is a schematic diagram of step 7 in Embodiment 1 of the present invention.

[0049] Figure 9 This is a schematic diagram of step 8 in Embodiment 1 of the present invention.

[0050] Figure 10 This is a schematic diagram of step 9 in Embodiment 1 of the present invention.

[0051] Figure 11 This is a schematic diagram of step 10 in Embodiment 1 of the present invention.

[0052] Figure 12 This is a structural schematic diagram of step 11 in Embodiment 1 of the present invention.

[0053] Figure 13 This is a schematic diagram of the structure of Embodiment 2 of the present invention.

[0054] Figure 14 This is a schematic diagram of step a in Embodiment 2 of the present invention.

[0055] Figure 15 This is a schematic diagram of step b in Embodiment 2 of the present invention.

[0056] Figure 16 This is a schematic diagram of step c in embodiment two of the present invention.

[0057] Figure 17 This is a schematic diagram of step d in Embodiment 2 of the present invention.

[0058] Figure 18 This is a schematic diagram of step e in Embodiment 2 of the present invention.

[0059] Figure 19 This is a schematic diagram of step f in Embodiment 2 of the present invention.

[0060] Figure 20 This is a schematic diagram of step g in Embodiment 2 of the present invention.

[0061] Figure 21 This is a schematic diagram of step h in Embodiment 2 of the present invention.

[0062] Figure 22 This is a schematic diagram of step i in embodiment two of the present invention.

[0063] Figure 23 This is a schematic diagram of step j in Embodiment 2 of the present invention.

[0064] Figure 24 This is a schematic diagram of step k in Embodiment 2 of the present invention.

[0065] Figure 25 These are diagrams of the optimized pixel arrangement schemes of Embodiment 1 and Embodiment 2 of the present invention.

[0066] Figure 26 These are the driving circuit diagrams for Embodiment 1 and Embodiment 2 of the present invention.

[0067] In the diagram: 1. Driver backplane; 2. Via; 3. Anode; 4. Semiconductor device; 41. P-type collector region; 42. N-type buffer layer; 43. N-type drift layer; 44. P-type base region; 45. Gate; 46. Metal shielding layer; 47. N+ region; 48. Emitter region; 49. SiO2 passivation protection layer; 410. Gate oxide layer; 5. ITO thin film layer; 6. Si layer; 7. SiO2 layer; 8. P-type silicon; 9. P-type single crystal silicon sensing thin film; 10. Tungsten; 11. Interlayer dielectric layer; 12. Common cathode; 13. Encapsulation layer; 14. RGB filter layer; 15. Microlens; 16. Thin film encapsulation layer. Detailed Implementation

[0068] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0069] Example 1

[0070] like Figure 1 As shown, a shielded grid-type image sensing device with piezoresistive sensing function includes: multiple pixels, each pixel including a red image sensing sub-pixel R, a green image sensing sub-pixel G, a blue image sensing sub-pixel B, and a pressure sensing sub-pixel S; a driving backplate 1, the driving backplate 1 having a plurality of regularly arranged vias 2, wherein the red image sensing sub-pixel R, green image sensing sub-pixel G, blue image sensing sub-pixel B, or pressure sensing sub-pixel S covers at least one via 2, the driving backplate 1 carries the multiple pixels, and drives the red image sensing sub-pixel R and G, respectively. Sub-pixel R, green image sensing sub-pixel G, and light-emitting sub-pixel B receive image information, and drive pressure sensing sub-pixel S receives pressure information; red image sensing sub-pixel R, green image sensing sub-pixel G, blue image sensing sub-pixel B, and pressure sensing sub-pixel S each include an anode 3, a semiconductor device 4, and an ITO thin film layer 5. The anode 3 is disposed on the drive backplate 1 and covers at least one via 2. The semiconductor device 4 is located on the side of the anode 3 away from the drive backplate 1, and the ITO thin film layer 5 is located on the side of the semiconductor device 4 away from the drive backplate 1.

[0071] The system also includes an interlayer dielectric layer 11 and a common cathode 12. The interlayer dielectric layer 11 is filled between the red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B, and the pressure sensing sub-pixel S. Electrode grooves are formed on the interlayer dielectric layer 11 corresponding to the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B. The common cathode 12 is located on the side of the interlayer dielectric layer 11 away from the driving backplate 1 and covers the electrode grooves. The common cathode 12 is in contact with the upper surfaces of the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B through the electrode grooves. In the pressure sensing sub-pixel S, the common cathode 8 is connected to the piezoresistive electrode of the P-type single-crystal silicon sensing thin film 9. The system also includes an encapsulation layer 13, which is located on the side of the common cathode 12 away from the driving backplate 1 and covers the common cathode 12.

[0072] It also includes an RGB filter layer 14, microlenses 15, and a thin-film encapsulation layer 16. The RGB filter layer 14 is disposed on the side of the encapsulation layer 13 away from the driving backplate 1. The RGB filter layer 14 includes a red filter unit R, a green filter unit G, a blue filter unit B, and a black matrix. The red filter unit R, the green filter unit G, and the blue filter unit B are arranged sequentially at intervals on the upper surface of the encapsulation layer 13. The black matrix is ​​disposed around the periphery of the red filter unit R, the green filter unit G, and the blue filter unit B. Microlenses 15 are provided on the side of the red filter unit R, the green filter unit G, and the blue filter unit B away from the driving backplate 1. The thin-film encapsulation layer 16 is disposed above the microlenses 15 and covers the microlenses 15 and the RGB filter layer 14.

[0073] The semiconductor device 4 includes a P-type collector region 41, an N-type buffer layer 42, an N-type drift layer 43, a P-type base region 44, a gate 45, a metal shielding layer 46, an N+ region 47, and an emitter region 48. The P-type collector region 41 is located on the side of the anode 3 away from the driving backplate 1. An N-type buffer layer 42 and an N-type drift layer 43 are sequentially formed on the P-type collector region 41. A P-type base region 44 is formed on the N-type drift layer 43. A gate 45 is provided from the upper surface of the P-type base region 44 to the upper part of the N-type drift layer 43. A metal shielding layer 46 is provided on the outside of the gate 45. An N+ region 47 is provided inside the N-type drift layer 43. An emitter region 48 is provided on the metal shielding layer 46.

[0074] The pressure sensing sub-pixel S has an ITO thin film layer 5 with a hollowed-out Si layer 6, a SiO2 layer 7 on the Si layer 6, a P-type silicon 8 on the SiO2 layer 7, a P-type single crystal silicon sensing film 9 with a piezoresistive electrode connected to the P-type silicon 8, and a through hole from the upper surface of the P-type silicon 8 to the lower surface of the Si layer 6. A tungsten 10 connecting the P-type single crystal silicon sensing film 9 and the ITO thin film layer 5 is provided in the through hole.

[0075] The fabrication method of the shielded grid image sensor with piezoresistive sensing function in Example 1 is as follows:

[0076] Step 1: As Figure 2 As shown, a number of regularly arranged vias 2 are formed on the drive backplate 1, and conductive material is filled in the vias 2. Subsequently, a number of anodes 3 are formed on the upper surface of the drive backplate 1, and each anode 3 covers at least one via 2.

[0077] Step 2: As Figure 3 As shown, a P-type collector region 41, an N-type buffer layer 42, and an N-type drift layer 43 are sequentially grown on the drive backplate 1 and the anode 3 to form a semiconductor layer;

[0078] Step 3: As Figure 4 As shown, the patterned semiconductor layer is filled with the removed portion by the interlayer dielectric layer 11, and the interlayer dielectric layer 11 is smoothed by a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer 11 is flush with the upper surface of the N-type drift layer 43.

[0079] Step 4: As Figure 5 As shown, ion implantation on the upper surface of the N-type drift layer 43 forms a P-type base region 44;

[0080] Step 5: As Figure 6 As shown, a trench with an arc-shaped cross section is etched from the upper surface of the P-type base region 44 to the upper part of the N-type drift layer 43, and a gate oxide layer 410 is grown on the surface of the trench.

[0081] Step 6: As Figure 7 As shown, a polysilicon gate 45 is grown in a trench with a gate oxide layer 410 on the surface. At the same time, a deep trench is dug on the outside of the polysilicon gate 45 and a metal shielding layer 46 is deposited. A SiO2 passivation protection layer 49 is grown on the outer surface of the metal shielding layer 46, the polysilicon gate 45 and the P-type base region 44.

[0082] Step 7: As Figure 8 As shown, a patterned SiO2 passivation protective layer 49 is formed, and a via is formed in the middle section of the SiO2 passivation protective layer 49. An N+ region 47 is formed by ion implantation into the P-type base region 44 through the via, and an emitter region 48 is grown on the SiO2 passivation protective layer 49.

[0083] Step 8: As Figure 9 As shown, an ITO thin film layer 5 is deposited on the emitter region 48, an interlayer dielectric layer 11 is grown, and the interlayer dielectric layer 11 is ground flat by a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer 11 is flush with the upper surface of the ITO thin film layer 5.

[0084] Step 9: As Figure 10As shown, a Si layer 6 is deposited on the ITO thin film layer 5 of the pressure sensing sub-pixel S and patterned to form a hollow structure. A thin SiO2 layer 7 and a P-type silicon 8 are grown sequentially on the top of the Si layer 6 of the hollow structure. After deep silicon etching and hole drilling, tungsten 10 is deposited in the hole using CVD process. Then, a P-type single crystal silicon sensing film 9 with a piezoresistive electrode is bonded by bonding process.

[0085] Step 10: As Figure 11 As shown, a common cathode 12 is provided, and a patterned encapsulation layer 13 is grown;

[0086] Step 11: As Figure 12 As shown, an RGB filter layer 14 is fabricated on the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B using a photolithography process. Microlenses 15 are then fabricated on the red filter unit R, the green filter unit G, and the blue filter unit B of the RGB filter layer 14. Finally, a thin film encapsulation layer 16 is fabricated on the RGB filter layer 14 and the microlenses 15. The current flow is shown by the red arrow inside the semiconductor device 4.

[0087] Example 2

[0088] The difference from Example 1 is as follows: Figure 13 As shown, a rectangular trench with a stepped bottom is etched from the upper surface of the P-type base region 44 to the lower part of the N-type drift layer 43, and a gate oxide layer is grown on the surface of the trench. A polysilicon gate 45 and a metal shielding layer 46 are grown on the two stepped surfaces respectively. At the same time, a SiO2 passivation protection layer 49 is grown on the outer surface of the metal shielding layer 46, the polysilicon gate 45 and the P-type base region 44.

[0089] The fabrication method of the shielded grid image sensor with piezoresistive sensing function in Example 2 is as follows:

[0090] Step a: As Figure 14 As shown, a number of regularly arranged vias 2 are formed on the drive backplate 1, and conductive material is filled in the vias 2. Subsequently, a number of anodes 3 are formed on the upper surface of the drive backplate 1, and each anode 3 covers at least one via 2.

[0091] Step b: As Figure 15 As shown, a P-type collector region 41, an N-type buffer layer 42, and an N-type drift layer 43 are sequentially grown on the drive backplate 1 and the anode 3 to form a semiconductor layer;

[0092] Step c: As Figure 16 As shown, the patterned semiconductor layer is filled with the removed portion by the interlayer dielectric layer 11, and the interlayer dielectric layer 11 is smoothed by a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer 11 is flush with the upper surface of the N-type drift layer 43.

[0093] Step d: As Figure 17 As shown, ion implantation on the upper surface of the N-type drift layer 43 forms a P-type base region 44;

[0094] Step e: as Figure 18 As shown, a rectangular trench with a stepped bottom is etched from the upper surface of the P-type base region 44 to the lower part of the N-type drift layer 43, and a gate oxide layer 410 is grown on the surface of the trench.

[0095] Step f: as Figure 19 As shown, a polysilicon gate 45 and a metal shielding layer 46 are grown on two step surfaces, respectively. At the same time, a SiO2 passivation protection layer 49 is grown on the outer surface of the metal shielding layer 46, the polysilicon gate 45 and the P-type base region 44.

[0096] Step g: as Figure 20 As shown, a patterned SiO2 passivation protective layer 49 is formed, and a via is formed in the middle section of the SiO2 passivation protective layer 49. An N+ region 47 is formed by ion implantation into the P-type base region 44 through the via, and an emitter region 48 is grown on the SiO2 passivation protective layer 49.

[0097] Step h: as Figure 21 As shown, an ITO thin film layer 5 is deposited on the emitter region 48, an interlayer dielectric layer 11 is grown, and the interlayer dielectric layer 11 is ground flat by a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer 11 is flush with the upper surface of the ITO thin film layer 5.

[0098] Step i: As Figure 22 As shown, a Si layer 6 is deposited on the ITO thin film layer 5 of the pressure sensing sub-pixel S and patterned to form a hollow structure. A thin SiO2 layer 7 and a P-type silicon 8 are grown sequentially on the top of the Si layer 6 of the hollow structure. After deep silicon etching and hole drilling, tungsten 10 is deposited in the hole using CVD process. Then, a P-type single crystal silicon sensing film 9 with a piezoresistive electrode is bonded by bonding process.

[0099] Step j: as Figure 23 As shown, a common cathode 12 is provided, and a patterned encapsulation layer 13 is grown;

[0100] Step k: as follows Figure 24 As shown, an RGB filter layer 14 is fabricated on the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B using a photolithography process. Microlenses 15 are then fabricated on the red filter unit R, the green filter unit G, and the blue filter unit B of the RGB filter layer 14. Finally, a thin film encapsulation layer 16 is fabricated on the RGB filter layer 14 and the microlenses 15. The current flow is shown by the red arrow inside the semiconductor device 4.

[0101] The optimized pixel arrangement schemes of Embodiment 1 and Embodiment 2 are as follows:Figure 25 As shown, a pixel includes a red image sensing sub-pixel R, a green image sensing sub-pixel G, a blue image sensing sub-pixel B, and a pressure sensing sub-pixel S. Spatially, a square has four vertices, each containing a green image sensing sub-pixel G and a blue image sensing sub-pixel B at its two diagonal vertices, and a red image sensing sub-pixel R and a pressure sensing sub-pixel S at the remaining two vertices. The side length of the square is equal to the pixel width. Four groups of red image sensing sub-pixels R, green image sensing sub-pixels G, and blue image sensing sub-pixels B or pressure sensing sub-pixels S form a group, sharing a single mask opening.

[0102] Example 1 and Example 2 adopt Figure 25 The pixel optimization arrangement scheme shown, combined with the high-resolution driving backplane 1, can break through the physical limits of the existing high-resolution metal mask FMM, achieving high resolution, high brightness, and high contrast display, while having a low response time.

[0103] Example 1 and Example 2 are combined as follows Figure 26 The driving circuit shown can improve the performance and reliability of the display, and has the advantages of high integration, low power consumption, high speed and good stability, making it widely applicable.

[0104] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A shielded grid-type image sensing device equipped with piezoresistive sensing function, characterized in that, The application relates to a pixel array and a driving backboard thereof. The pixel array comprises a plurality of pixels, each of which comprises a red image sensing sub-pixel R, a green image sensing sub-pixel G, a blue image sensing sub-pixel B and a pressure sensing sub-pixel S. The driving backboard (1) is provided with a plurality of regularly arranged through holes (2), the red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B or the pressure sensing sub-pixel S covers at least one through hole (2), the driving backboard (1) carries the plurality of pixels and drives the red image sensing sub-pixel R, the green image sensing sub-pixel G and the light-emitting sub-pixel B to receive image information and drives the pressure sensing sub-pixel S to receive pressure information. The red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B and the pressure sensing sub-pixel S all comprise an anode (3), a semiconductor device (4) and an ITO film layer (5), the anode (3) is arranged on the driving backboard (1) and covers at least one through hole (2), the semiconductor device (4) is located on the side, away from the driving backboard (1), of the anode (3), and the ITO film layer (5) is located on the side, away from the driving backboard (1), of the semiconductor device (4). The semiconductor device (4) comprises a P-type collector region (41), an N-type buffer layer (42), an N-type drift layer (43), a P-type base region (44), a gate (45), a metal shielding layer (46), an N+ region (47) and an emitter region (48). The ITO film layer (5) in the pressure sensing sub-pixel S is provided with a Si layer (6) with a hollow structure, the Si layer (6) is provided with a SiO2 layer (7), the SiO2 layer (7) is provided with P-type silicon (8), the P-type silicon (8) is connected with a P-type single-crystal silicon sensing film (9) with a pressure resistance electrode, a through hole is arranged from the upper surface of the P-type silicon (8) to the lower bottom surface of the Si layer (6), and tungsten (10) is arranged in the through hole and connected with the P-type single-crystal silicon sensing film (9) and the ITO film layer (5).

2. The shielded-gate image sensor device according to claim 1, wherein: The P-type collector region (41) is located on the side, away from the driving backboard (1), of the anode (3), the N-type buffer layer (42) and the N-type drift layer (43) are sequentially formed on the P-type collector region (41), the P-type base region (44) is formed on the N-type drift layer (43), the gate (45) is arranged from the upper surface of the P-type base region (44) to the upper portion of the N-type drift layer (43), the metal shielding layer (46) is arranged on the outer side of the gate (45), the N+ region (47) is arranged in the N-type drift layer (43), and the emitter region (48) is arranged on the metal shielding layer (46).

3. The shielded-gate image sensor device according to claim 1, wherein: It also includes an interlayer dielectric layer (11) and a common cathode (12), the interlayer dielectric layer (11) is produced to fill between the red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B and the pressure sensing sub-pixel S, the interlayer dielectric layer (11) on the red image sensing sub-pixel R, the green image sensing sub-pixel G and the blue image sensing sub-pixel B corresponding is provided with an electrode slot, the common cathode (12) is arranged on the side of the interlayer dielectric layer (11) away from the driving backboard (1) and covers the electrode slot, and the common cathode (12) is in contact with the upper surface of the red image sensing sub-pixel R, the green image sensing sub-pixel G and the blue image sensing sub-pixel B through the electrode slot, and in the pressure sensing sub-pixel S, the piezoresistive electrode of the P-type silicon (8) is connected with the P-type monocrystalline silicon sensing film (9).

4. The shielded-gate image sensor device according to claim 3, wherein: It also includes a packaging layer (13), the packaging layer (13) is located on the side of the common cathode (12) away from the driving backboard (1), and covers the common cathode (12).

5. The shielded-gate image sensor device according to claim 4, wherein: It also includes an RGB filter layer (14), a microlens (15) and a film packaging layer (16), the RGB filter layer (14) is arranged on the side of the packaging layer (13) away from the driving backboard (1), the RGB filter layer (14) includes a red filter unit R, a green filter unit G, a blue filter unit B and a black matrix, the red filter unit R, the green filter unit G and the blue filter unit B are sequentially and spacedly arranged on the upper surface of the packaging layer (13); the black matrix is arranged around the periphery of the red filter unit R, the green filter unit G and the blue filter unit B, the red filter unit R, the green filter unit G and the blue filter unit B are provided with the microlens (15) on the side away from the driving backboard (1), and the film packaging layer (16) is arranged above the microlens (15) and covers the microlens (15) and the RGB filter layer (14).

6. A method for manufacturing a shielded gate type image sensing device mounted with a piezoresistive sensing function according to any one of claims 1 to 5, characterized by, It includes the following steps: S1, a plurality of regularly arranged through holes (2) are formed on the driving backboard (1), and a conductive material is filled in the through holes (2), then a plurality of anodes (3) are formed on the upper surface of the driving backboard (1), and each anode (3) covers at least one through hole (2); S2, a P-type collector region (41), an N-type buffer layer (42) and an N-type drift layer (43) are sequentially grown on the driving backboard (1) and the anode (3) to form a semiconductor layer; S3, the semiconductor layer is patterned, the removed part is filled with an interlayer dielectric layer (11), and the interlayer dielectric layer (11) is polished flat by using a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer (11) is flush with the upper surface of the N-type drift layer (43); S4, a P-type base region (44) is formed by ion implantation on the upper surface of the N-type drift layer (43); S5, a groove with an arc-shaped structure is etched from the upper surface of the P-type base region (44) to the upper part of the N-type drift layer (43), and a gate oxide layer is grown on the surface of the groove. S7, growing a polysilicon gate (45) in a trench with a surface gate oxide layer, meanwhile, digging a trench outside the polysilicon gate (45) and depositing a metal shielding layer (46), and growing a SiO2 passivation layer (49) on the outer surface of the metal shielding layer (46), the polysilicon gate (45) and the P-type base region (44); S8, patterning the SiO2 passivation layer (49), forming a via hole in the middle of the SiO2 passivation layer (49), ion implanting to form an N+ region (47) in the P-type base region (44) through the via hole, and growing an emitter region (48) on the SiO2 passivation layer (49); S9, depositing an ITO thin film layer (5) on the emitter region (48), growing an interlayer dielectric layer (11), and using a chemical mechanical polishing process to polish the interlayer dielectric layer (11) to make the upper surface of the interlayer dielectric layer (11) flush with the upper surface of the ITO thin film layer (5); S10, depositing a Si layer (6) on the ITO thin film layer (5) of the pressure sensing sub-pixel S and patterning to form a hollow structure, growing a thin SiO2 layer (7) and a P-type silicon (8) on the top of the Si layer (6) of the hollow structure in sequence, then performing deep silicon etching to punch holes, and then depositing tungsten (10) in the holes by CVD process, and then binding the P-type single crystal silicon sensing film (9) with a piezoresistive electrode by bonding process; S11, setting a common cathode (12), and growing and patterning an encapsulation layer (13); S12, preparing an RGB filter layer (14) on the red image sensing sub-pixel R, the green image sensing sub-pixel G and the blue image sensing sub-pixel B by using a yellow light process, and manufacturing a microlens (15) on the red filter unit R, the green filter unit G and the blue filter unit B of the RGB filter layer (14), and finally manufacturing a thin film encapsulation layer (16) on the RGB filter layer (14) and the microlens (15).

7. A method for manufacturing a shielded gate type image sensing device mounted with a piezoresistive sensing function according to any one of claims 1 to 5, characterized by, The method comprises the following steps: Sa, forming a plurality of through holes (2) arranged regularly on a driving back plate (1), filling the through holes (2) with conductive material, and then forming a plurality of anodes (3) on the upper surface of the driving back plate (1), and each anode (3) covers at least one through hole (2); Sb, growing a P-type collector region (41), an N-type buffer layer (42) and an N-type drift layer (43) on the driving back plate (1) and the anode (3) in sequence to form a semiconductor layer; Sc, patterning the semiconductor layer, filling the removed part through the interlayer dielectric layer (11), and using a chemical mechanical polishing process to polish the interlayer dielectric layer (11) to make the upper surface of the interlayer dielectric layer (11) flush with the upper surface of the N-type drift layer (43); Sd, ion implanting to form a P-type base region (44) on the upper surface of the N-type drift layer (43); Se, etching a trench with a stepped rectangular structure at the bottom from the upper surface of the P-type base region (44) to the lower part of the N-type drift layer (43) and growing a gate oxide layer on the surface of the trench; Sf, growing polysilicon gate (45) and metal shielding layer (46) on two step surfaces respectively, and growing SiO2 passivation layer (49) on the outer surface of metal shielding layer (46), polysilicon gate (45) and P-type base region (44) at the same time; Sg, patterning SiO2 passivation layer (49), forming a through hole in the middle section of SiO2 passivation layer (49), ion implanting N+ region (47) to P-type base region (44) through the through hole, and growing emitter region (48) on SiO2 passivation layer (49); Sh, plating ITO thin film layer (5) on emitter region (48), growing interlayer dielectric layer (11), and using chemical mechanical polishing process to polish interlayer dielectric layer (11) to make the upper surface of interlayer dielectric layer (11) flush with the upper surface of ITO thin film layer (5); Si, depositing Si layer (6) on ITO thin film layer (5) of pressure sensing sub-pixel S and patterning to form a hollow structure, growing a thin SiO2 layer (7) and P-type silicon (8) on the top of Si layer (6) in the hollow structure in turn, then performing deep silicon etching to punch holes, and then depositing tungsten (10) in the holes by CVD process, and then binding P-type single crystal silicon sensing film (9) with piezoresistive electrode by bonding process; Sj, setting common cathode (12), growing and patterning packaging layer (13); Sk, preparing RGB filter layer (14) on red image sensing sub-pixel R, green image sensing sub-pixel G and blue image sensing sub-pixel B by yellow light process, and making microlens (15) on red filter unit R, green filter unit G and blue filter unit B of RGB filter layer (14), and finally making thin film packaging layer (16) on RGB filter layer (14) and microlens (15).

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