A back contact solar cell and a short process preparation method thereof

Abstract

The present invention belongs to the technical field of back-contact solar cells, and specifically relates to a back-contact solar cell and a short-process preparation method thereof, comprising the following steps: S2, sequentially depositing a first tunneling oxide layer and a P-type doped polycrystalline layer on the back of a silicon wafer to form a first semiconductor layer; a BSG layer naturally formed during the deposition of the P-type doped polycrystalline layer is used as a mask layer; after texturing and cleaning, S5, by LPCVD technology, a second tunneling oxide layer and an amorphous passivation layer are simultaneously deposited on the front and back sides, and the deposition temperature of the LPCVD technology is 430-620°C; wherein, the second tunneling oxide layer and the amorphous passivation layer deposited on the back side form a second semiconductor layer; the amorphous passivation layer is N-type amorphous silicon or a stack of intrinsic amorphous silicon and N-type amorphous silicon. The present invention simplifies the preparation process and reduces the equipment cost, and at the same time obtains a good passivation effect on both the front and back sides, thereby improving the battery conversion efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of back-contact solar cells, and in particular relates to a back-contact solar cell and a short-process preparation method thereof. Background Art

[0002] A conventional back contact solar cell manufacturing process includes:

[0003] S101, providing silicon wafers;

[0004] S102, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer in sequence, wherein the first semiconductor layer includes a tunneling oxide layer and an N-type doped polycrystalline layer formed in sequence on the back side; and the mask layer is a composite layer of silicon nitride and silicon oxynitride;

[0005] S103, performing a first etching on the first semiconductor layer on the back surface obtained in S102 to form first opening areas W1 distributed at intervals;

[0006] S104, forming a suede surface in the first opening area W1 on the back side through suede making and cleaning;

[0007] S105, then removing the mask layer;

[0008] S106, then forming a second semiconductor layer on the back side obtained in S105, and sequentially forming a front passivation layer and an anti-reflection layer on the front side. The second semiconductor layer, the front passivation layer and the anti-reflection layer are formed on the front and back sides respectively by plate-type PECVD. The second semiconductor layer includes an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer sequentially formed on the back side.

[0009] However, in the above preparation process, although the battery conversion effect is high, due to the poor alkali resistance of the PSG layer naturally formed in the deposition of the N-type doped polycrystalline layer, it is necessary to remove the PSG in S102 to form an independent mask layer, which is a film layer that blocks high-temperature strong alkali etching without affecting the mask area. At the same time, the mask layer needs to be removed in S105, and the process flow is relatively complicated. In S106, the front passivation layer and the second semiconductor layer need to be formed separately, and both use plate-type PECVD, which makes the process flow relatively complicated and the equipment expensive.

[0010] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0011] The purpose of the present invention is to overcome the defects of the prior art in the preparation of back-contact solar cells, such as the complex process flow and expensive equipment required to ensure the cell conversion efficiency, and to provide a back-contact solar cell and a short-process preparation method thereof, which simplifies the preparation process and reduces the equipment cost, while obtaining a better passivation effect on both the front and back sides, thereby improving the cell conversion efficiency.

[0012] In order to achieve the above object, in a first aspect, the present invention provides a short-process preparation method of a back-contact solar cell, comprising the following steps:

[0013] S1, provide silicon wafer;

[0014] S2, sequentially depositing a first tunneling oxide layer and a P-type doped polycrystalline layer on the back side of the silicon wafer to form a first semiconductor layer; the BSG layer naturally formed during the deposition of the P-type doped polycrystalline layer is used as a mask layer;

[0015] S3, performing a first etching on the first semiconductor layer on the back surface obtained in S2 to form preset first opening areas distributed at intervals;

[0016] S4, forming a velvet surface in the preset first opening area on the back side through velvet cleaning to form the first opening area; forming a velvet surface on the front side at the same time; and then selecting whether to perform a step of removing the BSG layer mask layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs;

[0017] S5. Depositing a second tunnel oxide layer and an amorphous passivation layer on the front and back surfaces simultaneously by LPCVD technology, wherein the deposition temperature of the LPCVD technology is 430-620° C.; wherein the second tunnel oxide layer and the amorphous passivation layer deposited on the back surface form a second semiconductor layer; and the amorphous passivation layer is N-type amorphous silicon or a stack of intrinsic amorphous silicon and N-type amorphous silicon;

[0018] S6. Depositing an anti-reflection layer on the outer surface of the amorphous passivation layer on the front side by using tubular PECVD technology, wherein the deposition temperature of the tubular PECVD technology is 400-600°C.

[0019] In some preferred embodiments of the present invention, the N-type amorphous silicon is oxygen-doped N-type amorphous silicon. Further preferably, the oxygen doping concentration of the oxygen-doped N-type amorphous silicon is 5e20 cm -3 -2e22cm -3 .

[0020] In some preferred embodiments of the present invention, the amorphous passivation layer is a stack of intrinsic amorphous silicon and N-type amorphous silicon, and the thickness ratio of the intrinsic amorphous silicon to the N-type amorphous silicon is (0.2 - 1):1.

[0021] In some preferred embodiments of the present invention, the ratio of the thickness of the first tunneling oxide layer to the thickness of the second tunneling oxide layer is 1:(0.1-1).

[0022] In some preferred embodiments of the present invention, the ratio of the surface doping index of the P-type doped polycrystalline layer and the amorphous passivation layer is (0.05-5):1, where the surface doping index refers to the ratio of the effective boron doping concentration or the effective phosphorus doping concentration of the corresponding layer to the thickness of the layer, and the unit of the effective boron doping concentration or the effective phosphorus doping concentration is cm -3 , the unit of thickness is nm.

[0023] In some preferred embodiments of the present invention, the thickness of the second tunneling oxide layer is 0.3-1.3 nm, the thickness of the amorphous passivation layer is 1.5-15 nm, and the effective phosphorus doping concentration of N-type amorphous silicon is 5e18 cm -3 -2e20cm -3 .

[0024] In some preferred embodiments of the present invention, the thickness of the first tunnel oxide layer is 1.3-2 nm, the thickness of the P-type doped polycrystalline layer is 50-150 nm, and the effective boron doping concentration is 5e18 cm -3 -4e20 cm -3 ; The thickness of the BSG layer is 10-40nm.

[0025] In some preferred embodiments of the present invention, the thickness of the second tunnel oxide layer is smaller than the thickness of the first tunnel oxide layer.

[0026] In some preferred embodiments of the present invention, the second tunneling oxide layer is ultra-thin tunneling silicon oxide and the thickness of the ultra-thin tunneling silicon oxide is 0.1-1.3 nm.

[0027] In some preferred embodiments of the present invention, the first semiconductor layer is formed by LPCVD deposition followed by diffusion annealing, or by tubular PECVD deposition followed by annealing.

[0028] In some preferred embodiments of the present invention, the short-process preparation method of the back-contact solar cell further comprises:

[0029] S7, performing a second etching on the second semiconductor layer corresponding to the polished area of ​​the back surface obtained in S6 to expose the first semiconductor layer and form a second opening area spaced apart from the first opening area;

[0030] S8, forming a conductive film layer to fully cover the back surface obtained in S7;

[0031] S9, then performing a third etching on the conductive film layer portion located between the second opening area and the first opening area on the back side obtained in S8 to form an insulating groove;

[0032] S10, forming metal electrodes on the outer surfaces of the second opening area and the first opening area corresponding to the back surface obtained in S9.

[0033] In a second aspect, the present invention provides a back-contact solar cell, which is produced by the short-process preparation method of the back-contact solar cell described in the first aspect.

[0034] Beneficial effects:

[0035] The present invention adopts the above-mentioned technical scheme, especially adopts the first tunneling oxide layer and the P-type doped polycrystalline layer as the first semiconductor layer, and uses the BSG layer (i.e., the borosilicate glass layer, which has better alkali resistance than the PSG layer) naturally formed during the deposition of the P-type doped polycrystalline layer (i.e., during its necessary diffusion or annealing process) as a mask layer, without the need to specially form a mask layer, thereby simplifying the preparation process of the mask layer and reducing the equipment cost; at the same time, the second semiconductor layer and the front passivation layer are simultaneously deposited by LPCVD, further simplifying the preparation process and reducing the equipment cost, and the film structure of the second semiconductor layer and the front passivation layer both adopts the second tunneling oxide layer and the amorphous passivation layer instead of polycrystalline silicon, and does not require diffusion annealing, further simplifying the preparation process, and the second semiconductor layer and the front passivation layer both adopt high-temperature process, so the front anti-reflection layer can also be formed by high-temperature deposition in a tubular furnace, without the need to use any plate-type PECVD equipment, which greatly reduces the equipment cost.

[0036] Moreover, the present invention adopts a tunneling polycrystalline passivation structure of the first semiconductor layer, and cooperates with the tunneling N-type amorphous passivation structure adopted by both the second semiconductor layer and the front passivation layer, which can take into account the passivation effect of the second semiconductor layer. At the same time, the front passivation layer adopts an N-type amorphous passivation structure with a larger bandgap width than the P-type, which can effectively avoid light absorption and has a good front passivation effect, thereby obtaining a good passivation effect on both the front and back sides, thereby improving the battery conversion efficiency. Under the same conditions, if a tunneling N-type polycrystalline passivation structure is adopted in the first semiconductor layer, the second semiconductor layer needs to be P-type. According to the method of the present invention, the front passivation layer and the second semiconductor layer are deposited simultaneously, so that the front passivation layer is also P-type, and the bandgap width of the P-type is smaller than that of the N-type, and the passivation effect is not as good as that of the N-type, so the light absorption is more serious, the passivation is worse, and the battery conversion efficiency will be lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 It is a schematic diagram of the structure of a silicon wafer;

[0039] Figure 2 A schematic diagram of the structure of forming a first tunneling oxide layer, a P-type doped polycrystalline layer, and a mask layer on the back of a silicon wafer;

[0040] Figure 3 for Figure 2 A schematic diagram of a structure in which a preset first opening area is formed;

[0041] Figure 4 for Figure 3 A schematic structural diagram of a first opening area on which a velvet surface is formed;

[0042] Figure 5 for Figure 4 A schematic diagram of a structure in which a second ultra-thin tunneling silicon oxide and an amorphous passivation layer are formed simultaneously on the upper and lower surfaces;

[0043] Figure 6 for Figure 5 A schematic diagram of a structure in which an anti-reflection layer is formed on the substrate;

[0044] Figure 7 for Figure 6 A schematic diagram of a structure in which a second opening area is formed;

[0045] Figure 8 for Figure 7 A schematic diagram of a structure in which a transparent conductive film layer is formed on the substrate;

[0046] Fig. 9 for Figure 8 A schematic diagram of a structure in which an insulating groove is formed;

[0047] Fig.10 for Fig. 9 Schematic diagram of the structure of forming a metal electrode.

[0048] Description of Reference Numerals

[0049] Silicon wafer 1, first tunneling oxide layer 2, P-type doped polycrystalline layer 3, mask layer 3B, preset first opening area W1A, first opening area W1, second ultra-thin tunneling silicon oxide 4, amorphous passivation layer 5, anti-reflection layer 6, second opening area W2, transparent conductive film layer 7, insulating groove W3, metal electrode 8. DETAILED DESCRIPTION

[0050] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0052] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0053] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0054] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0055] In a first aspect, the present invention provides a short-process preparation method for a back-contact solar cell, comprising the following steps:

[0056] S1, provide silicon wafers;

[0057] S2, sequentially depositing a first tunneling oxide layer and a P-type doped polycrystalline layer on the back side of the silicon wafer to form a first semiconductor layer; the BSG layer naturally formed during the deposition of the P-type doped polycrystalline layer is used as a mask layer;

[0058] S3, performing a first etching on the first semiconductor layer on the back surface obtained in S2 to form preset first opening areas distributed at intervals;

[0059] S4, forming a velvet surface in the preset first opening area on the back side through velvet cleaning to form the first opening area; forming a velvet surface on the front side at the same time; and then selecting whether to perform a step of removing the BSG layer mask layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs;

[0060] S5. Depositing a second tunnel oxide layer and an amorphous passivation layer on the front and back surfaces simultaneously by LPCVD technology, wherein the deposition temperature of the LPCVD technology is 430-620° C.; wherein the second tunnel oxide layer and the amorphous passivation layer deposited on the back surface form a second semiconductor layer; and the amorphous passivation layer is N-type amorphous silicon or a stack of intrinsic amorphous silicon and N-type amorphous silicon;

[0061] S6. Depositing an anti-reflection layer on the outer surface of the amorphous passivation layer on the front side by using tubular PECVD technology, wherein the deposition temperature of the tubular PECVD technology is 400-600°C.

[0062] The BSG layer mask layer described in S4 of the present invention can be completely removed, retained, or partially retained, which can be freely selected according to needs. The BSG layer is formed by natural oxidation during the deposition of the P-type doped polycrystalline layer (under the corresponding deposition high temperature conditions). Compared with the conventionally deposited silicon nitride mask layer (which is formed by gas deposition), the BSG layer is denser, has fewer hole defects, and is more conducive to protecting the underlying first semiconductor layer.

[0063] It can be understood that in S5, the second tunneling oxide layer and the amorphous passivation layer are sequentially deposited on the front side to form a front passivation layer; at the same time, the second tunneling oxide layer and the amorphous passivation layer are sequentially deposited on the back side to form a second semiconductor layer. The passivation structure of the second tunneling oxide layer and the amorphous passivation layer is adopted on both the front and back sides, which is conducive to the simultaneous deposition of the front and back sides, simplifies the process flow, reduces the equipment cost, and plays a synergistic passivation effect of interface passivation and field passivation, thereby improving the overall passivation effect. Among them, the second tunneling oxide layer and the amorphous passivation layer work together to passivate the silicon wafer interface. Under the same conditions, if a conventional tunneling polycrystalline passivation structure is used as the second semiconductor layer, then in the finger-crossing structure, since the conductivity of polycrystalline silicon is several orders of magnitude higher than that of amorphous silicon, there will be a serious short circuit between the first semiconductor and the second semiconductor, and polycrystalline needs to be formed through high-temperature diffusion. If polycrystalline is used, the performance of the first semiconductor will be affected.

[0064] In some preferred embodiments of the present invention, the N-type amorphous silicon is oxygen-doped N-type amorphous silicon and the oxygen doping concentration is 5e20cm -3 -2e22cm -3 The present invention adopts an amorphous passivation layer that is appropriately doped with oxygen, which is more conducive to reducing the refractive index and absorption coefficient of amorphous silicon, thereby further increasing the current of the battery.

[0065] When forming oxygen-doped N-type amorphous silicon, oxygen doping can be achieved by introducing a gas containing an oxygen source such as nitrous oxide into the original process gas, and the oxygen doping concentration can be controlled by adjusting the flow rate of the oxygen source. This is a prior art and will not be described in detail here.

[0066] In some preferred embodiments of the present invention, the amorphous passivation layer is a stack of intrinsic amorphous silicon and N-type amorphous silicon, and the thickness ratio of intrinsic amorphous silicon to N-type amorphous silicon is (0.2-1):1, for example, it can be 0.2:1, 0.3:1, 0.5:1, 0.7:1, 0.8:1, 0.9:1, 1:1, etc. and the range between any two point values. Using this stack as an amorphous passivation layer is more conducive to improving the passivation effect and reducing the series resistance, thereby improving the battery efficiency.

[0067] In some preferred embodiments of the present invention, the ratio of the thickness of the first tunneling oxide layer to the second tunneling oxide layer is 1: (0.1-1), preferably 1: (0.1-0.8). The use of the first tunneling oxide layer and the second tunneling oxide layer with a suitable thickness ratio is more conducive to improving the passivation effect and reducing the series resistance, thereby improving the battery efficiency. Furthermore, since the first semiconductor layer in the present invention is a P-type doped polycrystalline layer, the P-type doped polycrystalline layer needs to be formed by high-temperature diffusion. If the doping elements penetrate the first tunneling oxide layer during the diffusion process, the passivation effect will be seriously affected. Therefore, the thickness of the first tunneling oxide layer needs to be thick enough, and the second semiconductor layer adopts a tunneling amorphous passivation structure. The N-type amorphous silicon of the amorphous passivation layer can be formed by in-situ doping without high-temperature diffusion, and an excessively thick tunneling oxide layer will increase the series resistance. Therefore, the second tunneling oxide layer can be thinner than the first tunneling oxide layer.

[0068] In some preferred embodiments of the present invention, the ratio of the surface doping index of the P-type doped polycrystalline layer and the amorphous passivation layer is (0.05-5):1, preferably 0.05-0.3:1, and further preferably 0.1-0.3:1, wherein the surface doping index refers to the ratio of the effective boron doping concentration or the effective phosphorus doping concentration of the corresponding layer to the thickness of the layer, and the unit of the effective boron doping concentration or the effective phosphorus doping concentration is cm -3 The unit of thickness is nm. Using a P-type doped polycrystalline layer and an amorphous passivation layer with a suitable ratio of surface doping index is more conducive to improving the passivation effect and reducing the series resistance, thereby improving the battery efficiency.

[0069] In some preferred embodiments of the present invention, the thickness of the second tunnel oxide layer is 0.3-1.3 nm, and the thickness of the amorphous passivation layer is 1.5-15 nm. Using the second tunnel oxide layer and the amorphous passivation layer in a suitable thickness range is more conducive to taking into account the front optical loss, passivation effect and series resistance, thereby improving the battery efficiency.

[0070] The thickness of the second tunneling oxide layer is 0.1-1.3 nm, for example, 0.1 nm, 0.2 nm, 0.3 nm, 0.4 nm, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, etc., and the range between any two point values.

[0071] The thickness of the amorphous passivation layer is 1.5-15 nm, for example, 1.5 nm, 1.8 nm, 2.0 nm, 3.0 nm, 4.0 nm, 5.0 nm, 7.0 nm, 10.0 nm, 12.0 nm, 15.0 nm, etc., and the range between any two point values.

[0072] Preferably, the effective phosphorus doping concentration of N-type amorphous silicon is 5e18cm -3 -2e20cm -3 The use of an amorphous passivation layer with an appropriate effective phosphorus doping concentration is more conducive to taking into account the front optical loss, passivation effect and series resistance.

[0073] In some preferred embodiments of the present invention, the thickness of the first tunnel oxide layer is 1.3-2 nm, the thickness of the P-type doped polycrystalline layer is 50-150 nm, and the effective boron doping concentration is 5e18 cm -3 -4e20 cm -3 ; The thickness of the BSG layer is 10-40nm, preferably 20-40nm.

[0074] The thickness of the first tunneling oxide layer is 1.3-2 nm, and specifically can be 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2.0 nm, etc., and a range between any two point values.

[0075] In some preferred embodiments of the present invention, the thickness of the second tunnel oxide layer is less than the thickness of the first tunnel oxide layer, which is more conducive to reducing the series resistance.

[0076] In some preferred embodiments of the present invention, the second tunneling oxide layer is ultra-thin tunneling silicon oxide and the thickness of the ultra-thin tunneling silicon oxide is 0.1-1.3 nm. In the present invention, since the amorphous passivation layer adopts in-situ doping and does not require high-temperature diffusion doping, ultra-thin tunneling silicon oxide can be used, which ensures the series resistance and is more conducive to improving the battery efficiency.

[0077] In some preferred embodiments of the present invention, the first semiconductor layer is formed by LPCVD deposition followed by diffusion annealing, or by tubular PECVD deposition followed by annealing. It is understood that a BSG layer is naturally formed during the corresponding annealing process. Further preferably, the annealing temperature is 850-1050°C.

[0078] The specific deposition conditions of the LPCVD technology and tubular PECVD technology corresponding to each step of the present invention can be selected from the corresponding deposition conditions of the prior art, as long as the target film layer of the required thickness and doping concentration can be obtained, and will not be repeated here.

[0079] The anti-reflection layer of the present invention may be at least one of silicon nitride, silicon oxynitride and silicon oxide. The thickness of the anti-reflection layer may be, for example, 70-150 nm.

[0080] In some preferred embodiments of the present invention, the short-process preparation method of the back-contact solar cell further comprises:

[0081] S7, performing a second etching on the second semiconductor layer corresponding to the polished area of ​​the back surface obtained in S6 to expose the first semiconductor layer and form a second opening area spaced apart from the first opening area;

[0082] S8, forming a conductive film layer to fully cover the back surface obtained in S7;

[0083] S9, then performing a third etching on the conductive film layer portion located between the second opening area and the first opening area on the back side obtained in S8 to form an insulating groove;

[0084] S10, forming metal electrodes on the outer surfaces of the second opening area and the first opening area corresponding to the back surface obtained in S9.

[0085] In a second aspect, the present invention provides a back-contact solar cell, which is produced by the short-process preparation method of the back-contact solar cell described in the first aspect.

[0086] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0087] Example 1

[0088] A novel method for preparing a back-contact solar cell, comprising:

[0089] S1, such as Figure 1 As shown, a silicon wafer 1 is provided, and the silicon wafer 1 is polished and cleaned in sequence;

[0090] S2, such as Figure 2 As shown, a first tunneling oxide layer 2 (specifically, tunneling silicon oxide) and a P-type doped polycrystalline layer 3 are sequentially formed on the back side of the silicon wafer 1 to form a first semiconductor layer; a BSG layer naturally formed during the deposition of the P-type doped polycrystalline layer 3 is used as a mask layer 3B; the thickness of the first tunneling oxide layer 2 is 1.7 nm, the thickness of the P-type doped polycrystalline layer 3 is 120 nm, and the effective boron doping concentration is 1.2e20 cm -3 The first semiconductor layer is formed by diffusion annealing after being deposited by LPCVD technology, the highest annealing temperature is 980° C., and a BSG layer is naturally formed during the diffusion annealing process. The thickness of the mask layer 3B is 25 nm.

[0091] S3, such as Figure 3As shown, the first semiconductor layer is first etched on the back surface obtained in S2 to form preset first opening areas W1A distributed at intervals;

[0092] S4, such as Figure 4 As shown, through the texturing and cleaning, a velvet surface is formed in the preset first opening area W1A on the back side, forming the first opening area W1, and a velvet surface is formed on the front side at the same time;

[0093] S5, such as Figure 5 As shown, a second ultra-thin tunneling silicon oxide 4 and an amorphous passivation layer 5 are formed simultaneously on the front and back sides by LPCVD technology. The second ultra-thin tunneling silicon oxide 4 has a thickness of 1.0 nm, and the amorphous passivation layer 5 is N-type amorphous silicon with a thickness of 8 nm and an effective phosphorus doping concentration of 4e19cm -3 , the deposition temperature of the LPCVD technology is 580°C.

[0094] S6, such as Figure 6 As shown, an anti-reflection layer 6 is formed on the front side of the battery by using tubular PECVD technology. The anti-reflection layer 6 is silicon nitride with a thickness of 80 nm. The temperature of depositing the anti-reflection layer by using the tubular PECVD technology is 480°C.

[0095] S7, such as Figure 7 As shown, a second etching is then performed on the second semiconductor layer corresponding to the polished area of ​​the back surface obtained in S6 to expose the first semiconductor layer, thereby forming a second opening area W2 spaced apart from the first opening area W1;

[0096] S8, such as Figure 8 As shown, a transparent conductive film layer 7 is formed on the back surface obtained in S7 to fully cover the back surface;

[0097] S9, such as Fig. 9 As shown, the transparent conductive film layer 7 located between the second opening area W2 and the first opening area W1 on the back side obtained in S8 is subjected to a third etching to form an insulating groove W3;

[0098] S10, such as Fig.10 As shown, metal electrodes 8 are respectively formed on the outer surfaces of the second opening area W2 and the first opening area W1 on the back side obtained in S9.

[0099] Example 2

[0100] The method of Example 1 is followed, except that the type of amorphous passivation layer deposited on the front and back sides is replaced by oxygen-doped N-type amorphous silicon with an oxygen doping concentration of 8e20cm -3 、Effective phosphorus doping concentration is 8e19cm -3 , the thickness remains unchanged.

[0101] Example 3

[0102] The method of Example 1 is referred to, except that the type of amorphous passivation layer deposited on the front and back sides is replaced by a stack of intrinsic amorphous silicon (4 nm thick) and N-type amorphous silicon (4 nm thick, with the same doping concentration as the N-type amorphous silicon in Example 1).

[0103] Example 4

[0104] The method of Example 1 is referred to, except that the thickness of the first tunneling oxide layer and the second ultra-thin tunneling silicon oxide are adjusted to 1.3 nm. The thickness ratio of the first tunneling oxide layer and the second ultra-thin tunneling silicon oxide is calculated to be 1:1.

[0105] Example 5

[0106] The method of Example 1 is referred to, except that the thickness of the amorphous passivation layer is adjusted to 15 nm, so that the ratio of the surface doping index of the P-type doped polycrystalline layer and the amorphous passivation layer is 0.4:1.

[0107] Example 6

[0108] The method of Example 1 is followed, except that the effective boron doping concentration of the P-type doped polycrystalline layer is adjusted to 5e19cm -3 At this time, the thickness of the BSG layer naturally formed with the P-type doped polycrystalline layer is 15nm.

[0109] Comparative Example 1

[0110] The method of Example 1 is referred to, except that a conventional preparation process is adopted, and the specific difference is:

[0111] S2 uses N-type doped polysilicon (thickness 120nm, effective phosphorus doping concentration 1e20cm -3 ) replace the P-type doped polycrystalline layer, remove the PSG naturally formed during the deposition of N-type doped polysilicon, and then deposit the mask layer silicon nitride; and remove the mask layer after S4 texturing and cleaning;

[0112] Then, a second semiconductor layer is formed on the back surface obtained in S5, and an amorphous passivation layer (with the same composition structure as in Example 1) and a silicon nitride anti-reflection layer are formed on the front surface. The second semiconductor layer, the amorphous passivation layer and the silicon nitride anti-reflection layer are formed on the front and back surfaces respectively by plate-type PECVD; the second semiconductor layer includes an intrinsic amorphous silicon layer (with a thickness of 6 nm) and a P-type doped amorphous silicon layer (with a thickness of 10 nm and an effective boron doping concentration of 3e19 cm-1) formed in sequence on the back surface. -3 ).

[0113] Comparative Example 2

[0114] The method of Example 1 is carried out, except that,

[0115] S2 uses N-type doped polysilicon (thickness 120nm, effective phosphorus doping concentration 8e19cm -3 ) replace the P-type doped polycrystalline layer, remove the PSG naturally formed during the deposition of N-type doped polysilicon, and then deposit the mask layer silicon nitride; and remove the mask layer after S4 texturing and cleaning;

[0116] In S5, the corresponding N-type doped film layer of the amorphous passivation layer is replaced with a P-type doped film layer, and the second ultra-thin tunneling silicon oxide and the amorphous passivation layer are deposited simultaneously on the front and back sides according to the method of Example 1, that is, the front passivation layer is also P-type. In this comparative example 2, since the P-type has a smaller band gap than the N-type and the passivation effect is not as good as the N-type, the P-type front passivation layer absorbs more light, the passivation is worse, and the battery efficiency will be lower.

[0117] Comparative Example 3

[0118] The method of Example 1 is referred to, except that the N-type doped amorphous silicon film layer corresponding to the amorphous passivation layer in S5 is replaced by an N-type doped polysilicon film layer.

[0119] Test Case

[0120] The back-contact solar cells obtained in the above-mentioned embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The process cycle, equipment cost, and series resistance of each embodiment and comparative example were converted using embodiment 1 as a reference benchmark, and the data of embodiment 1 was normalized to 1. Other examples were converted based on embodiment 1, such as the process cycle of comparative example 1 / process cycle of embodiment 1 was 1.2. In the normalization process, the process cycle refers to the time from step 1 to step 10 for preparing a batch of cells.

[0121] Table 1

[0122]

[0123] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention can obtain basically the same or better passivation effect on the front and back sides while simplifying the preparation process and reducing equipment costs, thereby improving the battery conversion efficiency.

[0124] Furthermore, according to Example 1 and Examples 3-6, it can be seen that the preferred preparation method of the present invention is more conducive to improving the battery conversion efficiency.

[0125] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A short-process preparation method for back-contact solar cells, characterized in that: The steps include: S1, provide silicon wafers; S2, sequentially depositing a first tunneling oxide layer and a P-type doped polycrystalline layer on the back side of the silicon wafer to form a first semiconductor layer; the BSG layer naturally formed during the deposition of the P-type doped polycrystalline layer is used as a mask layer; S3, performing a first etching on the first semiconductor layer on the back surface obtained in S2 to form preset first opening areas distributed at intervals; S4, forming a velvet surface in the preset first opening area on the back side through velvet cleaning to form the first opening area; forming a velvet surface on the front side at the same time; and then selecting whether to perform a step of removing the BSG layer mask layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs; S5. Depositing a second tunnel oxide layer and an amorphous passivation layer on the front and back surfaces simultaneously by LPCVD technology, wherein the deposition temperature of the LPCVD technology is 430-620° C.; wherein the second tunnel oxide layer and the amorphous passivation layer deposited on the back surface form a second semiconductor layer; and the amorphous passivation layer is N-type amorphous silicon or a stack of intrinsic amorphous silicon and N-type amorphous silicon; S6. Depositing an anti-reflection layer on the outer surface of the amorphous passivation layer on the front side by using a tubular PECVD technology, wherein the deposition temperature of the tubular PECVD technology is 400-600° C.; S7, performing a second etching on the second semiconductor layer corresponding to the polished area of ​​the back surface obtained in S6 to expose the first semiconductor layer and form a second opening area spaced apart from the first opening area; S8, forming a conductive film layer to fully cover the back surface obtained in S7; S9, then performing a third etching on the conductive film layer portion located between the second opening area and the first opening area on the back side obtained in S8 to form an insulating groove; S10, forming metal electrodes on the outer surfaces of the second opening area and the first opening area corresponding to the back surface obtained in S9.

2. The short-process preparation method of back-contact solar cells according to claim 1, characterized in that: N-type amorphous silicon is oxygen-doped N-type amorphous silicon and the oxygen doping concentration is 5e20cm -3 -2e22cm -3 .

3. The short-process preparation method of back-contact solar cells according to claim 1, characterized in that: The amorphous passivation layer is a stack of intrinsic amorphous silicon and N-type amorphous silicon, and the ratio of the thickness of the intrinsic amorphous silicon to the N-type amorphous silicon is (0.2-1):1; and / or the ratio of the thickness of the first tunneling oxide layer to the second tunneling oxide layer is 1:(0.1-1).

4. The short-process preparation method of back-contact solar cells according to claim 1 or 3, characterized in that: The ratio of the surface doping index of the P-type doped polycrystalline layer and the amorphous passivation layer is (0.05-5):1, where the surface doping index refers to the ratio of the effective boron doping concentration or effective phosphorus doping concentration of the corresponding layer to the thickness of the layer. The unit of effective boron doping concentration or effective phosphorus doping concentration is cm -3 , the unit of thickness is nm.

5. The short-process preparation method of back-contact solar cells according to claim 1, characterized in that: The thickness of the second tunnel oxide layer is 0.3-1.3 nm, the thickness of the amorphous passivation layer is 1.5-15 nm, and the effective phosphorus doping concentration of N-type amorphous silicon is 5e18 cm -3 -2e20cm -3 .

6. The short-process preparation method of back-contact solar cells according to claim 1 or 5, characterized in that: The thickness of the first tunnel oxide layer is 1.3-2nm, the thickness of the P-type doped polycrystalline layer is 50-150nm, and the effective boron doping concentration is 5e18 cm -3 -4e20 cm -3 ; The thickness of the BSG layer is 10-40nm.

7. The short-process preparation method of back-contact solar cells according to claim 1, characterized in that: The thickness of the second tunnel oxide layer is smaller than the thickness of the first tunnel oxide layer.

8. The short-process preparation method of back-contact solar cells according to claim 1, characterized in that: The second tunneling oxide layer is ultra-thin tunneling silicon oxide, and the thickness of the ultra-thin tunneling silicon oxide is 0.1-1.3 nm.

9. The short-process preparation method of back-contact solar cells according to claim 1, characterized in that: The first semiconductor layer is formed by LPCVD deposition followed by diffusion annealing, or by tubular PECVD deposition followed by annealing.

10. A back contact solar cell, characterized in that: The solar cell is prepared by the short-process preparation method of the back-contact solar cell as described in any one of claims 1 to 9.

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