Display device and method for manufacturing same

Abstract

A display device and a method for manufacturing the same are disclosed. The display device comprises a display panel, and the display panel comprises a semiconductor wafer substrate; a complementary metal oxide semiconductor (CMOS) layer disposed on the first side of the semiconductor wafer substrate and including a plurality of display driving circuits driven independently of each other; a transistor layer disposed on the second side of the semiconductor wafer substrate and including a plurality of pixel driving circuits connected to the plurality of display driving circuits through contact holes in the semiconductor wafer substrate; a light-emitting element layer disposed on the second side of the semiconductor wafer substrate and including light-emitting elements driven by a plurality of pixel driving circuits; and an encapsulation layer disposed on the second side of the semiconductor wafer substrate.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0093174 filed in the Korean Intellectual Property Office on July 18, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0003] Wearable devices designed as glasses or helmets are currently being developed. The device is designed to project images at a distance close to the user's eyes. Examples of wearable devices include head-mounted display (HMD) devices or augmented reality (AR) glasses. Such wearable devices provide AR images or virtual reality (VR) images to the user.

[0004] Wearable devices such as HMD devices or AR glasses require displays with specifications of at least 2000 pixels per inch (PPI). This high resolution allows users to use the device for a long period of time without feeling uncomfortable or dizzy. In response to this requirement, the technology of organic light emitting diodes on silicon (OLEDoS) came into being. OLEDoS is a small organic light emitting display device with high resolution. OLEDoS is characterized in that an organic light emitting diode (OLED) is placed on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is already provided. Summary of the invention

[0005] Embodiments of the present disclosure provide a display device capable of improving the product yield of a display panel having a light emitting element disposed on a semiconductor wafer substrate and can be easily repaired. Embodiments of the present disclosure also provide a method for manufacturing the display device.

[0006] According to an embodiment of the present disclosure, a display device is provided, which includes a display panel, wherein the display panel includes: a semiconductor wafer substrate; a complementary metal oxide semiconductor (CMOS) layer, which is arranged on a first side of the semiconductor wafer substrate and includes a plurality of display driving circuits driven independently of each other; a transistor layer, which is arranged on a second side of the semiconductor wafer substrate and includes a plurality of pixel driving circuits connected to the plurality of display driving circuits through contact holes in the semiconductor wafer substrate; a light emitting element layer, which is arranged on the second side of the semiconductor wafer substrate and includes light emitting elements driven by the plurality of pixel driving circuits; and a packaging layer, which is arranged on the second side of the semiconductor wafer substrate.

[0007] The display panel includes a display area and a non-display area, a plurality of pixels including light emitting elements are disposed in the display area, and a plurality of display driving circuits overlap the plurality of pixels in the display area.

[0008] A plurality of display driving circuits are arranged at intervals in the CMOS layer.

[0009] The plurality of display driving circuits include the same circuit.

[0010] The multiple display driving circuits include: a first display driving circuit, which is arranged to correspond to a first area of ​​the display area and includes a first circuit for driving multiple pixel driving circuits; and a second display driving circuit, which is arranged to correspond to a second area of ​​the display area and includes a second circuit for driving multiple pixel driving circuits, and the first circuit and the second circuit are the same.

[0011] The multiple display driving circuits also include: a third display driving circuit, which is configured to correspond to a third area of ​​the display area and includes a third circuit for driving multiple pixel driving circuits; and a fourth display driving circuit, which is configured to correspond to a fourth area of ​​the display area and includes a fourth circuit for driving multiple pixel driving circuits, and the first circuit, the second circuit, the third circuit and the fourth circuit are the same.

[0012] The contact holes include: a plurality of first contact holes, connecting the first display driving circuit and the plurality of pixel driving circuits; a plurality of second contact holes, connecting the second display driving circuit and the plurality of pixel driving circuits; a plurality of third contact holes, connecting the third display driving circuit and the plurality of pixel driving circuits; and a plurality of fourth contact holes, connecting the fourth display driving circuit and the plurality of pixel driving circuits.

[0013] Each of the plurality of pixel driving circuits includes an oxide-based thin film transistor.

[0014] The display panel further includes: a color filter layer disposed on the second side of the semiconductor wafer substrate and including a color filter; and a light control layer disposed on the second side of the semiconductor wafer substrate and including a refractive film.

[0015] The display panel further includes: a first cover window disposed on the first side of the semiconductor wafer substrate; and a second cover window disposed on the second side of the semiconductor wafer substrate.

[0016] According to an embodiment of the present disclosure, a method for manufacturing a display device is provided, the method comprising the following steps: preparing a semiconductor wafer substrate; forming a CMOS layer on the front surface of the semiconductor wafer substrate, the CMOS layer including a plurality of display driving circuits driven independently of each other; attaching a first cover window to the CMOS layer; performing a chemical mechanical polishing (CMP) process step, the chemical mechanical polishing (CMP) process step polishing the rear surface of the semiconductor wafer substrate to expose contact holes connected to the plurality of display driving circuits; forming a transistor layer including a plurality of pixel driving circuits on the rear surface of the semiconductor wafer substrate, the plurality of pixel driving circuits being connected to the plurality of display driving circuits through contact holes; forming a light-emitting element layer on the transistor layer, the light-emitting element layer including light-emitting elements driven by the plurality of pixel driving circuits; and forming a packaging layer on the light-emitting element layer.

[0017] A display panel included in the display device includes a display area and a non-display area, a plurality of pixels including light emitting elements are disposed in the display area, and a plurality of display driving circuits overlap the plurality of pixels in the display area.

[0018] A plurality of display driving circuits are arranged at intervals in the CMOS layer.

[0019] The plurality of display driving circuits include the same circuit.

[0020] The multiple display driving circuits include: a first display driving circuit, which is arranged to correspond to a first area of ​​the display area and includes a first circuit for driving multiple pixel driving circuits; and a second display driving circuit, which is arranged to correspond to a second area of ​​the display area and includes a second circuit for driving multiple pixel driving circuits, and the first circuit and the second circuit are the same.

[0021] The multiple display driving circuits also include: a third display driving circuit, which is configured to correspond to a third area of ​​the display area and includes a third circuit for driving multiple pixel driving circuits; and a fourth display driving circuit, which is configured to correspond to a fourth area of ​​the display area and includes a fourth circuit for driving multiple pixel driving circuits, and the first circuit, the second circuit, the third circuit and the fourth circuit are the same.

[0022] The contact holes include: a plurality of first contact holes, connecting the first display driving circuit and the plurality of pixel driving circuits; a plurality of second contact holes, connecting the second display driving circuit and the plurality of pixel driving circuits; a plurality of third contact holes, connecting the third display driving circuit and the plurality of pixel driving circuits; and a plurality of fourth contact holes, connecting the fourth display driving circuit and the plurality of pixel driving circuits.

[0023] Each of the plurality of pixel driving circuits includes an oxide-based thin film transistor.

[0024] The method further includes: forming a color filter layer including a color filter on the encapsulation layer; and forming a light control layer including a refractive film on the color filter layer.

[0025] The method also includes attaching a second cover window to the light management layer.

[0026] According to the display device and the method for manufacturing the same according to the embodiment, the product yield of the display panel can be improved, and the repair of the display panel can be simplified, thereby reducing the manufacturing cost of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0028] Figure 1 is a perspective view showing a display device according to an embodiment;

[0029] Figure 2 is a plan view showing a front surface of a display panel according to an embodiment;

[0030] Figure 3 is a plan view showing a rear surface of a display panel according to an embodiment;

[0031] Figure 4 is a block diagram of a display device according to an embodiment;

[0032] Figure 5A is a diagram showing a semiconductor wafer for manufacturing a display panel according to a comparative example;

[0033] Figure 5B is a diagram showing a semiconductor wafer for manufacturing a display panel according to an embodiment;

[0034] Figure 6 is a block diagram showing connection between a display panel and any one of a plurality of display driving circuits according to an embodiment;

[0035] Figure 7 is a circuit diagram of a pixel of a display device according to an embodiment;

[0036] Figure 8 It is shown Figure 7 A diagram showing a driving timing of a pixel driving circuit shown in FIG.

[0037] Fig. 9 is a cross-sectional view of a portion of a display area of ​​a display panel according to an embodiment;

[0038] Fig.10 is a flow chart showing at least a portion of a process for manufacturing a display device according to an embodiment;

[0039] Fig.11 is a diagram showing steps of preparing a semiconductor wafer;

[0040] Fig.12 is a diagram showing a step of forming a complementary metal oxide semiconductor (CMOS) layer;

[0041] Fig.13 is a diagram showing a step of attaching a first cover window;

[0042] Fig.14 is a diagram showing steps of a chemical mechanical polishing pad (CMP) process;

[0043] Fig.15 is a diagram showing a step of forming a transistor layer;

[0044] Fig.16 is a diagram showing a step of forming a light emitting element layer and an encapsulation layer;

[0045] Fig.17 is a diagram showing a virtual reality device including a display device according to an embodiment; and

[0046] Fig.18 and Fig.19 : is a diagram showing a head mounted display device to which the display device according to the embodiment is applied. DETAILED DESCRIPTION

[0047] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

[0048] It will be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numerals may refer to the same components throughout the specification.

[0049] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0050] The features of each of the various embodiments of the present disclosure may be combined with each other in part or in whole, and may interact with each other in different technical aspects. In addition, the various embodiments may be implemented independently of each other, or may be implemented together in association with each other.

[0051] Figure 1 is a perspective view showing a display device 10 according to the embodiment.

[0052] Reference Figure 1 , the display device 10 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied to a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IOT) device. As another example, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs).

[0053] The display device 10 may be formed in a planar shape similar to a quadrilateral. For example, the display device 10 may have a planar shape similar to a quadrilateral having short sides in the horizontal direction DR1 and long sides in the vertical direction DR2. Figure 1 , DR3 represents a normal direction perpendicular to a plane formed by the horizontal direction DR1 and the vertical direction DR2. The corner where the short side and the long side meet may be rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display device 10 is not limited to a quadrilateral, and may be formed similarly to other polygons, a circle, or an ellipse.

[0054] The display device 10 includes a display panel 110 , a circuit board 120 , and a power supply unit 130 .

[0055] The display panel 110 uses a semiconductor wafer substrate 200 (see Figure 2 ) as a base substrate. The display panel 110 may include a main area MA and a sub-area SBA. Here, the semiconductor wafer substrate 200 may be referred to as a 'substrate'.

[0056] The main area MA may include pixels ( Figure 6 The display panel 110 may include a display area DA (PX in FIG. 1 ) and a non-display area NDA disposed around the display area DA. The non-display area NDA may refer to an area other than the display area DA. The display area DA may emit light from a plurality of light emitting areas or a plurality of opening areas. For example, the display panel 110 may include a pixel driving circuit ( Figure 7 PC in the middle), pixel defining film ( Fig. 9 PDL in the image processing unit) and light-emitting element as self-luminous element (LEL) ( Fig. 9 in LEL).

[0057] The light emitting element LEL may include at least one of an organic light emitting diode (organic LED, OLED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0058] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be an edge area of ​​the main area MA of the display panel 110. The non-display area NDA may include fan-out lines (e.g., gate lines, data lines, and emission control lines) extending from lines of the display area DA. Figure 4 The non-display area NDA may further include a display pad portion connecting the fan-out line FL and a plurality of display driving circuits 210 disposed on the front surface 201 of the semiconductor wafer substrate 200. For example, the display pad portion disposed in the non-display area NDA may be formed by a contact hole ( Figure 4 450 and Fig. 9 The CT210 and CT220 in the semiconductor wafer substrate 200 are electrically connected to a plurality of display driving circuits 210 disposed on the front surface 201 of the semiconductor wafer substrate 200.

[0059] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a main pad portion connected to the circuit board 120. Alternatively, the sub-area SBA may be omitted, and the main pad portion may be disposed in the non-display area NDA.

[0060] The circuit board 120 may be attached to the main pad of the display panel 110 using an anisotropic conductive film (ACF). Leads of the circuit board 120 may be electrically connected to the main pad of the display panel 110. The circuit board 120 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0061] The power supply unit 130 may be disposed on the circuit board 120 and may supply a power voltage to the display driving circuit 210 and the display panel 110. The power supply unit 130 may generate a driving voltage and supply the driving voltage to the driving voltage line VDL (see Figure 6 In addition, the power supply unit 130 may generate a common voltage and supply the common voltage to a common electrode (eg, Fig. 9 For example, the driving voltage may be a high potential voltage for driving the light emitting element LEL, and the common voltage may be a low potential voltage for driving the light emitting element LEL.

[0062] Figure 2 is a plan view showing the front surface 201 of the display panel 110 according to the embodiment. Figure 32 is a plan view showing the rear surface 202 of the display panel 110 according to the embodiment. Figure 2 In FIG. 1 , components disposed on the front surface 201 of the display panel 110 are shown as solid lines, and components disposed on the rear surface 202 of the display panel 110 are shown as dotted lines. Figure 3 , components disposed on the rear surface 202 of the display panel 110 are illustrated as solid lines, and components disposed on the front surface 201 of the display panel 110 are illustrated as dotted lines.

[0063] Reference Figure 2 The display panel 110 may be an organic light emitting diode on silicon (OLEDoS) panel using a semiconductor wafer substrate 200 as a base. For example, the display panel 110 may include a semiconductor wafer substrate 200. A CMOS layer 910 (see FIG. 1 ) including a complementary metal oxide semiconductor (CMOS) forming a display driving circuit 210 may be formed. Fig. 9 ) may be disposed on the front surface 201 of the semiconductor wafer substrate 200. The CMOS forming the display driving circuit 210 may include field effect transistors, for example, n-type metal oxide semiconductor field effect transistors (MOSFET) and / or p-type MOSFET. Here, the CMOS layer 910 may be referred to as a "first driving element layer".

[0064] According to an embodiment, a plurality of display driving circuits 210 driven independently of each other are embedded in one display panel 110. Each of the plurality of display driving circuits 210 may output a signal for driving the display panel 110 (eg, a signal for driving a pixel driving circuit ( Figure 7 The signal and voltage of the PC in the circuit.

[0065] A plurality of display driving circuits 210 are arranged at intervals on the CMOS layer ( Fig. 9 910 in the display area DA) and is set to correspond to the display area DA. Each of the plurality of display driving circuits 210 controls the pixel driving circuit ( Figure 7PC in). All of the multiple display driving circuits 210 may include the same circuit components. For example, the multiple display driving circuits 210 include circuits that are identical to each other and are configured to perform the same function. In other words, one display panel 110 includes multiple display driving circuits 210. However, the display panel 110 may use only one display driving circuit among the multiple display driving circuits 210 to control the pixel driving circuit PC. The reason why the display panel 110 according to the embodiment includes multiple display driving circuits 210 is to improve the yield of the display panel 110 among the number of net dies (net die) included in one semiconductor wafer 600. In other words, by including multiple display driving circuits 210, the yield of a single die can be improved. According to an embodiment, if at least one display driving circuit among the multiple display driving circuits 210 disposed on the front surface 201 of the semiconductor wafer substrate 200 is not defective, the display panel 110 manufactured by one die can be shipped as a non-defective product. In the display device 10 according to the embodiment of the present disclosure, since the display panel 110 can be easily repaired, the manufacturing cost can be reduced.

[0066] According to an embodiment, the plurality of display driving circuits 210 may include two or more display driving circuits 210. For example, the plurality of display driving circuits 210 include a first display driving circuit 211 and a second display driving circuit 212. The first display driving circuit 211 includes a first circuit 410 (see FIG. 4 ) disposed in the CMOS layer 910 to correspond to a first area of ​​the display area DA. Figure 4 The second display driving circuit 212 includes a second circuit 420 in the CMOS layer 910 that is arranged to correspond to a second area of ​​the display area DA (see Figure 4 ). The first circuit 410 and the second circuit 420 may be the same circuit. In addition, the plurality of display driving circuits 210 may further include a third display driving circuit 213 and a fourth display driving circuit 214, but the present disclosure is not limited thereto. The third display driving circuit 213 includes a third circuit 430 (see FIG. 1 ) disposed in the CMOS layer 910 and corresponding to the third area of ​​the display area DA. Figure 4 The fourth display driving circuit 214 includes a fourth circuit 440 in the CMOS layer 910 arranged to correspond to a fourth area of ​​the display area DA (see FIG. 1 ). Figure 4 ). The first to fourth circuits 410, 420, 430, and 440 may be the same circuit.

[0067] Reference Figure 3 , transistor layer ( Fig. 9 940) and the light emitting element layer ( Fig. 9 The transistor layer 940 may include a transistor for driving a light emitting element ( Fig. 9 The fan-out lines FL may be formed by penetrating the semiconductor wafer substrate 200 through contact holes ( Figure 4 450 and Fig. 9 The pixel driving circuit PC is electrically connected to the plurality of display driving circuits 210 disposed on the front surface 201 of the semiconductor wafer substrate 200 through the contact holes (CT210 and CT220). In other words, the pixel driving circuit PC can be electrically connected to the plurality of display driving circuits 210 disposed on the front surface 201 of the semiconductor wafer substrate 200 through the contact holes (CT210 and CT220). Figure 4 450 and Fig. 9 CT210 and CT220 in the display drive circuit 210 are electrically connected to the plurality of display drive circuits 210. For example, the plurality of display drive circuits 210 may include first to fourth display drive circuits 211, 212, 213, and 214, and in this case, the contact hole 450 may include a first contact hole ( Figure 4 451 in), the second contact hole ( Figure 4 452 in), the third contact hole ( Figure 4 453) and the fourth contact hole ( Figure 4 454 in ). Here, the transistor layer 940 may be referred to as a "second driving element layer".

[0068] The first contact hole 451 can connect the first display driving circuit 211 and the plurality of pixel driving circuits PC. In other words, the first contact hole 451 can be used to connect the first display driving circuit 211 to the display panel 110. For example, the first contact hole 451 can be provided in the non-display area NDA to connect the first display driving circuit 211 and the fan-out line ( Figure 4 FL) electrical connection.

[0069] The second contact hole 452 can connect the second display driving circuit 212 and the plurality of pixel driving circuits PC. In other words, the second contact hole 452 can be used to connect the second display driving circuit 212 to the display panel 110. For example, the second contact hole 452 can be provided in the non-display area NDA to connect the second display driving circuit 212 and the fan-out line ( Figure 4 FL) electrical connection.

[0070] The third contact hole 453 can connect the third display driving circuit 213 and the plurality of pixel driving circuits PC. In other words, the third contact hole 453 can be used to connect the third display driving circuit 213 to the display panel 110. For example, the third contact hole 453 can be provided in the non-display area NDA to connect the third display driving circuit 213 and the fan-out line ( Figure 4 FL) electrical connection.

[0071] The fourth contact hole 454 can connect the fourth display driving circuit 214 and the plurality of pixel driving circuits PC. In other words, the fourth contact hole 454 can be used to connect the fourth display driving circuit 214 to the display panel 110. For example, the fourth contact hole 454 can be provided in the non-display area NDA to connect the fourth display driving circuit 214 and the fan-out line ( Figure 4 FL) electrical connection.

[0072] The pixel driving circuit PC may be a circuit that drives each of the plurality of pixels PX disposed in the display area DA, and may include a plurality of thin film transistors ( Figure 7 T1, T2, T3, T4 and T5) and one or more capacitors ( Figure 7 The plurality of thin film transistors T1, T2, T3, T4, and T5 included in the pixel driving circuit PC may include oxide-based thin film transistors.

[0073] Here, the front surface 201 of the semiconductor wafer substrate 200 indicates a surface facing the first direction Z1 (e.g., the first normal direction) from the semiconductor wafer substrate 200. The rear surface 202 of the semiconductor wafer substrate 200 indicates a surface facing the second direction Z2 (e.g., the second normal direction) opposite to the first direction Z1 from the semiconductor wafer substrate 200. Here, the first direction Z1 indicates a normal direction along which the field effect transistor (e.g., MOSFET) of the CMOS layer 910 is formed from the semiconductor wafer substrate 200. Here, the second direction Z2 indicates a normal direction opposite to the first direction Z1.

[0074] Figure 4 FIG. 1 is a block diagram showing a configuration of a display device 10 according to an embodiment. Figure 4 In the embodiment, for the convenience of explanation, the first to fourth display driving circuits 211, 212, 213 and 214 and the display panel 110 are shown separately from each other, but the first to fourth display driving circuits 211, 212, 213 and 214 are embedded in the CMOS layer ( Fig. 9 910). Similarly, Figure 4 In the figure, for convenience of explanation, the fan-out line FL and the contact hole 450 are shown separately from the display panel 110 , but the fan-out line FL and the contact hole 450 may be provided in the non-display area NDA of the display panel 110 .

[0075] Reference Figure 4According to an embodiment, a first display driving circuit 211, a second display driving circuit 212, a third display driving circuit 213, and a fourth display driving circuit 214 are embedded in the display panel 110. The first to fourth display driving circuits 211, 212, 213, and 214 may be formed in a CMOS layer 910 disposed on a front surface 201 of a semiconductor wafer substrate 200.

[0076] The first display driving circuit 211 includes a first timing controller 411, a first gate driver 412, a first emission control driver 413, and a first data driver 414 as a first circuit 410. The first timing controller 411 controls the driving timing of the first gate driver 412, the first emission control driver 413, and the first data driver 414. The first timing controller 411 aligns the digital video data signal DATA (see FIG. 1 ) input from the outside according to the resolution and driving frequency of the display panel 110. Figure 6 ) (hereinafter, referred to as “data signal”). The first timing controller 411 supplies the aligned data signal DATA to the first data driver 414. The first gate driver 412 drives the gate line GL of the display panel 110 under the control of the first timing controller 411 (see Figure 6 The first data driver 414 drives the data lines DL of the display panel 110 under the control of the first timing controller 411 (see Figure 6 The first emission control driver 413 drives the emission control line EML of the display panel 110 under the control of the first timing controller 411 (see Figure 6 ). The gate line GL, the data line DL, and the emission control line EML of the display panel 110 are connected to the pixel driving circuit PC through the first contact hole 451 and the fan-out line FL. Therefore, the first display driving circuit 211 can control the pixel driving circuit PC.

[0077] The second display driving circuit 212 includes a second timing controller 421, a second gate driver 422, a second emission control driver 423, and a second data driver 424 as a second circuit 420. The second circuit 420 of the second display driving circuit 212 is substantially the same as the first circuit 410 of the first display driving circuit 211. Therefore, the description of the second circuit 420 will be replaced with the description of the first circuit 410. For example, the second timing controller 421 aligns the digital video data signal DATA input from the outside according to the resolution and driving frequency of the display panel 110, and supplies the aligned data signal DATA to the second data driver 424. The gate line GL, the data line DL, and the emission control line EML of the display panel 110 are connected to the pixel driving circuit PC through the second contact hole 452 and the fan-out line FL. Therefore, the second display driving circuit 212 can control the pixel driving circuit PC.

[0078] The third display driving circuit 213 includes a third timing controller 431, a third gate driver 432, a third emission control driver 433, and a third data driver 434 as a third circuit 430. The third circuit 430 of the third display driving circuit 213 is substantially the same as the first circuit 410 of the first display driving circuit 211. Therefore, the description of the third circuit 430 will be replaced with the description of the first circuit 410. The gate line GL, the data line DL, and the emission control line EML of the display panel 110 are connected to the pixel driving circuit PC through the third contact hole 453 and the fan-out line FL. Therefore, the third display driving circuit 213 can control the pixel driving circuit PC.

[0079] The fourth display driving circuit 214 includes a fourth timing controller 441, a fourth gate driver 442, a fourth emission control driver 443, and a fourth data driver 444 as a fourth circuit 440. The fourth circuit 440 of the fourth display driving circuit 214 is substantially the same as the first circuit 410 of the first display driving circuit 211. Therefore, the description of the fourth circuit 440 will be replaced with the description of the first circuit 410. The gate line GL, the data line DL, and the emission control line EML of the display panel 110 are connected to the pixel driving circuit PC through the fourth contact hole 454 and the fan-out line FL. Therefore, the fourth display driving circuit 214 can control the pixel driving circuit PC.

[0080] According to an embodiment, the functions of the first to fourth display driving circuits 211, 212, 213, and 214 may be substantially the same. Therefore, the operation timings of the first to fourth display driving circuits 211, 212, 213, and 214 may be substantially synchronized. Therefore, according to an embodiment of the present disclosure, even if some of the first to fourth display driving circuits 211, 212, 213, and 214 are determined to be defective, the display panel 110 may be driven using the remaining display driving circuits determined to be non-defective.

[0081] Figure 5A is a diagram illustrating a semiconductor wafer 500 for manufacturing a display panel according to a comparative example. Figure 5B is a diagram illustrating a semiconductor wafer 600 for manufacturing a display panel 110 according to an embodiment.

[0082] Reference Figure 5A, the semiconductor wafer 500 according to the comparative example may be a semiconductor wafer 500 for OLEDoS. According to the comparative example, the net die included in one semiconductor wafer 500 may include about 76 dies. Considering that the net die of the semiconductor wafer 500 used to manufacture a general driver IC includes about 1500 to about 2000 dies, this significantly reduces the number of dies. According to the comparative example, since each die 501 included in one semiconductor wafer 500 is designed to include one display driver circuit 510, the yield of the die determined to be non-defective is reduced.

[0083] On the other hand, refer to Figure 5B In the semiconductor wafer 600 according to the embodiment, the net dies included in one semiconductor wafer 600 include approximately 76 dies, but since a portion of the semiconductor wafer corresponding to one die 601 (e.g., one display panel 110) is designed to include a plurality of display driving circuits 210, the yield of the dies 601 determined to be non-defective is increased compared to the comparative example.

[0084] Figure 6 1 is a block diagram showing the connection between the display panel 110 and any one of a plurality of display driving circuits according to an embodiment. Figure 6 The timing controller 610 shown in FIG. 4 may be the first timing controller 411 of the first display driving circuit 211. For example, Figure 6 The gate driver 620 shown in FIG. 4 may be the first gate driver 412 of the first display driving circuit 211. For example, Figure 6 The emission control driver 630 shown in FIG. 4 may be the first emission control driver 413 of the first display driving circuit 211. For example, Figure 6 The data driver 640 shown in FIG. 4 may be the first data driver 414 of the first display driving circuit 211 .

[0085] Reference Figure 6 , the display panel 110 may include a display area DA and a non-display area NDA.

[0086] The display area DA may include a plurality of pixels PX, a plurality of driving voltage lines VDL connected to the respective pixels PX, a plurality of common voltage lines ( Figure 7 VSL in the figure), multiple gate lines GL, multiple emission control lines EML and multiple data lines DL.

[0087] Each of the plurality of pixels PX may be connected to a gate line GL, a data line DL, an emission control line EML, a driving voltage line VDL, and a common voltage line VSL. Each of the plurality of pixels PX includes a light emitting element LEL, and may include a plurality of thin film transistors and one or more capacitors as a pixel driving circuit PC for driving the light emitting element LEL. Figure 7 and Figure 8 The pixel driving circuit PC included in each pixel PX is described in detail.

[0088] The display panel 110 may include a plurality of display driving circuits 210. Each display driving circuit 210 may include a timing controller 610, a gate driver 620, an emission control driver 630, and a data driver 640.

[0089] The timing controller 610 may receive a data signal DATA and a timing signal from the circuit board 120. Based on the timing signal, the timing controller 610 may control the operation timing of the data driver 640 by generating a data control signal DCS, control the operation timing of the gate driver 620 by generating a gate control signal GCS, and control the operation timing of the emission control driver 630 by generating an emission control signal ECS.

[0090] The data driver 640 may convert the data signal DATA into an analog data voltage and supply the analog data voltage to the data line DL. The gate signal of the gate driver 620 may select the pixel PX supplied with the data voltage, and the selected pixel PX may receive the data voltage through the data line DL.

[0091] The power supply unit 130 may be provided on the circuit board 120, and may supply a power voltage to the display driving circuit 210 and the display panel 110. The power supply unit 130 may generate a driving voltage and supply the driving voltage to the driving voltage line VDL. In addition, the power supply unit 130 may generate a common voltage and supply the common voltage to a common electrode (e.g., a common electrode) shared by the light emitting elements LEL of the plurality of pixels PX. Fig. 9 The cathode electrode CE in the embodiment of the present invention.

[0092] The gate driver 620 can convert the gate signal ( Figure 7 GR, GI and GW) are supplied to the gate line GL.

[0093] The emission control driver 630 can transmit the emission signal ( Figure 7 EM in) is supplied to the emission control line EML.

[0094] Figure 7 is a circuit diagram of a pixel PX of the display device 10 according to the embodiment.

[0095] Reference Figure 7 , the pixel PX may include a light emitting element LEL (e.g., an organic light emitting diode) as a display element and a pixel driving circuit PC connected to the light emitting element LEL. The pixel driving circuit PC may include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, and a fifth thin film transistor T5, and a first capacitor C1 and a second capacitor C2. The first thin film transistor T1 may be a driving transistor whose source-drain current is determined according to a gate-source voltage, and each of the second to fifth thin film transistors T2 to T5 may be a switching transistor that is turned on / off according to a gate-source voltage (substantially a gate voltage). The first to fifth thin film transistors T1, T2, T3, T4, and T5 may be oxide-based thin film transistors. Depending on the type of transistor (p-type or n-type) and / or operating conditions, the first electrode of each of the first to fifth thin film transistors T1, T2, T3, T4, and T5 may be a source electrode SE (see Fig. 9 ) or drain electrode DE (see Fig. 9 ), and the second electrode of each of the first to fifth thin film transistors T1, T2, T3, T4 and T5 may be an electrode different from the first electrode. For example, when the first electrode is the source electrode SE, the second electrode may be the drain electrode DE.

[0096] The pixel PX may be connected to a first gate line GWL through which a first gate signal GW is transmitted, a second gate line GIL through which a second gate signal GI is transmitted, a third gate line GRL through which a third gate signal GR is transmitted, an emission control line EML through which an emission signal EM is transmitted, and a data line DL through which a data signal DATA is transmitted. The driving voltage line VDL may be used to transmit a first driving voltage ELVDD to the first thin film transistor T1. The initialization voltage line VIL may be used to transmit an initialization voltage VINT to a light emitting element LEL (e.g., an organic light emitting diode). The reference voltage line VRL may transmit a reference voltage VREF to a gate electrode of the first thin film transistor T1. In addition, according to the pixel structure, the initialization voltage line VIL may include a plurality of initialization voltage lines VIL (e.g., a first initialization voltage line VIL and a second initialization voltage line VIL) that transmit initialization voltages VINT of different sizes.

[0097] A plurality of first to fifth thin film transistors T1, T2, T3, T4 and T5 may include oxide semiconductor materials. Since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop will not be large even if the driving time is long. In other words, since oxide semiconductors do not significantly change the color of the image due to the voltage drop even when driven at a low frequency, oxide semiconductors can be driven at a low frequency. Therefore, since a plurality of first to fifth thin film transistors T1, T2, T3, T4 and T5 include oxide semiconductor materials, the generation of leakage current can be prevented and power consumption can be reduced. In addition, since oxide-based semiconductor transistors do not require a crystallization process performed by excimer laser annealing (ELA), which is a process for forming a low temperature polycrystalline silicon (LTPS) semiconductor transistor, its manufacturing cost can be reduced.

[0098] In addition, since the oxide semiconductor is sensitive to light, fluctuations in the amount of current may occur due to external light. Therefore, in order to enhance the absorption or reflection of external light, a metal layer may be provided on the lower side of the oxide semiconductor. At least some of the first to fifth thin film transistors T1, T2, T3, T4, and T5 may be double-gate transistors having a lower gate electrode (e.g., a counter gate electrode). The illustrated example shows that the first thin film transistor T1 is a double-gate transistor, but the present disclosure is not limited thereto.

[0099] The first thin film transistor T1 includes a gate electrode connected to a first node N1 (or a gate node), a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to a second electrode (e.g., a source electrode) of the fifth thin film transistor T5. The third node N3 may be an anode electrode (e.g., a gate electrode) connected to the light emitting element LEL. Fig. 9 The first thin film transistor T1 may be used as a driving transistor, and may receive a data signal DATA and control the size (eg, current amount) of a driving current Id flowing to the light emitting element LEL according to a switching operation of the second thin film transistor T2.

[0100] The second thin film transistor T2 (e.g., a data writing transistor) includes a gate electrode connected to the first gate line GWL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1 (or the gate electrode of the first thin film transistor T1). The second thin film transistor T2 can be turned on according to the first gate signal GW transmitted to the first gate line GWL to electrically connect the data line DL and the first node N1, and can provide the data signal DATA transmitted through the data line DL to the first node N1.

[0101] The third thin film transistor T3 (e.g., the first initialization transistor) includes a gate electrode connected to the third gate line GRL, a first electrode connected to the reference voltage line VRL, and a second electrode connected to the first node N1 (or the gate electrode of the first thin film transistor T1). The third thin film transistor T3 can be turned on according to the third gate signal GR transmitted through the third gate line GRL to provide the reference voltage VREF transmitted through the reference voltage line VRL to the first node N1.

[0102] The fourth thin film transistor T4 (e.g., the second initialization transistor) includes a gate electrode connected to the second gate line GIL, a first electrode connected to the third node N3 (or the second electrode of the first thin film transistor T1), and a second electrode connected to the initialization voltage line VIL. The fourth thin film transistor T4 can be turned on according to the second gate signal GI transmitted through the second gate line GIL to provide the initialization voltage VINT transmitted through the initialization voltage line VIL to the third node N3.

[0103] The fifth thin film transistor T5 (e.g., an emission control transistor) includes a gate electrode connected to an emission control line EML, a first electrode connected to a driving voltage line VDL, and a second electrode connected to a second node N2 (or a first electrode of the first thin film transistor T1). The fifth thin film transistor T5 can be turned on or off according to an emission signal EM transmitted through the emission control line EML.

[0104] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 as a storage capacitor may store a voltage corresponding to a threshold voltage of the first thin film transistor T1 and the data signal DATA.

[0105] The second capacitor C2 may be disposed between the third node N3 and the driving voltage line VDL.

[0106] The light emitting element LEL may include a pixel electrode (eg, Fig. 9 The anode electrode ANE in the pixel electrode and the common electrode facing the pixel electrode (eg, Fig. 9 The cathode electrode CE in the light emitting element LEL is connected to the cathode electrode CE in the light emitting element LEL, and the common electrode may be applied with the second driving voltage ELVSS. The common electrode of the light emitting element LEL may be connected to the common voltage line VSL transmitting the second driving voltage ELVSS. The common electrode of the light emitting element LEL may be commonly connected to a plurality of pixels PX.

[0107] Figure 8 It is shown Figure 7 3 is a diagram of the driving timing of the pixel driving circuit PC shown in FIG.

[0108] exist Figure 8EM[N][N+1] is the driving timing of the emission signal EM supplied to the pixel driving circuit PC of the pixels PX arranged in the Nth and N+1th rows of the plurality of pixels. Figure 8 GR[N][N+1] is the driving timing of the third gate signal GR supplied to the pixel driving circuit PC of the pixels PX arranged in the Nth row and the N+1th row. Figure 8 In , GI[N][N+1] is the driving timing of the second gate signal GI supplied to the pixel driving circuit PC of the pixels PX arranged in the Nth row and the N+1th row. Figure 8 , GW[N] is the driving timing of the first gate signal GW supplied to the pixel driving circuit PC of the pixel PX arranged in the Nth row. Figure 8 GW[N+1] is a driving timing of a first gate signal GW supplied to the pixel driving circuit PC of the pixel PX disposed in the N+1th row.

[0109] Reference Figure 8 , the pixel driving circuit PC may operate in a first period 801, a second period 802, a third period 803, and a fourth period 804 separated from each other during one frame. The first period 801, the second period 802, the third period 803, and the fourth period 804 may occur in sequence. Hereinafter, the operation of the pixel driving circuit PC of the pixel PX disposed in the Nth row will be mainly described.

[0110] The pixel driving circuit PC receives the third gate signal GR in a gate-on voltage state (e.g., a high state) in the first period 801. In the first period 801, the first gate signal GW, the second gate signal GI, and the emission signal EM are in a gate-off voltage state (e.g., a low state). The third thin film transistor T3 is turned on in response to the third gate signal GR, and transmits the reference voltage VREF to the first node N1. Therefore, the first node N1 is initialized to the reference voltage VREF.

[0111] The pixel driving circuit PC receives the second gate signal GI and the third gate signal GR in the gate-on voltage state (e.g., high state) in the second period 802. In the second period 802, the first gate signal GW and the emission signal EM are in the gate-off voltage state (e.g., low state). The fourth thin film transistor T4 is turned on in response to the second gate signal GI, and transmits the initialization voltage VINT to the third node N3. Therefore, the third node N3 is initialized to the initialization voltage VINT. In the second period 802, the third thin film transistor T3 remains in the on state.

[0112] The pixel driving circuit PC receives the emission signal EM and the third gate signal GR in the gate-on voltage state (e.g., high state) in the third period 803. In the third period 803, the first gate signal GW and the second gate signal GI are in the gate-off voltage state (e.g., low state). The fifth thin film transistor T5 may be turned on in response to the emission signal EM, and may transmit the first driving voltage ELVDD to the second node N2. The third thin film transistor T3 remains in the on state in the third period 803, and therefore, the first node N1 maintains the reference voltage VREF. The first thin film transistor T1 forms a current path connecting the second node N2 and the third node N3. When the gate voltage of the first thin film transistor T1 is less than or equal to the difference (VREF-Vth) between the reference voltage VREF and the threshold voltage Vth of the first thin film transistor T1, the first thin film transistor T1 may be turned off. The first capacitor C1 may store a voltage including the threshold voltage Vth of the first thin film transistor T1. The third period 803 may be a compensation period for compensating the threshold voltage Vth of the first thin film transistor T1.

[0113] The pixel driving circuit PC receives the first gate signal GW in the gate-on voltage state (e.g., high state) in the fourth period 804. In the fourth period 804, the second gate signal GI, the third gate signal GR, and the emission signal EM are in the gate-off voltage state (e.g., low state). The second thin film transistor T2 may be turned on in response to the first gate signal GW, and may transmit the data signal DATA to the first node N1. Therefore, the first node N1 has a data voltage in which the threshold voltage Vth of the first thin film transistor T1 is compensated.

[0114] After the fourth period 804 , the pixel driving circuit PC receives the emission signal EM in a gate-on voltage state (eg, a high state), and the first thin film transistor T1 supplies a driving current Id corresponding to the data signal DATA to the light emitting element LEL.

[0115] Fig. 9 is a cross-sectional view of a portion of a display area DA of a display panel 110 according to an embodiment.

[0116] Reference Fig. 9, the display panel 110 includes a semiconductor wafer substrate 200, and a CMOS layer 910 including a plurality of display driving circuits 210 is disposed on a front surface 201 of the semiconductor wafer substrate 200. A transistor layer 940 including transistors constituting a plurality of pixel driving circuits PC, a light emitting element layer 950, and a packaging layer 960 are disposed on a rear surface 202 of the semiconductor wafer substrate 200. In other words, the CMOS layer 910 is stacked along a first direction Z1 from the semiconductor wafer substrate 200, and the transistor layer 940, the light emitting element layer 950, and the packaging layer 960 are sequentially stacked along a second direction Z2 from the semiconductor wafer substrate 200.

[0117] The semiconductor wafer substrate 200 may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The semiconductor wafer substrate 200 may be a substrate doped with first type impurities.

[0118] The CMOS layer 910 including the MOSFET and the line electrode connected to the MOSFET is arranged in the first direction Z1, and the first direction Z1 is the direction from the semiconductor wafer substrate 200 toward the front surface 201 thereof. In other words, the CMOS layer 910 can be arranged on the top of the semiconductor wafer substrate 200. The CMOS layer 910 includes an n-type MOSFET and / or a p-type MOSFET. The first type impurity can be a p-type impurity, and the second type impurity can be an n-type impurity. Alternatively, the first type impurity can be an n-type impurity, and the second type impurity can be a p-type impurity.

[0119] Here, an n-type MOSFET MOS included in the CMOS layer 910 will be described as an example. The n-type MOSFET MOS may include a well region W1 doped with n-type impurities in a substrate doped with p-type impurities. The well region W1 may include a first low-concentration impurity region LDD1 and a second low-concentration impurity region LDD2 having an impurity concentration relatively lower than that of other portions of the well region W1. The first low-concentration impurity region LDD1 may form a source region S1, and the second low-concentration impurity region LDD2 may form a drain region D1. A channel CH disposed to overlap the gate G1 is formed between the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. An oxide film GI1 as an insulating layer may be disposed between the gate G1 and the well region W1.

[0120] The MOSFET MOS disposed on the front surface 201 of the semiconductor wafer substrate 200 constitutes a plurality of display driving circuits 210. The display driving circuits 210 are disposed to overlap with a plurality of pixels PX in the display area DA of the display panel 110. For example, a circuit formed by a combination of the MOSFET MOS disposed on the front surface 201 of the semiconductor wafer substrate 200 may constitute a reference Figure 4The first display driving circuit 211 , the second display driving circuit 212 , the third display driving circuit 213 and the fourth display driving circuit 214 are described.

[0121] One or more insulating layers 911 and 912 may be provided on the MOSFET MOS. For example, one or more insulating layers 911 and 912 are provided in a first direction Z1 from the MOSFET MOS. A line electrode CE100 penetrating a portion of the insulating layer 911 and connecting the MOSFET MOS to each other is provided in the first direction Z1 from the MOSFET MOS. The line electrode CE100 connecting the MOSFET MOS to each other may be electrically connected to the MOSFET MOS through contact holes CT110 and CT120 penetrating the insulating layer 911. A portion of the line electrode CE100 may be provided in the insulating layer 912. For example, the line electrode CE100 may include a first line electrode CE110 connected to a source region S1 of the MOSFET MOS and a second line electrode CE120 connected to a drain region D1 of the MOSFET MOS.

[0122] Some of the line electrodes CE100 disposed on the MOSFET MOS may be formed through contact holes CT210 and CT220 (eg, Figure 4 450 in FIG. 5) is electrically connected to the transistor layer 940 disposed on the rear surface 202 of the semiconductor wafer substrate 200. In other words, some of the line electrodes CE100 may be connected to the thin film transistors TFT1 (e.g., T1, T2, T3, T4, and T5 in FIG. 5) constituting the plurality of pixel driving circuits PC. Fig. 9 One contact hole CT210 or CT220 penetrating the semiconductor wafer substrate 200 is shown, but the number of the contact holes CT210 and CT220 may be plural, and the contact holes CT210 and CT220 may include the contact holes CT210 and CT220 as shown in FIG. Figure 4 The first to fourth contact holes 451, 452, 453 and 454 are described. For example, the contact holes CT210 or CT220 may include a plurality of first contact holes 451 connecting the first display driving circuit 211 and the plurality of pixel driving circuits PC, a plurality of second contact holes 452 connecting the second display driving circuit 212 and the plurality of pixel driving circuits PC, a plurality of third contact holes 453 connecting the third display driving circuit 213 and the plurality of pixel driving circuits PC, and a plurality of fourth contact holes 454 connecting the fourth display driving circuit 214 and the plurality of pixel driving circuits PC.

[0123] The first cover window 930 may be disposed in the first direction Z1 from the CMOS layer 910. For example, the first cover window 930 may include a glass material, but the present disclosure is not limited thereto. At least one protective layer may also be disposed between the first cover window 930 and the CMOS layer 910. The protective layer may include, for example, a protective film.

[0124] The transistor layer 940 including the thin film transistor TFT1 and the connection electrodes CE210 and CE220 connected to the thin film transistor TFT1 is disposed in the second direction Z2, which is a direction from the semiconductor wafer substrate 200 toward its rear surface 202. In other words, the transistor layer 940 may be disposed on the bottom of the semiconductor wafer substrate 200.

[0125] The thin film transistors TFT1 disposed on the rear surface 202 of the semiconductor wafer substrate 200 constitute a plurality of pixel driving circuits PC, and the pixel driving circuits PC are configured to drive the light emitting elements LEL. For example, the thin film transistors TFT1 disposed on the rear surface 202 of the semiconductor wafer substrate 200 may constitute a plurality of pixel driving circuits PC. Figure 7 The first to fifth thin film transistors T1, T2, T3, T4 and T5 are described.

[0126] The thin film transistor TFT1 (eg, T1, T2, T3, T4, and T5 in 7) includes an active layer ACT, a gate electrode GE, a drain electrode DE, and a source electrode SE disposed on the rear surface 202 of the semiconductor wafer substrate 200. The active layer ACT includes an oxide semiconductor material.

[0127] The active layer ACT of the thin film transistor TFT1 includes a source region, a drain region, and a channel region between the source region and the drain region. The source region and the drain region may be regions that have conductivity by doping the oxide semiconductor with ions or impurities. The buffer layer BF may be disposed between the active layer ACT of the thin film transistor TFT1 and the rear surface 202 of the semiconductor wafer substrate 200. For example, the buffer layer BF may contact the active layer ACT of the thin film transistor TFT1 and the rear surface 202 of the semiconductor wafer substrate 200.

[0128] The gate electrode GE of the thin film transistor TFT1 is disposed to overlap with the channel region of the active layer ACT. A gate insulating film 941 may be disposed between the gate electrode GE and the channel region of the active layer ACT.

[0129] The interlayer insulating film 942 is disposed in the second direction Z2 from the gate electrode GE of the thin film transistor TFT1. A source electrode SE connected to the source region through a source contact hole CT310 penetrating a portion of the interlayer insulating film 942 and a drain electrode DE connected to the drain region through a drain contact hole CT320 penetrating a portion of the interlayer insulating film 942 are disposed from the interlayer insulating film 942 in the second direction Z2.

[0130] One or more insulating layers 943 and 944 are provided from the thin film transistor TFT1 in the second direction Z2. The insulating layers 943 and 944 may include an inorganic insulating film and / or an organic insulating film. The connecting electrodes CE210 and CE220 that penetrate the portions of the insulating layers 943 and 944 may be provided from the thin film transistor TFT1 in the second direction Z2. The connecting electrodes CE210 and CE220 may connect the thin film transistors TFT1 to each other, or electrically connect the thin film transistor TFT1 and the light emitting element LEL through the contact holes CT410 and CT420.

[0131] One or more capacitor electrodes CPE1 and CPE2 are respectively disposed at the same layer as connection electrodes CE210 and CE220. For example, capacitor electrode CPE1 may be disposed at the same layer as connection electrode CE210, and capacitor electrode CPE2 may be disposed at the same layer as connection electrode CE220. Capacitor electrodes CPE1 and CPE2 may be disposed to face each other.

[0132] In the transistor layer 940, some of the thin film transistors TFT1 may be connected to the CMOS layer 910 disposed on the front surface 201 of the semiconductor wafer substrate 200. In other words, some of the thin film transistors TFT1 may be connected to the plurality of display driving circuits 210 through the contact holes CT210 and CT220 penetrating the semiconductor wafer substrate 200. Therefore, the thin film transistors TFT1 disposed in the transistor layer 940 may receive gate signals ( Figure 7 GR, GI and GWL), transmission signal EM and data signal DATA.

[0133] The light emitting element layer 950 including the light emitting element LEL is disposed in the second direction Z2 from the transistor layer 940. The light emitting element LEL includes an anode electrode ANE connected to the thin film transistor TFT1 through a contact hole CT510 penetrating a portion of the insulating layer 944 of the transistor layer 940, a light emitting layer EL covering the anode electrode ANE, and a cathode electrode CE covering the light emitting layer EL.

[0134] According to an embodiment, the light emitting layer EL may include an intermediate layer (or a common layer). The intermediate layer may have a series structure including a plurality of intermediate layers for emitting different lights. For example, the intermediate layer may include a first intermediate layer for emitting light of a first color, a second intermediate layer for emitting light of a second color, and a third intermediate layer for emitting light of a third color. The first intermediate layer, the second intermediate layer, and the third intermediate layer may be stacked sequentially.

[0135] The first intermediate layer may have a structure in which a first hole transport layer, a first organic light-emitting layer for emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer may have a structure in which a second hole transport layer, a second organic light-emitting layer for emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer may have a structure in which a third hole transport layer, a third organic light-emitting layer for emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0136] A first charge generation layer for supplying charges to the second intermediate layer and electrons to the first intermediate layer may be provided between the first intermediate layer and the second intermediate layer. A second charge generation layer for supplying charges to the third intermediate layer and electrons to the second intermediate layer may be provided between the second intermediate layer and the third intermediate layer.

[0137] The first intermediate layer may be disposed on the anode electrode ANE and the pixel defining film PDL, and may be disposed on the bottom surface of each groove formed between adjacent pixels. Due to the groove, the first to third intermediate layers may be disconnected between adjacent pixels. In other words, each of the plurality of grooves may be a structure for disconnecting the first to third intermediate layers of the light emitting layer EL between adjacent pixels.

[0138] The light emitting element layer 950 further includes a pixel defining film PDL that separates the light emitting regions of the light emitting element LEL and a spacer (or spacer) SP disposed on the pixel defining film PDL. The pixel defining film PDL and the spacer SP may be formed as an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. As an example, Fig. 9 It is shown that the pixel defining layer PDL divides the light emitting region of the first pixel PX1 and the light emitting region of the second pixel PX2 .

[0139] The encapsulation layer 960 covering the light emitting element LEL is disposed in the second direction Z2 from the light emitting element layer 950. The encapsulation layer 960 includes at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer 950. In addition, the encapsulation layer 960 includes at least one organic film to protect the light emitting element layer 950 from foreign matter such as dust. For example, the encapsulation layer 960 includes a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0140] The first encapsulation inorganic film TFE1 may be disposed on the cathode electrode CE as a common electrode, the encapsulation organic film TFE2 may be disposed on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be disposed on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed as a multilayer film in which one or more inorganic films of silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked. The encapsulation organic film TFE2 may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0141] The color filter layer CF including the color filter is arranged in the second direction Z2 from the encapsulation layer 960. The color filter may include a red color filter that transmits red light, a green color filter that transmits green light, and a blue color filter that transmits blue light, but the present disclosure is not limited thereto. When the light emitting element LEL of the light emitting element layer 950 emits white light, the color filter layer CF is provided. If the light emitting element LEL of the light emitting element layer 950 directly emits red light, green light, and blue light, the color filter layer CF may be omitted.

[0142] The light control layer MLA including the refractive film RM is disposed in the second direction Z2 from the color filter layer CF. The refractive film RM may refract incident light so that light emitted from the light emitting element layer 950 is guided toward the normal direction (e.g., the second direction Z2) of the display panel 110. Such a refractive film RM may also be referred to as a light control pattern.

[0143] The second cover window 970 may be disposed in the second direction Z2 from the light control layer MLA. The second cover window 970 may include a glass material, but the present disclosure is not limited thereto. At least one protective layer may also be disposed between the second cover window 970 and the light control layer MLA. The protective layer may include, for example, a protective film.

[0144] Fig.10 is a flowchart illustrating at least a portion of a process of manufacturing the display device 10 according to the embodiment. Fig.11 2 is a diagram showing a step of preparing a semiconductor wafer substrate 200 . Fig.12 9 is a diagram showing a step of forming a CMOS layer 910 . Fig.13 is a diagram illustrating a step of attaching the first cover window 930 . Fig.14 is a diagram showing the steps of a chemical mechanical polishing pad (CMP) process. Fig.15 9 is a diagram showing a step of forming the transistor layer 940 . Fig.16 9 is a diagram showing a step of forming the light emitting element layer 950 and the encapsulation layer 960 .

[0145] Can be referenced Figures 10 to 16At least some of the process steps mentioned in other figures in the present disclosure can be added before or after each manufacturing process described. Figures 10 to 16 Each manufacturing process described is preceded or followed by a process of manufacturing a known semiconductor and / or a process of manufacturing a known display panel 110 .

[0146] In the following, reference will be made to Figures 10 to 16 At least a part of a process of manufacturing the display device 10 according to the embodiment is described.

[0147] Reference Fig.10 and Fig.11 In step 1010, a semiconductor wafer substrate 200 may be prepared. The semiconductor wafer substrate 200 may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The semiconductor wafer substrate 200 may be a substrate doped with first type impurities.

[0148] Reference Fig.10 and Fig.12 In step 1020, a CMOS layer 910 may be formed on the front surface 201 of the semiconductor wafer substrate 200. The CMOS layer 910 including the MOSFET MOS and the line electrode CE100 connected to the MOSFET MOS is arranged in a first direction Z1, which is a direction from the semiconductor wafer substrate 200 toward the front surface 201 thereof. The CMOS layer 910 includes an n-type MOSFET and / or a p-type MOSFET. The first type impurity may be a p-type impurity, and the second type impurity may be an n-type impurity. Alternatively, the first type impurity may be an n-type impurity, and the second type impurity may be a p-type impurity.

[0149] The MOSFET MOS constitutes a plurality of display driving circuits 210, and the display driving circuits 210 are arranged to overlap with a plurality of pixels PX in the display area DA of the display panel 110. In other words, a circuit formed by a combination of the MOSFET MOS disposed on the front surface 201 of the semiconductor wafer substrate 200 may constitute a reference Figure 4 The first display driving circuit 211 , the second display driving circuit 212 , the third display driving circuit 213 and the fourth display driving circuit 214 are described.

[0150] Reference Fig.10 and Fig.13 In step 1030, a first cover window 930 may be attached to the CMOS layer 910. For example, the first cover window 930 may include a glass material, but the present disclosure is not limited thereto. At least one protective layer may be provided between the first cover window 930 and the CMOS layer 910. The protective layer may include, for example, a protective film.

[0151] Reference Fig.10 and Fig.14 In step 1040, a chemical mechanical polishing (CMP) process may be performed on the rear surface 202 of the semiconductor wafer substrate 200. When the CMP process is performed on the semiconductor wafer substrate 200, the contact holes ( Figure 4 450 and Fig. 9 The contact holes 450 are configured to connect the CMOS layer 910, in other words, to connect the plurality of display driving circuits 210 and the thin film transistors TFT1 to be formed on the rear surface 202 of the semiconductor wafer substrate 200.

[0152] Reference Fig.10 and Fig.15 In step 1050, a transistor layer 940 may be formed on the rear surface 202 of the semiconductor wafer substrate 200. The thin film transistor TFT1 includes an active layer ACT, a gate electrode GE, a drain electrode DE, and a source electrode SE disposed on the rear surface 202 of the semiconductor wafer substrate 200. The active layer ACT includes an oxide semiconductor material.

[0153] An interlayer insulating film 942 is disposed in the second direction Z2 from the gate electrode GE of the thin film transistor TFT1. A source electrode SE penetrating a portion of the interlayer insulating film 942 and connected to the source region and a drain electrode DE penetrating a portion of the interlayer insulating film 942 and connected to the drain region are disposed in the second direction Z2 from the interlayer insulating film 942. The process of forming the source electrode SE and the drain electrode DE may include a line process of connecting the source electrodes SE (or drain electrodes DE) of some thin film transistors TFT1 disposed on the front surface 201 of the semiconductor wafer substrate 200 and the MOSFET MOS of the CMOS layer 910 to each other through the contact holes CT210 and CT220.

[0154] One or more insulating layers 943 and 944 are provided in the second direction Z2 from the thin film transistor TFT1. The insulating layers 943 and 944 may include an inorganic insulating film and / or an organic insulating film. Connecting electrodes CE210 and CE220 that penetrate portions of the insulating layers 943 and 944 may be provided in the second direction Z2 from the thin film transistor TFT1. The connecting electrodes CE210 and CE220 may connect the thin film transistors TFT1 to each other or electrically connect the thin film transistor TFT1 to the light emitting element LEL. The capacitor electrodes CPE1 and CPE2 may be provided in the same layer as the connecting electrodes CE210 and CE220, respectively, and the capacitor electrodes CPE1 and CPE2 may be manufactured by the same process as the connecting electrodes CE210 and CE220, respectively.

[0155] Reference Fig.10 and Fig.16In step 1060, a light emitting element layer 950 and an encapsulation layer 960 may be formed on the transistor layer 940. A color filter layer CF, a light control layer MLA including a refractive film RM, and a second cover window 970 may also be disposed in a second direction Z2 from the encapsulation layer 960. The second cover window 970 may include a glass material, but the present disclosure is not limited thereto. At least one protective layer may also be disposed between the second cover window 970 and the light control layer MLA. The protective layer may include, for example, a protective film.

[0156] The display device 10 according to the embodiment may be a display device 10 included in a mobile electronic device. The display device 10 according to the embodiment may be included in a wearable device that is developed in the form of glasses or a helmet and is focused at a distance close to the user's eyes. For example, the wearable device may be a head-mounted display (HMD) device or AR glasses. Such a wearable device provides an augmented reality (hereinafter referred to as "AR") screen or a virtual reality (hereinafter referred to as "VR") screen to the user.

[0157] Fig.17 is a schematic diagram showing a virtual reality device including the display device 10 according to an embodiment.

[0158] Fig.17 FIG. 1 shows a virtual reality device 1700 to which a display device 1760 according to an embodiment is applied. Here, the display device 1760 may be, for example, a device including the above-mentioned Figures 1 to 16 For example, the display device 1760 may be the display device 10 according to the embodiment.

[0159] Reference Fig.17 The virtual reality device 1700 according to the embodiment may be an AR glasses in the form of glasses. The virtual reality device 1700 according to the embodiment may include a display device 1760, a left-eye lens 1711, a right-eye lens 1712, a support frame 1720, glasses frame legs 1731 and 1732, a reflective member 1740, and a receiving portion 1750.

[0160] exist Fig.17 , the virtual reality device 1700 in the form of AR glasses is shown, but the virtual reality device 1700 according to the embodiment can also be applied to HMD. In other words, the virtual reality device 1700 according to the embodiment is not limited to Fig.17 The virtual reality device 1700 shown in FIG. 1 may be applied to various other mobile electronic devices in various forms.

[0161] The accommodation portion 1750 may include a display device 1760 and a reflective member 1740. An image displayed on the display device 1760 may be reflected by the reflective member 1740 and provided to the right eye of the user through the right eye lens 1712. Therefore, the user may view the virtual reality image displayed on the display device 1760 through the right eye.

[0162] Fig.17 17 shows that the housing 1750 is disposed at the right distal end of the support frame 1720, but the embodiments of the present disclosure are not limited thereto. For example, the housing 1750 may be disposed at the left distal end of the support frame 1720. In this case, the image displayed on the display device 1760 may be reflected by the reflective member 1740 and provided to the left eye of the user through the left eye lens 1711. Therefore, the user may view the virtual reality image displayed on the display device 1760 through the left eye. Optionally, two of the housings 1750 may be disposed at the left distal end and the right distal end of the support frame 1720. In this case, the user may view the virtual reality image displayed on the display device 1760 through both the left eye and the right eye.

[0163] Fig.18 and Fig.19 is a diagram showing an HMD device to which the display device 10 according to the embodiment is applied.

[0164] Reference Fig.18 and Fig.19 The display device 10 according to the embodiment may be applied to an HMD device. The HMD device includes a first display device 1910 and a second display device 1920, each of which may be the display device 10 according to the embodiment. The first display device 1910 provides an image to the right eye of the user, and the second display device 1920 provides an image to the left eye of the user.

[0165] The first lens array 1930 may be disposed between the first display device 1910 and the receiving portion cover 1810. The first lens array 1930 may include a plurality of lenses 1931. The plurality of lenses 1931 may be formed as convex lenses convex in the direction of the receiving portion cover 1810.

[0166] The second lens array 1940 may be disposed between the second display device 1920 and the receiving portion cover 1810. The second lens array 1940 may include a plurality of lenses 1941. The plurality of lenses 1941 may be formed as convex lenses convex in the direction of the receiving portion cover 1810.

[0167] The receiving portion 1830 receives the first display device 1910, the second display device 1920, the first lens array 1930, and the second lens array 1940. In order to receive the first display device 1910, the second display device 1920, the first lens array 1930, and the second lens array 1940, one surface of the receiving portion 1830 may be opened.

[0168] The receiving portion cover 1810 is provided to cover the opened surface of the receiving portion 1830. The receiving portion cover 1810 may include a first opening 1821 at which a left eye of a user is provided and a second opening 1822 at which a right eye of the user is provided. Fig.18 and Fig.19 1821 and the second opening 1822 are shown to be formed in a quadrilateral shape, but the present disclosure is not limited thereto. The first opening 1821 and the second opening 1822 may be formed in a circular shape or an elliptical shape. Alternatively, the first opening 1821 and the second opening 1822 may be combined to form one opening.

[0169] The first opening 1821 may be aligned with the second display device 1920 and the second lens array 1940, and the second opening 1822 may be aligned with the first display device 1910 and the first lens array 1930. Therefore, the user may view the image of the first display device 1910 magnified as a virtual image by the first lens array 1930 through the second opening 1822, and may view the image of the second display device 1920 magnified as a virtual image by the second lens array 1940 through the first opening 1821.

[0170] The head mounting band 1840 is used to fix the receiving portion 1830 to the user's head so that the first opening 1821 and the second opening 1822 of the receiving portion cover 1810 are respectively disposed on the user's left eye and right eye. The head mounting band 1840 may be connected to the upper surface, the left side surface, and the right side surface of the receiving portion 1830.

[0171] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the disclosed embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments are not intended to be limiting.

Claims

1. A display device, comprising: Display panel, Wherein, the display panel comprises: Semiconductor wafer substrate; a complementary metal oxide semiconductor layer disposed on the first side of the semiconductor wafer substrate and including a plurality of display driving circuits driven independently of each other; a transistor layer disposed on the second side of the semiconductor wafer substrate and comprising a plurality of pixel driving circuits connected to the plurality of display driving circuits through contact holes in the semiconductor wafer substrate; a light emitting element layer disposed on the second side of the semiconductor wafer substrate and including light emitting elements driven by the plurality of pixel driving circuits; and A packaging layer is disposed on the second side of the semiconductor wafer substrate.

2. The display device according to claim 1, wherein: The display panel includes a display area and a non-display area, a plurality of pixels including the light emitting element are arranged in the display area, and The plurality of display driving circuits overlap the plurality of pixels in the display area.

3. The display device according to claim 2, wherein: The plurality of display driving circuits are disposed at intervals in the complementary metal oxide semiconductor layer.

4. The display device according to claim 2, wherein: The plurality of display driving circuits include identical circuits.

5. The display device according to claim 4, wherein: The plurality of display driving circuits include: a first display driving circuit, arranged to correspond to a first area of ​​the display area and comprising a first circuit for driving the plurality of pixel driving circuits; and a second display driving circuit, arranged to correspond to a second area of ​​the display area and comprising a second circuit for driving the plurality of pixel driving circuits, and The first circuit and the second circuit are identical.

6. The display device according to claim 5, wherein: The plurality of display driving circuits further include: a third display driving circuit, arranged to correspond to a third area of ​​the display area and comprising a third circuit for driving the plurality of pixel driving circuits; and a fourth display driving circuit, arranged to correspond to a fourth area of ​​the display area and comprising a fourth circuit for driving the plurality of pixel driving circuits, and The first circuit, the second circuit, the third circuit and the fourth circuit are identical.

7. The display device according to claim 6, wherein: The contact hole comprises: a plurality of first contact holes, connecting the first display driving circuit and the plurality of pixel driving circuits; a plurality of second contact holes, connecting the second display driving circuit and the plurality of pixel driving circuits; a plurality of third contact holes, connecting the third display driving circuit and the plurality of pixel driving circuits; and A plurality of fourth contact holes connect the fourth display driving circuit and the plurality of pixel driving circuits.

8. The display device according to claim 1, wherein: Each of the plurality of pixel driving circuits includes an oxide-based thin film transistor.

9. The display device according to claim 1, wherein: The display panel further includes: a color filter layer disposed on the second side of the semiconductor wafer substrate and comprising a color filter; and The light control layer is disposed on the second side of the semiconductor wafer substrate and includes a refractive film.

10. The display device according to claim 9, wherein: The display panel further includes: a first cover window disposed on the first side of the semiconductor wafer substrate; and The second cover window is disposed on the second side of the semiconductor wafer substrate.

11. A method for manufacturing a display device, the method comprising the following steps: preparing a semiconductor wafer substrate; forming a complementary metal oxide semiconductor layer on the front surface of the semiconductor wafer substrate, the complementary metal oxide semiconductor layer including a plurality of display driving circuits driven independently of each other; attaching a first cover window to the complementary metal oxide semiconductor layer; performing a chemical mechanical polishing pad process step, wherein the chemical mechanical polishing pad process step polishes the rear surface of the semiconductor wafer substrate to expose contact holes connected to the plurality of display driving circuits; forming a transistor layer including a plurality of pixel driving circuits on the rear surface of the semiconductor wafer substrate, the plurality of pixel driving circuits being connected to the plurality of display driving circuits through the contact holes; forming a light-emitting element layer on the transistor layer, the light-emitting element layer including light-emitting elements driven by the plurality of pixel driving circuits; as well as An encapsulation layer is formed on the light emitting element layer.

12. The method according to claim 11, wherein: A display panel included in the display device includes a display area and a non-display area, a plurality of pixels including the light emitting element are arranged in the display area, and The plurality of display driving circuits overlap the plurality of pixels in the display area.

13. The method according to claim 12, wherein: The plurality of display driving circuits are disposed at intervals in the complementary metal oxide semiconductor layer.

14. The method according to claim 12, wherein: The plurality of display driving circuits include identical circuits.

15. The method according to claim 14, wherein: The plurality of display driving circuits include: a first display driving circuit, arranged to correspond to a first area of ​​the display area and comprising a first circuit for driving the plurality of pixel driving circuits; and a second display driving circuit, arranged to correspond to a second area of ​​the display area and comprising a second circuit for driving the plurality of pixel driving circuits, and The first circuit and the second circuit are identical.

16. The method according to claim 15, wherein: The plurality of display driving circuits further include: a third display driving circuit, arranged to correspond to a third area of ​​the display area and comprising a third circuit for driving the plurality of pixel driving circuits; and a fourth display driving circuit, arranged to correspond to a fourth area of ​​the display area and comprising a fourth circuit for driving the plurality of pixel driving circuits, and The first circuit, the second circuit, the third circuit and the fourth circuit are identical.

17. The method according to claim 16, wherein: The contact hole comprises: a plurality of first contact holes, connecting the first display driving circuit and the plurality of pixel driving circuits; a plurality of second contact holes, connecting the second display driving circuit and the plurality of pixel driving circuits; a plurality of third contact holes, connecting the third display driving circuit and the plurality of pixel driving circuits; and A plurality of fourth contact holes connect the fourth display driving circuit and the plurality of pixel driving circuits.

18. The method according to claim 11, wherein: Each of the plurality of pixel driving circuits includes an oxide-based thin film transistor.

19. The method according to claim 11, further comprising: forming a color filter layer including a color filter on the encapsulation layer; as well as A light control layer including a refractive film is formed on the color filter layer.

20. The method of claim 19, further comprising attaching a second cover window to the light management layer.

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