Preparation method of thermoelectric transistor power generation device

Abstract

The invention relates to the technical field of thermoelectric conversion and semiconductor devices, and particularly discloses a preparation method of a bipolar junction thermoelectric transistor power generation device. According to the specific technical scheme, a liquid phase epitaxy technology is adopted, hydrogen, inert gas or a mixture of the hydrogen and the inert gas serves as protective gas, P-type and N-type thermoelectric thin films are hidden and epitaxially grown on a substrate through a mask plate technology, an electrode material is prepared through a physical deposition technology, and finally the bipolar junction thermoelectric transistor power generation device is prepared. According to the thermoelectric transistor generator prepared by the invention, the Seebeck voltage generated by the temperature difference under the room temperature condition can directly drive the thermoelectric transistor to work normally, and the output power and the thermoelectric conversion efficiency can be greatly improved by utilizing the signal amplification principle of the triode; the thermoelectric generator can be used for thermoelectric power generation at any temperature and any temperature difference, and can supply power to different types of electric appliances.

Description

Technical Field

[0001] The invention relates to the technical field of thermoelectric conversion and semiconductor devices, and in particular to a method for preparing a bipolar junction thermoelectric transistor power generation device. Background Art

[0002] In order to alleviate the current energy crisis, it is necessary to develop new, clean and environmentally friendly renewable energy and conversion technologies, including thermoelectric power generation. Since the carriers inside the thermoelectric power generation material will move in a directional manner under the drive of the temperature field, thus forming a potential difference at both ends, the thermoelectric generator can make full use of various heat sources including waste heat and directly convert them into electrical energy.

[0003] At present, in order to improve the output performance (output power and conversion efficiency) of thermoelectric generators, a variety of optimization methods have been proposed, such as band engineering, material nano-scaling, material low-dimensionality, and device structure optimization design.

[0004] For thermoelectric generators, there has always been a difficult problem to overcome, namely the strong coupling characteristics between their own performance parameters (electrical conductivity, Seebeck coefficient and thermal conductivity). The optimization methods mentioned above do not completely solve this problem. Most optimization methods can only hope that the increase in a certain performance parameter can be greater than the decrease in another performance parameter, thus failing to achieve the decoupling of thermoelectric performance parameters. Therefore, this problem causes the thermoelectric conversion efficiency to be far lower than the power generation efficiency of traditional heat engines, thus limiting its large-scale commercialization process. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a method for preparing a bipolar junction thermoelectric transistor power generation device.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0007] The invention discloses a method for preparing a bipolar junction thermoelectric transistor power generation device, which adopts liquid phase epitaxy technology, uses hydrogen, inert gas or a mixture of hydrogen and inert gas as protective gas, uses mask plate technology to conceal and epitaxially grow P-type and N-type thermoelectric films on a substrate, uses physical deposition technology to prepare electrode materials, prepares a bipolar junction thermoelectric transistor chip, packages the chip, and leads out an output terminal electrode to manufacture a thermoelectric transistor power generation device.

[0008] Preferably, the method comprises the following steps:

[0009] (1) Determine the composition, shape, and size of the thermoelectric thin film materials required to grow in each region of the PNP / NPN bipolar junction thermoelectric transistor, the spacing between each bipolar junction thermoelectric transistor, and various performance parameters of the device through optimization design;

[0010] (2) Calculating the raw material ratio of the mother solution or solvent required for the epitaxial growth of P-type and N-type thermoelectric materials, weighing and mixing them according to the ratio, and then placing them into the liquid phase epitaxial furnace;

[0011] (3) cleaning the substrate and the mask, fixing the mask on the substrate, and then fixing the substrate on the sample stage, placing it in a liquid phase epitaxial furnace, evacuating the vacuum and filling it with protective gas;

[0012] (4) growing a thin film on a substrate covered with a mask plate multiple times according to the composition of the thermoelectric material. After each growth is completed, the mask plate with the thin film grown is removed, and a new mask plate is placed to re-grow or continue to grow the thin film;

[0013] (5) After the growth of step (4) is completed, the mask plate is taken out, and the mask plate for growing electrodes is placed in it, and electrodes are grown on it, and finally a thermoelectric transistor chip is obtained;

[0014] (6) The chip packaging technology is used to package the thermoelectric transistor chip, and its output electrode is led out to make a thermoelectric transistor power generation device.

[0015] Preferably, in step (3), protective gas is first introduced to wash the furnace 0 to 6 times, and then the protective gas is filled into the furnace to reach 0.1 to 20 atm or the flow rate is maintained at 5 to 200 ml / min.

[0016] Preferably, in step (4), after each growth is completed, the vacuum is re-drawn, the furnace is cleaned, and a protective gas is filled; in step (4), after each growth is completed, the film is subsequently treated, and the subsequent treatment includes heat treatment, ion implantation or ion beam thinning.

[0017] Preferably, in step (4), during the thin film growth process, the substrate is placed on a sample stage, and the sample stage moves at a speed of 0.01 to 200 mm / min in the vertical or horizontal direction; the rotation speed of the sample stage is 0 to 20 r / min or the stirring speed of the mother liquid molten pool in the liquid phase epitaxial furnace is 0 to 20 r / min; the temperature difference between the substrate and the mother liquid formed after the raw materials required to grow the thermoelectric material are melted is controlled at 1 to 25°C.

[0018] Preferably, the lattice parameter of the substrate matches the lattice parameter of the P-type and N-type base films, and the difference is no more than 2%.

[0019] Preferably, the bipolar junction thermoelectric transistor prepared in step (4) and step (5) has a planar structure arranged sequentially or a stacked structure arranged layer by layer in a vertical direction.

[0020] Preferably, the thermoelectric transistor chip prepared in step (4) and step (5) is formed by combining a plurality of the bipolar junction thermoelectric transistors in series, in parallel, or in a combination of series and parallel.

[0021] The present invention has the following beneficial effects:

[0022] 1. The main purpose of the present invention is to prepare a bipolar junction thermoelectric transistor (hereinafter referred to as a thermoelectric transistor) power generation device. The vertical or horizontal liquid phase epitaxial growth technology used in the present invention can prepare high-quality P-type and N-type thin film thermoelectric materials, and can construct directly connected PNP / NPN heterojunctions. Under the action of temperature difference, the migration of carriers inside the device will cause changes in the built-in electric field, thereby realizing the forward bias of the PN junction (emitter junction) and the reverse bias of the NP junction (collector junction), and forming a bipolar junction transistor circuit through external leads. At the same time, according to the circuit characteristics of the bipolar junction transistor (the emitter current determines the output current, and the collector voltage determines the output voltage), the decoupling of the conductivity (determined by the output current) and the Seebeck coefficient (determined by the output voltage) can be achieved, thereby improving the conversion efficiency of the thermoelectric device.

[0023] 2. The thermoelectric transistor power generation device prepared by the present invention can realize the normal operation of the thermoelectric transistor directly driven by the Seebeck voltage generated by the temperature difference under room temperature conditions. By utilizing the signal amplification principle of the triode, a huge improvement in output power and thermoelectric conversion efficiency can be obtained. It can be used for thermoelectric power generation under any temperature and any temperature difference conditions, and can power different types of electrical appliances. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of PNP heterojunction and temperature gradient;

[0025] Figure 2 The schematic diagram of the horizontal thermoelectric transistor structure after the circuit is connected; the low temperature end of the P1 region is the emitter of the device, the N region is the base of the device, and the high temperature end of the P2 region is the collector of the device;

[0026] Figure 3 It is a schematic diagram of the structure of a sample stage for vertical liquid phase epitaxial growth;

[0027] Figure 4 Schematic diagram of mask structure; (1) Mask for preparation of P1 region; (2) Mask for preparation of N region; (3) Mask for preparation of P2 region; (4) Mask for preparation of electrode;

[0028] Figure 5 It is a schematic diagram of the appearance structure of a planar thermoelectric transistor;

[0029] Figure 6Schematic diagram of the structure of a thermoelectric transistor power generation device chip consisting of 10 junction transistors connected in series. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] Unless otherwise specified, the technical means used in the embodiments are conventional means well known to those skilled in the art.

[0032] The invention discloses a method for preparing a power generation device based on a PNP / NPN bipolar junction thermoelectric transistor (hereinafter referred to as a thermoelectric transistor). A vertical or horizontal liquid phase epitaxial furnace is used as preparation equipment, and hydrogen, high-purity inert gas or a mixed gas thereof is selected as a process protective gas.

[0033] The present invention adopts the most commonly used (Bi x Sb 1-x )2(Te y Se 1-y )3-based room-temperature thermoelectric material as an example, other thermoelectric materials that currently have broad application prospects can also be prepared into thermoelectric transistors through this method.

[0034] Taking the PNP thermoelectric transistor as an example (the same below, no further details), it is composed of a P-type region 1 (referred to as the P1-type region), an N-type region and a P-type region 2 (referred to as the P2-type region) directly connected, and its constituent materials are P-type thin film thermoelectric material 1 (referred to as the P1-type thin film), N-type thin film thermoelectric material (referred to as the N-type thin film) and P-type thin film thermoelectric material 2 (referred to as the P2-type thin film).

[0035] The present invention adopts liquid phase epitaxy technology, uses high-purity hydrogen, inert gas or a mixture of hydrogen and inert gas as protective gas, and uses mask plate technology to conceal and epitaxially grow P-type and N-type (Bi x Sb 1-x )2(Te y Se 1-y )3(x / y=0-1), referred to as (Bi x Sb 1-x )2(Te y Se 1-y )3 bases, composed of (Bi x Sb 1-x )2(Te y Se 1-y)3-based PNP / NPN heterojunction, and physical deposition and other techniques are used to prepare electrode materials. Finally, a bismuth telluride-based PNP / NPN bipolar junction thermoelectric transistor is prepared. Under the action of temperature gradient, the device can realize the forward bias of the emitter and the reverse bias of the collector, and use the signal amplification principle of the triode to achieve the improvement of output power.

[0036] As one embodiment, the preparation of the device includes the following steps:

[0037] (1) Through optimization design, determine the composition, size, shape of the thermoelectric thin film materials required to grow in each PNP / NPN area, the spacing between each bipolar junction thermoelectric transistor, and various performance parameters of the device.

[0038] (2) Calculate the P-type and N-type (Bi) according to the phase diagram x Sb 1-x )2(Te y Se 1-y ) The raw materials of the mother solution or solvent required for the epitaxial growth of the 3-based thermoelectric material are weighed and mixed in a glove box and then placed in a beaker / crucible. The beaker or crucible containing the mixed raw materials is then placed in a liquid phase epitaxial furnace. It should be noted that the preparation can be carried out in a vertical or horizontal liquid phase epitaxial furnace, and the liquid phase epitaxial furnace can be a single temperature zone, a two-temperature zone, or a three-temperature zone furnace to ensure the quality of the liquid phase epitaxial growth of the thermoelectric thin film material.

[0039] The material composition, size, shape, structure, etc. of the sample stage used for liquid phase epitaxial growth are not limited. It only needs to meet the functions of carrying samples, achieving liquid phase epitaxial film growth, facilitating the regulation of epitaxial film quality, and mass production.

[0040] (3) Ultrasonic cleaning and drying of the substrate to remove surface contaminants (dust, organic matter, etc.). The composition of the substrate material is not limited, but the requirement is that the lattice parameters of the substrate material are consistent with the epitaxy (Bi x Sb 1-x )2(Te y Se 1-y ) The lattice parameters of the 3-base films match, that is, the difference is no more than 2%.

[0041] (4) Select appropriate materials and make the mask plate according to the device design requirements. After cleaning, attach it to the substrate and fix the substrate and mask plate with a suitable adhesive. Put the sample stage with the substrate and mask plate installed into the liquid phase epitaxial furnace, evacuate the chamber and fill it with hydrogen, inert gas or a mixture of hydrogen and inert gas as a protective gas. To ensure the purity of the atmosphere in the furnace chamber, wash the furnace several times and then fill it with hydrogen, inert gas or a mixture of hydrogen and inert gas to 0.1-20atm or maintain a flow rate of 5-200ml / min. The type of inert gas is not limited, such as argon, nitrogen, etc., which is used as a protective gas to prevent oxidation.

[0042] The material composition of the mask plate is not limited. The main requirements are stable performance and easy completion of its structure and size processing according to device design requirements.

[0043] (5) Growth: It can be divided into two, three or even multiple growths, such as P1, N, P2 or N1, P, N2. x Sb 1-x )2(Te y Se 1-y )3-based thin film; each growth requires the proportion of solvent raw materials to be configured according to the composition requirements of the thermoelectric material designed for the transistor, re-evacuation, and then filling with high-purity hydrogen, inert gas or a mixture of hydrogen and inert gas for protection. The specific number of growth times depends on the requirements of the device performance on the film performance parameters.

[0044] By arbitrarily adjusting (Bi x Sb 1-x )2(Te y Se 1-y )3-based thin film thermoelectric materials, such as the content of each element, such as Bi, Sb, Se and Te, and the type and amount of various dopants, control the composition of the mother solution or solvent, and then control the growth (Bi x Sb 1-x )2(Te y Se 1-y )3 base film material composition, P / N type and carrier concentration. Because (Bi x Sb 1-x )2(Te y Se 1-y )3-based thermoelectric materials can achieve N-type and P-type conduction by changing the stoichiometric ratio and the type and amount of dopants; in addition, p-type Bi2Te3 can be obtained by selectively dissolving Sb at the Bi site and Se at the Te site to obtain n-type Bi2Te3.

[0045] For example, taking the three-time sequential growth of a PNP thermoelectric transistor as an example, the first time, a mask plate for growing a P1 type thin film is placed, and a P1 type thin film is grown, which serves as the emitter of the transistor; after the growth of the P1 region is completed, the sample stage is taken out, the substrate is kept unchanged, the mask plate for growing the P1 type thin film is removed, and a mask plate for growing an N type thin film is placed, and after the growth of the N type thin film is completed, it serves as the base of the transistor; at this time, the two types of thin film materials form a PN junction (emitter junction), the sample stage is taken out, the mask plate for growing the N type thin film is removed, and a mask plate for growing a P2 type thin film is placed, and the last P2 type thin film is grown, which serves as the collector, and forms an NP junction (collector junction) with the N region thin film, and finally a PNP heterojunction is obtained.

[0046] The structure of the PNP / NPN heterojunction can be a planar structure in which PNP / NPN are arranged in sequence in the horizontal direction ( Figure 5 The schematic diagram of the structure is given), or it can be a stacked structure with PNP / NPN stacked layer by layer in the vertical direction. Whether it is a planar structure or a stacked structure, the specific size, shape and structure as well as various performance parameters of the device can be arbitrarily designed and manufactured according to actual needs.

[0047] The melted mother liquid is kept warm at 410-610℃, and the holding temperature is related to the proportion of solvent elements. When using the vertical liquid phase epitaxy process, the substrate needs to be lowered to a position 5cm above the mother liquid and the substrate rotation device needs to be turned on; when using the horizontal liquid phase epitaxy process, the substrate needs to be moved left or right to the center below the molten pool, and the rotation or stirring device of the molten pool needs to be turned on; if necessary, the substrate and the molten pool can be non-rotating or the rotation rate can be zero. Specifically: When using the vertical liquid phase epitaxy process, the rotation speed of the substrate can be adjusted within the range of 0-20r / min. When using the horizontal liquid phase epitaxy process, the rotation or stirring speed of the molten pool can be adjusted within the range of 0-20r / min. The vertical or horizontal movement speed of the sample stage corresponding to the vertical and horizontal epitaxial furnaces can be controlled between 0.01 and 200mm / min; the temperature difference between the substrate and the mother liquid is controlled between 1 and 25℃.

[0048] (6) The film grown by each liquid phase epitaxial growth can be treated by combining epitaxial film heat treatment, ion implantation and other epitaxial film post-treatment techniques to ensure its quality and performance. Alternatively, the post-treatment techniques may not be used according to actual conditions.

[0049] (7) Take out the grown PNP heterojunction and place it into a mask plate for growing electrodes, and use thin film growth techniques such as vacuum evaporation, electron beam deposition, ion beam deposition, physical deposition, etc. to prepare electrodes and circuits, and finally obtain a thermoelectric transistor chip. The composition of the electrode or circuit material of the thermoelectric transistor is not limited, such as Au, Ag, Cu, Al, etc.

[0050] (8) Test the performance parameters of the manufactured devices and analyze and inspect their quality in a timely manner.

[0051] (9) According to the input voltage and power requirements of the electrical device, the above-mentioned thermoelectric transistor chip can be composed of any number of PNP or NPN bipolar junction thermoelectric transistors connected in series, in parallel, or in a combination of series and parallel. For example, a thermoelectric transistor power generation device chip composed of 10 junction transistors connected in series is Figure 6 shown.

[0052] (10) The chip packaging technology is used to package the thermoelectric transistor chip, and its output terminal electrode is led out to complete the preparation of the thermoelectric transistor power generation device.

[0053] The thermal transistor temperature difference power generation device disclosed in the present invention can be applied to temperature difference power generation or thermoelectric detection by using the temperature difference formed between various cold sources and heat sources with no restrictions on the absolute values ​​of the high and low temperature ends.

[0054] The present invention is applicable to the research, design, analysis and optimization of any device and instrument in the field of thermoelectricity or temperature difference electricity based on the principle of thermoelectric transistors, and the development of thermoelectric transistor devices; including but not limited to thermoelectric transistor power generation devices, thermometers, and detectors.

[0055] The present invention adopts the most commonly used (Bi x Sb 1-x )2(Te y Se 1-y )3-based room-temperature thermoelectric material as an example, other thermoelectric materials that currently have broad application prospects can also be prepared into thermoelectric transistors through this method.

[0056] The present invention will be further described below in conjunction with specific embodiments.

[0057] Example

[0058] To prepare (Bi x Sb 1-x )2(Te y Se 1-y )3-based thermoelectric transistor as an example, including the following steps:

[0059] (1) Through theoretical calculation, determine the composition, shape, and size of the thin film required to grow in each PNP area, the spacing between transistors, and the various performance parameters of the device.

[0060] (2) A wafer (single crystal silicon wafer) with 500 nm thick SiO2 on the surface is selected as the substrate, and the wafer is pre-treated and cut into 10×10 mm squares, and surface contaminants are removed by ultrasonic cleaning and drying.

[0061] (3) According to the binary phase diagrams of Bi-Te, Sb-Te, and Bi-Se, the mass of Bi powder, Te powder, Sb powder, and Se powder required to grow P and N type thin films is calculated by the lever rule (in intrinsic Bi2Te3, n-type and p-type conduction can be achieved by changing the stoichiometric ratio. For example, according to the phase diagram, when the atomic ratio Te / Bi=9, the film composition is N type, then the mass ratio of the two elements required is Te / Bi=5.495. If 10g of Bi powder is taken, then 54.95g of Te element needs to be weighed. In addition, p-type can be obtained by selecting Sb solid solution in the Bi position and n-type can be obtained by solid solution in the Te position (Bi x Sb 1-x )2(Te y Se 1-y )3-based thermoelectric material. The specific mass is also calculated according to the doping ratio through the phase diagram), weighed in an Ar gas-protected glove box, mixed in an agate mortar, and then placed in a clean quartz beaker, and finally the beaker containing the mixed raw materials is placed in a liquid phase epitaxial furnace;

[0062] (4) placing the cut silicon wafer on the graphite sample stage, fixing the processed graphite sheet mask plate on the surface of the silicon wafer, and fixing the silicon wafer, the mask plate and the sample stage with heat-resistant glue, and finally placing the installed sample stage in the liquid phase epitaxial furnace;

[0063] (5) The liquid phase epitaxial furnace is evacuated, and an inert gas (argon) is introduced to wash the furnace three times, and then Ar gas is introduced to achieve normal pressure protection.

[0064] (6) The powder is fully heated until it melts, and then kept at the liquidus temperature. The temperature of the substrate is controlled by the vertical height of the sample stage to maintain the temperature difference between the mother liquid and the substrate at 10°C. P1 type, N type, and P2 type (Bi x Sb 1-x )2(Te y Se 1-y )3-based thin film materials form two directly connected PN junctions, and finally obtain a PNP heterojunction, in which the low-temperature end of the P1N junction can be used as the emitter junction of the triode, and the high-temperature end of the NP2 can be used as the collector junction of the triode. During the growth process, the sample stage rotation speed is 10r / min, the vertical movement speed of the sample stage is 0.1mm / min, the temperature difference between the substrate and the molten mother liquid is 10℃, and the growth time is 20s.

[0065] When it is necessary to prepare an NPN type heterojunction, the order of film growth is changed to N1, P, N2 type, and two directly connected NP junctions are formed to form an NPN heterojunction. The specific component ratio can be calculated and weighed according to step (2).

[0066] (7) After taking out the PNP heterojunction, a graphite sheet is used as a mask plate, and a circuit and an electrode are prepared by physical deposition technology to prepare a thermoelectric transistor chip. The parameters of the prepared thermoelectric transistor chip are shown in Table 1.

[0067] The principle schematic diagram of the PNP thermoelectric transistor epitaxial wafer provided by the present invention is as follows Figure 1 and Figure 2 The schematic diagram of the sample stage structure is shown in Figure 3 As shown, the schematic diagram of the mask plate structure is as follows Figure 4 The appearance diagram of a single device is shown in Figure 5 shown.

[0068] Table 1 shows the parameters of the thermoelectric transistor prepared by the present invention.

[0069] area Epitaxial Materials Length / mm Width / μm Thickness / μm <![CDATA[Carrier concentration / cm -3 > <![CDATA[P1 type thin film (emitter)]]> <![CDATA[P1-Bi2Te3]]> 6 300 20 <![CDATA[2.3×10 19 ]]> N-type thin film (base) <![CDATA[N-Bi2Te3]]> 6 0.04 20 <![CDATA[2.8×10 19 ]]> <![CDATA[P2 type thin film (collector)]]> <![CDATA[P2-Bi2Te3]]> 6 300 20 <![CDATA[3.4×10 19 ]]>

[0070] The embodiments described above are only descriptions of the preferred modes of the present invention, and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A method for preparing a bipolar junction thermoelectric transistor power generation device, characterized in that: Liquid phase epitaxy technology is adopted, with hydrogen, inert gas or a mixture of hydrogen and inert gas as protective gas, mask plate technology is used to conceal and epitaxially grow P-type and N-type thermoelectric films on the substrate, and physical deposition technology is used to prepare electrode materials to prepare bipolar junction thermoelectric transistor chips. The chip is packaged and the output end electrode is led out to make a thermoelectric transistor power generation device.

2. The preparation method according to claim 1, characterized in that: The following steps are involved: (1) Determine the composition, shape, and size of the thermoelectric thin film materials required to grow in each region of the PNP / NPN bipolar junction thermoelectric transistor, the spacing between each bipolar junction thermoelectric transistor, and various performance parameters of the device through optimization design; (2) Calculating the raw material ratio of the mother solution or solvent required for the epitaxial growth of P-type and N-type thermoelectric materials, weighing and mixing them according to the ratio, and then placing them into the liquid phase epitaxial furnace; (3) cleaning the substrate and the mask, fixing the mask on the substrate, and then fixing the substrate on the sample stage, placing it in a liquid phase epitaxial furnace, evacuating the vacuum and filling it with protective gas; (4) growing a thin film on a substrate covered with a mask plate multiple times according to the composition of the thermoelectric material. After each growth is completed, the mask plate with the thin film grown is removed, and a new mask plate is placed to re-grow or continue to grow the thin film; (5) After the growth of step (4) is completed, the mask plate is taken out, and the mask plate for growing electrodes is placed in it, and electrodes are grown on it, and finally a thermoelectric transistor chip is obtained; (6) The chip packaging technology is used to package the thermoelectric transistor chip, and its output electrode is led out to make a thermoelectric transistor power generation device.

3. The preparation method according to claim 1, characterized in that: In step (3), protective gas is first introduced to wash the furnace 0 to 6 times, and then the protective gas is filled into the furnace to reach 0.1 to 20 atm or the flow rate is maintained at 5 to 200 ml / min.

4. The preparation method according to claim 1, characterized in that: In step (4), after each growth is completed, the vacuum is re-drawn, the furnace is cleaned, and a protective gas is filled; in step (4), after each growth is completed, the film is subsequently treated, and the subsequent treatment includes heat treatment, ion implantation or ion beam thinning.

5. The preparation method according to claim 1, characterized in that: In step (4), during the thin film growth process, the substrate is placed on a sample stage, and the sample stage moves at a speed of 0.01 to 200 mm / min in the vertical or horizontal direction; the rotation speed of the sample stage is 0 to 20 r / min or the stirring speed of the mother liquid molten pool in the liquid phase epitaxial furnace is 0 to 20 r / min; the temperature difference between the substrate and the mother liquid formed after the raw materials required to grow the thermoelectric material are melted is controlled at 1 to 25°C.

6. The preparation method according to claim 1, characterized in that: The lattice parameter of the substrate matches the lattice parameter of the P-type and N-type base films, and the difference is no more than 2%.

7. The preparation method according to claim 1, characterized in that: The bipolar junction thermoelectric transistor prepared in step (4) and step (5) has a planar structure arranged in sequence or a stacked structure arranged layer by layer in a vertical direction.

8. The preparation method according to claim 5, characterized in that: The thermoelectric transistor chip prepared in step (4) and step (5) is formed by combining a plurality of the bipolar junction thermoelectric transistors in series, parallel or a combination of series and parallel.

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