Method for forming capacitor structure

Abstract

The method for forming the capacitor structure comprises a plurality of processes. A single layer of carbon film is deposited on a plurality of top portions of the plurality of bottom electrode plates. And patterning the single-layer carbon film. After patterning the single-layer carbon thin film, the bottom electrode plate is etched based on the single-layer carbon thin film. After the bottom electrode plate is etched, the single-layer carbon film is removed. Forming a dielectric layer on the bottom electrode plate; a plurality of top electrode plates aligned with the bottom electrode plates are formed on the dielectric layer. In this way, the underlying structure below the carbon film is prevented from being broken or damaged unexpectedly.

Description

Technical Field

[0001] The present disclosure relates to a method of forming a capacitor structure. Background Art

[0002] The memory structure may include one or more capacitors. As the critical dimension (CD) of the memory structure decreases, the memory structure needs more support strength to maintain the overall structural strength stable, or to withstand less stress during the formation process to avoid cracking and damage of the formed memory structure.

[0003] Therefore, how to provide a method for forming a capacitor structure of a storage structure, which can form the capacitor structure in a low stress environment, is one of the problems that technicians in the relevant field want to solve. Summary of the invention

[0004] One aspect of the present disclosure relates to a method of forming a capacitor structure.

[0005] According to one or more embodiments of the present disclosure, a method for forming a capacitor structure includes multiple processes. Depositing a single-layer carbon film on multiple tops of multiple bottom electrode plates. Patterning the single-layer carbon film. After patterning the single-layer carbon film, etching the bottom electrode plate based on the single-layer carbon film. After the bottom electrode plate is etched, removing the single-layer carbon film. Forming a dielectric layer on the bottom electrode plate. Forming multiple top electrode plates aligned with the bottom electrode plate on the dielectric layer.

[0006] In one or more embodiments of the present disclosure, the single-layer carbon film is deposited by a plasma enhanced chemical vapor deposition process at a temperature ranging between 600° C. and 650° C.

[0007] In one or more embodiments of the present disclosure, the method for forming a capacitor structure further comprises a plurality of processes: depositing a first dielectric anti-reflection layer on the single-layer carbon film; and directly depositing a second dielectric anti-reflection layer on the first dielectric anti-reflection layer.

[0008] In some embodiments of the present disclosure, the first dielectric anti-reflection layer and the second dielectric anti-reflection layer are deposited by a chemical vapor deposition process.

[0009] In some embodiments of the present disclosure, the first dielectric anti-reflection layer and the second dielectric anti-reflection layer are silicon oxynitride, and the oxygen and nitrogen compositions of the first dielectric anti-reflection layer are different from the oxygen and nitrogen compositions of the second dielectric anti-reflection layer.

[0010] In some embodiments of the present disclosure, the method for forming a capacitor structure further includes a plurality of processes: forming an anti-reflection coating on the second dielectric anti-reflection layer; forming a photoresist layer on the anti-reflection coating, wherein the anti-reflection coating and the photoresist layer are formed by a coating process, and patterning the single-layer carbon film includes etching the single-layer carbon film through the photoresist layer.

[0011] In one or more embodiments of the present disclosure, the bottom electrode plate is formed in a stack of multiple nitride layers and multiple oxide layers, and etching the bottom electrode plate further includes etching the nitride layer and the oxide layer until the top surface of the lowest one of the nitride layers.

[0012] In some embodiments of the present disclosure, an etching selectivity ratio between the single-layer carbon film and the oxide layer is equal to or greater than 30.

[0013] In one or more embodiments of the present disclosure, each of the bottom electrode plates has a U-shaped profile, and the U-shaped profile of each bottom electrode plate has a bottom connected to the conductive layer. Etching the bottom electrode plates includes etching the two side wall portions closest to the two bottom electrode plates to define a common bottom electrode area.

[0014] One aspect of the present disclosure relates to a method of forming a capacitor structure.

[0015] According to one or more embodiments of the present disclosure, a method for forming a capacitor structure includes multiple processes. Depositing a carbon film on a stack of multiple nitride layers and multiple oxide layers and on multiple bottom electrode plates within the stack of nitride layers and oxide layers. Patterning the carbon film. After the carbon film is patterned, etching the bottom electrode plate and the stack of nitride layers and oxide layers based on the carbon film. After the bottom electrode plate and the stack of nitride layers and oxide layers are etched, removing the carbon film. Removing the oxide layer. Forming a dielectric layer on the bottom electrode plate. Forming multiple top electrode plates aligned with the bottom electrode plate on the dielectric layer.

[0016] In one or more embodiments of the present disclosure, the carbon thin film is deposited by a plasma enhanced chemical vapor deposition process at a temperature ranging between 600°C and 650°C.

[0017] In one or more embodiments of the present disclosure, the method for forming a capacitor structure further comprises a plurality of processes: depositing a first dielectric anti-reflection layer on the carbon film and directly depositing a second dielectric anti-reflection layer on the first dielectric anti-reflection layer.

[0018] In some embodiments of the present disclosure, the method for forming a capacitor structure further includes multiple processes: forming an anti-reflection coating on the second dielectric anti-reflection layer; forming a photoresist layer on the anti-reflection coating, wherein the anti-reflection coating and the photoresist layer are formed by a coating process, and patterning the carbon film includes etching the carbon film through the photoresist layer.

[0019] In one or more embodiments of the present disclosure, an etching selectivity ratio between the carbon film and the oxide layer is equal to or greater than 30.

[0020] In one or more embodiments of the present disclosure, each of the bottom electrode plates is a hollow tube having a U-shaped profile, and each of the top electrode plates is filled between two adjacent ones of the bottom electrode plates.

[0021] One aspect of the present disclosure relates to a method of forming a capacitor structure.

[0022] According to one or more embodiments of the present disclosure, a method for forming a capacitor structure includes multiple processes. Depositing a carbon film on multiple bottom electrode plates. Depositing a first dielectric anti-reflection layer on the carbon film. Directly depositing a second dielectric anti-reflection layer on the first dielectric anti-reflection layer, wherein the oxygen and nitrogen composition of the first dielectric anti-reflection layer is different from the oxygen and nitrogen composition of the second dielectric anti-reflection layer. Forming an anti-reflection coating on the second dielectric anti-reflection layer. Forming a photoresist layer on the anti-reflection coating. Patterning the carbon film. After the carbon film is patterned, etching the bottom electrode plate based on the carbon film. After the bottom electrode plate is etched, forming a dielectric layer on the bottom electrode plate. Forming multiple top electrode plates aligned with the bottom electrode plate on the dielectric layer.

[0023] In one or more embodiments of the present disclosure, each of the top electrode plates is formed at a common bottom electrode region spanning at least two of the bottom electrode plates.

[0024] In one or more embodiments of the present disclosure, the anti-reflection coating and the photoresist layer are formed by a coating process.

[0025] In one or more embodiments of the present disclosure, depositing the carbon film on the bottom electrode plate includes depositing the carbon film on a stack of a plurality of oxide layers and a plurality of nitride layers surrounding the bottom electrode plate.

[0026] In one or more embodiments of the present disclosure, the carbon thin film is deposited by a plasma enhanced chemical vapor deposition process at a temperature ranging between 600°C and 650°C.

[0027] In summary, in one or more embodiments of the present disclosure, a small amount of carbon film can be used as a hard mask to etch the underlying structure below the carbon film, thereby reducing stress accumulation in the underlying structure and preventing unexpected cracking or damage to the underlying structure below the carbon film.

[0028] The above description is only used to illustrate the problem to be solved by the present disclosure, the technical means to solve the problem, and the effects produced, etc. The specific details of the present disclosure will be described in detail in the following implementation methods and related drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The advantages and drawings of the present disclosure should be better understood by referring to the following embodiments and the accompanying drawings. The description of these drawings is only for exemplifying the embodiments, and therefore should not be considered to limit the individual embodiments or the scope of the invention claims.

[0030] Figure 1A schematic cross-sectional view of an intermediate structure for forming a capacitor structure according to one or more embodiments of the present disclosure is shown;

[0031] Figure 2A A schematic top view of a plurality of bottom electrode plates is shown according to one or more embodiments of the present disclosure;

[0032] Figure 2B To illustrate Figure 2A A schematic cross-sectional view of

[0033] Figure 3 A schematic cross-sectional view showing a method of forming a carbon film on a bottom electrode plate according to one or more embodiments of the present disclosure is shown;

[0034] Figure 4 A schematic cross-sectional view showing a method of forming a dielectric anti-reflection layer on a carbon film according to one or more embodiments of the present disclosure is shown;

[0035] Figure 5 A schematic cross-sectional view showing the formation of an anti-reflective coating and a photoresist layer on the anti-reflective coating according to one or more embodiments of the present disclosure;

[0036] Figure 6 A schematic cross-sectional view of etching a dielectric anti-reflective layer according to one or more embodiments of the present disclosure is shown;

[0037] Figure 7 A schematic cross-sectional view of a patterned carbon film is shown according to one or more embodiments of the present disclosure;

[0038] Figure 8 A schematic cross-sectional view illustrating the removal of a photoresist layer, an anti-reflective coating layer, and a dielectric anti-reflective layer according to one or more embodiments of the present disclosure;

[0039] Fig. 9A and Fig. 9B A schematic top view and a schematic cross-sectional view are shown for illustrating a bottom electrode plate and a stack of a nitride layer and an oxide layer based on etching of a carbon film according to one or more embodiments of the present disclosure;

[0040] Fig.10 A schematic cross-sectional view showing the removal of a carbon film and an oxide layer according to one or more embodiments of the present disclosure is shown;

[0041] Fig.11 A schematic cross-sectional view showing a method of forming a high-k dielectric layer on a bottom electrode plate according to one or more embodiments of the present disclosure;

[0042] Fig.12 A schematic cross-sectional view showing a plurality of top electrode plates formed on a high-k dielectric layer according to one or more embodiments of the present disclosure; and

[0043] Fig.13 The present invention is a flowchart illustrating a method for forming a capacitor structure according to one or more embodiments of the present invention. DETAILED DESCRIPTION

[0044] The following examples are described in detail with the accompanying drawings, but the examples provided are not intended to limit the scope of the present disclosure, and the description of the structural operation is not intended to limit the order of its execution. Any device with equal functions produced by the re-combination of components is within the scope of the present disclosure. In addition, the drawings are for illustration purposes only and are not drawn in their original size. For ease of understanding, the same or similar components in the following description will be described with the same symbols.

[0045] In addition, the terms used throughout the specification and claims generally have the ordinary meaning of each term used in the field, in the context of this disclosure, and in the specific context, unless otherwise noted. Certain terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art on the description of the present disclosure.

[0046] Herein, the terms “first”, “second”, etc. are merely used to distinguish elements or operating methods with the same technical terminology, and are not intended to indicate an order or to limit the present disclosure.

[0047] In addition, the words "include", "including", "provide" and similar terms are open-ended limitations in this article, meaning including but not limited to.

[0048] Further, in this article, unless the text specifically limits the article, "a", "an" and "the" may refer to a single one or more. It will be further understood that "comprising", "including", "having" and similar words used in this article indicate the features, regions, integers, steps, operations, elements and / or components described therein, but do not exclude the described or additional one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0049] As the critical dimension (CD) decreases, the storage structure requires more nitride crystals to support strength to maintain the overall structural strength. Due to etching selectivity, in one or more embodiments of the present disclosure, one or more layers of carbon film and dielectric anti-reflective layer can be used to replace the stack of nitride and oxide to form a capacitor structure in the storage structure. In one or more embodiments of the present disclosure, a fewer number of carbon film layers can be used to reduce stress to avoid cracks or film stripping on the formed capacitor structure.

[0050] Please refer to Figure 1 . Figure 1A schematic cross-sectional view of an intermediate structure 100 for forming a capacitor structure is shown according to one or more embodiments of the present disclosure, wherein two layers of carbon film 160 and carbon film 170 are formed in the intermediate structure 100 .

[0051] In one or more embodiments of the present disclosure, the conductive layer 105 is formed on a substrate. The substrate may include, for example, a silicon substrate or other suitable semiconductor substrate. For the purpose of clarity, Figure 1 The substrate below the conductive layer 105 is not shown. In one or more embodiments of the present disclosure, the conductive layer 105 includes metal, such as tungsten or other suitable metal materials. Figure 1 As shown, the conductive layer 105 extends along a direction x.

[0052] like Figure 1 As shown, nitride layer 110 is located above conductive layer 105. The top surface of conductive layer 105 is covered by nitride layer 110, so that nitride layer 110 can protect conductive layer 105 and prevent conductive layer 105 from being damaged. Oxide layer 115 is located above nitride layer 110. Nitride layer 120 is located above oxide layer 115. Oxide layer 125 is located above nitride layer 120. Nitride layer 130 is located above oxide layer 125. Oxide layer 135 is located above nitride layer 130. Nitride layer 140 is located above oxide layer 135. Nitride layer 110, nitride layer 120, nitride layer 130, nitride layer 140, oxide layer 115, oxide layer 125, and oxide layer 135 can be regarded as a semiconductor storage stack above conductive layer 105. A plurality of bottom electrode plates 150 are formed in the semiconductor memory stack of the nitride layers 110 , 120 , 130 , 140 and the oxide layers 115 , 125 , and 135 .

[0053] like Figure 1 As shown, the bottom electrode plate 150 is a hollow tube extending along the direction z. The bottom electrode plate 150 extends through the nitride layer 110, the oxide layer 115, the nitride layer 120, the oxide layer 125, the nitride layer 130, the oxide layer 135 and the nitride layer 140 in sequence along the direction z, and extends to the conductive layer 105. In one or more embodiments of the present disclosure, the nitride layer 110, the nitride layer 120, the nitride layer 130, and the nitride layer 140 can be regarded as a support layer for supporting the bottom electrode plate 150. The oxide layer 115, the oxide layer 125 and the oxide layer 135 can be regarded as a supporting sacrificial layer and removed in a subsequent further process.

[0054] In one or more embodiments of the present disclosure, the nitride layer 110, the nitride layer 120, the nitride layer 130, and the nitride layer 140 include titanium nitride or silicon nitride. In one or more embodiments of the present disclosure, the oxide layer 115 includes borophosphosilicate glass (BPSG). In one or more embodiments of the present disclosure, the oxide layer 125 includes tetraethoxysilane (TEOS) oxide. In one or more embodiments of the present disclosure, the material of the bottom electrode plate 150 may include a conductive material, such as a metal material.

[0055] exist Figure 1 In the schematic cross-sectional view of , each bottom electrode plate 150 is a hollow tube having a U-shaped profile, and the bottom of the bottom electrode plate 150 is connected to the same conductive layer 105 .

[0056] After forming the bottom electrode plate 150 in the semiconductor memory stack of the nitride layer 110, the nitride layer 120, the nitride layer 130, the nitride layer 140 and the oxide layer 115, the oxide layer 125 and the oxide layer 135, two hard mask layers are formed over the top surface of the nitride layer 140 and on top of the bottom electrode plate 150. Figure 1 As shown, one set of hard mask layers includes a carbon film 160 and a dielectric anti-reflective layer 165 located above the top surface of the nitride layer 140 and the top of the bottom electrode plate 150, and another set of hard mask layers includes a carbon film 170 located above the dielectric anti-reflective layer 165 and a dielectric anti-reflective layer 175 located above the carbon film 170. The dielectric anti-reflective layer 165 and the dielectric anti-reflective layer 175 can be considered as a dielectric anti-reflective coating layer (DARC layer for short).

[0057] In one or more embodiments of the present disclosure, the carbon film 160 is formed by a deposition process. For example, the carbon film 160 is deposited on the top surface of the nitride layer 140 by a plasma enhanced chemical vapor deposition (PECVD) process. In the exemplary plasma enhanced chemical vapor deposition process, propylene (C3H6) is provided and reacted with plasma to deposit the carbon film 160. In some embodiments of the present disclosure, the carbon film 160 is deposited at a temperature of approximately 550°C, and the density of the formed carbon film 160 is 1.71 g / cm 3 , the stress is +231MPa, and the modulus is 126GPa. It is worth noting that the plus sign of the stress means that the carbon film 160 can apply tensile stress to the underlying structure below. For the etchant of the oxide layer 115, the oxide layer 125, and the oxide layer 135, the etching selectivity of the carbon film 160 can be 15, where the etching selectivity is the ratio of the etching rate of the etchant on the carbon film 160 to the etching rate of the etchant on the oxide layer 115, the oxide layer 125, and the oxide layer 135.

[0058] After the carbon film 160 is formed, a dielectric anti-reflection layer 165 is deposited on the carbon film 160 by a chemical deposition (CVD) process. In some embodiments of the present disclosure, the dielectric anti-reflection layer 165 is a SiON film deposited on the carbon film 160 by reacting SiH4 gas and N2O gas.

[0059] The carbon film 170 can be deposited on the dielectric anti-reflection layer 165 by a PECVD process similar to the PECVD process of the carbon film 160, and has similar density, stress, modulus, and etching selectivity. Then, the dielectric anti-reflection layer 175 is deposited on the carbon film 170 by a CVD process similar to the CVD process of the dielectric anti-reflection layer 165.

[0060] Subsequently, an optical hard mask 185 and a photoresist layer 190 are formed on the dielectric anti-reflection layer 175. The optical hard mask 185 is formed on the dielectric anti-reflection layer 165 and the photoresist layer 190. An underlayer 180 is located under the optical hard mask 185. In one or more embodiments of the present disclosure, the underlayer 180, the hard mask 185, and the photoresist layer 190 can be formed by a coating process.

[0061] The carbon films 160 and 170 as hard mask layers can be patterned through the photoresist layer 190, and the bottom electrode plate 150 and the semiconductor storage stack of the nitride layer 110, the nitride layer 120, the nitride layer 130, the nitride layer 140 and the oxide layer 115, the oxide layer 125 and the oxide layer 135 can be etched based on the patterned carbon films 160 and 170.

[0062] In one or more embodiments of the present disclosure, the stress accumulation of the carbon films 160 and 170 may cause structural cracks and damage the bottom electrode plate 150. Abnormal profiles caused by stress accumulation will appear in the formed capacitor structure. In one or more embodiments of the present disclosure, a single-layer carbon film can be used as a hard mask layer for etching the bottom electrode plate and the oxide layer, and the single-layer carbon film has low stress and can improve the stress accumulation phenomenon.

[0063] Please refer to Figures 2A to 12 as well as Fig.13 . Figures 2A to 12 A plurality of schematic top views and a plurality of schematic cross-sectional views are shown for illustrating a capacitor structure 200 formed according to one or more embodiments of the present disclosure. Fig.13 A flow chart of a method 300 for forming a capacitor structure 200 is shown according to one or more embodiments of the present disclosure.

[0064] Figure 2AA schematic top view of a plurality of bottom electrode plates 250 is shown according to one or more embodiments of the present disclosure. Figure 2B Draw Figure 2A A schematic cross-sectional view of Figure 2B A schematic cross-sectional view along a line passing through the edge of the array of bottom electrode plates 250 in direction x is depicted.

[0065] like Figure 2A As shown, a plurality of bottom electrode plates 250 are formed above the conductive layer 205. For the purpose of clarity, one or more layers are not shown. Figure 2A In. Figure 2A In the embodiment, the bottom electrode plates 250 are spaced equidistantly in the x-direction and the y-direction to form an array. Figure 2B A schematic cross section at the edge of the array of bottom electrode plates 250 is shown.

[0066] exist Figure 2B In the embodiment, a semiconductor memory stack of semiconductor layers is formed over a conductive layer 205 and around a bottom electrode plate 250. The semiconductor memory stack includes a nitride layer 210 over the conductive layer 205, an oxide layer 215 over the nitride layer 210, a nitride layer 220 over the oxide layer 215, an oxide layer 225 over the nitride layer 220, a nitride layer 230 over the oxide layer 225, an oxide layer 235 over the nitride layer 230, and a nitride layer 240 over the oxide layer 235. The top surface of the conductive layer 205 is covered by the nitride layer 210. The top surface of the nitride layer 210 is exposed.

[0067] like Figure 2B As shown, each bottom electrode plate 250 is a hollow tube with a U-shaped profile, and the bottom of the U-shaped profile of the bottom electrode plate 250 is connected to the same conductive layer 205. The bottom portion of the bottom electrode plate 250 extends sequentially through the nitride layer 210, the oxide layer 215, the nitride layer 220, the oxide layer 225, the nitride layer 230, the oxide layer 235 and the nitride layer 240 along the direction z. The open top of the bottom electrode plate 250 has a length CD1 in the direction x. The length CD1 can be regarded as a critical dimension at which the bottom electrode plate 250 can be observed.

[0068] Please refer to Figure 3 and Fig.13 In process 301 , a single carbon film 260 is deposited on a bottom electrode plate 250 and a stack of nitride layers 210 , 220 , 230 , 240 and oxide layers 215 , 225 and 235 surrounding the bottom electrode plates 250 . Figure 3 A schematic cross-sectional view of forming a carbon film 260 on a bottom electrode plate 250 is shown according to one or more embodiments of the present disclosure.

[0069] In one or more embodiments of the present disclosure, the carbon film 260 is formed by a deposition process. For example, the carbon film 260 is deposited on the top surface of the nitride layer 240 by a plasma enhanced chemical vapor deposition (PECVD) process. In detail, during the PECVD process of the carbon film 260, propylene (C3H6) is provided and reacts with plasma to deposit the carbon film 260.

[0070] In some embodiments of the present disclosure, the carbon film 260 is deposited at a temperature between 600° C. and 650° C. For example, the carbon film 260 is deposited at a temperature of 625° C., and the density of the formed carbon film 260 is 1.93 g / cm 3 , the stress is -50 MPa, and the modulus is 162 GPa. It should be noted that the negative sign of the stress means that the carbon film 260 can apply compressive stress to the underlying structure (eg, the bottom electrode plate 250).

[0071] The carbon film 260 deposited at high temperature can have a large density. Figure 1 The difference between the carbon film 160 or 170 deposited at 550° C. and the carbon film 260 deposited at 625° C. is that the density of the carbon film 260 is greater than that of the carbon film 160 or 170. The carbon film 260 having a large density may also have a large modulus and a large etching selectivity compared to the oxide. In one or more embodiments of the present disclosure, the etching selectivity is the ratio of the etching rate of the etchant etching the carbon film 260 to the etching rate of the etchant etching the oxide layers 215, 225, and 235, which may be, for example, 30.

[0072] like Figure 1 The difference between the carbon film 160 deposited at 550° C. and the carbon film 260 deposited at 625° C. is that the stress of the carbon film 260 is different from the stress of the carbon film. The stress magnitude of the carbon film 260 is smaller than the stress magnitude of the carbon film 160 or 170. The stress direction of the carbon film 260 is opposite to the stress direction of the carbon film 160 or 170. The carbon film 260 has a large density and a large modulus, so that the carbon film 260 has a small extension portion and does not apply tensile stress to the underlying structure below. The carbon film 260 has a small compressive stress, which can prevent the underlying structure below from being broken or damaged.

[0073] In one or more embodiments of the present disclosure, during the deposition of the carbon film 260, carbon may be deposited inside the bottom electrode plate 250. The carbon deposited inside the bottom electrode plate 250 may be removed in a subsequent further removal process for the carbon film 260.

[0074] Please refer to Figure 4 and Fig.13In process 302 , dielectric anti-reflection layers 265 and 266 are deposited on the carbon film 260 . Figure 4 A schematic cross-sectional view of forming dielectric anti-reflection layers 265 and 266 on a carbon film 260 is shown according to one or more embodiments of the present disclosure.

[0075] like Figure 4 As shown, after the carbon film 260 is formed, a dielectric anti-reflection layer 265 is deposited directly on the carbon film 260 by a CVD process. In some embodiments of the present disclosure, the dielectric anti-reflection layer 265 can be a film of SiON deposited on the carbon film 260 by a reaction of SiH4 gas and N2O gas. The present disclosure then deposits a dielectric anti-reflection layer 266 directly on the dielectric anti-reflection layer 265. Similarly, the dielectric anti-reflection layer 266 can be a film of SiON deposited on the carbon film 260 by a reaction of SiH4 gas and N2O gas. In one or more embodiments of the present disclosure, the dielectric anti-reflection layers 265 and 266 have different oxygen and silicon compositions. For example, the dielectric anti-reflection layer 265 can be a silicon-rich (Si-rich) anti-reflection layer, and the dielectric anti-reflection layer 266 can be an oxygen-rich (O-rich) anti-reflection layer. In one or more embodiments of the present disclosure, the oxygen and silicon compositions of the dielectric anti-reflective layers 265 and 266 may be adjusted based on the photolithographic design of the carbon film 260 .

[0076] Please refer to Figure 5 and Fig.13 In process 303 , a bottom anti-reflection coating 270 is formed directly on the dielectric anti-reflection layer 266 , and a photoresist layer 275 is formed on the bottom anti-reflection coating 270 . Figure 5 According to one or more embodiments of the present disclosure, a schematic cross-sectional view of forming an anti-reflection coating 270 and forming a photoresist layer 275 on the anti-reflection coating 270 is shown. In one or more embodiments of the present disclosure, the anti-reflection coating 270 and the photoresist layer 275 are formed by a coating process.

[0077] like Figure 5 As shown, after forming a photoresist layer 275 on the bottom anti-reflection coating 270, the photoresist layer 275 is developed, and the developed photoresist layer 275 has a plurality of openings 275o. The plurality of openings 275o are aligned with the regions between the plurality of bottom electrode plates 250. Each opening 275o has a length CD2 in the direction x.

[0078] Please refer to Figure 6 , Figure 7 and Fig.13 In process 304 , the carbon film 260 is patterned through the photoresist layer 275 .

[0079] Figure 6A schematic cross-sectional view of etching the dielectric anti-reflective layers 265 and 266 is shown according to one or more embodiments of the present disclosure. Figure 6 As shown, the opening 275 o extends through the dielectric antireflective layers 265 and 266 to the top surface of the carbon film 260 .

[0080] After etching the dielectric anti-reflection layers 265 and 266 , the carbon thin film 260 below the dielectric anti-reflection layers 265 and 266 is patterned. Figure 7 A schematic cross-sectional view of a patterned carbon film 260 is shown according to one or more embodiments of the present disclosure.

[0081] Please refer to Figure 8 and Fig.13 In process 305 , the photoresist layer 275 , the anti-reflection coating 270 , and the dielectric anti-reflection layers 265 and 266 are removed. Figure 8 A schematic cross-sectional view of removing the photoresist layer 275, the anti-reflective coating 270, and the dielectric anti-reflective layers 265 and 266 is shown according to one or more embodiments of the present disclosure. Figure 8 As shown, the patterned carbon film 260 includes an opening 260o having a length CD2 in the direction x. The opening 260o of the carbon film 260 is aligned with the area between the bottom electrode plate 250. The length CD2 can be regarded as a critical dimension of the patterned carbon film 260. In one or more embodiments of the present disclosure, the length CD2 of each opening 260o of the carbon film 260 is greater than the length CD1 of each bottom electrode plate 250 in the direction x (e.g., Figure 2B shown).

[0082] Please refer to FIG. 9A to FIG. 9B and Fig.13 In process 306 , the bottom electrode plate 250 and the stack of the nitride layers 210 , 220 , 230 , 240 and the oxide layers 215 , 225 , 235 are etched based on the patterned carbon film 260 to define a plurality of common bottom electrode regions 255 . Fig. 9A and Fig. 9B According to one or more embodiments of the present disclosure, a schematic top view and a schematic cross-sectional view of etching a bottom electrode plate based on a carbon film 260 and stacking nitride layers 210 , 220 , 230 , 240 and oxide layers 215 , 225 , 235 are shown.

[0083] like Fig. 9A As shown, a plurality of common bottom electrode regions 255 are formed between four adjacent bottom electrode plates 250. For the purpose of clear description, Fig. 9A The carbon film 260 , the nitride layers 210 , 220 , 230 , 240 , and the oxide layers 215 , 225 , and 235 are not shown.

[0084] Fig. 9B2 is a schematic cross-sectional view near the edge of the array of bottom electrode plates 250. For a group of four adjacent bottom electrode plates 250, the four adjacent bottom electrode plates 250, the nitride layers 220, 230, 240 and the oxide layers 215, 225 and 235 between the four adjacent bottom electrode plates 250 are etched based on the openings 260o of the patterned carbon film 260, thereby defining a plurality of common bottom electrode regions 255, wherein the patterned carbon film 260 with the openings 260o can be regarded as a hard mask. The sidewall portions of the four adjacent bottom electrode plates 250 are etched. Fig. 9B The schematic cross-sectional view shown illustrates that the common bottom electrode region 255 spans across two adjacent bottom electrode plates 250 , wherein the two adjacent bottom electrode plates 250 have etched sidewall portions.

[0085] In one or more embodiments of the present disclosure, the bottom electrode plate 250, the nitride layers 220, 230 and 240, and the oxide layers 215, 225 and 235 can be etched respectively by three sets of dry etching processes with different conditions. It should be noted that after the three sets of etching processes with different conditions, the carbon material of the carbon film 260 has a sufficient residual thickness, so that the carbon film 260 can be ensured to have a high protective ability for the underlying structure including the bottom electrode plate 250 below, and the carbon film 260 has a high etching selectivity. For example, compared to the thickness before etching to define the common bottom electrode region 255, after etching the bottom electrode plate 250, the nitride layers 220, 230 and 240, and the oxide layers 215, 225 and 235 and defining the common bottom electrode region 255, the carbon film 260 can still have a residual thickness of more than 50%. The etching selectivity of the carbon film 260 (i.e., the ratio of the etching rate of the carbon film 260 to the etching rate of the oxide layers 215, 225, and 235 in the etching process of the oxide layers 215, 225, and 235) may be equal to or greater than 30. The single-layer carbon film 260 deposited at a high temperature has a large density, low applied stress, and exhibits a stable structure, which can prevent the film from breaking and avoid short circuits in the subsequently formed storage structure.

[0086] As an example but not to overly limit the present disclosure, after defining the common bottom electrode region 255 , the thickness of the carbon film 260 in the direction z may be 149 nm.

[0087] Please refer to Fig.10 and Fig.13 In process 307 , the carbon film 260 and the oxide layers 215 , 225 , and 235 are removed. Fig.10A schematic cross-sectional view of removing the carbon film 260 and the oxide layers 215, 225, and 235 is depicted according to one or more embodiments of the present disclosure. In some embodiments of the present disclosure, the carbon film 260 and the oxide layers 215, 225, and 235 can be removed in different processes. After removing the carbon film 260 and the oxide layers 215, 225, and 235, the nitride layers 210, 220, 230, and 240 support the bottom electrode plate 250. The array of bottom electrode plates 250 includes a plurality of common bottom electrode regions 255 having a length CD3 in the direction x. Each length CD3 is greater than Figure 8 Length CD2 shown.

[0088] As an example and not to overly limit the present disclosure, the length CD2 may be 27.4 nm and the length CD3 may be 35 nm. As an example and not to limit the present disclosure, the length CD2 may be 23.8 nm and the length CD3 may be 32 nm.

[0089] Please refer to Fig.11 and Fig.13 In process 308 , a dielectric layer 280 is deposited on the bottom electrode plate 250 . Fig.11 A schematic cross-sectional view of forming a high-k dielectric layer 280 on a bottom electrode plate 250 is shown according to one or more embodiments of the present disclosure. Fig.11 As shown, the dielectric layer 280 spans across the plurality of common bottom electrode regions 255 and the bottom electrode plate 250. In one or more embodiments of the present disclosure, the dielectric layer 280 may be a high-k dielectric material.

[0090] Please refer to Fig.12 and Fig.13 In process 309 , a top electrode plate 285 is formed on the dielectric layer 280 and fills the bottom electrode plate 250 . Fig.12 According to one or more embodiments of the present disclosure, a schematic cross-sectional view of forming a plurality of top electrode plates 285 on a high-k dielectric layer 280 is shown, wherein the top electrode plates 285 are formed on a plurality of common bottom electrode regions 255 between the bottom electrode plates 250. Fig.12 As shown, one of the top electrode plates 285 spans across two adjacent bottom electrode plates 250 in the direction x. The bottom electrode plates 250, the dielectric layer 280, and the top electrode plates 285 form a plurality of capacitors of the capacitor structure 200, wherein the formed capacitors share the same dielectric layer 280, and each of the formed capacitors includes one of the top electrode plates 285 and four directly adjacent bottom electrode plates 250 connected to each other through the dielectric layer 280 in the corresponding common bottom electrode region 255.

[0091] In summary, in one or more embodiments of the present disclosure, a small amount of carbon film can be used as a hard mask for etching the underlying structure. For example, a single-layer carbon film can be used as a hard mask. In one or more embodiments of the present disclosure, the single-layer carbon film can be deposited and formed at a high temperature and has a high density, modulus, and a larger etching selectivity than the oxide layer. A small amount of stress accumulation effect will appear in the underlying structure below the single-layer carbon film, thereby avoiding unexpected fracture or damage to the bottom electrode plate used for the capacitor in the underlying structure below the single-layer carbon film when the capacitor structure is formed.

[0092] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the definition of the attached claims.

[0093] It is obvious to those skilled in the art that various modifications and variations may be made to the structure of the embodiments of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present invention as long as they fall within the scope of the attached protection.

[0094]

Explanation of symbols

[0095] 100: Intermediate structure

[0096] 105: Conductive layer

[0097] 110,120,130,140: Nitride layer

[0098] 115,125,135: Oxide layer

[0099] 150: Bottom electrode plate

[0100] 160:Carbon film

[0101] 165: Dielectric anti-reflection layer

[0102] 170:Carbon film

[0103] 175: Dielectric anti-reflection layer

[0104] 180: Bottom

[0105] 185:Hard Mask

[0106] 190: Photoresist layer

[0107] 200: Capacitor structure

[0108] 205: Conductive layer

[0109] 210,220,230,240: Nitride layer

[0110] 215,225,235: Oxide layer

[0111] 250: Bottom electrode plate

[0112] 255: shared bottom electrode area

[0113] 260:Carbon film

[0114] 260o: Opening

[0115] 265,266: Dielectric antireflection layer

[0116] 270: Anti-reflective coating

[0117] 275: Photoresist layer

[0118] 275o: Opening

[0119] 280: Dielectric layer

[0120] 285: Top electrode plate

[0121] 300: Methods

[0122] 301~309: Process

[0123] CD1,CD2,CD3:Length

[0124] x,y,z: direction.

Claims

1. A method for forming a capacitor structure, characterized in that: include: Depositing a single-layer carbon film on multiple top portions of multiple bottom electrode plates; patterning the single-layer carbon film; After patterning the single-layer carbon film, etching the plurality of bottom electrode plates based on the single-layer carbon film; After the plurality of bottom electrode plates are etched, removing the single-layer carbon film; forming a dielectric layer on the plurality of bottom electrode plates; as well as A plurality of top electrode plates aligned with the plurality of bottom electrode plates are formed on the dielectric layer.

2. The method according to claim 1, characterized in that The single-layer carbon film is deposited by a plasma enhanced chemical vapor deposition process at a temperature ranging between 600°C and 650°C.

3. The method according to claim 1, characterized in that Further including: depositing a first dielectric anti-reflection layer on the single-layer carbon film; and A second dielectric anti-reflection layer is directly deposited on the first dielectric anti-reflection layer.

4. The method according to claim 3, characterized in that The first dielectric anti-reflection layer and the second dielectric anti-reflection layer are deposited by a chemical vapor deposition process.

5. The method according to claim 3, characterized in that: The first dielectric anti-reflection layer and the second dielectric anti-reflection layer are silicon oxynitride, and oxygen and nitrogen compositions of the first dielectric anti-reflection layer are different from oxygen and nitrogen compositions of the second dielectric anti-reflection layer.

6. The method according to claim 3, characterized in that: Further including: forming an anti-reflection coating on the second dielectric anti-reflection layer; as well as A photoresist layer is formed on the anti-reflection coating, wherein the anti-reflection coating and the photoresist layer are formed by a coating process, and patterning the single-layer carbon film includes etching the single-layer carbon film through the photoresist layer.

7. The method according to claim 1, characterized in that The plurality of bottom electrode plates are formed in a stack of a plurality of nitride layers and a plurality of oxide layers, and etching the plurality of bottom electrode plates further comprises: The plurality of nitride layers and the plurality of oxide layers are etched until a top surface of a lowest one of the plurality of nitride layers.

8. The method according to claim 7, characterized in that An etching selectivity ratio of the single-layer carbon film to the plurality of oxide layers is equal to or greater than 30.

9. The method according to claim 1, characterized in that: Each of the multiple bottom electrode plates has a U-shaped profile, and the U-shaped profile of each of the multiple bottom electrode plates has a bottom connected to the conductive layer. Etching the multiple bottom electrode plates includes etching the two side wall portions of the two most adjacent ones of the multiple bottom electrode plates to define a common bottom electrode area.

10. A method for forming a capacitor structure, characterized in that: include: Depositing a carbon film on a stack of multiple nitride layers and multiple oxide layers and multiple bottom electrode plates within the stack of multiple nitride layers and multiple oxide layers; patterning the carbon film; After the carbon film is patterned, etching the stack of the plurality of bottom electrode plates, the plurality of nitride layers, and the plurality of oxide layers based on the carbon film; After the plurality of bottom electrode plates and the stack of the plurality of nitride layers and the plurality of oxide layers are etched, removing the carbon film; removing the plurality of oxide layers; forming a dielectric layer on the plurality of bottom electrode plates; as well as A plurality of top electrode plates aligned with the plurality of bottom electrode plates are formed on the dielectric layer.

11. The method according to claim 10, characterized in that The carbon thin film is deposited by a plasma enhanced chemical vapor deposition process at a temperature ranging between 600°C to 650°C.

12. The method according to claim 10, characterized in that Further including: depositing a first dielectric anti-reflection layer on the carbon film; and A second dielectric anti-reflection layer is directly deposited on the first dielectric anti-reflection layer.

13. The method according to claim 12, characterized in that Further including: forming an anti-reflection coating on the second dielectric anti-reflection layer; A photoresist layer is formed on the anti-reflection coating, wherein the anti-reflection coating and the photoresist layer are formed by a coating process, and patterning the carbon film includes etching the carbon film through the photoresist layer.

14. The method according to claim 10, characterized in that An etching selectivity ratio of the carbon film to the plurality of oxide layers is equal to or greater than 30.

15. The method according to claim 10, characterized in that Each of the plurality of bottom electrode plates is a hollow tube having a U-shaped profile, and each of the plurality of top electrode plates is filled between the most adjacent two of the plurality of bottom electrode plates.

16. A method for forming a capacitor structure, characterized in that: include: Depositing a carbon film on a plurality of bottom electrode plates; depositing a first dielectric anti-reflection layer on the carbon film; depositing a second dielectric anti-reflection layer directly on the first dielectric anti-reflection layer, wherein the oxygen and nitrogen composition of the first dielectric anti-reflection layer is different from the oxygen and nitrogen composition of the second dielectric anti-reflection layer; forming an anti-reflection coating on the second dielectric anti-reflection layer; forming a photoresist layer on the anti-reflective coating; patterning the carbon film; After the carbon film is patterned, etching the plurality of bottom electrode plates based on the carbon film; After the plurality of bottom electrode plates are etched, forming a dielectric layer on the plurality of bottom electrode plates; as well as A plurality of top electrode plates aligned with the plurality of bottom electrode plates are formed on the dielectric layer.

17. The method according to claim 16, characterized in that Each of the plurality of top electrode plates is formed at a common bottom electrode region spanning at least two of the plurality of bottom electrode plates.

18. The method according to claim 16, characterized in that The anti-reflection coating and the photoresist layer are formed by a coating process.

19. The method according to claim 16, characterized in that Depositing the carbon film on the bottom electrode plates includes depositing the carbon film on a stack of oxide layers and nitride layers surrounding the bottom electrode plates.

20. The method according to claim 16, characterized in that The carbon thin film is deposited by a plasma enhanced chemical vapor deposition process at a temperature ranging between 600°C to 650°C.

Images