Integrated circuit device with angled transistors

Abstract

IC devices with angled transistors and related assemblies and methods are disclosed herein. If the longitudinal axis of an elongated semiconductor structure (e.g., a fin or nanobelt) based on which the transistor is constructed is at an angle other than 0 or 90 degrees with respect to the edges of the front or back side of a support structure on / in which the transistor resides, e.g., between 10 and 80 degrees with respect to at least one of these edges, the transistor can be constructed. The transistor is referred to as "angled". Angled transistors provide a promising approach to increase transistor density over a limited area of a semiconductor chip.

Description

Background Art

[0001] Over the past several decades, the scaling of features in integrated circuits (ICs) has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features enables the density of functional units to be increased on the limited area of ​​a semiconductor chip. For example, shrinking transistor size allows an increasing number of memory or logic devices to be incorporated on a chip, facilitating the manufacture of products with increased capacity. However, the drive to continually increase capacity is not without its problems. The necessity to optimize the performance of each device and each contact becomes increasingly important. Careful design of transistors can aid in this optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments will be easily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, the same reference numerals represent the same structural elements. In the various figures of the accompanying drawings, the embodiments are shown by way of example and not limitation.

[0003] Figure 1 A perspective view of an example IC device implementing a nanoribbon transistor in accordance with some embodiments is provided.

[0004] Figure 2 A perspective view of an example IC device implementing a fin-based field effect transistor (FinFET) in accordance with some embodiments is provided.

[0005] Figure 3A-3B A top view of an example IC device having non-angled elongated semiconductor structures is provided in accordance with some embodiments.

[0006] Figures 4A-4B A top view of an example IC device having angled elongated semiconductor structures is provided in accordance with some embodiments.

[0007] Figures 5A-5Q A schematic diagram of a cross-sectional side view of an example IC device integrating non-angled and angled transistors according to some embodiments is provided.

[0008] Figures 6A-6F Top views of example IC devices having angled elongated semiconductor structures patterned according to different patterning techniques are provided in accordance with some embodiments.

[0009] Figures 7A-7G Top views of results of various processes of a ring trimming method for fabricating an IC device having an angled elongated semiconductor structure are provided in accordance with some embodiments.

[0010] Figures 8A-8F Provided are methods that can be used according to some embodiments Figures 7A-7GA top view of an alternative arrangement of various components of an IC device fabricated by the method is shown.

[0011] Figures 9A-9D Top views of various processes of a staggered via formation method for fabricating an IC device that integrates angled elongated semiconductor structures with a regular array of vias are provided in accordance with some embodiments.

[0012] Fig.10 Top views of wafers and dies that may include one or more IC devices with angled transistors according to any of the embodiments disclosed herein are provided.

[0013] Fig.11 is a cross-sectional side view of an IC package including an IC device having an angled transistor according to any embodiment disclosed herein.

[0014] Fig.12 is a cross-sectional side view of an IC device assembly including an IC device having an angled transistor according to any embodiment disclosed herein.

[0015] Fig.13 is a block diagram of an example computing device including an IC device having angled transistors according to any embodiment disclosed herein.

[0016] Fig.14 is a block diagram of an example processing device including an IC device having angled transistors according to any embodiment disclosed herein. DETAILED DESCRIPTION

[0017] IC devices with angled transistors and related components and methods are disclosed herein. The devices, components, and methods disclosed herein each have several innovative aspects, no single aspect being solely responsible for all of the desirable properties disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the following description and accompanying drawings.

[0018] In order to explain the IC device with angled transistors proposed herein, it may be useful to first understand the phenomena that may be at work in such an arrangement. The following basic information may be considered as a basis on which the present disclosure may be properly explained. This information is provided for the purpose of explanation only and, therefore, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

[0019] A field effect transistor (FET), such as a metal oxide semiconductor (MOS) FET (MOSFET), is a three-terminal device including source, drain and gate terminals, and uses an electric field to control the current flowing through the device. A FET typically includes a semiconductor channel material, a source region and a drain region provided in the channel material, and a gate stack including at least a gate electrode material and optionally also a gate insulator, wherein the gate stack is provided on a portion of the channel material between the source region and the drain region.

[0020] Recently, FETs with non-planar architectures, such as FinFETs (sometimes also called “gate-all-around transistors” or “tri-gate transistors”) and nanoribbon / nanowire transistors (sometimes also called “gate-all-around (GAA) transistors”), have been widely explored as alternatives to transistors with planar architectures.

[0021] In a FinFET, an elongated semiconductor structure shaped as a fin (i.e., an elongated structure including a semiconductor material) extends away from a substrate (e.g., from a semiconductor substrate or any suitable support structure). The portion of the fin closest to the substrate may be surrounded by an insulator material. This insulator material, typically an oxide, is typically referred to as "shallow trench isolation" (STI), and the portion of the fin surrounded by the STI is referred to as a "sub-fin portion" or simply "sub-fin". The gate stack may surround the upper portion of the fin (i.e., the portion farthest from the substrate). The portion of the fin surrounded by the gate stack is referred to as the "channel" or "channel portion" of the FinFET. The semiconductor material of the channel portion is typically referred to as the "channel material" of the transistor. FinFETs are sometimes referred to as "tri-gate transistors" because, in use, such transistors can form conductive channels on three "sides" of the channel portion of the fin. Source and drain regions are provided in the fins on opposite sides of the gate stack, forming the source and drain of the FinFET, respectively.

[0022] In a nanoribbon transistor, a gate stack may be provided around a portion of an elongated semiconductor structure referred to as a "nanoribbon", with gates formed on all sides of the nanoribbon. The "channel" or "channel portion" of a nanoribbon transistor is the portion of the nanoribbon surrounded by the gate stack. Such a transistor is sometimes referred to as a "GAA transistor" because, in use, such a transistor may form a conductive channel on all "sides" of the channel portion of the nanoribbon. Source and drain regions are provided in the nanoribbon on each side of the gate stack, forming the source and drain of the nanoribbon transistor, respectively. In some arrangements, the term "nanoribbon" is used to describe an elongated semiconductor structure having a substantially rectangular cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term "nanowire" is used to describe a similar structure, but having a substantially circular or square cross-section. In the following, the single term "nanoribbon transistor" is used to describe all non-planar transistors in which the gate stack substantially surrounds all sides of the elongated semiconductor structure, regardless of the shape of the cross-section. Therefore, as used herein, the term "nanoribbon transistor" is used to cover transistors having an elongated semiconductor structure with a substantially rectangular cross-section (possibly with rounded corners), transistors having an elongated semiconductor structure with a substantially square cross-section (possibly with rounded corners), transistors having an elongated semiconductor structure with a substantially circular or elliptical / oval cross-section, and transistors having an elongated semiconductor structure with any polygonal cross-section.

[0023] As described above, both FinFETs and nanoribbon transistors are built on an elongated semiconductor structure. The longitudinal axis of such a structure can be defined as the shortest line between the source region and the drain region of a FinFET or nanoribbon transistor. Typically, such a line extends substantially parallel to the support structure (e.g., die, chip, substrate, carrier substrate, or packaging substrate) on which the transistor resides / in which it resides, and is one of the lines of symmetry of the transistor (at least for an idealized version of the transistor that does not reflect unexpected manufacturing variations that may affect the actual geometry of the transistor). Traditionally, FinFETs and nanoribbon transistors are oriented on a support structure so that the longitudinal axes of their elongated semiconductor structures (i.e., fins or nanoribbons, respectively) are parallel to the front and back sides of the support structure, and are perpendicular or parallel to different edges of the support structure, in particular perpendicular or parallel to different edges of the front or back sides of the support structure. In contrast to such conventional implementations, embodiments of the present disclosure provide IC devices with angled transistors, wherein a transistor is referred to as "angled" if the longitudinal axis of the elongated semiconductor structure upon which the transistor is constructed is at an angle other than 0 or 90 degrees relative to an edge of the front or back side of a support structure on which / in which the transistor resides, such as an angle between 10 and 80 degrees relative to at least one edge of the front or back side of the support structure (because not only one but two angles can be defined in any two lines intersecting each other, the two angles adding up to 180 degrees, so for angled structures / transistors, the angle referred to herein refers to the smaller of the two angles of any given pair of two lines). Angled transistors provide a promising method for increasing transistor density, particularly FinFET and nanoribbon transistor density, on a limited area of ​​a semiconductor chip, and embodiments of the present disclosure provide solutions for the layout and patterning of angled transistors and the integration of angled and non-angled transistors.

[0024] In the following detailed description, various aspects of the illustrative implementations may be described using terms that are commonly used by those skilled in the art to convey the essence of their work to other technicians in the field. For example, in the context of source / drain (S / D) regions, the term "region" can be used interchangeably with the terms "contact" and "terminal" of transistors. In another example, as used herein, the term "connection" means a direct electrical or magnetic connection between connected things without any intermediate device, while the term "coupling" means a direct electrical or magnetic connection between connected things, or an indirect connection through one or more passive or active intermediate devices. The term "circuit" means one or more passive and / or active components that are arranged to cooperate with each other to provide the desired function. If the terms "oxide", "carbide", "nitride", "sulfide", etc. are used, it refers to a compound containing oxygen, carbon, nitrogen, sulfur, etc., respectively, the term "high-k dielectric" refers to a material with a dielectric constant (k) higher than silicon oxide, and the term "low-k dielectric" refers to a material with k lower than silicon oxide. The terms "substantially," "close," "approximately," "almost," and "about" generally refer to within + / -20% of a target value, such as within + / -5% or within + / -2%, based on the context of specific values ​​described herein or known in the art. Similarly, terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, generally refer to within + / -1-20% of a target value, such as + / -1-10% of a target value or + / -1-5% of a target value, based on the context of specific values ​​described herein or known in the art.

[0025] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with the two layers, or may have one or more intervening layers. Conversely, a first layer "above" a second layer is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intervening layers.

[0026] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used in reference to a measurement range, the term "between" includes both ends of the measurement range. As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0027] The description may use the phrases "in an embodiment" or "in multiple embodiments," each of which may refer to one or more of the same or different embodiments. In addition, the terms "including," "comprising," "having," and the like used with respect to the embodiments of the present disclosure are synonymous. The present disclosure may use perspective-based descriptions, such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments. The drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object merely indicates that different instances of the same object are referenced, and is not intended to imply that the objects so described must be in a given sequence in time, space, rank, or in any other manner.

[0028] In the following detailed description, reference is made to the accompanying drawings which form a part of the description and in which are shown by way of illustration embodiments that may be practiced. It should be understood that other embodiments may be utilized and that structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be construed in a restrictive sense. For convenience, similar elements represented by different reference numerals after a dash in the present figures, such as edges 303-1, 303-2, 303-3 and 303-4, may be collectively referred to as, for example, "edge 303" without a reference numeral after the dash. In order not to clutter the figures, if multiple instances of certain elements are shown, only some of the elements may be labeled with a reference numeral. Multiple figures having the same number and different letters may be referenced without the letters, for example, Figures 5A-5Q May be cited as "Figure 5".

[0029] In the accompanying drawings, some schematic diagrams of example structures of various devices and components described herein may be shown with exact right angles and straight lines, but it should be understood that when any structure described herein is examined using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images, these schematic diagrams may not reflect real-world process limitations that may cause features to appear less than "ideal." In such images of real structures, possible processing defects may also be visible, such as imperfectly straight edges of material, tapered vias or other openings, inadvertent rounded corners or thickness variations of different material layers, accidental spiral, edge or combined dislocations within a crystal region, and / or accidental dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device manufacturing. Examination of layout and mask data using, for example, an optical microscope, TEM or SEM and reverse engineering of portions of the device to reconstruct the circuit, and / or examination of cross-sections of the device using, for example, physical failure analysis (PFA) to detect the shape and position of various device elements described herein, will allow the presence of IC devices with angled transistors described herein to be determined.

[0030] Various operations may be described as a plurality of discrete actions or operations in sequence in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations are necessarily sequence-dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed, and / or the described operations may be omitted.

[0031] Various IC devices having angled transistors as described herein may be implemented in or associated with one or more components associated with the IC, and / or may be implemented between various such components. In various embodiments, components associated with the IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, and the like. Components associated with the IC may include components mounted on the IC or connected to the IC. The IC may be analog or digital and may be used in many applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, and the like, depending on the components associated with the IC. The IC may be used as part of a chipset for performing one or more related functions in a computer.

[0032] Figure 1 A perspective view of an example IC device 100 implementing a nanoribbon transistor 110 is provided in accordance with some embodiments. Nanoribbon transistor 110 is one example of an angled transistor that may be included in various IC devices and components described herein.

[0033] Steering Figure 1 1 , IC device 100 may include semiconductor material, which may include one or more semiconductor materials, formed into a nanoribbon 104 (i.e., an elongated semiconductor structure) extending substantially parallel to support structure 102. Transistor 110 may be based on nanoribbon 104 by having gate stack 106 at least partially surround a portion of the nanoribbon referred to as a "channel portion" and by having source and drain regions (at the Figure 1 The first S / D region 114-1 and the second S / D region 114-2 are shown in FIG. 1 and are formed on either side of the gate stack 106. In some embodiments, an oxide material layer ( Figure 1 not specifically shown).

[0034] Figure 1 The IC device 100 shown in FIG. 1 and the IC devices shown in other figures of the present disclosure are intended to illustrate the relative arrangement of some of the components, and the IC device 100 or portions thereof may include other components not shown (e.g., electrical contacts to the S / D regions 114 of the transistor 110, additional layers such as spacer layers around the gate stack 106 of the transistor 110, etc.). For example, although not shown in FIG. Figure 1 , but a dielectric spacer may be provided between a first S / D contact that may be coupled to a first S / D region 114-1 of the transistor 110 and the gate stack 106 and between a second S / D contact that may be coupled to a second S / D region 114-2 of the transistor 110 and the gate stack 106 to provide electrical isolation between the source, gate, and drain contacts (generally, the "contacts" described herein may also be referred to as "electrodes"). In another example, although not shown in FIG. Figure 1 10 is specifically shown in the drawings, but at least a portion of transistor 110 may be surrounded by an insulator material, such as any suitable interlayer dielectric (ILD) material. In some embodiments, such an insulator material may be a high-k dielectric, including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for this purpose may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium oxide silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In other embodiments, the insulator material surrounding a portion of transistor 110 may be a low-k dielectric material. Some examples of low-k dielectric materials include, but are not limited to, silicon dioxide, carbon-doped oxides, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fused silica glass (FSG), and organosilicates such as silsesquioxanes, siloxanes, or organosilicate glasses.

[0035] Implementations of the present disclosure may be formed or performed on any suitable support structure 102, such as a substrate, die, wafer, or chip. The support structure 102 may be, for example, Fig.10 The wafer 2000 may be or be included in a die, such as discussed below. Fig.10 The support structure 102 may be a semiconductor substrate composed of a semiconductor material system including, for example, an N-type or P-type material system. In one implementation, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or an SOI substructure. In other implementations, the semiconductor substrate may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of III-V materials (i.e., materials of Groups III and V of the Periodic Table), II-VI materials (i.e., materials of Groups II and IV of the Periodic Table), or Group IV materials (i.e., materials of Group IV of the Periodic Table). In some embodiments, the substrate may be amorphous. In some embodiments, the support structure 102 may be a printed circuit board (PCB) substrate. Although a few examples of materials from which support structure 102 may be formed are described herein, any material that may be used as a basis upon which the IC devices having angled transistors described herein may be constructed falls within the spirit and scope of the present disclosure.

[0036] For example, the nanoribbon 104 can take the form of a nanowire or a nanoribbon. In some embodiments, the cross-sectional area of ​​the nanoribbon 104 (i.e., Figure 1 The area in the xz plane of the example coordinate system xyz shown) can be between about 25 and 10,000 square nanometers, including all values ​​and ranges therein (e.g., between about 25 and 1,000 square nanometers, or between about 25 and 500 square nanometers). The cross section of the nanoribbon 104 is a cross section along a plane perpendicular to the longitudinal axis 120 of the nanoribbon 104, where the longitudinal axis 120 can be, for example, along Figure 1 In some embodiments, the width of the nanoribbon 104 (i.e., in a plane parallel to the support structure 102 and in a direction perpendicular to the longitudinal axis 120 (e.g., along the Figure 1 The dimension measured along the x-axis of the example coordinate system shown) can be the thickness (or "height") of the nanoribbon 104 (i.e., the dimension measured in a plane perpendicular to the support structure 102 (e.g., along the x-axis of the example coordinate system shown). Figure 1 The dimension measured along the z-axis of the example coordinate system shown) is at least about 3 times, including all values ​​and ranges therein, such as at least about 4 times or at least about 5 times. It should be noted that Figure 1The xyz coordinate system is shown aligned so that the longitudinal axis 120 is along the y-axis, which is merely for ease of explanation of this particular figure. In other figures, the angled transistors are explained with reference to their longitudinal axes as being somewhere in the xy plane, but not aligned with the y-axis or the x-axis because the edges of the support structure are assumed to be aligned with those axes and the transistors are angled, meaning that they are at an angle between 10 and 80 degrees relative to the y-axis and / or the x-axis. Thus, when transistor 110 is an angled transistor of any subsequent figure, the longitudinal axis 120 is not aligned with the y-axis or the x-axis. Figure 1 The y-axis is shown aligned but at an angle between 10 degrees and 80 degrees relative to the y-axis.

[0037] although Figure 1 The nanoribbon 104 shown in is shown as having a rectangular cross-section, but the nanoribbon 104 may alternatively have a cross-section that is rounded at the corners or otherwise irregularly shaped, and the gate stack 106 may conform to the shape of the nanoribbon 104. The terms "front side" and "back side" of the nanoribbon may refer to the faces of the nanoribbon 104 that are substantially parallel to the support structure 102, the term "sidewall" (or "side") of the nanoribbon may refer to the opposite face of the nanoribbon 104 that is substantially perpendicular to the support structure 102 and extends in the direction of the longitudinal axis 120 of the nanoribbon 104, and the term "end" of the nanoribbon may refer to the opposite face of the nanoribbon 104 that is substantially perpendicular to the longitudinal axis 120 of the nanoribbon 104.

[0038] Nanoribbons 104 may be formed of one or more semiconductor materials, collectively referred to as "channel materials." In general, the channel material of any angled transistor described herein, such as the channel material of transistor 110, may be composed of a semiconductor material system, including, for example, an N-type or P-type material system. In some embodiments, the channel material may include a substantially single-crystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the channel material may include a compound semiconductor having a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In), and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material may include a combination of semiconductor materials.

[0039] For some example N-type transistor embodiments (i.e., for embodiments in which the transistor including the channel material is an N-type metal oxide semiconductor (NMOS) transistor), the channel material may include a III-V material having a relatively high electron mobility, such as, but not limited to, InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some In x Ga 1-x As fin embodiments, the In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In 0.7 Ga 0.3 As). For some example P-type transistor embodiments (i.e., for embodiments in which the transistor including the channel material is a P-type metal oxide semiconductor (PMOS) transistor), the channel material may advantageously be a Group IV material having high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7.

[0040] In some embodiments, the channel material may be a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Typically, the channel material may include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium.

[0041] As described above, the channel material may include IGZO. IGZO-based devices have several desirable electrical and manufacturing properties. Compared to other semiconductors, IGZO has a high electron mobility, for example, in the range of 20-50 times that of amorphous silicon. In addition, typical features of amorphous IGZO (a-IGZO) transistors are high band gap, low temperature process compatibility, and low manufacturing cost compared to other semiconductors. IGZO can be deposited as a uniform amorphous phase while maintaining a higher carrier mobility than oxide semiconductors (such as zinc oxide). Different formulations of IGZO include different proportions of indium oxide, gallium oxide, and zinc oxide. One specific form of IGZO has the chemical formula InGaO3(ZnO)5. Another exemplary form of IGZO has an indium: gallium: zinc ratio of 1:2:1. In various other examples, the IGZO can have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and / or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). The IGZO can also include ternary dopants, such as aluminum or nitrogen.

[0042] In some embodiments, any of the angled transistors described herein, such as transistor 110, may be thin film transistors (TFTs). A TFT is a special type of FET made by depositing an active semiconductor material on a support portion (e.g., a support structure as described above) that may be a non-conductive support portion. Some such materials may be deposited at relatively low temperatures, which allows them to be deposited within the thermal budget imposed by back-end manufacturing to avoid damage to front-end components, such as logic devices of an IC device in which the transistor may be included. Therefore, in some embodiments, the channel material of any of the angled transistors described herein (e.g., transistor 110) may be a semiconductor material deposited at a relatively low temperature, and may include any of the oxide semiconductor materials described above.

[0043] In other embodiments, instead of being deposited at a relatively low temperature as described above with reference to the TFT, the channel material of any angled transistor described herein (e.g., transistor 110) may be epitaxially grown in conditions that would normally involve relatively high temperature processing. In such embodiments, the channel material may include any of the semiconductor materials described above, including oxide semiconductor materials. In some such embodiments, the channel material may be epitaxially grown directly on a semiconductor layer of a support structure on which the transistor will be fabricated, in a process referred to as "monolithic integration." In other such embodiments, the channel material of any angled transistor described herein (e.g., transistor 110) may be epitaxially grown on a semiconductor layer of another support structure, and then the epitaxially grown layer of channel material may be transferred to a support structure on which the transistor will reside, in a process referred to as "layer transfer," in which case the latter support structure may, but need not, include a semiconductor layer prior to the layer transfer. Layer transfer advantageously allows the formation of non-planar transistors, such as FinFETs or nanoribbon transistors, on a support structure or in a layer that does not include semiconductor material (e.g., in the back end of an IC device). Layer transfer also advantageously allows the formation of transistors of any architecture (eg, non-planar or planar transistors) without negatively impacting the relatively high temperature epitaxial growth process that may already exist on the device on the support structure.

[0044] Channel materials deposited at relatively low temperatures are typically polycrystalline, polycrystalline, or amorphous semiconductors, or any combination thereof. Epitaxially grown channel materials are typically highly crystalline (e.g., single crystal or single crystal) materials. Therefore, it is possible to identify whether the channel material of any angled transistor described herein (e.g., transistor 110) is deposited or epitaxially grown by examining the grain size of the active portion of the channel material (e.g., the portion of the channel material that forms the transistor channel). An average grain size of the channel material of any angled transistor described herein (e.g., transistor 110) between approximately 0.5 mm and 1 mm (in which case the material may be polycrystalline) or less than approximately 0.5 mm (in which case the material may be polycrystalline or amorphous) may indicate that the channel material has been deposited (e.g., in which case the transistor including such channel material is a TFT). On the other hand, an average grain size of the channel material of any angled transistor described herein (e.g., transistor 110) equal to or greater than about 1 mm (in which case the material may be a single crystalline material) may indicate that the channel material has been epitaxially grown and included in the final device either by monolithic integration or by layer transfer.

[0045] In some embodiments, the channel material of any angled transistor described herein (e.g., transistor 110) may include a two-dimensional (2D) semiconductor material, i.e., a semiconductor material having a thickness of a few nanometers or less, wherein electrons in the material move freely in the 2D plane, but their restricted motion in a third direction is governed by quantum mechanics. In some such embodiments, such a channel material may include a single atomic monolayer of a 2D semiconductor material, while in other such embodiments, such a channel material may include five or more atomic monolayers of a 2D semiconductor material. Examples of 2D materials that may be used to implement the channel material of any angled transistor described herein include, but are not limited to, graphene, hexagonal boron nitride, or a transition metal chalcogenide.

[0046] The gate stack 106 including the gate electrode material 108 and the optional gate insulator 112 may completely or nearly completely surround a portion of the nanoribbon 104, such as Figure 1 As shown, the channel portion of transistor 110 is the active region (channel region) of the channel material in the portion of nanoribbon 104 surrounded by gate stack 106. Figure 1 The gate insulator 112 is not shown in the perspective view of the IC device 100 shown, but is Figure 1 The gate insulator 112 is shown in the inset 130 of FIG. 1 , which provides a cross-sectional side view of a portion of the nanoribbon 104 with the gate stack 106 surrounding the nanoribbon 104. Figure 1 As shown, the gate insulator 112 may surround a lateral portion / cross-section of the nanoribbon 104 , and the gate electrode material 108 may surround the gate insulator 112 .

[0047] Depending on whether the transistor 110 is a PMOS transistor or an NMOS transistor, the gate electrode material 108 may include at least one P-type work function metal or an N-type work function metal. When the transistor 110 is a PMOS transistor, a p-type work function metal may be used as the gate electrode material 108, and when the transistor 110 is an NMOS transistor, an N-type work function metal may be used as the gate electrode material 108. For a PMOS transistor, metals that may be used for the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode material 108 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 108 may include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a filling metal layer. Additional layers may be included adjacent to the gate electrode material 108 for other purposes, such as as diffusion barriers and / or adhesion layers.

[0048] In some embodiments, the gate insulator 112 may include one or more high-k dielectrics, including any of the materials discussed herein with reference to the insulator material that may surround portions of the transistor 110. In some embodiments, during fabrication of the transistor 110, an annealing process may be performed on the gate insulator 112 to improve the quality of the gate insulator 112. In some embodiments, the gate insulator 112 may have a thickness that may be between about 0.5 nanometers and 3 nanometers, including all values ​​and ranges therein (e.g., between about 1 nanometer and 3 nanometers, or between about 1 nanometer and 2 nanometers), although in other embodiments, the gate insulator 112 may have a thickness greater than 3 nanometers. In some embodiments, the gate stack 106 may be surrounded by a gate spacer, Figure 1 Such a gate spacer will be configured to provide separation between the gate stack 106 and the source / drain contacts of the transistor 110 and may be made of a low-k dielectric material, some examples of which have been provided above. The gate spacer may include holes or air gaps to further reduce its dielectric constant.

[0049] In some embodiments, the gate insulator 112 may include a hysteresis material or a hysteresis arrangement, which together may be referred to as a "hysteresis element." The transistor 110 in which the gate insulator 124 includes a hysteresis element may be described as a "hysteresis transistor" and may be used to implement a hysteresis memory. Hysteresis memory refers to a memory technology that employs a hysteresis material or arrangement, where a material or arrangement may be described as hysteretic if the material or arrangement exhibits a dependence of its state on the material's history (e.g., a dependence on a previous state of the material). Ferroelectric (FE) and antiferroelectric (AFE) materials are examples of hysteresis materials. Layers of different materials arranged in a stack to exhibit a charge trapping phenomenon are examples of hysteresis arrangements.

[0050] FE or AFE materials are materials that exhibit spontaneous electric polarization (i.e., displacement of positive and negative charges from their original positions) over a range of temperatures, where the polarization can be reversed or redirected by applying an electric field. In particular, AFE materials are materials that can exhibit a state in which electric dipoles from ions and electrons in the material can form a substantially ordered (e.g., substantially crystalline) array with adjacent dipoles oriented in opposite (antiparallel) directions (i.e., each oriented dipole can form an interpenetrating sublattice, roughly similar to a checkerboard pattern), while FE materials are materials that can exhibit a state in which all dipoles point in the same direction. Because charge displacements in FE and AFE materials can be maintained for a period of time even in the absence of an electric field, such materials can be used to implement memory cells. Because the current state of the electric dipoles in FE and AFE materials depends on the previous state, such materials are hysteresis materials. Memory technology that stores logic states based on the orientation of electric dipoles in the FE or AFE material (i.e., based on their polarization) is called "FE memory", where the term "ferroelectric" is used to convey the similarity of FE memory to ferromagnetic memory, even though iron (Fe) is typically not present in the FE or AFE material.

[0051] A stack of alternating layers of material configured to exhibit charge trapping is an example of a hysteresis arrangement. Such a stack may include as few as two layers of material, one of which is a charge trapping layer (i.e., a layer of material configured to trap charge when a voltage is applied to the material), and another of which is a tunneling layer (i.e., a layer of material through which charge tunnels to the charge trapping layer). The tunneling layer may include an insulator material, such as a material including silicon and oxygen (e.g., silicon oxide), or any other suitable insulator. The charge trapping layer may include a metal or semiconductor material configured to trap charge. Because the trapped charge may remain in the charge trapping arrangement for a period of time even in the absence of an electric field, such an arrangement may be used to implement a memory cell. Because the presence and / or amount of trapped charge in the charge trapping arrangement depends on the previous state, such an arrangement is a hysteresis arrangement. Memory technology that stores logic states based on the amount of charge trapped in the hysteresis arrangement may be referred to as a "charge trap memory."

[0052] Hysteresis memories have the potential for adequate non-volatility, short programming time, low power consumption, high endurance, and high-speed writes. Furthermore, hysteresis memories can be manufactured using processes compatible with standard complementary metal oxide semiconductor (CMOS) technology. Therefore, over the past few years, these types of memories have become promising candidates for many evolving applications.

[0053] In some embodiments, the hysteresis element of the gate insulator 112 may be provided as a layer of FE or AFE material. Such FE / AFE materials may include one or more materials that can exhibit sufficient FE / AFE behavior even in thin dimensions, for example, such as an insulator material that is at least about 5%, for example at least about 7%, or at least about 10% in an orthorhombic phase and / or a tetragonal phase (e.g., as a material in which up to about 95-90% of the material may be amorphous or in a monoclinic phase). For example, such a material may be based on hafnium and oxygen (e.g., hafnium oxide), with various dopants added to ensure a sufficient amount of orthorhombic or tetragonal phase. Some examples of such materials include materials containing hafnium, oxygen, and zirconium (e.g., hafnium zirconium oxide (HfZrO, also referred to as HZO)), materials containing hafnium, oxygen, and silicon (e.g., silicon-doped (Si-doped) hafnium oxide), materials containing hafnium, oxygen, and germanium (e.g., germanium-doped (Ge-doped) hafnium oxide), materials containing hafnium, oxygen, and aluminum (e.g., aluminum-doped (Al-doped) hafnium oxide), and materials containing hafnium, oxygen, and yttrium (e.g., yttrium-doped (Y-doped) hafnium oxide). However, in other embodiments, any other material that exhibits FE / AFE behavior at thin dimensions may be used as a hysteresis element and is within the scope of the present disclosure.

[0054] In other embodiments, the hysteresis element of the gate insulator 112 may be provided as a stack of alternating layers of a material that can trap charge. In some such embodiments, the stack may be a two-layer stack, where one layer is a charge trapping layer and the other layer is a tunneling layer. The tunneling layer may include an insulator material, such as a material including silicon and oxygen (e.g., silicon oxide), or any other suitable insulator. The charge trapping layer may include a conductive material, such as a metal or a semiconductor material. In some embodiments, the charge trapping layer may include a substoichiometric material (i.e., a material that includes less than a stoichiometric amount of a reagent). The substoichiometric material may include a concentration of at least about 10 18 Vacancies / cm3, for example, at a concentration of about 10 18 Vacancy / cubic centimeter and about 10 22 -10 23Vacancy / cubic centimeter. As is known in the art, a vacancy refers to a position where an atom (e.g., oxygen or nitrogen) that should be present is missing, thereby providing a defect in the material. For example, the substoichiometric material of any hysteresis element described herein may include oxygen, and the vacancy may be an oxygen vacancy, or the substoichiometric material may include nitrogen, and the vacancy may be a nitrogen vacancy. During operation, charge may be trapped in the vacancy of the substoichiometric material. Therefore, realizing a substoichiometric material with vacancies is a way to provide a charge trapping layer for a hysteresis arrangement. In general, any material with a defect that can trap charge can be used as a charge trapping layer / used in a charge trapping layer. Such defects are very harmful to the operation of logic devices, and therefore, careful steps are usually taken to avoid the presence of these defects. However, for memory devices, such defects are desirable because charge trapping can be used to represent different memory states of memory cells.

[0055] In some embodiments where the hysteresis element is provided as a stack of alternating layers of a material that can trap charge, the stack may be a three-layer stack, wherein the insulator material is provided on both sides of the charge trapping layer. In such embodiments, the layer of insulator material on one side of the charge trapping layer may be referred to as a "tunneling layer", while the layer of insulator material on the other side of the charge trapping layer may be referred to as a "field layer".

[0056] In various embodiments where the hysteresis element is provided as a stack of alternating layers of a material that can trap charge, the thickness of each layer of the stack can be between about 0.5 and 10 nanometers, including all values ​​and ranges therein, such as between about 0.5 and 5 nanometers. In some embodiments of a three-layer stack, the thickness of each layer of the insulator material can be about 0.5 nanometers, and the thickness of the charge trapping layer can be between about 1 and 8 nanometers, such as between about 2.5 and 7.5 nanometers, such as about 5 nanometers. In some embodiments, the total thickness of the hysteresis element, which is provided as a stack of alternating layers of a material that can trap charge (i.e., a hysteresis arrangement), can be between about 1 and 10 nanometers, such as between about 2 and 8 nanometers, such as about 6 nanometers.

[0057] Turning to the S / D region 114 of the transistor 110, in some embodiments, the S / D region may be highly doped, for example, with a dopant concentration of about 10 μm / cm3. 21The S / D regions of the transistor 110 may include a dopant in order to advantageously form an ohmic contact with the corresponding S / D electrodes, although these regions may also have lower dopant concentrations and, in some embodiments, may form Schottky contacts. Regardless of the exact doping level, the S / D regions of the transistor may be regions with a higher dopant concentration than other regions, for example, higher than the dopant concentration in the channel portion (i.e., the channel material extending between the first S / D region 114-1 and the second S / D region 114-2), and therefore, may be referred to as a "highly doped" (HD) region. The channel portion of the transistor 110 may include a semiconductor material having a doping concentration significantly less than that of the S / D region 114.

[0058] The S / D region 114 of the transistor 110 can generally be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the nanoribbon 104 to form source and drain regions. An annealing process to activate the dopants and diffuse them further into the nanoribbon 104 can follow the ion implantation process. In the latter process, portions of the nanoribbon 104 can first be etched to form grooves at the locations of the future S / D regions 114. An epitaxial deposition process can then be performed to fill the grooves with materials for making the S / D regions 114. In some implementations, the S / D regions 114 can be made using silicon alloys such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy can be in-situ doped with dopants such as boron, arsenic, or phosphorus. In further embodiments, the S / D regions 114 can be formed using one or more alternative semiconductor materials, such as germanium or III-V materials or alloys. And in further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D zones 114. In some embodiments, the distance between the first and second S / D zones 114 (i.e., the dimension measured along the longitudinal axis 120 of the nanoribbon 104) may be between about 5 and 40 nanometers, including all values ​​and ranges therein (e.g., between about 22 and 35 nanometers, or between about 20 and 30 nanometers).

[0059] In some embodiments, the angled transistors described herein may be implemented in a memory array. In some such embodiments, the angled transistor may be coupled to a storage element to form a 1T-1X memory cell of the memory array, wherein the "1T" in the term "1T-1X memory cell" indicates that the memory cell includes one transistor (T), and wherein the "1X" in the term "1T-1X memory cell" indicates that the memory cell includes one storage element (X). In other embodiments, the angled transistor may be coupled to multiple storage elements, or the angled transistor may be coupled to another transistor to form one or more memory cells of the memory array, all of which are within the scope of the present disclosure. In general, a storage element may be any suitable IC component that can be programmed to a target data state (e.g., corresponding to a specific charge stored on the storage element or corresponding to a specific resistance state of the storage element) by applying an electric field or energy (e.g., a positive or negative voltage or current pulse) to the storage element for a specific duration. In various embodiments, the storage element may be a capacitor, a resistive storage element, a resistive random access memory (RRAM) device, a wire memory device, a phase change memory (PCM) device, a magnetic random access memory (MRAM) device, and the like.

[0060] Figure 1 An example of using transistor 110 as part of a memory cell is shown in FIG. 1 , showing that IC device 100 may include memory cell 160, memory cell 160 including transistor 110 electrically coupled to S / D region 114-2 and storage element 166. In various embodiments, storage element 166 may include one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance change material. In some embodiments, storage element 166 may include two electrodes 167-1 and 167-2 separated by a memory material 169. An example of electrodes 167 and memory material 169 of storage element 166 is shown in FIG. Figure 1162, although in other embodiments, the spatial arrangement of the memory material 169 and the electrode 167 may be different, as long as the memory material 169 is spatially located between the electrode 167-1 and the electrode 167-2 (e.g., the memory material 169 need not be a planar layer, but may be arranged in any kind of three-dimensional arrangement). The memory material 169 may be any suitable material that can be brought into a target state by applying an electric field or energy (e.g., a positive or negative voltage or current pulse) to one or both electrodes 167 of the storage element 166 for a specific duration, thereby programming the storage element 166 to a target data state (e.g., corresponding to a specific charge stored on the storage element 166 or corresponding to a specific resistance state of the storage element 166). Such a storage element 166 may be electrically coupled to the S / D region 114-2 by coupling an electrode 167-1 of the storage element 166 to the S / D region 114-2 (e.g., in some embodiments, the electrode 167-1 of the storage element 166 and the contact to the S / D region 114-2 may be a shared contact of a suitable conductive material).

[0061] As an example, a dynamic random access memory (DRAM) cell may include a storage element 166 in the form of a capacitor for storing a bit value or memory state of the cell (e.g., a logical "1" or "0"), and an access transistor implemented as a transistor 110 that controls access to the cell (e.g., access to write information to the cell or access to read information from the cell). Such a memory cell may be referred to as a "1T-1C memory cell," highlighting the fact that it uses one transistor (i.e., the "1T" in the term "1T-1C memory cell") and one capacitor (i.e., the "1C" in the term "1T-1C memory cell"). In such an embodiment, the electrode 167 may be a capacitor electrode, and the memory material 169 may be a capacitor insulator. In some embodiments, the memory material 169 of such a capacitor may be a dielectric material. In other embodiments, the memory material 169 of such a capacitor may be a hysteresis element, for example, as described above with reference to embodiments in which the gate insulator 112 is a hysteresis element.

[0062] In another example, the storage element 166 can be a resistive storage element (also referred to herein as a "resistive switch") that includes a memory material 169 of a resistance-changing material, i.e., during operation, the memory material 169 can switch between two different non-volatile states: a high resistance state (HRS) and a low resistance state (LRS). The state of the resistive storage element can be used to represent a data bit (e.g., a logic "1" for HRS and a logic "0" for LRS, or vice versa). The resistive storage element can have a voltage threshold, above which the resistive storage element is in the LRS; driving the resistive storage element into the LRS can be referred to as setting (with an associated set threshold voltage). Similarly, the resistive storage element can have a voltage threshold, above which the resistive storage element is in the HRS; driving the resistive storage element into the HRS can be referred to as resetting (with an associated reset threshold voltage).

[0063] In another example, the storage element 166 may be a RRAM device; in such an embodiment, the memory material 169 may include an oxygen exchange layer (eg, hafnium) and an oxide layer, as is known in the art.

[0064] In yet another example, the memory element 166 may be a wire memory device (e.g., a conductive bridging random access memory (CBRAM) device); in such an embodiment, the memory material 169 may include a solid electrolyte, and one electrode 167 of the memory element 166 may be an electrochemically active material (e.g., silver or copper), and the other electrode 167 of the memory element 166 may be an inert material (e.g., an inert metal), as known in the art. In some such embodiments, a chemical barrier layer (e.g., tantalum, tantalum nitride, or tungsten) may be disposed between the electrochemically active electrode and the solid electrolyte to mitigate diffusion of the electrochemically active material into the solid electrolyte.

[0065] In some embodiments, storage element 166 may be a PCM device; in such embodiments, memory material 169 may include a chalcogenide or other phase change memory material.

[0066] In some embodiments, the storage element 166 may be an MRAM device; in such embodiments, the memory material 169 may include a thin tunnel barrier material, and the electrode 167 of the storage element 166 may be magnetic (e.g., ferromagnetic). As is known in the art, an MRAM device may operate based on the principle of tunnel magnetoresistance between two magnetic layers (e.g., electrodes of the storage element 166) separated by a tunnel junction (e.g., the memory material of the storage element 166). The MRAM device may have two stable states: when the magnetic moments of the two magnetic layers are aligned parallel to each other, the MRAM device may be in LRS, and when aligned antiparallel, the MRAM device may be in HRS.

[0067] Figure 2 A perspective view of an example IC device 200 implementing a FinFET 210 is provided in accordance with some embodiments. FinFET 210 is another example of an angled transistor that may be included in the various IC devices and components described herein.

[0068] Figure 2 The IC device 200 shown is intended to illustrate the relative arrangement of some of the components, and the IC device 200 or portions thereof may include other components that are not shown. Figure 2 , but a dielectric spacer may be provided between a first S / D contact that may be coupled to a first S / D region 214-1 of the transistor 210 and the gate stack 206 and between a second S / D contact that may be coupled to a second S / D region 214-2 of the transistor 210 and the gate stack 206 to provide electrical isolation between the source, gate, and drain contacts. In another example, although there is no Figure 2 Although not specifically shown in FIG. 2 , at least a portion of transistor 210 may be surrounded by an insulator material, such as any suitable ILD material.

[0069] Steering Figure 2 In detail, the IC device 200 may include a semiconductor material, which may include one or more semiconductor materials, formed into a fin 204 extending away from the support structure 202. By having a gate stack 206 at least partially surrounding a channel portion of the fin 204, and by having source and drain regions on either side of the gate stack 206 ( Figure 2 As shown in FIG. 2 as a first S / D region 214-1 and a second S / D region 214-2, a FinFET 210 may be formed on the basis of the fin 204. Figure 2As shown, the gate stack 206 includes a gate electrode material 208 and a gate insulator 212, each of which completely or nearly completely surrounds a channel portion of the fin 204, although the gate insulator 212 may be absent in other embodiments of the IC device 200. The description provided above with reference to the support structure 102, the gate stack 106, the gate electrode material 108, the gate insulator 112, and the S / D region 114 is applicable to the support structure 202, the gate stack 206, the gate electrode material 208, the gate insulator 212, and the S / D region 214, respectively, and therefore, for the sake of brevity, is not repeated. Figure 2 Also shown is STI 216, which surrounds the sidewalls of sub-fin portion 218 of fin 204. STI 216 can include any of the insulator materials described above, such as any suitable ILD material. The description provided above with reference to the channel material of transistor 110 is applicable to the semiconductor material of at least the channel portion of fin 204 (e.g., the semiconductor material of at least a portion of fin 204 surrounded by gate stack 206), and therefore, for the sake of brevity, it is not repeated.

[0070] The longitudinal axis 220 of the fin 204 can be along the y-axis of the example coordinate system shown in the present figure. The FinFET 210 can have a gate length (i.e., the distance between the first and second S / D regions 214-1, 214-2), a dimension measured along the longitudinal axis 220, which in some embodiments can be between 2 and 60 nanometers, including all values ​​and ranges therein (e.g., between 5 and 20 nanometers, or between 5 and 30 nanometers). Although the fin 204 is Figure 2 204, but the fin 204 may alternatively have a rounded or angled cross-section at the "top" of the fin 204, and the gate stack 206 may conform to the rounded or angled fin 204. In use, the FinFET 210 may form a conductive channel on three "sides" of the fin 204, potentially improving performance relative to single-gate transistors (which may form a conductive channel on one "side" of the channel material or substrate) and dual-gate transistors (which may form a conductive channel on two "sides" of the channel material or substrate). It should be noted that similar to Figure 1 , Figure 2 The xyz coordinate system is shown aligned so that the longitudinal axis 220 is along the y-axis, which is merely for ease of explanation of this particular figure. In other figures, the angled transistors are explained with reference to their longitudinal axes as being somewhere in the xy plane, but not aligned with the y-axis or the x-axis because the edges of the support structures are assumed to be aligned with those axes and the transistors are angled, meaning that they are at an angle between 10 degrees and 80 degrees relative to the y-axis and / or the x-axis. Thus, when FinFET 210 is an angled transistor in any subsequent figure, the longitudinal axis 220 is not aligned with the y-axis, as shown in FIG. Figure 2As shown, instead, they are at an angle between 10 and 80 degrees relative to the y-axis.

[0071] Figure 2 An example of using FinFET 210 as part of a memory cell is shown in FIG. 2 , showing that IC device 200 may include memory cell 260 including FinFET 210 electrically coupled to S / D region 214-2 and storage element 266. In some embodiments, storage element 266 may include two electrodes 267-1 and 267-2 separated by a memory material 269. An example of electrode 267 and memory material 269 of storage element 266 is shown in FIG. Figure 2 262, although in other embodiments, the spatial arrangement of the memory material 269 and the electrode 267 may be different, as long as the memory material 269 is spatially located between the electrode 267-1 and the electrode 267-2 (e.g., the memory material 269 need not be a planar layer, but may be arranged in any kind of three-dimensional arrangement). The description provided above with reference to the memory element 166, the electrode 167, and the memory material 169 applies to the memory element 266, the electrode 267, and the memory material 269, respectively, and therefore, for the sake of brevity, is not repeated.

[0072] Nanoribbon 104 or fin 204 may be an elongated semiconductor structure upon which any angled transistor described herein may be constructed (ie, any angled transistor may be implemented as, for example, transistor 110 or FinFET 210). Figure 3A-3B and Figures 4A-4B The differences between non-angled elongated semiconductor structures and angled elongated semiconductor structures are described. Specifically, Figure 3A-3B An example IC device 300 having a non-angled elongated semiconductor structure 304 is shown in accordance with some embodiments, and Figures 4A-4B An example IC device 300 is shown having an angled elongated semiconductor structure 306. Figure 3A-3B and Figures 4A-4B and in some subsequent figures (e.g., Figures 6A-6F ) are indicated by different patterns in these drawings so as not to confuse the drawings with too many reference numerals. Figure 3A-3B and Figures 4A-4B A legend showing the correspondence between reference numerals and patterns is provided on the right side of FIG. Figure 3A-3B and Figures 4A-4B Different patterns are used to illustrate the support structure 302 , the non-angled elongated semiconductor structure 304 , and the angled elongated semiconductor structure 306 .

[0073] Figure 3A-3B and Figures 4A-4B The IC device 300 shown in FIG. 1 is intended to illustrate the relative arrangement of some of the components, and the IC device 300 or portions thereof may include other components not shown. For example, although not shown in FIG. Figure 3A-3B and Figures 4A-4B 300, but the IC device 300 may include transistors implemented in or based on the elongated semiconductor structures 304, 306, which transistors will include gate stacks, S / D regions and other parts, for example, as described above with reference to Figure 1 and 2 In another example, although there is no Figure 3A-3B and Figures 4A-4B Although not specifically shown in FIG. 3 , at least portions of the elongated semiconductor structures 304 , 306 may be surrounded by an insulator material, such as any suitable ILD material.

[0074] like Figure 3A-3B and Figures 4A-4B As shown, IC device 300 may include support structure 302, which may include four edges 303, respectively shown as edges 303-1, 303-2, 303-3 and 303-4. Edge 303 may be an edge of the front side of support structure 302 or the back side of support structure 302, depending on whether non-angled elongated semiconductor structure 304 and angled elongated semiconductor structure 306 are provided on the front side or the back side of support structure 302. Support structure 302 may be any support structure 102 / 202 described herein. Support structure 302 is rectangular, and therefore, adjacent edges 303 are 90 degrees relative to each other (e.g., edges 303-1 and 303-2 are adjacent and 90 degrees relative to each other, edges 303-2 and 303-3 are adjacent and 90 degrees relative to each other, etc.).

[0075] like Figure 3A-3B As shown, a plurality of parallel non-angled elongated semiconductor structures 304 may be provided on a support structure 302 . Figure 3A-3B The non-angled elongated semiconductor structures 304 shown in FIG. 3 are parallel because their longitudinal axes 320 are parallel to each other (in order not to clutter the drawing, the longitudinal axes 320 are parallel to each other). Figure 3A-3B Only one such longitudinal axis 320 is shown in each of the drawings. Figure 3A-3B The elongated semiconductor structures 304 are shown as "non-angled" because their longitudinal axes 320 are at an angle of 0 or 90 degrees relative to all edges 303 of the support structure 302. Figure 3A In FIG. 1 , the longitudinal axis 320 is at an angle of 0 degrees relative to each of the edges 303-1 and 303-3, and at an angle of 90 degrees relative to each of the edges 303-2 and 303-4, while in FIG. Figure 3B, longitudinal axis 320 is at an angle of 90 degrees relative to each of edges 303-1 and 303-3, and at an angle of 0 degrees relative to each of edges 303-2 and 303-4. One or more transistors (e.g., transistor 110 and / or FinFET 210) may be formed along any and each non-angled elongated semiconductor structure 304, thereby forming a non-angled transistor as described herein.

[0076] like Figures 4A-4B As shown, a plurality of parallel angled elongated semiconductor structures 306 may be provided on a support structure 302 . Figures 4A-4B The angled elongated semiconductor structures 306 shown in FIG. 3 are parallel because their longitudinal axes 320 are parallel to each other (in order not to clutter the drawing, the longitudinal axes 320 are parallel to each other). Figures 4A-4B Only one such vertical axis 320 is shown in each of the Figures. Figures 4A-4B The elongated semiconductor structures 306 are shown as "angled" because their longitudinal axes 320 are at an angle that is neither 0 nor 90 degrees relative to any edge 303 of the support structure 302. Figures 4A-4B In each of the elongated semiconductor structures 306, the longitudinal axis 320 is angled between approximately 10 degrees and 80 degrees relative to each edge 303. One or more transistors (e.g., transistor 110 and / or FinFET 210) may be formed along any and each angled elongated semiconductor structure 306, thereby forming an angled transistor as described herein.

[0077] In various embodiments, both the non-angled elongated semiconductor structure 304 and the angled elongated semiconductor structure 306 may be provided on a single support structure 302, some examples of such embodiments being Figures 5A-5Q Shown in.

[0078] Figures 5A-5Q A schematic diagram of a cross-sectional side view of an example IC device 310 integrating non-angled and angled transistors according to some embodiments is provided. IC device 310 may be Figure 3A-3B The IC device 300 and Figures 4A-4B An example of a combination of IC devices 300 is shown. To this end, Figures 5A-5Q Shown with Figure 3A-3B and Figures 4A-4B The same reference numerals are shown in the Figure 3A-3B and Figures 4A-4B Elements similar or analogous to those described herein, so that Figures 5A-5QThe description of those elements will not be repeated. As described above, each IC device 310 shows a support structure 302 having a first face 312-1 and a second face 312-2 (the second face 312-2 is opposite to the first face 312-1, wherein one face 312 may be the front / side face of the support structure 302 and the other face 312 may be the back / side face of the support structure 302), a layer 314 of non-angled elongated semiconductor structures having at least one non-angled transistor 315 (hereinafter referred to as "non-angled layer 314"), and a layer 316 of angled elongated semiconductor structures having at least one angled transistor 317 (hereinafter referred to as "angled layer 316").

[0079] Figure 5A Details of the non-angled layer 314 and the angled layer 316 are shown. Specifically, Figure 5A The non-angled layer 314 may include reference Figure 3A-3B N non-angled elongated semiconductor structures 304 are depicted, and at least one of the N non-angled elongated semiconductor structures 304 may include a non-angled transistor 315 . Figure 5A It is also shown that the angled layer 316 may include reference Figures 4A-4B The M angled elongated semiconductor structures 306, and at least one of the M angled elongated semiconductor structures 306 may include an angled transistor 317. Each of N and M may be an integer equal to or greater than 1.

[0080] In order not to clutter the drawing, the details of the non-angled layer 314 and the angled layer 316 are only shown in FIG. Figure 5A is shown in, and Figure 5B-5Q Only these layers and one example transistor in each of these layers are shown. Figures 5A-5QOnly one non-angled transistor 315 in the non-angled layer 314 and one angled transistor 317 in the angled layer 316 are shown, but this is only to avoid cluttering the drawing, and in various other embodiments of the IC device 310, any one of the N non-angled elongated semiconductor structures 304 of the non-angled layer 314 may include any number (zero or more) of non-angled transistors 315, and any one of the M angled elongated semiconductor structures 306 of the angled layer 316 may include any number (zero or more) of angled transistors 317. Any non-angled transistor 315 may be formed along any non-angled elongated semiconductor structure 304, for example as a nanoribbon transistor 110 or a FinFET 210 (possibly coupled to a storage element 166 / 266, as described above), and any angled transistor 317 may be formed along any and each angled elongated semiconductor structure 306, for example as a nanoribbon transistor 110 or a FinFET 210 (possibly coupled to a storage element 166 / 266, as described above). Thus, any of non-angled transistor 315 and angled transistor 317 may include a source region (e.g., one of S / D regions 114 / 214), a drain region (e.g., the other of S / D regions 114 / 214), and a channel region (e.g., a portion of nanoribbon 104 or fin 204 surrounded by gate stack 106 / 206) spatially located between a source region and a drain region, as described above, wherein for non-angled transistor 315, the shortest line extending between the source region and the drain region (i.e., longitudinal axis 120 / 220) is substantially parallel to at least one edge 303 of support structure 302, and for angled transistor 317, the shortest line extending between the source region and the drain region (i.e., longitudinal axis 120 / 220) is angled between 10 degrees and 80 degrees relative to the same edge 303 of support structure 302. Edge 303 is not at Figures 5A-5Q 3 and 4, and are Figures 5A-5Q The edge of the first side 312 - 1 or the second side 312 - 2 of the support structure 302 is shown.

[0081] Figure 5A An embodiment is shown in which a non-angled transistor 315 is provided on a first region of a first side 312-1 of a support structure 302, and an angled transistor 317 is provided on a second region of the first side 312-1 of the support structure 302 that does not overlap with the first region (i.e., both the non-angled transistor 315 and the angled transistor 317 are provided side by side with each other on the same side 312-1 or on the same side of the support structure 302).

[0082] exist Figure 5AIn some embodiments of IC device 310, support structure 302 may be a substrate of semiconductor material, or may be a substrate having a surface including a layer of semiconductor material, and transistors 315 and 317 may be monolithically formed on the same surface 312 of support structure 302 such that the channel regions of these transistors include the semiconductor material of support structure 302. Figure 5A In other embodiments of the IC device 310, some of the transistors 315 and 317 may be monolithically formed on the first side 312-1 of the support structure 302, while others may be provided on the same side 312-1 using a layer transfer process, as described above. Figure 5A In other embodiments of the IC device 310, all transistors 315 and 317 may be provided on the same side 312-1 using a layer transfer process. Unless otherwise described, these variations generally apply to Figure 5B-5Q Other embodiments of the IC device 310 are shown with the modification that transistors 315 and 317 need not be as Figure 5A are provided side by side on the same surface, but as shown Figure 5B-5Q Supplied as shown.

[0083] Figure 5B and 5C An embodiment of an IC device 310 is shown in which transistors 315 and 317 are provided on opposite faces 312, for example, non-angled transistor 315 may be provided on first face 312-1, and angled transistor 317 may be provided on second face 312-2. For example, in some embodiments, support structure 302 may be a substrate of semiconductor material, or may be a substrate having a surface of first face 312-1 and a surface of second face 312-2 including a layer of semiconductor material, and non-angled and angled transistors 315, 317 may be monolithically formed on different faces 312 of support structure 302 such that channel regions of these transistors include semiconductor material. Figure 5B and 5C The embodiment of the invention may differ in that the projections of the transistors 315, 317 on the support structure 302 (ie, the footprints of the transistors 315, 317) may be positioned relative to each other. Figure 5B Embodiments are shown in which the projection of angled transistor 317 on support structure 302 completely overlaps or is located within the projection of non-angled transistor 315 on support structure 302, or the projection of non-angled transistor 315 on support structure 302 completely overlaps or is located within the projection of angled transistor 317 on support structure 302. On the other hand, Figure 5CAn embodiment is shown in which the projection of angled transistor 317 on support structure 302 is offset (e.g., does not overlap, or overlaps by less than about 75%, e.g., overlaps by less than about 25%) relative to the projection of non-angled transistor 315 on support structure 302. In some embodiments, Figures 5A-5C Any transistors 315 , 317 of the IC device 310 may be monolithically integrated on the support structure 302 such that the channel regions of these transistors include channel material from different portions of the semiconductor material of the support structure 302 .

[0084] Figure 5D-5O An embodiment of an IC device 310 is shown in which non-angled layers 314 and angled layers 316 are provided on the same side 312 (e.g., first side 312-1) of a support structure 302, stacked on top of each other with a bonding layer 318 and / or a redistribution layer (RDL) 324 therebetween. Such an embodiment may be advantageous in, for example, reducing parasitic effects and / or reducing delays in exchanging signals between transistors and other devices of the non-angled layers 314 and angled layers 316 because there is no support structure 302 between these layers.

[0085] Figure 5D-5I , 5K-5L and 5N-5O show embodiments in which the non-angled transistor 315 is in a first layer above the first side 312-1 of the support structure 302, the angled transistor 317 is in a second layer above the first side 312-1 of the support structure 302 (i.e., the first and second layers are on the same side 312-1 of the support structure 302 and are closer to the first side 312-1 of the support structure 302 than the second side 312-2 of the support structure 302), and the IC device also includes a bonding layer 318 between the first layer and the second layer. Figure 5D-5I , 5K-5L, and 5N-5O IC device 310 may be fabricated by forming a non-angled layer 314 having one or more non-angled transistors 315 on a first IC die, forming an angled layer 316 having one or more angled transistors 317 on a second IC die, and then bonding the two IC dies together using hybrid bonding with a bonding layer 318 therebetween. For example, hybrid fabrication may be used to fabricate Figure 5D-5I, 5K-5L and 5N-5O, wherein a non-angled layer 314 is first formed on a first IC die, an angled layer 316 is formed on a second IC die, and then the two IC dies are bonded together using hybrid manufacturing with a bonding layer 318 therebetween. As used herein, "hybrid manufacturing" refers to the manufacture of an IC device (e.g., a microelectronic assembly) by bonding together at least two IC dies manufactured by different manufacturers, using different materials, or different manufacturing techniques. In some embodiments, the bonding of the faces of the first and second IC dies can be performed using an insulator-insulator bonding (e.g., as an oxide-oxide bonding), wherein the insulating material of the first IC die is bonded to the insulating material of the second IC die. In some embodiments, bonding material 318 can be present between the faces of the first and second IC dies that are bonded together. To this end, bonding material can be applied to one or both faces of the first and second IC dies that should be bonded, and then the first and second IC dies are brought together, possibly while applying appropriate pressure and heating the assembly to an appropriate temperature (e.g., to a moderately high temperature, e.g., between about 50 and 200 degrees Celsius) for a period of time. In some embodiments, the bonding material 318 may be an adhesive material that ensures that the first and second IC dies are attached to each other. In some embodiments, the bonding material 318 may be an etch stop material. In some embodiments, the bonding material 318 may be both an etch stop material and have suitable adhesive properties to ensure that the first and second IC dies are attached to each other. In some embodiments, the bonding material 318 may include silicon, nitrogen, and carbon, wherein the atomic percentage of any of these materials may be at least 1%, for example, between about 1% and 50%, indicating that these elements are intentionally added as opposed to accidental impurities with concentrations typically below about 0.1%. Both nitrogen and carbon having these concentrations in addition to silicon are typically not used in conventional semiconductor manufacturing processes, in which nitrogen or carbon is typically used in combination with silicon, and therefore, this may be a characteristic feature of hybrid bonding. Using an etch stop material (wherein the atomic percentage of any of these materials may be at least 1%, for example, SiOCN) at an interface including silicon, nitrogen, and carbon (i.e., the interface between the first and second IC dies) may be advantageous because such a material may both act as an etch stop material and have sufficient adhesive properties to bond the first and second IC dies together. In addition, an etch stop material including silicon, nitrogen, and carbon at the interface between the first and second IC dies, where the atomic percentage of any of these materials may be at least 1%, may be advantageous in improving the etch selectivity of the material relative to an etch stop material that may be used in different first and second IC dies. In some embodiments, bonding material 318 may not be used, but there is still a bonding interface created by bonding the first and second IC dies to each other.Using, for example, selective area diffraction (SED), such a bonding interface may be identifiable as a seam or thin layer in the microelectronic assembly, even when the particular material of the insulator of the first and second IC dies bonded together may be the same, in which case the bonding interface will still be noticed as a seam or thin layer that would otherwise appear as a bulk insulator (e.g., bulk oxide) layer.

[0086] Figure 5D-5I The differences between the embodiments of 5K-5L and 5N-5O lie in whether the non-angled transistor 315 or the angled transistor 317 is at the bottom of the stack (i.e., closer to the support structure 302), and whether the bond is a face-to-face (F2F) bond or a face-to-back (F2B) bond between the non-angled layer 314 and the angled layer 316.

[0087] Figure 5D-5F and Figure 5K-5L It is shown that angled layer 316 and therefore angled transistor 317 may be at the bottom of the stack (ie, closer to first face 312 - 1 of support structure 302 than non-angled layer 314 and therefore non-angled transistor 315 ).

[0088] Figure 5D An embodiment is shown where the bonding layer 318 may be located between and in contact with each of the angled layer 316 at the bottom of the bonding layer 318 and the non-angled layer 314 at the top of the bonding layer 318 .

[0089] Figure 5EAn embodiment is shown in which a metallization stack 322 may be present between the bonding layer 318 and the non-angled layer 314 (e.g., in contact with each of them). As is known in the art, a metallization stack refers to a collection or levels of several levels in which conductive lines are provided and conductive vias provide electrical connectivity between conductive lines of different layers. Conductive lines and vias together may be referred to as "interconnects," wherein the term "interconnect" may be used to describe any element formed of a conductive material for providing electrical connectivity to one or more components associated with an IC and / or between various such components. In the context of an IC die / chip, the term "interconnect" may refer to both wires / conductors (sometimes also referred to as "wires" or "metal lines" or "trench") and conductive vias (sometimes also referred to as "vias" or "metal vias"). In general, the term "conductive line" may be used to describe a conductive element isolated by a dielectric material, which typically includes an interlayer low-k dielectric provided within the plane of the IC die / chip. On the other hand, the term "conductive via" may be used to describe a conductive element that interconnects two or more conductive lines of different levels of a metallization stack. To this end, a through hole can be provided that is substantially perpendicular to the plane of the IC die / chip or a support structure on which the IC structure is provided, and the through hole can interconnect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels. Sometimes, metal lines and through holes may be referred to as "conductive lines / traces" and "conductive vias", respectively, to emphasize the fact that these elements include conductive materials (such as but not limited to metals). The metallization stack is typically provided in the back end of the line (BEOL) layer of the IC die, that is, in a layer farther away from the die than the front end of the line (FEOL) layer that implements the front end transistors. Thus, the presence of metallization stack 322 between bonding layer 318 and non-angled layer 314 and bonding layer 318 between metallization stack 322 and angled layer 316 may indicate that metallization stack 322 was initially (i.e., prior to bonding) part of a first IC die that included non-angled layer 314, metallization stack 322 was initially on top of non-angled layer 314, wherein the first IC die was then bonded face-down to the front side of a second IC die that included angled layer 316. In other words, Figure 5E An embodiment of a F2F bond between non-angled layer 314 and angled layer 316 is shown, where angled layer 316 is located at the bottom (ie, closer to support structure 302).

[0090] Fig. 5FAn embodiment is shown in which the non-angled layer 314 is located between (e.g., in contact with each of) the bonding layer 318 and the metallization stack 322. The presence of the non-angled layer 314 between the bonding layer 318 and the metallization stack 322 may indicate that the metallization stack 322 was originally (i.e., before bonding) part of a first IC die including the non-angled layer 314, with the metallization stack 322 on top of the non-angled layer 314, wherein the first IC die was then bonded backside down to the front side of a second IC die including the angled layer 316. In other words, Fig. 5F An embodiment of a F2B bond between an angled layer 316 and a non-angled layer 314 is shown, wherein the angled layer 316 is located at the bottom (i.e., closer to the support structure 302). This can be performed as follows. Once the non-angled layer 314 is formed on the first IC die, and the metallization stack 322 is formed on the non-angled layer 314, a carrier substrate can be attached to the top of the first IC die (e.g., the carrier substrate can be attached so that the metallization stack 322 is between the non-angled layer 314 and the carrier substrate). Such a carrier substrate can be any support structure capable of providing mechanical stability for the non-angled layer 314 and the metallization stack 322. The first IC die can then be flipped (i.e., the carrier substrate is placed at the bottom for further processing) so that the first IC die can be thinned (e.g., gradually removed) from the back side, for example, until the non-angled layer 314 is exposed. At this point, the carrier substrate can provide mechanical stability for the arrangement. Such a first IC die with the non-angled layer 314 exposed from the back side of the first IC die may then be bonded to the front side of a second IC die (eg, bonded to the angled layer 316 ).

[0091] Figure 5G-5I and Figure 5N-5O It is shown that non-angled layer 314 and therefore non-angled transistor 315 may be at the bottom of the stack (ie, closer to first face 312 - 1 of support structure 302 than angled layer 316 and therefore angled transistor 317 ).

[0092] Figure 5G An embodiment is shown in which the bonding layer 318 can be located between and in contact with each of the non-angled layer 314 at the bottom of the bonding layer 318 and the angled layer 316 at the top (ie, Figure 5G Similar to Figure 5D , but the top and bottom layers are inverted relative to the bonding layer 318).

[0093] Figure 5HAn embodiment is shown in which a metallization stack 322 may be present between (e.g., in contact with each of) the bonding layer 318 and the angled layer 314. The presence of the metallization stack 322 between the bonding layer 318 and the angled layer 316 and the bonding layer 318 between the metallization stack 322 and the non-angled layer 314 may indicate that the metallization stack 322 was initially (i.e., prior to bonding) a part of the second IC die including the angled layer 316, the metallization stack 322 was initially on top of the angled layer 316, wherein the second IC die was then bonded face-down to the front side of the first IC die including the non-angled layer 314. In other words, Figure 5H An embodiment of a F2F bond between non-angled layer 314 and angled layer 316 is shown, wherein non-angled layer 314 is located at the bottom (ie, closer to support structure 302).

[0094] Fig.5I An embodiment is shown in which the angled layer 316 is located between the bonding layer 318 and the metallization stack 322 (e.g., in contact with each of them). The presence of the angled layer 316 between the bonding layer 318 and the metallization stack 322 can indicate that the metallization stack 322 was originally (i.e., before bonding) a part of the second IC die including the angled layer 316, the metallization stack 322 being on top of the angled layer 316, wherein the second IC die is then bonded backside down to the front side of the first IC die including the non-angled layer 314. In other words, Fig.5I An embodiment of a F2B bond between an angled layer 316 and a non-angled layer 314 is shown, wherein the non-angled layer 314 is located at the bottom (i.e., closer to the support structure 302). This can be done as follows. Once the angled layer 316 is formed on the second IC die, and the metallization stack 322 is formed on the angled layer 316, a carrier substrate can be attached to the top of the second IC die (e.g., the carrier substrate can be attached so that the metallization stack 322 is between the angled layer 316 and the carrier substrate). Such a carrier substrate can be any support structure capable of providing mechanical stability for the angled layer 316 and the metallization stack 322. The second IC die can then be flipped (i.e., the carrier substrate is placed at the bottom for further processing) so that the second IC die can be thinned (e.g., gradually removed) from the back side, for example, thinned until the angled layer 316 is exposed. At this point, the carrier substrate can provide mechanical stability for the arrangement. Such a second IC die with the angled layer 316 exposed from the back side of the second IC die may then be bonded to the front side of the first IC die (eg, bonded to the non-angled layer 314 ).

[0095] Figure 5J-5O An embodiment is shown, in which, similar to Figure 5D-5I, there is no support structure 302 between the non-angled layer 314 and the angled layer 316, but there is an RDL 324 between them.

[0096] Figure 5J An embodiment is shown in which an RDL 324 can be located between and in contact with each of an angled layer 316 at the bottom of the RDL 324 and a non-angled layer 314 at the top of the RDL 324. The RDL 324 can be similar to the bonding layer 318 in that it can provide a means for mechanically attaching the angled layer 316 and the non-angled layer 314 together. However, in addition to mechanical stability, as the name "RDL" implies, it includes interconnects that provide electrical connectivity between IC components of the angled layer 316 (angled transistor 317 is a non-limiting example of such an IC component) and IC components of the non-angled layer 314 (non-angled transistor 315 is a non-limiting example of such an IC component). To this end, the RDL 324 can include any interconnect arrangement (i.e., conductive vias and / or conductive lines) configured to provide such electrical connectivity. In some embodiments, the RDL 324 can be implemented using staggered via formation, as described below with reference to FIG. 9.

[0097] Figure 5K Shows something like Figure 5E The embodiment of the IC device 310 is shown, except that it also includes an RDL 324 between (eg, in contact with each of) the angled layer 316 and the bonding layer 318, so that the bonding layer 318 is now between (eg, in contact with each of) the RDL 324 and the metallization stack 322.

[0098] Figure 5L Shows something like Fig. 5F An embodiment of the IC device 310 is shown, except that it also includes an RDL 324 between the angled layer 316 and the bonding layer 318 (e.g., in contact with each of them), so that the bonding layer 318 is now between the RDL 324 and the non-angled layer 314 (e.g., in contact with each of them).

[0099] Figure 5M An embodiment is shown where the RDL 324 may be located between and in contact with each of the non-angled layer 314 at the bottom of the RDL 324 and the angled layer 316 at the top of the RDL 324 .

[0100] Figure 5N Shows something like Figure 5HAn embodiment of the IC device 310 is shown, except that it also includes an RDL 324 between the non-angled layer 314 and the bonding layer 318 (e.g., in contact with each of them), so the bonding layer 318 is now between the RDL 324 and the metallization stack 322 (e.g., in contact with each of them).

[0101] Fig.5O Shows something like Fig.5I An embodiment of the IC device 310 is shown, except that it also includes an RDL 324 between (eg, in contact with each of) the non-angled layer 314 and the bonding layer 318, so that the bonding layer 318 is now between (eg, in contact with each of) the RDL 324 and the angled layer 316.

[0102] Figure 5P and 5Q An embodiment of an IC device 310 is shown in which transistors 315 and 317 are provided on the same side 312 of the support structure 302 (eg, on the first side 312-1), but some may be nested within others. Specifically, Figure 5P An embodiment is shown in which the angled transistor 317 is one of a plurality of angled transistors 317 provided on the first side 312-1 of the support structure 302, and the non-angled transistor 315 is nested between the plurality of angled transistors 317. On the other hand, Figure 5Q An embodiment is shown in which the non-angled transistor 315 is one of a plurality of non-angled transistors 315 provided on the first side 312-1 of the support structure 302, and the angled transistor 317 is nested between the plurality of non-angled transistors 315. In some embodiments, Figure 5P and 5Q Any transistors 315 , 317 of the IC device 310 may be monolithically integrated on the support structure 302 such that the channel regions of these transistors include channel material from different portions of the semiconductor material of the support structure 302 .

[0103] Figures 6A-6F A top view of an example IC device 324 having an angled elongated semiconductor structure 306 patterned according to different patterning techniques is provided in accordance with some embodiments. Figures 6A-6F Chinese Figures 4A-4B The same designations are used to indicate the same elements and to indicate the same Figures 4A-4B The angled elongated semiconductor structure 306 provides a description applicable to Figures 6A-6F , and vice versa. The general outline of the support structure 302 is Figures 6A-6F3 and 4, and some longitudinal axes 320 are shown in dashed lines. Figures 6A-6F 3 and 4 are also shown in a manner similar to how they are shown in FIGS. 3 and 4 .

[0104] Figures 6A-6F The IC device 324 shown in FIG. 1 is intended to illustrate the relative arrangement of some of the components, and the IC device 300 or portions thereof may include other components not shown. For example, although not shown in FIG. Figures 6A-6F As specifically shown in FIG. 1 , the IC device 324 may include a transistor implemented in or based on the angled elongated semiconductor structure 306, which transistor may include a gate stack, S / D regions, and other parts, such as those described above with reference to FIG. Figure 1 and 2 In another example, although there is no Figures 6A-6F 3. Although not specifically shown in FIG. 3, at least a portion of the angled elongated semiconductor structure 306 may be surrounded by an insulator material, such as any suitable ILD material. Figures 6A-6F The angled elongated semiconductor structure 306 shown in the figure can be part of any IC device 310 described with reference to FIG5 (for example, any transistor 317 shown in FIG5 can be implemented based on any angled elongated semiconductor structure 306 shown in FIG6), even if the integration of the angled elongated semiconductor structure 306 and the non-angled elongated semiconductor structure 304 explained with reference to FIG5 is not shown in FIG6.

[0105] In various embodiments, the angled elongated semiconductor structures 306 may be fabricated by first forming a longer angled elongated semiconductor structure of a suitable semiconductor material, and then cutting and / or trimming the longer structure to form the various angled elongated semiconductor structures 306 described herein. For example, Figures 6A-6F Each of the two angled elongated semiconductor structures 306 is shown formed from a single longer angled elongated semiconductor structure, an example of which is shown in FIG. Fig. 6A One of the pairs of angled elongated semiconductor structures 306 is identified within the dashed outline 323 in FIG. Fig. 6A As shown, two angled elongated semiconductor structures 306 may be formed from a single longer angled elongated semiconductor structure by providing a cut 325, such as using a cut line 330, thereby forming a pair of angled elongated semiconductor structures 306 having a shared longitudinal axis 320 (for the pair of angled elongated semiconductor structures 306, the longitudinal axis 320 is at Fig. 6A 3, but for two similar pairs of angled elongated semiconductor structures 306, the longitudinal axis 320 is at Fig. 6A2 as the first longitudinal axis 320-1 and the second longitudinal axis 320-2). In various embodiments, the patterning of the cut line pattern can be performed by using one or more cut line patterns (e.g., Figures 6A-6D ), using one or more cut through hole patterns (e.g., Fig. 6E ), or patterning using one or more cutting line patterns and one or more cutting through-hole patterns (e.g., Fig. 6F 306. In general, using a cut line or cut via to separate a semiconductor structure into two parts refers to providing a line or via filled with an insulator material (e.g., any ILD material described above, or leaving an opening as a gap) to electrically isolate two parts of what was previously a continuous semiconductor structure.

[0106] Details of the steering line patterning, Fig. 6A A first pair of angled elongated semiconductor structures 306-1 and 306-2 sharing a single longitudinal axis 320-1 and a second pair of angled elongated semiconductor structures 306-3 and 306-4 sharing a single longitudinal axis 320-2 are shown. Fig. 6A Other pairs of angled elongated semiconductor structures 306 are shown in FIG. 3 but are not labeled to avoid cluttering the drawing. A longitudinal axis is referred to as being shared between a pair of angled elongated semiconductor structures 306 when a single longitudinal axis 320 of one structure 306 of the pair of structures 306 will overlap with a single longitudinal axis 320 of the other structure 306 of the pair of structures 306. Fig. 6A As shown, different pairs of longitudinal axes 320 are parallel to each other and each is angled between 10 and 80 degrees relative to an edge of support structure 302 (e.g., edge 303-1). Fig. 6A , a first end 328-1 and a second end 328-2 may be defined for each angled elongated semiconductor structure 306, where by way of example, two pairs of ends 328 are labeled for each of the structures 306-1 and 306-2. The ends 328 may be defined such that for each structure 306, the first end 328-1 is closer to the bottom of the drawing than the second end 328-2. Thus, for each pair of structures 306, the first end 328-1 of one structure 306 is opposite or facing the second end 328-2 of the other structure 306.

[0107] Fig. 6A The patterning using a single cut line 330 is shown because Fig. 6A All first ends 328-1 of the structure 306 shown in the upper portion are along a single line 332-1, and Fig. 6AAll of the second ends 328-2 of the structures 306 shown in the lower portion are along a single line 332-2 that is parallel to line 332-1. Thus, lines 332-1 and 332-2 illustrate the boundaries (sidewalls) of a cut line 330 that is used to cut through a longer angled elongated semiconductor structure (such as the semiconductor structure shown within outline 323) to form pairs 306. As a result of using this line patterning, each of the projections of the first end 328-1 of the first angled structure 306-1 and the projections of the second end 328-2 of the second angled structure 306-2 onto a plane parallel to the support structure 302 is a straight line, each of the projections of the first end 328-1 of the third angled structure 306-3 and the projections of the second end 328-2 of the fourth angled structure 306-4 is a straight line, and so on.

[0108] Fig. 6A The illustrated IC device 324 shows a relatively straightforward implementation in which a single cut line 330 is used for pattern cutting to form all pairs of angled elongated semiconductor structures 306. Fig. 6A , Figure 6B Patterning using cut lines is shown, but different cut lines 330 are used to form different pairs of angled elongated semiconductor structures 306. For example, a first cut line 330-1 may be defined by the boundaries of lines 332-11 and 332-21, a second cut line 330-2 may be defined by the boundaries of lines 332-12 and 332-22, and a third cut line 330-3 may be defined by the boundaries of lines 332-13 and 332-23, as shown in FIG. Figure 6B In order not to confuse the drawings, Figure 6B The end 328 and the longitudinal axis 332 are not specifically shown in FIG. 1 , but other than the differences described, the Fig. 6A The description of the end 328 and the shaft 332 provided is applicable to Figure 6B .

[0109] Depend on Fig. 6A and Figure 6B The one or more cutting lines 330 defined by the boundary of the pair of lines 332-1 and 332-2 shown in FIG. 1 all have the same width (e.g., for Figure 6A-6B As shown in FIG. 3 , the distance between the different cutting lines 330 is the same as that between the lines 332-1 and 332-2. Figure 6C As shown, this is not necessarily the case. Figure 6B , Figure 6C The patterning using different cut lines 330 is shown to form different pairs of angled elongated semiconductor structures 306, but different from Figure 6B, the width of the cutting line 330 is different. For example, the first cutting line 330-1 may be defined by the boundary of the lines 332-11 and 332-21, the second cutting line 330-2 may be defined by the boundary of the lines 332-12 and 332-22, and the third cutting line 330-3 may be defined by the boundary of the lines 332-13 and 332-23. Figure 6C As shown, it is similar to Figure 6B .and Figure 6B The difference is that the distance between lines 332-11 and 332-21 is different from the distance between lines 332-12 and 332-22 and the distance between lines 332-13 and 332-23. Figure 6B The end 328 and the longitudinal axis 332 are not specifically shown in FIG. 1 , but other than the differences described, the Fig. 6A The description of the end 328 and the shaft 332 provided is applicable to Figure 6B .

[0110] Figures 6A-6C An embodiment is shown in which one or more cutting lines 330 used to cut the longer angled elongated semiconductor structure to form the pair of angled elongated semiconductor structures 306 are substantially parallel to one edge 303 of the support structure 302 (e.g., parallel to edges 303-1 and 303-3). However, in other embodiments, this may be different, i.e., one or more cutting lines 330 used to cut any longer angled elongated semiconductor structure to form a pair of angled elongated semiconductor structures 306 may be at an angle other than 0 or 90 degrees relative to any edge 303. An example of this is shown in FIG. Fig.6D , a first cut line 330-1 and a second cut line 330-2 are shown, each of which is at an angle between 0 and 90 degrees relative to the edges 303-1 and 303-3, i.e., such cut lines 330 are angled cut lines. The use of angled cut lines 330 can result in unique shapes of the ends 328 of the respective angled elongated semiconductor structures 306. For example, as shown for the angled elongated semiconductor structure 306-1, its first end 328-1 is aligned with the angled cut line 330-1 and is therefore angled relative to the edge 303 in the same manner as the cut line 330-1 is angled, but its second end 328-2 can still be parallel to the edges 303-1 and 303-3. For Fig.6D The other angled elongated semiconductor structures 306 shown in , illustrate the same situation.

[0111] In addition to using cutting lines 330, in some embodiments, cutting through holes 340 may be used, e.g. Fig. 6EAs shown. Three example cut vias 340-1, 340-2, and 340-3 are shown, each having a substantially elliptical top-down (i.e., cross-section of the via) shape, but in other embodiments, the shape may be circular, square, rectangular, or any other polygon, possibly with rounded corners. The use of cut vias 340 may result in unique shapes for the ends 328 of each of the angled elongated semiconductor structures 306. For example, as shown for angled elongated semiconductor structure 306-1, its first end 328-1 is aligned with cut via 330-1 and is therefore curved in the same manner as the boundary of cut via 340-1 is curved, but its second end 328-2 may still be parallel to edges 303-1 and 303-3. For Fig. 6E The other angled elongated semiconductor structures 306 shown in FIG. 3 show the same situation. It should be noted that Fig. 6E The cutting holes 340 shown in FIG. 3 are angled in that their axes 342-1 and 342-2 (labeled for cutting hole 340-1 as an example) are not parallel or perpendicular to any edge 303. However, in other embodiments, the axes 342 of at least some of the cutting holes 340 may be aligned with some of the edges 303 (not specifically shown in this figure).

[0112] Figures 6A-6E The cut lines 330 and cut through holes 340 shown in FIG. 3 provide some examples of how patterning may be performed to perform cutting to separate the longer angled elongated semiconductor structure into the pair of angled elongated semiconductor structures 306, 306. In various embodiments, any number of cut lines 330 and any number of cut through holes 340 may be used alone or in combination to perform such patterning. Fig. 6F An example of using a cut line 330 and a cut via 340 in combination in a single IC device 324 is shown, wherein angled elongated semiconductor structures 306-1 and 306-2 are formed by cutting using the cut via 340, and angled elongated semiconductor structures 306-3 and 306-4 are formed by cutting using the cut line 330. The description of the cut line 330 and the cut via 340 provided above is applicable to Fig. 6F The IC device 324 is described above and therefore will not be repeated for the sake of brevity.

[0113] The IC devices with angled transistors disclosed herein can be manufactured using any suitable technique. For example, Figures 7A-7G A top view of the results of various processes of a ring trimming method for fabricating an IC device having an angled elongated semiconductor structure according to some embodiments is provided (wherein Figures 8A-8F Provides the ability to use Figures 7A-7G Some alternative arrangements of the method implementation) and Figures 9A-9DTop views of various processes of a staggered via formation method for fabricating an IC device incorporating angled elongated semiconductor structures (eg, which may be fabricated according to any embodiment of the method of FIG. 7 , with possible variations of FIG. 8 ) are provided in accordance with some embodiments.

[0114] The IC devices shown in FIGS. 7-9 are intended to illustrate the relative arrangement of some of the components, and these IC devices or portions thereof may include other components that are not shown. For example, although not specifically shown in FIGS. 7-9, the IC devices shown in these figures may include transistors implemented in or based on the angled elongated semiconductor structures shown, and these transistors will include gate stacks, S / D regions, and other parts, such as those described above with reference to Figure 1 and 2 7-9 . In another example, although not specifically shown in FIGS. 7-9 , at least a portion of the angled elongated semiconductor structure or a portion of other elements shown in FIGS. 7-9 may be surrounded by an insulator material, such as any suitable ILD material. The angled elongated semiconductor structure shown in FIGS. 7-9 may be part of any IC device 310 described with reference to FIG. 5 (e.g., any transistor 317 shown in FIG. 5 may be implemented based on any angled elongated semiconductor structure shown in FIGS. 7-9 ), even though the integration of the angled elongated semiconductor structure with the non-angled elongated semiconductor structure explained with reference to FIG. 5 is not shown in FIGS. 7-9 .

[0115] Although the operations of the manufacturing method shown in Figures 7 and 9 are shown one at a time and in a particular order, these operations may be performed in any suitable order and may be repeated as desired. For example, the operations may be performed in a different order to reflect the structure of the IC device in which the angled transistor will be included. In addition, the example manufacturing method shown in Figures 7 and 9 may include other operations not specifically shown in the drawings, such as various cleaning or planarization operations known in the art. For example, in some embodiments, the support structure and the layers of various other materials subsequently deposited thereon may be cleaned before, after, or during any process of the manufacturing method shown in Figures 7 and 9, such as to remove oxides, surface-bound organic and metallic contaminants, and subsurface contaminants. In some embodiments, cleaning may be performed using, for example, a chemical solution (e.g., peroxide), and / or ultraviolet (UV) radiation combined with ozone, and / or oxidizing the surface (e.g., using thermal oxidation) and then removing the oxide (e.g., using hydrofluoric acid (HF)). In another example, the arrangement / device described herein may be planarized before, after, or during any process of the manufacturing method shown in Figures 7 and 9 described herein, such as to remove an overlying layer or excess material. In some embodiments, planarization may be performed using a wet or dry planarization process, for example, chemical mechanical planarization (CMP), which may be understood as a process utilizing a polishing surface, abrasives, and slurries to remove overlying layers and planarize a surface.

[0116] Fig. 7A An IC device 350A is shown, showing that the ring trimming method can begin by providing a support structure 302 (shown as a dashed rectangular outline) having an edge 303 as described above, and providing an angled elongated structure 352 of a backbone material 354 (at Fig. 7A Only one structure 352 is marked in Fig. 7A All other structures 352 of the ring trimming method show the same pattern). The angled elongated structures 352 of the backbone material 354 can be provided using any suitable patterning technique, such as, but not limited to, photolithography or electron beam (e-beam) patterning, possibly in combination with a suitable etching technique, for example, dry etching, such as radio frequency (RF) reactive ion etching (RIE) or inductively coupled plasma (ICP) RIE. In some embodiments, the etching performed in the ring trimming method may include anisotropic etching, using, for example, an etchant in the form of a chemically active ionized gas (i.e., plasma) using, for example, bromine (Br) and chlorine (Cl) based chemicals. In some embodiments, during etching in the ring trimming method, the IC structure may be heated to an elevated temperature, for example, to a temperature between approximately room temperature and 200 degrees Celsius, including all values ​​and ranges therein, to cause the byproducts of the etching to become sufficiently volatile to be removed from the surface. As Fig. 7AAs shown, a first alignment line 356-1 and a second alignment line 356-2 can be defined so that a first end 358-1 of the angled elongated structure 352 of the trunk material 354 can be aligned with the first alignment line 356-1, and a second end 358-2 of the angled elongated structure 352 of the trunk material 354 can be aligned with the second alignment line 356-2.

[0117] Figure 7B An IC device 350B is shown that is substantially identical to IC device 350A (although not shown in the figure to avoid cluttering the drawing). Figure 7B Repeat again Fig. 7A ), showing that the ring trimming method can continue to deposit a liner 360 on the sidewalls of the angled elongated structure 352 of the trunk material 354. The liner 360 can be deposited on the sidewalls using any suitable conformal deposition technique, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) and / or physical vapor deposition (PVD) process (e.g., sputtering). As a result of the conformal deposition, the thickness of the liner 360 can be substantially the same along the sidewalls of the angled elongated structure 352 of the trunk material 354. This means that a new first end 362-1 can be defined as the first end 358-1 of the angled elongated structure 352 of the trunk material 354 with the liner 360 thereon, and a new second end 362-2 can be defined as the second end 362-2 of the angled elongated structure 352 of the trunk material 354 with the liner 360 thereon. Similar to the first end 358-1, the new first end 362-1 can still be aligned, but is now aligned with the first alignment line 364-1 (the first alignment line 364-1 is the first alignment line 356-1 moved a distance corresponding to the thickness of the pad 360), and the new second end 362-2 can still be aligned, but is now aligned with the second alignment line 364-2 (the second alignment line 364-2 is the second alignment line 356-2 moved a distance corresponding to the thickness of the pad 360).

[0118] Figure 7C An IC device 350C is shown that is substantially identical to IC device 350B (although not shown in the figure to avoid cluttering the drawing). Figure 7C Repeat Figure 7A-7B), showing that the ring trimming method can continue to remove the trunk material 354, leaving only the liner 360 previously deposited on the sidewalls of the angled elongated structure 352 of the trunk material 354. Assuming that the trunk material 354 and the liner 360 have sufficient etch selectivity, this removal of the trunk material 354 without substantially removing the liner 360 can be performed using a selective etch. As is known in the art, two materials are said to have "sufficient etch selectivity" when the etchant used to etch one material does not substantially etch the other material, thereby enabling selective etching of one material without etching the other material. Any suitable anisotropic or isotropic etching technique can be used to selectively remove the trunk material 354. If the etchant prefers to remove material in one direction rather than in all directions, the etch is described as "anisotropic", while if the etchant can remove material by etching the material in different directions, the etch is described as "isotropic". Dry etching is an example of an anisotropic etch, while wet etching is an example of an isotropic etch.

[0119] Fig.7D An IC device 350D is shown that is substantially identical to IC device 350C (although not shown in the figure to avoid cluttering the drawing). Fig.7D Repeat again Figures 7A-7C ), showing that the ring trimming method can then continue to use the pattern of the pad 360 of the IC device 350C as an etch mask to perform an anisotropic etch (e.g., dry etch) to remove the semiconductor material of the support structure 302 not covered by the etch mask, thereby forming an angled elongated semiconductor structure 366 having a shape corresponding to the pad 360. Subsequently, when the pad 360 has served its purpose, the pad 360 can be removed, leaving only the angled elongated semiconductor structure 366, as shown in FIG. Fig.7D As described above, this manufacturing method may be used when the semiconductor material of support structure 302 is used as the channel material of a future angled transistor, and angled elongated semiconductor structure 366 is used as a basis for forming angled elongated semiconductor structure 306 through monolithic integration.

[0120] The substantially straight portion of the angled elongated semiconductor structure 366 of the IC device 350D can then be used as an angled elongated semiconductor structure that can be patterned to form an angled transistor as described above. However, it is not desirable to have loops at the first end 362-1 and the second end 362-2 of the angled elongated semiconductor structure 366. Therefore, Fig. 7E An IC device 350E is shown that is substantially identical to IC device 350D (although not shown in the figure to avoid cluttering the drawing). Fig. 7E Repeat again Figures 7A-7D), showing that the ring trimming method can then continue to provide a first cut line 368-1 and a second cut line 368-2 to electrically isolate the ring of the angled elongated semiconductor structure 366 at the first end 362-1 and the second end 362-2 from the straight portion of the angled elongated semiconductor structure 366 (i.e., the portion between the ring at the first end 362-1 and the second end 362-2). Specifically, the first cut line 368-1 can be used to electrically isolate some (e.g., all) of the ring portions of the first end 362-1 of the angled elongated semiconductor structure 366, while the second cut line 368-2 can be used to electrically isolate some (e.g., all) of the ring portions of the first end 362-1 of the angled elongated semiconductor structure 366, leaving a substantially straight portion 367 of the angled elongated semiconductor structure 366 between the cut lines 368-1 and 368-2. Fig. 7E 303-2 and 303-4, and substantially perpendicular to edges 303-1 and 303-3. Similarly, in some embodiments, second cut line 368-2 may be substantially parallel to edges 303-1 and 303-3, and substantially perpendicular to edges 303-2 and 303-4. Similar to the cut line 330 described above, the cut line 368 may be filled with any suitable insulator material to provide electrical isolation of the ring from the substantially straight portion 367 of the angled elongated semiconductor structure 366.

[0121] Multiple U-shaped loop portions of semiconductor material that are substantially the same as the substantially straight portion 367 of the angled elongated semiconductor structure 366 at the first end 362-1 and similar multiple U-shaped loop portions at the second end 362-2 will be detectable in the final structure because the U-shaped portions of semiconductor material are not electrically connected to anything and are simply retained in the final device as a result of using the loop trimming methods described herein. Therefore, in some embodiments, these U-shaped portions of semiconductor material can be surrounded by insulator material on all sides.

[0122] As Figures 7A-7EAs a result of the patterning, if the substantially straight portion 367 of the angled elongated semiconductor structure 366 between the first end 362-1 and the second end 362-2 is a fin extending away from the support structure 302, the U-shaped portion will also extend away from the support structure 302 in a similar manner and to the same height. On the other hand, if the substantially straight portion 367 of the angled elongated semiconductor structure 366 between the first end 362-1 and the second end 362-2 is a nanoribbon provided on the support structure 302, the U-shaped portion will be in the same layer as the nanoribbon, also provided on the support structure 302 in a similar manner, and may have the same insulator material as the nanoribbon between them and the support structure 302.

[0123] In some embodiments, the dimension of such a U-shaped loop portion at the first end 362-1 or at the second end 362-2 in the longitudinal direction of the angled elongated semiconductor structure 366 (e.g., the longitudinal axis 320 described above) will be at most 10% of the length of the substantially straight portion 367 of the angled elongated semiconductor structure 366 between the first end 362-1 and the second end 362-2. The projection of the U-shaped loop portion of semiconductor material onto the support structure 302 may be a curve, which will be very different from a similar projection of the substantially straight portion 367 of the angled elongated semiconductor structure 366 between the first end 362-1 and the second end 362-2 (which will be a rectangle). In some embodiments, the width of any cut line 368 may be between about 3 nanometers and 1000 nanometers, for example, between about 5 nanometers and 100 nanometers, or between about 10 nanometers and 75 nanometers.

[0124] The substantially straight portion 367 of the angled elongated semiconductor structure 366 between the first end 362-1 and the second end 362-2 may then be patterned according to various patterning techniques, for example, as described with reference to Figures 6A-6F The substantially straight portion 367 of the angled elongated semiconductor structure 366 described (eg, between the first end 362-1 and the second end 362-2) may be Figures 6A-6F The longer angled elongated semiconductor structure is used as a starting point in the patterning of to produce the individual angled elongated semiconductor structures 306 described herein).

[0125] In the ring trimming method described above, the backbone material 354 may include any material having sufficient etch selectivity relative to the liner 360, for example, any of the spacer materials described herein. The liner 360 may be any material capable of being used as an etch mask to etch the semiconductor material of the underlying support structure 302, i.e., the liner 360 may include any material having sufficient etch selectivity relative to the semiconductor material of the support structure 302, for example, a material including silicon and nitrogen (e.g., silicon nitride), or any other suitable material. Further variations of the above-described ring trimming method are possible and are described in detail below. Figure 7F and 7G In these alternative embodiments, the backbone material 354 and the liner 360 may be selected differently than described above, depending on which variation of the ring trimming method is being implemented.

[0126] Figure 7F Shown with Figure 7C The IC device 350C shown is substantially the same as the IC device 350F except that it has been further processed to form cut lines 368-1 and 368-2, as shown in reference Fig. 7E Such an embodiment may be used if the pad 360 is already a semiconductor material based on which an angled transistor may be formed. Thus, in such an embodiment, the substantially straight portion 367 of the angled elongated semiconductor structure of the pad 360 between the first end 362-1 and the second end 362-2 may be a longer angled elongated semiconductor structure, used as Figures 6A-6F 306 to produce various angled elongated semiconductor structures 306 as described herein. In such an embodiment, liner 360 may include any suitable semiconductor material, such as those described with reference to the channel materials of transistors 110 and 210, as long as it can be deposited as a liner. For example, liner 360 may include any semiconductor material that can be used in a TFT, such as any of the polycrystalline, polycrystalline, or amorphous semiconductors described above. Figure 7F In another example, the liner 360 may include any 2D semiconductor material, such as any of the above-mentioned graphene, hexagonal boron nitride, or transition metal chalcogenides. Figure 7F In the embodiment of FIG. 3 , the backbone material 354 is removed, so the backbone material 354 may be selected to be any material having sufficient etching selectivity relative to the liner 360 .

[0127] Figure 7G An IC device 350G is shown, which is substantially similar to Figure 7B The IC device 350B is shown to be identical except that it has been further processed to form cut lines 368-1 and 368-2, as shown in reference Fig. 7E In other words, IC device 350G is substantially the same as Figure 7FThe IC device 350F shown is identical except that the backbone material 354 is not removed. Figure 7F , if the pad 360 is already based on a semiconductor material on which an angled transistor can be formed (as shown in reference Figure 7F described above), you can use Figure 7G Embodiment of. Figure 7F The embodiment is opposite, because in Figure 7G In the embodiment of , the backbone material 354 is not removed, so the backbone material 354 need not (although it may) be selected to have sufficient etch selectivity relative to the pad 360, but the backbone material 354 does need to provide electrical insulation between the various instances of the angled elongated semiconductor structure substantially straight portion 367 of the pad 360 between the first end 362-1 and the second end 362-2. Figure 7G In the embodiment of the present invention, the backbone material 354 may include any suitable spacer material.

[0128] Although not specifically shown, Figures 7A-7G The ring trimming method shown may also include other manufacturing operations related to the manufacture of other components of the angled transistor. Figures 7A-7G The ring trimming method shown may also include, for example, using a reference Figures 6A-6F The principles discussed are used to pattern angled elongated structures of semiconductor materials (e.g., if Fig. 7E version, then patterning the angled elongated semiconductor structure 366, or if implementing Figure 7F or Figure 7G In another example, the semiconductor material of the patterned pad 360 is patterned. Figures 7A-7G The ring trimming method shown may also include angled elongated structures based on semiconductor materials (e.g., if implemented Fig. 7E version, then the angled elongated semiconductor structure 366, or if the implementation Figure 7F or Figure 7G 360) to form angled transistors (e.g., transistor 110 and / or transistor 210 as described above), and to integrate at least some of such angled transistors with non-angled transistors (e.g., as described in reference Figures 5A-5Q described above).

[0129] The above ring trimming method is not limited to Figures 7A-7G The arrangement of various components of IC device 350 is shown. Figures 8A-8F Shows that you can use Figures 7A-7G The method shown produces some alternative arrangements of various components of an IC device. Figures 8A-8F Each of the Fig. 7EThe IC device 350 of the embodiment shown in the figure is slightly different in layout. Figures 8A-8F Use with Fig. 7E The same or similar reference numerals used in the present invention refer to similar or similar components, and thus only the description is made of Figures 8A-8F Relative to Fig. 7E Therefore, in addition to Figures 8A-8F In addition to the differences in the arrangement of Figures 7A-7G All descriptions of the ring dressing method provided are applicable to Figures 8A-8F The IC device 350 shown. In particular, even if not specifically shown, Figures 8A-8F Any arrangement may alternatively be based on Figure 7F or Figure 7G In other words, similar modifications can be applied to rearrange Figure 7F or Figure 7G The various components of the embodiment are to achieve Figures 8A-8F The arrangement is like rearranging Fig. 7E All of these embodiments are within the scope of the present disclosure.

[0130] exist Fig. 7E In the embodiment of FIG. 3 , the first alignment line 364 - 1 and the second alignment line 364 - 2 are perpendicular to each other and are aligned with the corresponding edge 303 of the support structure 302. This need not be the case in other embodiments. Fig. 8A An example is shown in , showing that one of the alignment lines (e.g., first alignment line 364-1) can be angled relative to edge 303, while the other alignment line (e.g., second alignment line 364-2) can still be aligned (non-angled) relative to edge 303. Another example is shown in Figure 8B , it is shown that the two alignment lines may be angled relative to edge 303 .

[0131] Figures 8A-8B It is shown that the first and second cut lines 368-1, 368-2 can be parallel to the respective alignment lines 364, for example, the first cut line 368-1 can be substantially parallel to the first alignment line 364-1 and the second cut line 368-2 can be substantially parallel to the second alignment line 364-2. This need not be the case in other embodiments. Figure 8C An example is shown in , showing that one of the cut lines (e.g., the first cut line 368-1) can be angled (i.e., not parallel) relative to the first alignment line 364-1, while the other cut line (e.g., the second cut line 368-2) can still be aligned (i.e., parallel) relative to the corresponding alignment line (i.e., the second alignment line 364-2). Another example is shown in Fig.8D, it is shown that two cut lines 368 can be angled (i.e., not parallel) relative to their respective alignment lines 364. This embodiment in which the cut lines 368 are not parallel to the alignment lines 364 is applicable to any embodiment of the IC device 350, regardless of whether all alignment lines 364 are aligned with the edge 303 of the support structure (e.g., as shown in FIG. Figure 7E-7G ), or whether some or all of the alignment lines 364 are angled relative to the edge 303 of the support structure (e.g., as shown in Figures 8A-8D shown).

[0132] Figure 7E-7G and Figures 8A-8D A single cut line 368-1 is shown for breaking the loop at the first end 362-1, and another single cut line 368-2 is shown for breaking the loop at the second end 362-2. This need not be the case in other embodiments. Fig. 8E An example is shown in , showing that multiple cutting lines 368 can be used, some cutting lines for only one end 362, while other cutting lines extend over multiple ends 362, to perform trimming to break the loop at the first end 362-1 and the second end 362-2. Fig. 8E The arrangement of the five cut lines 368-1 to 368-5 shown in the figure is merely illustrative, and in other embodiments of the IC device 350, any number of cut lines 368 may be used, any of which may be aligned with the edge 303 and / or with the corresponding alignment line 364, or not.

[0133] Figure 7E-7G and Figures 8A-8E Two or more cutting lines 368 are shown for breaking the loop at the first end 362-1 and the second end 362-2. This need not be the case in other embodiments. An example is Fig.8F , it is shown that a cutting through hole 370 may be used to perform trimming to break the ring at the first end 362 - 1 and / or the second end 362 - 2 . Fig.8F The arrangement of the two cutting vias 370-1 and 370-2 shown in is merely illustrative, and in other embodiments of the IC device 350, any number of cutting vias 370 may be used, any of which may be aligned with the edge 303 and / or with the corresponding alignment line 364, or not. Similar to the cutting vias 340 described above, the cutting vias 370 may be filled with any suitable insulator material to provide electrical isolation of the ring from the substantially straight portion 367 of the angled elongated semiconductor structure 366.

[0134] Figures 9A-9DTop views of various processes of a staggered via formation method for fabricating an IC device that integrates angled elongated semiconductor structures and a regularly spaced array of vias are provided in accordance with some embodiments.

[0135] Fig.9A FIG. 4 shows an IC device 400A showing that a staggered via formation method may begin with providing a support structure 302 having an edge 303 as described above (shown as a dashed rectangular outline), and providing an angled elongated semiconductor structure 306 as described above (shown as a dashed rectangular outline). Fig.9A Only one structure 306 is marked in Fig.9A 8 ). Any suitable manufacturing technique may be used to provide the angled elongated semiconductor structure 306 , such as but not limited to using any embodiment of the ring trimming method of FIG. 7 (possibly with variations of FIG. 8 ), possibly in combination with any of the patterning techniques described with reference to FIG. 6 .

[0136] The angled elongated semiconductor structure 306 may be used as a basis for forming transistors thereon (i.e., angled transistors), such as any of the transistors 110, 210 described above. Additionally, other IC components may be further formed based on the angled elongated semiconductor structure 306, such as the memory cells 160, 260 described above. The various IC components (i.e., transistors, memory elements, etc.) formed based on the angled elongated semiconductor structure 306 will have terminals (e.g., transistors will have gate terminals, drain terminals, and source terminals, memory elements will have first and second electrode terminals, etc.), which will need to be electrically connected to electrically interconnect the various IC components to each other and to other components of the IC device, as required by a particular design. Because there are numerous ways in which different IC components, such as transistors and memory elements, may be implemented based on the angled elongated semiconductor structure 306 of the IC device 400A, the details of these components are not described herein. Fig.9A is shown in, and Fig. 9B Continuing to show the IC device 400B, the method further includes providing a through hole 402 to connect to the Fig.9A The angled elongated semiconductor structures 306 implement various terminals of the IC component.

[0137] exist Fig. 9B Only one through hole 402 is labeled, but multiple such through holes are shown in the same pattern. Fig. 9B9, various terminals electrically coupled to (e.g., conductively contacted with) a through-hole 402 are labeled with two-digit reference numerals, such as 11, 12, 13, 14, 15, 21, 22, etc., where the first digit indicates the row in which the terminal is arranged, and the second digit indicates the column in which the terminal is arranged. The through-holes 402 may be provided to obtain optimal overlap with the terminals of various IC components formed based on the angled elongated semiconductor structures 306. As a result, the through-holes 402 may not be perfectly arranged with each other in their respective rows and / or columns. For example, as Fig. 9B As shown, the through hole 402 coupled to terminal 12, the through hole 402 coupled to terminal 22, the through hole 402 coupled to terminal 32, and the through hole 402 coupled to terminal 42 (i.e., the four through holes 402 coupled to different terminals of the same column, column 2) are not aligned in the same manner with respect to any single alignment line. For the through holes arranged in a given column, a vertical alignment line can be used, for example, if a single vertical line can be drawn in the xy plane through the center of each through hole, then the through holes of the given column will be aligned. Alternatively, the vertical alignment line can be a line on one side of all through holes 402 of a given column, such as Fig. 9B However, the through holes 402 of column 2 are not aligned with respect to line 404 because Fig. 9B As shown, not all of the vias 402 in column 2 have a right side along line 404. A careful analysis of the other vias 402 reveals that the vias 402 in the other columns also similarly lack alignment with a single vertical line. For the rows of IC device 400B, the vias 402 coupled to the terminals of a given row are not aligned in the same manner because the distances between different nearest neighbor pairs of vias 402 in a given row are not necessarily the same. For example, for row 1, the vias coupled to terminals 11 and 12 form one nearest neighbor pair, and the vias coupled to terminals 12 and 13 form another nearest neighbor pair, but the distance 406-1 between the vias coupled to terminals 11 and 12 is not equal to the distance 406-2 between the vias coupled to terminals 12 and 13, as shown in FIG. Fig. 9B A careful analysis of other vias 402 reveals that other nearest neighbor pairs of vias 402 in the same row 1 or other rows are also lacking in alignment.

[0138] In order to electrically interconnect IC components based on the angled elongated semiconductor structures 306 of the IC device 400B, the vias 402 need to be coupled to a regular array of vias that can be stacked above them. As used herein, an array of vias is described as "regular" if the vias of the array are arranged in columns and rows, where the vias are aligned both in their rows and in their columns. The vias in a given row can be described as "aligned" if the vias can be aligned along a single horizontal line (in the drawing plane of FIG. 9 ) and have the same distance between different nearest neighbor pairs of vias in the row. The vias in a given column can be described as "aligned" if the vias can be aligned along a single vertical line (in the drawing plane of FIG. 9 ) and have the same distance between different nearest neighbor pairs of vias in the column. Such a regular array of vias is shown as Fig. 9C The through-holes 408 of the IC device 400C are provided to at least partially overlap with the corresponding through-holes 402, and there is a one-to-one correspondence between the through-holes 408 and the through-holes 402, because one through-hole 408 is electrically coupled to (e.g., conductively contacts) one and only one through-hole 402, and vice versa. For example, the conductive material that at least partially fills the through-holes 402 and 408 can contact each pair of staggered through-holes 402 and through-holes 408. It is the provision of through-holes 408 staggered above through-holes 402 that names the method shown in FIG. 9 as a "staggered through-hole formation method."

[0139] Ideally, all of the vias 408 will have maximum overlap with the corresponding via 402 because greater overlap means lower contact resistance at the interface between the via 402 and the via 408 stacked on top of the via 402. However, as described above, the vias 408 must be in a regular array, however, due to the nature of the angled orientation of the elongated semiconductor structure 306, the vias 402 are not in a regular array. Therefore, the process of arranging the vias 408 on top of the vias 402 can be started by selecting one terminal where the overlap will be maximized, and then the remaining vias 408 will be aligned relative to the vias 408 of the selected terminal because all of the vias 408 are in a regular array and therefore the position of one of them determines the position of the others. Fig. 9C As shown, the terminal of this selection may be, for example, terminal 23, Fig. 9C408 at terminal 23. Maximizing the overlap between through-hole 402 at terminal 23 and through-hole 408 means setting the position of through-hole 408 at terminal 23. The remaining through-holes 408 are then arranged relative to through-hole 408 at terminal 23 by ensuring that the regular array is achieved. For example, this means that for column 3, the distance between through-hole 408 at terminal 23 and through-hole 408 at terminal 33 is substantially the same as the distance between through-hole 408 at terminal 23 and through-hole 408 at terminal 13, and substantially the same as the distance between through-hole 408 at terminal 33 and through-hole 408 at terminal 43, and all through-holes 408 of column 3 are aligned along a single vertical line (e.g., Fig. 9B A vertical line is shown in the figure, but in order not to confuse the figure, it is not Fig. 9C Specific examples are shown in Figure 2).

[0140] The inventors of the present disclosure have recognized that when implementing the above-described method of staggered through-hole formation, the misalignment between the through-hole 408 and the corresponding through-hole 402 below the through-hole 408 increases in all directions starting from the selected terminal for which the alignment is optimized. In other words, the misalignment increases in the radially outward direction (i.e., starting from a certain center point and increasing in all directions from that point). By observing that the misalignment of a pair of through-holes 402 and 408 is smallest at the selected terminal 23, increases somewhat for the nearest neighbor terminals 13, 24, 33, and 22, increases a little more for the second nearest neighbor terminals 12, 14, 34, and 32, and increases more (0.1% to 0.2%) for the third nearest neighbor terminals 25, 43, and 21. Fig. 9C The third nearest neighbor terminal above the terminal 23 is not shown in the figure), and for the terminal farther than the third nearest neighbor terminal (for example, Fig. 9C In the example, terminals 36 and 46 show the largest misalignment) and further increase, the Fig. 9C This radial outward expansion of the misalignment between via 402 and via 408 from the selected terminal is seen in FIG. This radial outward expansion of the misalignment between via 402 and via 408 from the selected terminal is in stark contrast to misalignments that may be caused by manufacturing process limitations, as the latter are typically observed on the wafer as starting from one side and increasing in a single direction (e.g., to the other side). Therefore, the radial outward expansion of the misalignment between via 402 and via 408 from the selected terminal is a characteristic indication or characteristic of using the staggered via formation method as described herein.

[0141] The selected terminal that maximizes the overlap between vias 402 and 408 need not be located substantially in the center of the array of terminals. Fig.9D An IC device 400D is shown, showing the reference Figures 9A-9CThe method described has an alternative arrangement of through-holes 402 and through-holes 408 interleaved thereon, but the terminal selected is terminal 12. Even for such a terminal, an increased radial outward expansion of the misalignment between through-holes 402 and 408 can be observed.

[0142] In some implementations, there may come a point where the misalignment between vias 402 and 408 becomes too great and no effective contact can be made between vias 402 and 408, e.g. Fig.9D As shown in FIG. 4A and FIG. 4B , there is a large misalignment between through holes 402 and 408 of terminal 47. Therefore, referring to FIG. Figures 9A-9C The described method may be repeated for another selected terminal in a different portion of the terminal array.Thus, in some embodiments, IC device 400 may include a plurality of selected terminals from which the misalignment radiates outwardly to a certain point.

[0143] It should be noted that although Figures 9B-9D 9. The through holes 402 and 408 shown in FIG. 4 have a substantially square top-down shape (i.e., their cross-sections), but this is not necessarily the case. In other embodiments of the IC device 400, any of the through holes 402 and 408 may have other cross-sections, such as a rectangular cross-section (possibly with rounded corners), a substantially circular or elliptical / oval cross-section, or any other polygonal cross-section (possibly with rounded corners), etc. In addition, in different embodiments of the IC device 400, the alignment loss shown for the through hole 402 may be different. For example, in some embodiments, the through holes 402 coupled to the terminals of a given column may not be aligned in the same manner because the distances between different nearest neighbor pairs of the through holes 402 of a given column are not necessarily the same. In another example, the through holes 402 coupled to the terminals of a given row may not be aligned in the same manner because there may not be a single alignment line (e.g., a single horizontal line in the view of FIG. 9) along which the through holes 402 coupled to the terminals of a given row are aligned. For the arrangement of the through holes 402 of the IC device 400, any combination of such example misalignments may exist.

[0144] Any of the angled transistors described herein (e.g., as described in reference Figure 1 , 24 ), and any non-angled transistors that can be integrated on the same support structure as the angled transistors (e.g., as described with reference to FIG. 5 ) can be used to implement any suitable component. For example, in various embodiments, the transistors described herein can be part of one or more of the following: a central processing unit, a memory device (e.g., a high bandwidth memory device), a memory cell, a logic circuit, an input / output circuit, a field programmable gate array (FPGA) component (such as an FPGA transceiver or FPGA logic), a power delivery circuit, an amplifier (e.g., a III-V amplifier), a peripheral component interconnect Express (PCIE) circuit, a double data rate (DDR) transmission circuit, a computing device (e.g., a wearable or handheld computing device), and the like.

[0145] The IC devices with angled transistors disclosed herein may be included in any suitable electronic device. Figure 10-14 Various examples of apparatus that may include one or more IC devices having angled transistors disclosed herein are shown.

[0146] Fig.10 2002, which may include one or more IC devices having angled transistors. In some embodiments, the die 2002 may be included in an IC package according to any of the embodiments disclosed herein. For example, any of the die 2002 may be used as a Fig.11Any die 2256 in the IC package 2200 shown. Wafer 2000 can be composed of semiconductor materials and can include one or more die 2002 having IC structures formed on the surface of wafer 2000. Each die 2002 can be a repeating unit of a semiconductor product that includes any suitable IC (e.g., an IC that includes one or more IC devices having angled transistors as described herein). After the fabrication of the semiconductor product is completed (e.g., after fabrication of any embodiment of an IC device having angled transistors as described herein), wafer 2000 can undergo a singulation process in which each die 2002 is separated from each other to provide discrete "chips" of the semiconductor product. Specifically, a device including one or more angled transistors as disclosed herein can take the form of wafer 2000 (e.g., unsingulated) or die 2002 (e.g., singulated). Die 2002 can include supporting circuitry to route electrical signals to various memory cells, transistors, capacitors, and any other IC components. In some embodiments, the wafer 2000 or die 2002 may implement or include a memory device (e.g., a hysteresis memory device), a logic device (e.g., an AND gate, an OR gate, a NAND gate, or a NOR gate), or any other suitable circuit element. Multiple of these devices may be combined on a single die 2002. For example, a memory array formed by multiple memory devices may be combined with a processing device (e.g., Fig.11 A processing device 2402) or other logic configured to store information in a memory device or execute instructions stored in a memory array is formed on the same die 2002.

[0147] Fig.11 is a side cross-sectional view of an example IC package 2200 that may include one or more IC devices having angled transistors according to any embodiment disclosed herein. In some embodiments, IC package 2200 may be a system-in-package (SiP).

[0148] The packaging substrate 2252 can be formed of a dielectric material (e.g., a ceramic, a laminate film, an epoxy resin film having filler particles therein, etc.) and can have a conductive path extending through the dielectric material between surface 2272 and surface 2274, or between different locations on surface 2272, and / or between different locations on surface 2274.

[0149] Package substrate 2252 may include conductive contacts 2263 coupled to conductive paths 2262 through package substrate 2252 , allowing die 2256 and / or circuitry within interposer 2257 to be electrically coupled to respective conductive contacts 2264 (or other devices included in package substrate 2252 , not shown).

[0150] The IC package 2200 may include an interposer 2257 coupled to a package substrate 2252 via conductive contacts 2261 of the interposer 2257 , first level interconnects 2265 , and conductive contacts 2263 of the package substrate 2252 . Fig.11 First level interconnects 2265 are shown as solder bumps, but any suitable first level interconnects 2265 may be used. In some embodiments, interposer 2257 may not be included in IC package 2200; instead, die 2256 may be coupled directly to conductive contacts 2263 at face 2272 via first level interconnects 2265.

[0151] The IC package 2200 may include one or more dies 2256 coupled to an interposer 2257 via conductive contacts 2254 of the die 2256, first level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive paths (not shown) through the interposer 2257, allowing circuits within the die 2256 to be electrically coupled to the respective conductive contacts 2261 (or other devices included in the interposer 2257, not shown). Fig.11 The illustrated first level interconnect 2258 is a solder bump, but any suitable first level interconnect 2258 may be used. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; a conductive contact may be recessed into a surface of a component, flush with a surface of a component, or extend away from a surface of a component, and may take any suitable form (e.g., a conductive pad or a socket).

[0152] In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first level interconnect 2265, and a mold compound 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. As appropriate, an example material that may be used for the underfill material 2266 and the mold compound 2268 is an epoxy resin molding material. The second level interconnect 2270 may be coupled to the conductive contact 2264. Fig.11 The second level interconnects 2270 shown in the figure are solder balls (e.g., for a ball grid array arrangement), but any suitable second level interconnects 22770 may be used (e.g., pins in a pin grid array arrangement or contacts in a contact grid array arrangement). The second level interconnects 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference to Fig.12 discussed.

[0153] The die 2256 may take the form of any embodiment of the die 2002 discussed herein (e.g., may include any embodiment of an IC device with angled transistors described herein). In embodiments where the IC package 2200 includes multiple die 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The die 2256 may include circuitry that performs any desired function. For example, one or more of the die 2256 may be a logic die (e.g., a silicon-based die), and one or more of the die 2256 may be a memory die (e.g., a high-bandwidth memory), including an embedded memory die as described herein. In some embodiments, any die 2256 may include one or more IC devices with angled transistors, e.g., as described above; in some embodiments, at least some of the die 2256 may not include any IC devices with angled transistors.

[0154] Fig.11 The IC package 2200 shown may be a flip chip package, although other package architectures may also be used. For example, the IC package 2200 may be a ball grid array (BGA) package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer level chip scale package (WLCSP) or a panel fan-out (FO) package. Fig.11 Two dies 2256 are shown in the IC package 2200, but the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0155] Fig.12 is a cross-sectional side view of an IC device assembly 2300, which may include a component having one or more IC devices having an angled transistor according to any embodiment disclosed herein. IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (which may be, for example, a motherboard). IC device assembly 2300 includes components disposed on a first side 2340 of circuit board 2302 and an opposing second side 2342 of circuit board 2302; typically, components may be disposed on one or both sides 2340 and 2342. In particular, any suitable component of IC device assembly 2300 may include any of the one or more IC devices having an angled transistor according to any embodiment disclosed herein; for example, any IC package discussed below with reference to IC device assembly 2300 may take the form described above with reference to FIG. Fig.11Any form of the embodiments of IC package 2200 discussed (eg, may include one or more IC devices having angled transistors provided on die 2256).

[0156] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 2302 (optionally in combination with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB substrate.

[0157] Fig.12 The illustrated IC device assembly 2300 includes a package-on-interposer structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling component 2316. The coupling component 2316 can electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and can include solder balls (e.g., Fig.12 as shown), male and female portions of the socket, adhesive, bottom fill material and / or any other suitable electrical and / or mechanical coupling structure.

[0158] The package-on-interposer structure 2336 may include an IC package 2320 coupled to the interposer 2304 via a coupling component 2318. The coupling component 2318 may take any form suitable for the application, such as the forms discussed above with reference to the coupling component 2316. The IC package 2320 may be or include, for example, a die ( Fig.10 In particular, IC package 2320 may include one or more IC devices having angled transistors as described herein. Fig.12 A single IC package 2320 is shown in the figure, but multiple IC packages can be coupled to the interposer 2304; in fact, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intermediate substrate for bridging the circuit board 2302 and the IC package 2320. In general, the interposer 2304 can extend the connection to a wider spacing or reroute the connection to a different connection. For example, the interposer 2304 can couple the IC package 2320 (e.g., a die) to the BGA of the coupling component 2316 for coupling to the circuit board 2302. Fig.12 In the illustrated embodiment, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304; in other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected through interposer 2304.

[0159] The interposer 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 2304 may include metal interconnects 2308 and through-holes 2310, including but not limited to through-silicon vias (TSVs) 2306. The interposer 2304 may also include embedded devices 2314, including passive and active devices. These devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any package-on-interposer structure known in the art.

[0160] IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0161] Fig.12 The illustrated IC device assembly 2300 includes a package-on-package structure 2334 coupled to the second side 2342 of the circuit board 2302 via a coupling component 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together via a coupling component 2330 such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any embodiment of the coupling component 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any embodiment of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0162] Fig.13 2400, which may include one or more components including one or more IC devices having angled transistors according to any of the embodiments disclosed herein. For example, any suitable component among the components of computing device 2400 may include a die having one or more angled transistors as described herein (e.g., Fig.10Any one or more components of computing device 2400 may include Fig.11 IC package 2200 or Fig.12 The IC device 2300 may be included therein.

[0163] Multiple parts in Fig.13 2400, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single system-on-chip (SoC) die.

[0164] Additionally, in various embodiments, computing device 2400 may not include Fig.13 2400 may include one or more components shown, but the computing device 2400 may include interface circuitry for coupling to the one or more components. For example, the computing device 2400 may not include the display device 2412, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 2412 may be coupled. In another set of examples, the computing device 2400 may not include the audio input device 2416 or the audio output device 2414, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which the audio input device 2416 or the audio output device 2414 may be coupled.

[0165] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as a cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque MRAM.

[0166] In some embodiments, computing device 2400 may include a communication chip 2406 (e.g., one or more communication chips). For example, communication chip 2406 may be configured to manage wireless communications to transmit data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation over a non-solid medium. The term does not mean that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0167] The communication chip 2406 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including Wi-Fi (IEEE 1402.11 series), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 amendments)), Long Term Evolution (LTE) projects and any amendments, updates and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 1402.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed the IEEE 1402.16 standard conformance and interoperability testing. The communication chip 2406 can operate according to the Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA) or LTE networks. The communication chip 2406 may operate in accordance with Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2406 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivative protocols, as well as any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication chip 2406 may operate in accordance with other wireless protocols. The computing device 2400 may include an antenna 2408 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0168] In some embodiments, the communication chip 2406 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2406 can include multiple communication chips. For example, the first communication chip 2406 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and the second communication chip 2406 can be dedicated to long-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip 2406 can be dedicated to wireless communications, and the second communication chip 2406 can be dedicated to wired communications.

[0169] The computing device 2400 may include a battery / power circuit 2410. The battery / power circuit 2410 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).

[0170] Computing device 2400 may include a display device 2412 (or corresponding interface circuitry, as discussed above). For example, display device 2412 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0171] Computing device 2400 may include audio output device 2414 (or corresponding interface circuitry, as discussed above). For example, audio output device 2414 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0172] Computing device 2400 may include audio input device 2416 (or corresponding interface circuitry, as discussed above). Audio input device 2416 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0173] Computing device 2400 may include other output devices 2418 (or corresponding interface circuitry, as discussed above). Examples of other output devices 2418 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0174] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry, as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (e.g., a mouse, a stylus, a touchpad), a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0175] Computing device 2400 may include GPS device 2422 (or corresponding interface circuitry, as discussed above). GPS device 2422 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0176] The computing device 2400 may include a security interface device 2424. The security interface device 2424 may include any device that provides security features for the computing device 2400 or any individual component therein (e.g., the processing device 2402 or the memory 2404). Examples of security features may include authorization, access to digital certificates, access to items in a keychain, etc. Examples of the security interface device 2424 may include a software firewall, a hardware firewall, anti-virus software, a content filtering device, or an intrusion detection device.

[0177] In some embodiments, computing device 2400 may include a temperature detection device 2426 and a temperature regulation device 2428 .

[0178] The temperature detection device 2426 may include any device capable of determining the temperature of the computing device 2400 or any individual component thereof (e.g., the temperature of the processing device 2402 or the memory 2404). In various embodiments, the temperature detection device 2426 may be configured to determine the temperature of an object (e.g., the computing device 2400, a component of the computing device 2400, a device coupled to the computing device, etc.), the temperature of an environment (e.g., a data center including the computing device 2400, controlled by the computing device 2400, or otherwise associated with the computing device 2400), and the like. The temperature detection device 2426 may include one or more temperature sensors. Different temperature sensors of the temperature detection device 2426 may have different locations within and around the computing device 2400. The temperature sensor may generate data (e.g., digital data) representing the detected temperature and provide the data to another device, e.g., the temperature regulating device 2428, the processing device 2402, the memory 2404, and the like. In some embodiments, the temperature sensor of the temperature detection device 2426 may be turned on or off, for example, by the processing device 2402 or an external system. The temperature sensor detects temperature when it is turned on and does not detect temperature when it is turned off. In other embodiments, the temperature sensor of the temperature detection device 2426 can detect temperature continuously and automatically, or detect temperature at a predetermined time or at a time triggered by an event associated with the computing device 2400 or any component therein.

[0179] The temperature regulating device 2428 may include any device configured to change (e.g., reduce) the temperature, for example, based on one or more target temperatures and / or based on temperature measurements performed by the temperature detection device 2426. The target temperature may be a preferred temperature. The target temperature may depend on the settings in which the computing device 2400 operates. In some embodiments, the target temperature may be 200 degrees Kelvin or less. In some embodiments, the target temperature may be 20 degrees Kelvin or less, or 5 degrees Kelvin or less. The target temperatures of different objects and different environments of or associated with the computing device 2400 may be different. In some embodiments, the cooling provided by the temperature regulating device 2428 may be a multi-stage process with a temperature range from room temperature to 4K or less.

[0180] In some embodiments, the temperature adjustment device 2428 may include one or more cooling devices. Different cooling devices may have different locations in and around the computing device 2400. The cooling device of the temperature adjustment device 2428 may be associated with one or more temperature sensors of the temperature detection device 2426, and may be configured to operate based on the temperature detected by the temperature sensor. For example, the cooling device may be configured to determine whether the detected ambient temperature is higher than the target temperature, or whether the detected ambient temperature is higher than the target temperature by a predetermined value, or whether any other temperature-related conditions associated with the temperature of the computing device 2400 are met. In response to determining that one or more temperature-related conditions associated with the temperature of the computing device 2400 are met (for example, in response to determining that the detected ambient temperature is higher than the target temperature), the cooling device may trigger its cooling mechanism and begin to reduce the ambient temperature. Otherwise, the cooling device will not trigger any cooling. The cooling device of the temperature adjustment device 2428 may operate with various cooling mechanisms, such as evaporative cooling, radiative cooling, conductive cooling, convection cooling, other cooling mechanisms, or any combination thereof. The cooling device of the temperature adjustment device 2428 may include a coolant, such as water, oil, liquid nitrogen, liquid helium, etc. In some embodiments, the temperature regulating device 2428 can be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator. In some embodiments, the temperature regulating device 2428 or any portion thereof (e.g., one or more separate cooling devices) can be connected very closely (e.g., less than about 1 meter) to the computing device 2400, or can be provided in a separate housing in which a dedicated heat exchanger (e.g., a compressor, a heating, ventilation, and air conditioning (HVAC) system, liquid helium, liquid nitrogen, etc.) can reside.

[0181] By maintaining the target temperature, the energy consumption of the computing device 2400 (or its components) can be reduced, while computing efficiency can be improved. For example, when the computing device 2400 (or its components) is operated at a lower temperature, energy dissipation (e.g., heat dissipation) can be reduced. In addition, the energy consumed by semiconductor components (e.g., the energy required to switch transistors of any component of the computing device 2400) can also be reduced. Various semiconductor materials can have lower resistivity and / or higher mobility at lower temperatures. In this way, the current per unit power supply voltage can be increased by reducing the temperature. Conversely, for the same current that will be required, the power supply voltage can be reduced by reducing the temperature. Since energy is related to the power supply voltage, the energy consumption of semiconductor components can also be reduced. In some implementations, the energy saved due to reduced heat dissipation and reduced energy consumed by semiconductor components or components of the computing device may exceed (sometimes significantly exceed) the cost associated with the energy required for cooling.

[0182] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0183] Fig.14 2500, which may include one or more IC devices having angled transistors according to any of the embodiments disclosed herein. For example, any suitable component of the components of the processing device 2500 may include a die having one or more angled transistors as described herein (e.g., Fig.10 Any one or more components of the processing device 2500 may include the IC device 2300 ( Fig.12 ) or is included therein. Any one or more components of the processing device 2500 may include Fig.11 IC package 2200 or Fig.12 IC device 2300 or included therein. Any one or more components of processing device 2500 may include Fig.13 The processing device 2500 may be or be included in the computing device 2400; for example, the processing device 2500 may be the processing device 2402 of the computing device 2400.

[0184] Multiple parts in Fig.14 2500, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the processing device 2500 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC die or coupled to a single support structure, such as a single carrier substrate.

[0185] Additionally, in various embodiments, the processing device 2500 may not include Fig.14 The processing device 2500 may include one or more components shown, but the processing device 2500 may include interface circuits for coupling to one or more components. For example, the processing device 2500 may not include the memory 2504, but may include display device interface circuits (e.g., connectors and driver circuits) to which the memory 2504 may be coupled.

[0186] Processing device 2500 may include logic circuitry 2502 (eg, one or more circuits configured to implement logic / computational functions). Examples of such circuitry include ICs that implement one or more of input / output (I / O) functions, arithmetic operations, data pipelining, and the like.

[0187] In some embodiments, logic circuit 2502 may include one or more circuits responsible for reading / writing data stored in memory 2504. To this end, logic circuit 2502 may include one or more I / O ICs configured to control access to data stored in memory 2504.

[0188] In some embodiments, the logic circuit 2502 may include one or more high-performance computing dies configured to perform various operations on the data stored in the memory 2504 (e.g., arithmetic and logic operations, pipelining of data from one or more storage dies of the memory 2504 and possibly also data from external devices / chips). In some embodiments, the logic circuit 2502 may be configured to only control I / O access to the data, but not perform any operations on the data. In some embodiments, the logic circuit 2502 may implement an IC configured to implement I / O control of the data stored in the memory 2504, assemble data from the memory 2504 for transmission (e.g., transmission via a central bus) to a device / chip inside or outside the processing device 2500, etc. In some embodiments, the logic circuit 2502 may not be configured to perform any operations on the data other than I / O and assembly for transmission to the memory 2504.

[0189] Processing device 2500 may include memory 2504, which may include one or more ICs configured to implement memory circuits (e.g., ICs implementing one or more of a memory device, a memory array, control logic configured to control the memory device and array, etc.). In some embodiments, memory 2504 may be substantially as described above with reference to memory 2404 ( Fig.13 ) is implemented as described in the above. In some embodiments, the memory 2504 may be a designated device configured to provide storage functions to components of the processing device 2500 (i.e., local), while the memory 1604 may be configured to provide system-level storage functions to the entire computing device 2400 (i.e., global). In some embodiments, the memory 2504 may include a memory that shares a die with the logic circuit 2502.

[0190] In some embodiments, memory 2504 may include flat memory (sometimes also referred to as "flat hierarchical memory" or "linear memory"), and therefore may also be referred to as "basin memory". As is known in the art, flat memory or linear memory refers to a memory addressing paradigm in which memory can appear to a program as a single continuous address space in which the processor can directly and linearly address all available memory locations without having to resort to memory segmentation or paging schemes. Thus, the memory implemented in memory 2504 may be a memory that is not divided into hierarchical layers or levels in terms of access to its data.

[0191] In some embodiments, memory 2504 may include hierarchical memory. In this context, hierarchical memory refers to the concept of computer architecture in which computer storage is divided into levels based on memory characteristics, such as response time, complexity, capacity, performance, and control technology. Designs for high performance may need to consider the limitations of the memory hierarchy, i.e., the size and capabilities of each component. With hierarchical memory, each of the various memory components can be viewed as a memory hierarchy (m1, m2, ... m n ), where each member m i Usually higher than the next highest member of the hierarchy m i+1 Smaller and faster. To limit the wait of higher levels, the response of the lower levels of the hierarchical memory structure can be to fill the buffer and then signal to activate the transmission. For example, in some embodiments, the hierarchical memory implemented in memory 2504 can be divided into four main storage levels: 1) internal storage (e.g., processor registers and cache), 2) main memory (e.g., system RAM and controller card), and 3) online mass storage (e.g., secondary storage), and 4) offline block storage (e.g., tertiary and offline storage). However, because the number of levels in the memory hierarchy and the performance at each level have increased over time and may continue to increase in the future, this example hierarchical division only provides a non-limiting example of how memory 2504 can be arranged.

[0192] The processing device 2500 may include a communication device 2506, which may be substantially as described above with reference to the communication chip 2406 ( Fig.13 ) is implemented as described above. In some embodiments, the communication device 2506 can be a designated device configured to provide communication functions to the components of the processing device 2500 (i.e., local), while the communication chip 2406 can be configured to provide system-level communication functions to the entire computing device 2400 (i.e., global).

[0193] The processing device 2500 may include an interconnect 2508, which may include any element or device including a conductive material for providing electrical connectivity to one or more components of or associated with the processing device 2500 and / or between various such components. Examples of the interconnect 2508 include conductive lines / lines (also sometimes referred to as “lines” or “metal lines” or “trench”) and conductive vias (also sometimes referred to as “vias” or “metal vias”), metallization stacks, redistribution layers, metal-insulator-metal (MIM) structures, and the like.

[0194] The processing device 2500 may include a temperature detection device 2510, which may be substantially as described above with reference to Fig.13 In some embodiments, the temperature sensing device 2510 may be implemented as described above with respect to the temperature sensing device 2426 of the processing device 2500, but is configured to determine temperature on a more local scale, i.e., the temperature of the processing device 2500, its components. In some embodiments, the temperature sensing device 2510 may be a designated device configured to provide temperature sensing functionality for components of the processing device 2500 (i.e., local), while the temperature sensing device 2426 may be configured to provide system-level temperature sensing functionality for the entire computing device 2400 (i.e., global).

[0195] The processing device 2500 may include a temperature regulating device 2512, which may be substantially as described above with reference to Fig.13 In some embodiments, temperature regulation device 2512 may be implemented as described above with respect to temperature regulation device 2428 of the processing device 2500, but is configured to regulate temperature on a more local scale, i.e., the temperature of the processing device 2500, its components. In some embodiments, temperature regulation device 2512 may be a designated device configured to provide temperature regulation functions for components of processing device 2500 (i.e., local), while temperature regulation device 2428 may be configured to provide system-level temperature regulation functions for the entire computing device 2400 (i.e., global).

[0196] The processing device 2500 may include a battery / power circuit 2514, which may be substantially as described above with reference to Fig.13 In some embodiments, the battery / power circuit 2514 may be a designated device (i.e., local) configured to provide battery / power functions for components of the processing device 2500, while the battery / power circuit 2410 may be configured to provide system-level battery / power functions (i.e., global) for the entire computing device 2400.

[0197] The processing device 2500 may include a hardware security device 2516, which may be substantially as described above with reference to Fig.13The hardware security device 2516 may be implemented as described in the security interface device 2424 of the embodiment of the present invention. In some embodiments, the hardware security device 2516 may be a physical computing device configured to protect and manage digital keys, perform encryption and decryption functions of digital signatures, authentication and other cryptographic functions. In some embodiments, the hardware security device 2516 may include one or more secure cryptographic processor chips.

[0198] The above description of implementations illustrated in the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Unless otherwise specified, in various embodiments, features described with respect to one of the drawings may be combined with features described with respect to other drawings.

[0199] The following paragraphs provide various examples of the embodiments disclosed herein.

[0200] Example A1 provides an IC device including: a support structure (e.g., a die, a substrate, a carrier substrate, etc.); a first transistor provided on the support structure; and a second transistor provided on the support structure, wherein each of the second transistor and the first transistor includes a source region, a drain region, and a channel region spatially located between the source region and the drain region, wherein the shortest line extending between the source region and the drain region of the first transistor is substantially parallel to an edge (e.g., at least one edge) of the support structure, and wherein the shortest line extending between the source region and the drain region of the second transistor is at an angle between 10 degrees and 80 degrees relative to the edge of the support structure. The edge of the support structure can be, for example, an edge of one of the opposite front and back sides of the support structure.

[0201] Example A2 provides an IC device according to Example A1, wherein the support structure has a first side and an opposing second side.

[0202] Example A3 provides an IC device according to Example A2, wherein the first transistor is provided on a first region of a first side of a support structure, and the second transistor is provided on a second region of the first side of the support structure that does not overlap with the first region (i.e., the two transistors are provided on the same side or on the same side of the support structure). In some embodiments, the support structure can be a substrate of a semiconductor material, or can be a substrate having a surface including a layer of semiconductor material, and the non-angled transistor and the second transistor can be monolithically formed on the same side of the support structure such that the channel regions of the transistors include semiconductor material.

[0203] Example A4 provides an IC device according to Example A2, wherein a first transistor is provided on a first side of a support structure and a second transistor is provided on a second side of the support structure. In some embodiments, the support structure can be a substrate of a semiconductor material, or can be a substrate having a surface of a first side and a surface of a second side including a layer of semiconductor material, and the non-angled transistor and the second transistor can be monolithically formed on different sides of the support structure such that channel regions of the transistors include semiconductor material.

[0204] Example A5 provides an IC device according to Example A4, wherein a projection of the second transistor on the support structure completely overlaps with or is located within a projection of the first transistor on the support structure, or a projection of the first transistor on the support structure completely overlaps with or is located within a projection of the second transistor on the support structure.

[0205] Example A6 provides an IC device according to Example A4, wherein a projection of the second transistor on the support structure is offset relative to a projection of the first transistor on the support structure (eg, does not overlap, or overlaps by less than about 75%).

[0206] Example A7 provides an IC device according to Example A2, wherein the second transistor is one of a plurality of second transistors provided on the first side of the support structure, and the first transistor is nested between the plurality of second transistors.

[0207] Example A8 provides the IC device according to Example A2, wherein the first transistor is one of a plurality of first transistors provided on the first side of the support structure, and the second transistor is nested between the plurality of first transistors.

[0208] Example A9 provides an IC device according to any of Examples A1-A8, wherein the support structure is a substrate including a semiconductor material, the channel region of the first transistor includes a first portion of the semiconductor material, and the channel region of the second transistor includes a second portion of the semiconductor material.

[0209] Example A10 provides an IC device according to Example A1, wherein a supporting structure has a first side and an opposite second side, a first transistor is in a first layer above the first side of the supporting structure, and a second transistor is in a second layer above the first side of the supporting structure (i.e., the first and second layers are on the same side of the supporting structure and are closer to the first side of the supporting structure than to another second side of the supporting structure), and the IC device also includes a bonding layer between the first layer and the second layer.

[0210] Example A11 provides an IC device according to Example A10, wherein the bonding layer includes a bonding material, which includes an etch stop material comprising silicon, nitrogen and carbon, wherein the atomic percentage of silicon, nitrogen and carbon in the etch stop material is at least about 1%, such as at least about 5%, such as between about 1% and 50%, which indicates that these elements are intentionally added as opposed to accidental impurities whose concentration is typically less than about 0.1%.

[0211] Example A12 provides the IC device according to any of Examples A10-A11, wherein the second layer is closer to the first side of the support structure than the first layer.

[0212] Example A13 provides an IC device according to Example A12, further including a metallization stack, wherein the metallization stack is between the bonding layer and the first layer, and the bonding layer is between the metallization stack and the second layer (i.e., the metallization stack is part of a first IC die including the first layer and the metallization stack on top of the first layer, wherein the first IC die is then face-down bonded to the front of a second IC die including the second layer).

[0213] Example A14 provides an IC device according to Example A13, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, wherein the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.

[0214] Example A15 provides an IC device according to Example A12, further including a metallization stack, wherein the first layer is between the bonding layer and the metallization stack (i.e., the metallization stack is part of a first IC die including the first layer and the metallization stack on top of the first layer, wherein the first IC die is then bonded backside down to the front of a second IC die including the second layer).

[0215] Example A16 provides an IC device according to Example A15, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, wherein the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the first layer.

[0216] Example A17 provides the IC device according to any of Examples A10-A11, wherein the first layer is closer to the first side of the support structure than the second layer.

[0217] Example A18 provides an IC device according to Example A17, further including a metallization stack, wherein the metallization stack is between the bonding layer and the second layer, and the bonding layer is between the metallization stack and the first layer (i.e., the metallization stack is part of a second IC die including the second layer and the metallization stack on top of the second layer, wherein the second IC die is then bonded face down to the front of the first IC die including the first layer).

[0218] Example A19 provides an IC device according to Example A18, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, wherein the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.

[0219] Example A20 provides an IC device according to Example A17, further including a metallization stack, wherein the second layer is between the bonding layer and the metallization stack (i.e., the metallization stack is part of a second IC die including the second layer and the metallization layer on top of the second layer, wherein the second IC die is then bonded backside down to a front portion of the first IC die including the first layer).

[0220] Example A21 provides an IC device according to Example A20, further comprising a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, wherein the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the second layer.

[0221] Example B1 provides an IC device comprising a support structure (e.g., a die, a substrate, a carrier substrate, etc.); and a plurality of angled structures (e.g., angled elongated semiconductor structures 306) provided on the support structure, the plurality of angled structures comprising at least a first angled structure (e.g., 306-1) and a second angled structure (e.g., 306-2), wherein each angled structure comprises a first end (e.g., 328-1), a second end opposite to the first end (e.g., 328-2), and a longitudinal axis (e.g., 320) extending between the first end and the second end, wherein the longitudinal axis of each angled structure is at an angle between 10 degrees and 80 degrees relative to an edge of the support structure (the edge of the support structure can be, for example, an edge of one of two opposite surfaces of the support structure), and wherein the longitudinal axis of the first angled structure and the longitudinal axis of the second angled structure are a shared longitudinal axis.

[0222] Example B2 provides an IC device according to Example B1, wherein the first end of the first angled structure is opposite to the second end of the second angled structure (i.e., the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), and each of the projections of the first end of the first angled structure on a plane parallel to the supporting structure and the projections of the second end of the second angled structure on the plane are straight lines.

[0223] Example B3 provides an IC device according to Example B2, wherein a straight line of a projection of a first end of the first angled structure on the plane is parallel to a straight line of a projection of a second end of the second angled structure on the plane.

[0224] Example B4 provides an IC device according to any one of Examples B2-B3, wherein at least one (e.g., all) of the straight lines of the projections of the first end of the first angled structure on the plane and the straight lines of the projections of the second end of the second angled structure on the plane are substantially parallel to an edge of the support structure.

[0225] Example B5 provides an IC device according to any one of Examples B2-B3, wherein at least one of the straight line of the projection of the first end of the first angled structure on the plane and the straight line of the projection of the second end of the second angled structure on the plane is at an angle between 10 degrees and 80 degrees relative to the edge of the supporting structure.

[0226] Example B6 provides an IC device according to Example B5, wherein at least one of a projection of the second end of the first angled structure on the plane and a projection of the first end of the second angled structure on the plane are substantially parallel to an edge of the support structure.

[0227] Example B7 provides an IC device according to any one of Examples B1-B6, wherein the shared longitudinal axis is a first shared longitudinal axis, the plurality of angled structures further include a third angled structure (e.g., 306-3) and a fourth angled structure (e.g., 306-4), the longitudinal axis of the third angled structure and the longitudinal axis of the fourth angled structure are a second shared longitudinal axis, and the first shared longitudinal axis (e.g., 320-1) and the second shared longitudinal axis (e.g., 320-2) are substantially parallel and at a distance from each other (i.e., they do not overlap or coincide).

[0228] Example B8 provides an IC device according to Example B7, wherein the first end of the first angled structure is opposite to the second end of the second angled structure (i.e., the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), wherein the first end of the third angled structure is opposite to the second end of the fourth angled structure (i.e., the first end of the third angled structure is closer to the second end of the fourth angled structure than the second end of the third angled structure, and the second end of the fourth angled structure is closer to the first end of the third angled structure than the first end of the fourth angled structure), and wherein each of the projections of the first end of the first angled structure on a plane parallel to the support structure, the projection of the second end of the second angled structure on the plane, the projection of the first end of the third angled structure on the plane, and the projection of the second end of the fourth angled structure on the plane is a straight line.

[0229] Example B9 provides an IC device according to Example B8, wherein the straight line of the projection of the first end of the first angled structure on the plane is parallel to the straight line of the projection of the second end of the second angled structure on the plane, and the straight line of the projection of the first end of the third angled structure on the plane is parallel to the straight line of the projection of the second end of the fourth angled structure on the plane.

[0230] Example B10 provides an IC device according to any one of Examples B8-B9, wherein at least one (e.g., all) of the straight lines of the projections of the first end of the first angled structure on the plane and the straight lines of the projections of the second end of the second angled structure on the plane are substantially parallel to the edge of the supporting structure, and at least one (e.g., all) of the straight lines of the projections of the first end of the third angled structure on the plane and the straight lines of the projections of the second end of the fourth angled structure on the plane are substantially parallel to the edge of the supporting structure.

[0231] Example B11 provides an IC device according to any one of Examples B8-B10, wherein a straight line of a projection of a first end of a first angled structure on the plane and a straight line of a projection of a first end of a third angled structure on the plane are in different planes perpendicular to the support structure.

[0232] Example B12 provides an IC device according to Example B11, wherein a straight line of a projection of a second end of the second angled structure on the plane and a straight line of a projection of a second end of the fourth angled structure on the plane are in different planes perpendicular to the support structure.

[0233] Example B13 provides an IC device according to any one of Examples B8-B12, wherein the distance between a straight line of a projection of a first end of a first angled structure on the plane and a straight line of a projection of a second end of a second angled structure on the plane is different from the distance between a straight line of a projection of a first end of a third angled structure on the plane and a straight line of a projection of a second end of a fourth angled structure on the plane.

[0234] Example B14 provides an IC device according to any one of Examples B8-B10, wherein a straight line of a projection of a first end of a first angled structure on the plane and a straight line of a projection of a first end of a third angled structure on the plane are in a single first plane perpendicular to the supporting structure, and a straight line of a projection of a second end of a second angled structure on the plane and a straight line of a projection of a second end of a fourth angled structure on the plane are in a single second plane perpendicular to the supporting structure.

[0235] Example B15 provides an IC device according to any one of Examples B8-B10 or B14, wherein the distance between the straight line of the projection of the first end of the first angled structure on the plane and the straight line of the projection of the second end of the second angled structure on the plane is the same as the distance between the straight line of the projection of the first end of the third angled structure on the plane and the straight line of the projection of the second end of the fourth angled structure on the plane.

[0236] Example B16 provides an IC device according to Example B1, wherein the first end of the first angled structure is opposite to the second end of the second angled structure (i.e., the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), and wherein each of the projection of the first end of the first angled structure on a plane parallel to the supporting structure and the projection of the second end of the second angled structure on the plane is a curve.

[0237] Example B17 provides an IC device according to Example B16, wherein a curve of a projection of a first end of the first angled structure on the plane and a curve of a projection of a second end of the second angled structure on the plane are portions of an ellipse or an oval.

[0238] Example B18 provides an IC device according to any of Examples B1-B17, wherein the angled structure includes a semiconductor material.

[0239] Example B19 provides an IC device according to any of Examples B1-B18, wherein the one or more angled structures are fins of one or more semiconductor materials, the fins extending away from a substrate (wherein the substrate may be part of a support structure or may be between the support structure and the fins).

[0240] Example B20 provides an IC device according to any of Examples B1-B19, wherein the one or more angled structures are nanoribbons of one or more semiconductor materials.

[0241] Example B21 provides an IC device according to any one of Examples B1-B20, further including a transistor provided on a support structure, wherein the transistor includes a source region, a drain region, and a channel region spatially located between the source region and the drain region, wherein the shortest line extending between the source region and the drain region of the transistor is a shared longitudinal axis, and wherein the channel region of the transistor includes semiconductor material of a first angled structure (i.e., the transistor is formed based on the first angled structure).

[0242] Example B22 provides an IC device according to Example B21, further including a storage element coupled to the transistor.

[0243] Example B23 provides an IC device according to Example B22, wherein the storage element is coupled to a source region or a drain region of the transistor.

[0244] Example B24 provides an IC device according to any of Examples B22-B23, wherein the storage element is one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance change material.

[0245] Example B25 provides an IC device according to any one of Examples B21-B24, wherein the transistor is a first transistor, the IC device also includes a second transistor provided on the support structure, and the shortest line extending between the source region of the second transistor and the drain region of the second transistor is substantially parallel to the edge of the support structure.

[0246] Example B26 provides an IC device according to Example B25, wherein the support structure has a first side and an opposing second side.

[0247] Example B27 provides an IC device according to Example B26, wherein the first transistor is provided on a first region of a first side of a support structure, and the second transistor is provided on a second region of the first side of the support structure that does not overlap with the first region (i.e., both the non-angled transistor and the second transistor are provided on the same side or on the same side of the support structure). In some embodiments, the support structure can be a substrate of a semiconductor material, or can be a substrate having a surface including a layer of semiconductor material, and the non-angled transistor and the second transistor can be monolithically formed on the same side of the support structure such that the channel regions of the transistors include semiconductor material.

[0248] Example B28 provides an IC device according to Example B26, wherein a first transistor is provided on a first side of a support structure and a second transistor is provided on a second side of the support structure. In some embodiments, the support structure can be a substrate of a semiconductor material, or can be a substrate having a surface of a first side and a surface of a second side including a layer of semiconductor material, and the non-angled transistor and the second transistor can be monolithically formed on different sides of the support structure such that channel regions of the transistors include semiconductor material.

[0249] Example B29 provides an IC device according to Example B28, wherein a projection of the second transistor on the support structure completely overlaps with or is located within a projection of the first transistor on the support structure, or a projection of the first transistor on the support structure completely overlaps with or is located within a projection of the second transistor on the support structure.

[0250] Example B30 provides an IC device according to example B28, wherein a projection of the second transistor on the support structure is offset (eg, does not overlap, or overlaps by less than about 75%) relative to a projection of the first transistor on the support structure.

[0251] Example B31 provides an IC device according to example B26, wherein the second transistor is one of a plurality of second transistors provided on the first side of the support structure, and the first transistor is nested between the plurality of second transistors.

[0252] Example B32 provides an IC device according to example B26, wherein the first transistor is one of a plurality of first transistors provided on a first side of the support structure, and the second transistor is nested between the plurality of first transistors.

[0253] Example B33 provides an IC device according to any of Examples B25-B32, wherein the support structure is a substrate including a semiconductor material, the channel region of the first transistor includes a first portion of the semiconductor material, and the channel region of the second transistor includes a second portion of the semiconductor material.

[0254] Example B34 provides an IC device according to Example B25, wherein a supporting structure has a first side and an opposite second side, a first transistor is in a first layer above the first side of the supporting structure, and a second transistor is in a second layer above the first side of the supporting structure (i.e., the first and second layers are on the same side of the supporting structure and are closer to the first side of the supporting structure than to another second side of the supporting structure), and the IC device also includes a bonding layer between the first layer and the second layer.

[0255] Example B35 provides an IC device according to Example B34, wherein the bonding layer includes a bonding material, which includes an etch stop material comprising silicon, nitrogen and carbon, wherein the atomic percentage of silicon, nitrogen and carbon in the etch stop material is at least about 1%, such as at least about 5%, such as between about 1% and 50%, which indicates that these elements are intentionally added as opposed to accidental impurities having concentrations typically less than about 0.1%.

[0256] Example B36 provides an IC device according to any of Examples B34-B35, wherein the second layer is closer to the first side of the support structure than the first layer.

[0257] Example B37 provides an IC device according to Example B36, further including a metallization stack, wherein the metallization stack is between the bonding layer and the first layer, and the bonding layer is between the metallization stack and the second layer (i.e., the metallization stack is part of a first IC die including the first layer and the metallization layer on top of the first layer, wherein the first IC die is then bonded face down to the front of a second IC die including the second layer).

[0258] Example B38 provides an IC device according to Example B37, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, wherein the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.

[0259] Example B39 provides an IC device according to Example B36, further including a metallization stack, wherein the first layer is between the bonding layer and the metallization stack (i.e., the metallization stack is part of a first IC die including the first layer and a metallization layer on top of the first layer, wherein the first IC die is then bonded backside down to a front of a second IC die including the second layer).

[0260] Example B40 provides an IC device according to Example B39, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, wherein the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the first layer.

[0261] Example B41 provides an IC device according to any of Examples B34-B35, wherein the first layer is closer to the first side of the support structure than the second layer.

[0262] Example B42 provides an IC device according to Example B41, further including a metallization stack, wherein the metallization stack is between the bonding layer and the second layer, and the bonding layer is between the metallization stack and the first layer (i.e., the metallization stack is part of a second IC die including the second layer and the metallization layer on top of the second layer, wherein the second IC die is then bonded face down to the front of the first IC die including the first layer).

[0263] Example B43 provides an IC device according to Example B42, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, wherein the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.

[0264] Example B44 provides an IC device according to Example B41, further including a metallization stack, wherein the second layer is between the bonding layer and the metallization stack (i.e., the metallization stack is part of a second IC die including the second layer and the metallization layer on top of the second layer, wherein the second IC die is then bonded backside down to a front portion of the first IC die including the first layer).

[0265] Example B45 provides an IC device according to Example B44, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, wherein the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the second layer.

[0266] Example C1 provides an IC device comprising a support structure (e.g., a die, a substrate, a carrier substrate, etc.); an elongated structure of semiconductor material (e.g., a fin or a nanoribbon) provided on the support structure; and another structure of semiconductor material proximate to the elongated structure (i.e., the same material as the elongated structure), wherein a projection of the elongated structure on the support structure is substantially rectangular, and a projection of the another structure on the support structure is a curve.

[0267] Example C2 provides an IC device according to Example C1, wherein a projection of the further structure on the support structure has a U-shape.

[0268] Example C3 provides an IC device according to any one of Examples C1-C2, wherein the rectangle has a first dimension in a first direction and a second dimension in a second direction, the first direction is perpendicular to the second direction, the first dimension is greater than the second dimension, and the curve has a portion extending along the first direction.

[0269] Example C4 provides an IC device according to Example C3, wherein lines in the rectangle along the first direction overlap with lines in the curved line portion along the first direction.

[0270] Example C5 provides an IC device according to any of Examples C3-C4, wherein the first direction is at an angle between 10 degrees and 80 degrees relative to an edge of the support structure (the edge of the support structure can be, for example, an edge of one of two opposing surfaces of the support structure).

[0271] Example C6 provides the IC device according to any of Examples C3-C5, wherein a dimension of the curved portion extending along the first direction is less than 10% of the first dimension of the rectangle.

[0272] Example C7 provides an IC device according to any of Examples C1-C6, wherein a distance between the elongated structure and the further structure is between about 3 nanometers and 1000 nanometers, for example between about 5 nanometers and 100 nanometers, or between about 10 nanometers and 75 nanometers.

[0273] Example C8 provides the IC device according to any of Examples C1-C7, wherein the elongated structure is a fin extending away from the support structure, and the further structure is a curved structure extending away from the support structure.

[0274] Example C9 provides an IC device according to Example C8, wherein a height of the fin is substantially equal to a height of the curved structure.

[0275] Example C10 provides an IC device according to any of Examples C1-C7, wherein the elongated structure is a nanoribbon extending parallel to the support structure, and the further structure is a curved structure extending parallel to the support structure.

[0276] Example C11 provides an IC device according to Example C10, further comprising an insulator material between the nanoribbon and the support structure and between the bending structure and the support structure.

[0277] Example C12 provides an IC device according to any of Examples C1-C11, wherein a distance from the support structure to a surface of the elongated structure farthest from the support structure is substantially equal to a distance from the support structure to a surface of the further structure farthest from the support structure.

[0278] Example C13 provides an IC device according to any of Examples C1-C12, further comprising an insulator material between the elongated structure and the further structure.

[0279] Example C14 provides an IC device according to any of Examples C1-C13, wherein the further structure is not electrically connected to any other element or component of the IC device.

[0280] Example C15 provides the IC device according to any of Examples C1-C14, wherein the further structure is surrounded by insulator material on all sides (ie, the further structure is not electrically connected to anything in the IC device).

[0281] Example D1 provides an IC device comprising a support structure (e.g., a die, a substrate, a carrier substrate, etc.); a plurality of angled structures (e.g., angled elongated semiconductor structures 306) provided above the support structure, wherein individual angled structures of the plurality of angled structures comprise semiconductor material and are elongated structures having a longitudinal axis that is substantially parallel to the support structure and is at an angle between 10 degrees and 80 degrees relative to an edge of the support structure (the edge of the support structure may be, for example, an edge of one of two opposing faces of the support structure); a plurality of IC components based on the plurality of angled structures, the plurality of IC components having a plurality of terminals; and an array of stacked through-hole pairs comprising a first stacked through-hole pair, a second stacked through-hole pair, and a third stacked through-hole pair, each stacked through-hole pair of the array comprising a first through-hole electrically coupled to a different one of the terminals and a second through-hole stacked above the first through-hole and electrically coupled to the first through-hole, wherein the overlap between the first through-hole and the second through-hole of the first stacked through-hole pair is greater than the overlap of the second stacked through-hole pair and the overlap of the third stacked through-hole pair, and wherein the second stacked through-hole pair and the third stacked through-hole pair are located on opposite sides of the first stacked through-hole pair.

[0282] Example D2 provides an IC device according to Example D1, wherein an overlap of the first stacked via pair is the largest of all stacked via pairs of the array.

[0283] Example D3 provides the IC device of any of Examples D1-D2, wherein the overlap decreases radially outward from the first stacked via pair.

[0284] Example D4 provides an IC device according to any of Examples D1-D3, wherein an overlap of a first stacked via pair is greater than an overlap of each stacked via pair that is a nearest neighbor of the first stacked via pair.

[0285] Example D5 provides an IC device according to Example D4, wherein an overlap of at least one stacked via pair that is a nearest neighbor of a first stacked via pair is greater than an overlap of at least one stacked via pair that is a second nearest neighbor of the first stacked via pair.

[0286] Example D6 provides an IC device according to any of Examples D1-D5, wherein an overlap of at least two stacked via pairs that are nearest neighbors of a first stacked via pair is greater than an overlap of at least two stacked via pairs that are second nearest neighbors of the first stacked via pair.

[0287] Example D7 provides an IC device according to any of Examples D1-D6, wherein for each stacked via pair, the first via is between a terminal and the second via.

[0288] Example D8 provides an IC device according to any one of Examples D1-D7, wherein the second through holes of the array of stacked through hole pairs are arranged in rows and columns, and for each row, the distances between the nearest neighbor second through holes of different pairs in the row are substantially the same, and for each column, the distances between the nearest neighbor second through holes of different pairs in the column are substantially the same.

[0289] Example D9 provides an IC device according to Example D8, wherein for each row, the second vias of the row are aligned along a single line, and for each column, the second vias of the column are aligned along a single line.

[0290] Example D10 provides an IC device according to any one of Examples D1-D9, further including a plurality of non-angled structures (e.g., non-angled elongated semiconductor structures 304) provided above the array of stacked through-hole pairs, wherein individual ones of the plurality of non-angled structures include semiconductor material and are elongated structures having a longitudinal axis substantially parallel to a supporting structure and parallel or perpendicular to an edge of the supporting structure (the same edge as in Example 1); and a plurality of additional IC components based on the plurality of non-angled structures, the plurality of additional IC components having a plurality of additional terminals, wherein one or more second through-holes of the array of stacked through-hole pairs are electrically coupled to the one or more additional terminals.

[0291] Example E1 provides an IC device according to any of the preceding Examples A, B, C, or D, wherein the IC device includes or is a part of a central processing unit.

[0292] Example E2 provides an IC device according to any of the foregoing examples A, B, C, or D, wherein the IC device includes or is a portion of a memory device, such as a high bandwidth memory device.

[0293] Example E3 provides an IC device according to any of the preceding examples A, B, C, or D, wherein the IC device further includes a plurality of memory cells, each memory cell including a storage element.

[0294] Example E4 provides an IC device according to Example E3, wherein the storage element is one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance change material.

[0295] Example E5 provides an IC device according to any of the preceding Examples A, B, C, or D, wherein the IC device includes or is part of a logic circuit.

[0296] Example E6 provides an IC device according to any of the preceding Examples A, B, C, or D, wherein the IC device includes or is part of an input / output circuit.

[0297] Example E7 provides an IC device according to any of the preceding Examples A, B, C, or D, wherein the IC device includes or is part of an FPGA transceiver.

[0298] Example E8 provides an IC device according to any of the foregoing examples A, B, C, or D, wherein the IC device includes FPGA logic or is part of FPGA logic.

[0299] Example E9 provides an IC device according to any of the preceding Examples A, B, C, or D, wherein the IC device includes or is part of a power delivery circuit.

[0300] Example E10 provides an IC device according to any of the preceding Examples A, B, C, or D, wherein the IC device includes or is part of a III-V amplifier.

[0301] Example E11 provides an IC device according to any of the foregoing examples A, B, C, or D, wherein the IC device includes a PCIE circuit or a DDR transmission circuit or is a part of a PCIE circuit or a DDR transmission circuit.

[0302] Example E12 provides an IC package including an IC device according to any of the foregoing Examples A, B, C, D, or E; and an additional IC component coupled to the IC die.

[0303] Example E13 provides the IC package according to Example E12, wherein the additional IC component includes one of a package substrate, an interposer, or an additional IC die.

[0304] Example E14 provides a computing device comprising a carrier substrate and an IC device coupled to the carrier substrate, wherein the IC device is an IC device according to any of the aforementioned examples A, B, C, D or E, or the IC device is included in an IC package according to any of examples E12-E13.

[0305] Example E15 provides a computing device according to Example E14, wherein the computing device is a wearable or handheld computing device.

[0306] Example E16 provides a computing device according to Example E14 or E15, wherein the computing device further includes one or more communication chips and an antenna.

[0307] Example E17 provides a computing device according to any of Examples E14-E16, wherein the carrier substrate is a motherboard.

[0308] Example E18 provides a method of manufacturing an IC device, the method comprising providing an IC device according to any of the preceding examples.

Claims

1. An integrated circuit (IC) device, comprising: Support structure; a plurality of angled structures on the support structure, wherein individual angled structures of the plurality of angled structures comprise semiconductor material and have a longitudinal axis that is substantially parallel to the support structure and is angled between 10 degrees and 80 degrees relative to an edge of the support structure; A plurality of IC components based on a plurality of angled structures, the plurality of IC components having a plurality of terminals; as well as An array of stacked via pairs, comprising a first stacked via pair, a second stacked via pair, and a third stacked via pair, each stacked via pair comprising: a first through hole electrically coupled to a different one of the terminals, and a second via stacked over and electrically coupled to the first via, Wherein an overlap between the first through hole and the second through hole of the first stacked through hole pair is greater than an overlap of the second stacked through hole pair and an overlap of the third stacked through hole pair, and wherein the second stacked through hole pair and the third stacked through hole pair are located on opposite sides of the first stacked through hole pair. 2 . The IC device of claim 1 , wherein the overlap of the first stacked via pair is the largest among all stacked via pairs of the array. 3 . The IC device of claim 1 , wherein the overlap decreases radially outward from the first stacked via pair. 4 . The IC device of claim 1 , wherein an overlap of a first stacked via pair is greater than an overlap of each stacked via pair that is a nearest neighbor of the first stacked via pair. 5 . The IC device of claim 4 , wherein an overlap of at least one stacked via pair that is a nearest neighbor of a first stacked via pair is greater than an overlap of at least one stacked via pair that is a second nearest neighbor of the first stacked via pair.

6. The IC device of any one of claims 1-5, wherein an overlap of at least two stacked via pairs that are nearest neighbors of a first stacked via pair is greater than an overlap of at least two stacked via pairs that are second nearest neighbors of the first stacked via pair.

7. The IC device of any one of claims 1-5, wherein for each stacked via pair, a first via is between a terminal and a second via.

8. The IC device according to any one of claims 1 to 5, wherein: The second vias of the array of stacked via pairs are arranged in rows and columns, For each row, the distances between the nearest neighbor second through holes of different pairs in the row are substantially the same, and For each column, the distances between different pairs of nearest neighbor second through holes in the column are substantially the same.

9. The IC device of claim 8, wherein: For each row, the second vias of that row are aligned along a single line, and For each column, the second through-holes of that column are aligned along a single line.

10. The IC device according to any one of claims 1 to 5, further comprising: a plurality of non-angled structures overlying the array of stacked via pairs, wherein individual non-angled structures of the plurality of non-angled structures comprise semiconductor material and are elongated structures having a longitudinal axis substantially parallel to the support structure and parallel or perpendicular to an edge of the support structure; as well as a plurality of additional IC components based on the plurality of non-angled structures, the plurality of additional IC components having a plurality of additional terminals, One or more second vias of the array of stacked via pairs are electrically coupled to one or more further terminals.

11. An integrated circuit (IC) device comprising: substrate; as well as a first angled structure and a second angled structure on the substrate, in: Each of the first angled structure and the second angled structure includes a first end, a second end opposite the first end, and a longitudinal axis extending between the first end and the second end, A longitudinal axis of each of the first angled structure and the second angled structure is at an angle between 10 degrees and 80 degrees relative to an edge of the substrate, and The longitudinal axis of the first angled structure and the longitudinal axis of the second angled structure are a shared longitudinal axis.

12. The IC device of claim 11, wherein: The first end of the first angled structure is opposite to the second end of the second angled structure, and Each of a projection of a first end of the first angled structure onto a plane parallel to the substrate and a projection of a second end of the second angled structure onto the plane is a straight line. 13 . The IC device of claim 12 , wherein a straight line of a projection of a first end of a first angled structure onto the plane is parallel to a straight line of a projection of a second end of a second angled structure onto the plane.

14. The IC device of claim 12, wherein at least one of a straight line of a projection of a first end of the first angled structure on the plane and a straight line of a projection of a second end of the second angled structure on the plane is at an angle between 10 degrees and 80 degrees relative to an edge of the substrate.

15. The IC device of claim 11, wherein: The first end of the first angled structure is opposite to the second end of the second angled structure, and Each of a projection of a first end of the first angled structure onto a plane parallel to the substrate and a projection of a second end of the second angled structure onto the plane is a curved line. 16 . The IC device of claim 15 , wherein a curve of a projection of a first end of the first angled structure on the plane and a curve of a projection of a second end of the second angled structure on the plane are portions of an ellipse or an oval.

17. The IC device of any one of claims 11-16, wherein the first angled structure and the second angled structure are fins or nanoribbons of one or more semiconductor materials.

18. The IC device of any one of claims 11-16, further comprising a transistor on the substrate, wherein: The transistor includes a source region, a drain region, and a channel region between the source region and the drain region. The line between the source region and the drain region of the transistor is the shared vertical axis, and A channel region of the transistor includes semiconductor material in a first angled structure.

19. An integrated circuit (IC) device comprising: Support structure; An elongated structure of semiconductor material on a support structure; as well as Another structure of semiconductor materials, in: The distance between the elongated structure and the other structure is between about 3 nanometers and 1000 nanometers. The projection of the elongated structure on the supporting structure is substantially rectangular, and In addition, the projection of the structure on the supporting structure is a curve.

20. The IC device of claim 19, wherein: The rectangle has a first dimension in a first direction and a second dimension in a second direction, the first direction being perpendicular to the second direction, The first dimension is greater than the second dimension, The curved line has a portion extending along the first direction, and a size of the portion of the curved line in the first direction is less than 10% of the first size.

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