Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device is provided with: a metal oxide layer that is provided on an insulating surface and has aluminum as a main component; an oxide semiconductor layer disposed over the metal oxide layer; a gate electrode facing the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The water contact angle of the upper surface of the metal oxide layer is 20 DEG or less.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, one embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel and a method for manufacturing the semiconductor device. Background Art

[0002] In recent years, the development of semiconductor devices that use oxide semiconductors for channels instead of amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon has been continuously advanced (e.g., Patent Documents 1 to 6). Semiconductor devices that use oxide semiconductors in channels can be formed with a simple structure and by a low-temperature process, just like semiconductor devices that use amorphous silicon in channels. It is known that semiconductor devices that use oxide semiconductors in channels have higher mobility than semiconductor devices that use amorphous silicon in channels.

[0003] In order to make a semiconductor device using an oxide semiconductor in a channel operate stably, it is important to supply oxygen to the oxide semiconductor layer in its manufacturing process to reduce oxygen vacancies formed in the oxide semiconductor layer. For example, as one method of supplying oxygen to the oxide semiconductor layer, a technology of forming an insulating layer covering the oxide semiconductor layer under the condition that the insulating layer contains more oxygen is disclosed.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0007] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0008] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0009] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0010] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0011] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0012] Problems to be solved by the invention

[0013] However, the insulating layer formed under the condition of containing more oxygen will contain many defects. Under its influence, abnormal characteristics of the semiconductor device or characteristic changes in reliability tests may occur, which are believed to be caused by the capture of electrons in the defects. On the other hand, if an insulating layer with fewer defects is used, the oxygen contained in the insulating layer cannot be increased. Therefore, oxygen cannot be fully supplied from the insulating layer to the oxide semiconductor layer. In this way, it is required to realize a structure that can reduce the defects in the insulating layer that cause the characteristic changes of the semiconductor device and at the same time repair the oxygen deficiencies formed in the oxide semiconductor layer.

[0014] In addition, by relatively increasing the ratio of indium contained in the oxide semiconductor layer, a semiconductor device with high mobility can be obtained. However, when the ratio of indium contained in the oxide semiconductor layer is high, oxygen vacancies are easily formed in the oxide semiconductor layer. Therefore, in order to achieve high mobility while maintaining high reliability, it is necessary to work on the structure of the insulating layer around the oxide semiconductor layer.

[0015] An object of one embodiment of the present invention is to realize a semiconductor device with high reliability and high mobility.

[0016] Means for solving problems

[0017] A semiconductor device involved in one embodiment of the present invention comprises: a metal oxide layer arranged on an insulating surface and mainly composed of aluminum; an oxide semiconductor layer arranged on the metal oxide layer; a gate electrode opposite to the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein the water contact angle of the upper surface of the metal oxide layer is less than 20°.

[0018] In a method for manufacturing a semiconductor device according to an embodiment of the present invention, a metal oxide layer mainly composed of aluminum is formed on an insulating surface, and the surface of the metal oxide layer is subjected to plasma treatment in such a manner that the water contact angle of the surface of the metal oxide layer becomes 20° or less. An oxide semiconductor layer is formed on the surface subjected to surface modification, a gate insulating layer is formed on the oxide semiconductor layer, and a gate electrode is formed on the gate insulating layer to be opposed to the oxide semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present invention.

[0020] Figure 2 It is a plan view schematically showing a semiconductor device according to an embodiment of the present invention.

[0021] Figure 3It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0022] Figure 4 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0023] Figure 5 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0024] Figure 6 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0025] Figure 7 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0026] Figure 8 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0027] Fig. 9 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0028] Fig.10 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0029] Fig.11 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0030] Fig.12 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Fig.13 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0032] Fig.14 It is a flowchart showing a method for manufacturing a semiconductor device according to a modification of one embodiment of the present invention.

[0033] Fig.15 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a modification example of one embodiment of the present invention.

[0034] Fig.16 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a modification example of one embodiment of the present invention.

[0035] Fig.17It is a cross-sectional view schematically showing a semiconductor device according to a modified example of one embodiment of the present invention.

[0036] Fig.18 It is a flowchart showing a method for manufacturing a semiconductor device according to a modification of one embodiment of the present invention.

[0037] Fig.19 It is a cross-sectional view schematically showing a semiconductor device according to a modified example of one embodiment of the present invention.

[0038] Fig. 20 It is a plan view schematically showing a semiconductor device according to a modified example of one embodiment of the present invention.

[0039] Fig.21 It is a flowchart showing a method for manufacturing a semiconductor device according to a modification of one embodiment of the present invention.

[0040] Fig. 22 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a modification example of one embodiment of the present invention.

[0041] Fig.23 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a modification example of one embodiment of the present invention.

[0042] Fig.24 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0043] Fig.25 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0044] Fig.26 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0045] Fig. 27 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0046] Fig.28 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0047] Fig.29 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0048] Fig.30 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0049] Fig.31It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0050] Fig.32 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0051] Fig.33 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0052] Fig.34 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0053] Fig.35 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0054] Fig.36 It is a plan view schematically showing a display device according to one embodiment of the present invention.

[0055] Fig.37 This is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention.

[0056] Fig.38 : is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention.

[0057] Fig.39 It is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0058] Fig.40 It is a plan view of a pixel electrode and a common electrode of a display device according to an embodiment of the present invention.

[0059] Fig.41 : is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention.

[0060] Fig.42 It is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0061] Fig.43 This is a diagram showing the results of XPS analysis of the surface of the metal oxide layer by plasma treatment.

[0062] Fig.44 This is a diagram showing the reliability test results of the semiconductor device to which condition 1 was applied.

[0063] Fig.45 This is a diagram showing the reliability test results of the semiconductor device to which condition 2 was applied.

[0064] Fig.46 This is a diagram showing the reliability test results of the semiconductor device to which condition 3 was applied.

[0065] Fig.47 This is a diagram showing the reliability test results of the semiconductor device to which condition 4 was applied.

[0066] Fig.48 This is a diagram showing the reliability test results of the semiconductor device to which condition 5 was applied. DETAILED DESCRIPTION

[0067] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is of course included in the scope of the present invention. In order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically indicated in the accompanying drawings compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and each figure, the same figure mark is marked for the same configuration as that described in the accompanying drawings that have appeared, and the detailed description is sometimes appropriately omitted.

[0068] "Semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are a form of semiconductor devices. The semiconductor device of the embodiment shown below may also be a transistor used in an integrated circuit (IC) such as a display device, a microprocessor (MPU), or a memory circuit.

[0069] A "display device" refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure that is equipped with other optical components (such as polarization components, backlight sources, touch panels, etc.) relative to a display unit. As long as there is no technical contradiction, the "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described later, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified for explanation, but the structure in this embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0070] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for ease of explanation, the above or below phrases are used for explanation, but for example, the up-and-down relationship between the substrate and the oxide semiconductor layer may be configured in a different direction than that shown in the figure. In the following description, for example, the expression "oxide semiconductor layer on the substrate" is only used to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. Above or below means the stacking order in a structure having multiple layers stacked, and in the case of a pixel electrode described as above a transistor, it may also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of a pixel electrode described as vertically above a transistor, it means a positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0071] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a combination of multiple elements of A to C. In addition, the above expressions do not exclude the case where α includes other elements.

[0072] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0073] <First Embodiment>

[0074] use Figures 1 to 13 A semiconductor device 10 according to an embodiment of the present invention will be described.

[0075] [Configuration of Semiconductor Device 10]

[0076] use Figure 1 and Figure 2 The configuration of a semiconductor device 10 according to an embodiment of the present invention will be described. Figure 1 It is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present invention. Figure 2 It is a plan view schematically showing a semiconductor device according to an embodiment of the present invention.

[0077] like Figure 1As shown, the semiconductor device 10 is provided on a substrate 100. The semiconductor device 10 includes a gate electrode 105, gate insulating layers 110 and 120, a metal oxide layer 130 (also referred to as a metal oxide layer), an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished, they are sometimes collectively referred to as the source electrode or the drain electrode 200.

[0078] The gate electrode 105 is provided on the substrate 100. The gate insulating layer 110 and the gate insulating layer 120 are provided on the substrate 100 and the gate electrode 105. The metal oxide layer 130 is provided on the gate insulating layer 120. The metal oxide layer 130 is in contact with the gate insulating layer 120. The oxide semiconductor layer 140 is provided on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. The surface of the main surface of the oxide semiconductor layer 140 that is in contact with the metal oxide layer 130 is referred to as a lower surface 142. The end of the metal oxide layer 130 is substantially consistent with the end of the oxide semiconductor layer 140.

[0079] In this embodiment, no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 130 and the substrate 100 .

[0080] In this embodiment, the metal oxide layer 130 is connected to the gate insulating layer 120, and the oxide semiconductor layer 140 is connected to the metal oxide layer 130. However, the present invention is not limited to this structure. Other layers may be provided between the gate insulating layer 120 and the metal oxide layer 130. Other layers may also be provided between the metal oxide layer 130 and the oxide semiconductor layer 140.

[0081] exist Figure 1 In the embodiment, the side wall of the metal oxide layer 130 and the side wall of the oxide semiconductor layer 140 are arranged in a straight line, but the present invention is not limited to this configuration. The angle of the side wall of the metal oxide layer 130 relative to the main surface of the substrate 100 may be different from the angle of the side wall of the oxide semiconductor layer 140 relative to the main surface of the substrate 100. The cross-sectional shape of the side wall of at least one of the metal oxide layer 130 and the oxide semiconductor layer 140 may be curved.

[0082] The gate electrode 160 is opposite to the oxide semiconductor layer 140. The gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. The surface in contact with the gate insulating layer 150 among the main surfaces of the oxide semiconductor layer 140 is referred to as an upper surface 141. The surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143. The insulating layers 170 and 180 are provided on the gate insulating layer 150 and the gate electrode 160. The insulating layers 170 and 180 are provided with openings 171 and 173 reaching the oxide semiconductor layer 140. The source electrode 201 is provided inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0083] The gate electrode 105 has a function as a bottom gate of the semiconductor device 10 and a function as a light shielding film for the oxide semiconductor layer 140. The gate insulating layer 110 has a function as a barrier film for shielding impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The gate insulating layers 110 and 120 have a function as a gate insulating layer for the bottom gate. The metal oxide layer 130 is a layer containing a metal oxide mainly composed of aluminum, and has a function as a gas barrier film for shielding gases such as oxygen and hydrogen.

[0084] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is a region vertically below the gate electrode 160 in the oxide semiconductor layer 140. The source region S is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 140 in the channel region CH has physical properties as a semiconductor. The oxide semiconductor layer 140 in the source region S and the drain region D has physical properties as a conductor.

[0085] The gate electrode 160 has the function of serving as the top gate of the semiconductor device 10 and as a light shielding film for the oxide semiconductor layer 140. The gate insulating layer 150 has the function of serving as a gate insulating layer for the top gate and has the function of releasing oxygen through heat treatment in the manufacturing process. The insulating layers 170 and 180 have the function of insulating the gate electrode 160 from the source electrode or the drain electrode 200 to reduce the parasitic capacitance between the two. The operation of the semiconductor device 10 is mainly controlled by the voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. However, in the case where the gate electrode 105 is used only as a light shielding film, it is also possible to place the gate electrode 105 in a floating state instead of supplying a specific voltage to the gate electrode 105. That is, the gate electrode 105 may also be simply referred to as a "light shielding film".

[0086] In this embodiment, a dual-gate transistor in which gate electrodes are provided both above and below the oxide semiconductor layer is used as an example of the semiconductor device 10, but the present invention is not limited to this configuration. For example, a bottom-gate transistor in which the gate electrode is provided only below the oxide semiconductor layer or a top-gate transistor in which the gate electrode is provided only above the oxide semiconductor layer may be used as the semiconductor device 10. The above configuration is only one embodiment, and the present invention is not limited to the above configuration.

[0087] like Figure 2 As shown, in a top view, the top view pattern of the metal oxide layer 130 is substantially the same as the top view pattern of the oxide semiconductor layer 140. Figure 1 and Figure 2 , the lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130. In particular, in the present embodiment, the lower surface 142 of the oxide semiconductor layer 140 is entirely covered by the metal oxide layer 130. In the first direction D1, the width of the gate electrode 105 is greater than the width of the gate electrode 160. The first direction D1 is a direction connecting the source electrode 201 and the drain electrode 203, and is a direction indicating the channel length L of the semiconductor device 10. Specifically, the length in the first direction D1 of the region (channel region CH) where the oxide semiconductor layer 140 overlaps with the gate electrode 160 is the channel length L, and the width in the second direction D2 of the channel region CH is the channel width W.

[0088] In this embodiment, a configuration in which the entire lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130 is exemplified, but the present invention is not limited to this configuration. For example, a portion of the lower surface 142 of the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. For example, the entire lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may be covered by the metal oxide layer 130, and the entire or a portion of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be covered by the metal oxide layer 130. That is, the entire or a portion of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be in contact with the metal oxide layer 130. However, in the above configuration, a portion of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may not be covered by the metal oxide layer 130, and the other portion of the lower surface 142 may be in contact with the metal oxide layer 130.

[0089] In this embodiment, a configuration in which the gate insulating layer 150 is formed on the entire surface and the openings 171 and 173 are provided in the gate insulating layer 150 is exemplified, but the present invention is not limited to this configuration. The gate insulating layer 150 may also be patterned. For example, the gate insulating layer 150 may be patterned in such a manner that the oxide semiconductor layer 140 in the source region S and the drain region D is exposed. That is, the gate insulating layer 150 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 140 may be in contact with the insulating layer 170 in these regions.

[0090] exist Figure 2 , a configuration in which the source electrode or drain electrode 200 does not overlap with the gate electrode 105 and the gate electrode 160 in a plan view is illustrated, but the present invention is not limited to this configuration. For example, the source electrode or drain electrode 200 may overlap with at least one of the gate electrode 105 and the gate electrode 160 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0091] [Material of Each Component of Semiconductor Device 10]

[0092] As the substrate 100, a glass substrate, a quartz substrate, a sapphire substrate, or other light-transmitting rigid substrate can be used. When the substrate 100 needs to be flexible, a substrate containing resin such as a polyimide substrate, an acrylic substrate, a siloxane-based substrate, or a fluororesin substrate can be used as the substrate 100. When a substrate containing resin is used as the substrate 100, impurities can be introduced into the above-mentioned resin in order to improve the heat resistance of the substrate 100. In particular, when the semiconductor device 10 is a top-emitting display, since the substrate 100 does not need to be transparent, impurities that reduce the transparency of the substrate 100 can also be used. When the semiconductor device 10 is used in an integrated circuit that is not a display device, a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a substrate that is not light-transmitting such as a conductive substrate such as a stainless steel substrate can be used as the substrate 100.

[0093] As the gate electrode 105, the gate electrode 160, and the source electrode or the drain electrode 200, a common metal material can be used. For example, as these members, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys thereof or compounds thereof can be used. As the gate electrode 105, the gate electrode 160, and the source electrode or the drain electrode 200, the above-mentioned materials can be used in a single layer form, or in a stacked form.

[0094] As the gate insulating layers 110, 120 and the insulating layers 170, 180, a common insulating material can be used. For example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers.

[0095] As the gate insulating layer 150, an insulating layer containing oxygen among the above insulating layers is used. For example, as the gate insulating layer 150, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x), aluminum oxide nitride (AlO x N y ) and other inorganic insulating layers.

[0096] An insulating layer having a function of releasing oxygen by heat treatment is used as the gate insulating layer 120. For example, the temperature of the heat treatment for releasing oxygen from the gate insulating layer 120 is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, for example, when a glass substrate is used as the substrate 100, the gate insulating layer 120 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10.

[0097] As the gate insulating layer 150, an insulating layer with few defects is used. For example, when the composition ratio of oxygen in the gate insulating layer 150 is compared with the composition ratio of oxygen in an insulating layer having the same composition as the gate insulating layer 150 (hereinafter referred to as "another insulating layer"), the composition ratio of oxygen in the gate insulating layer 150 is closer to the stoichiometric ratio with respect to the insulating layer than the composition ratio of oxygen in the other insulating layer. Specifically, silicon oxide (SiO x ), the oxygen composition ratio of silicon oxide used as the gate insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio of silicon oxide used as the insulating layer 180. For example, as the gate insulating layer 150, a layer in which no defects are observed when evaluated by an electron spin resonance method (ESR) may be used.

[0098] The above SiO x N y and AlO x N y It is a silicon compound or aluminum compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y and AlN x O y These are silicon compounds and aluminum compounds containing oxygen at a ratio smaller than that of nitrogen (x>y).

[0099] As the metal oxide layer 130, a metal oxide containing aluminum as a main component can be used. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x) or other inorganic insulating layers. The so-called “metal oxide layer with aluminum as the main component” means that the ratio of aluminum contained in the metal oxide layer 130 is greater than 1% of the entire metal oxide layer 130. The ratio of aluminum contained in the metal oxide layer 130 may also be greater than 5% and less than 70%, greater than 10% and less than 60%, or greater than 30% and less than 50% of the entire metal oxide layer 130. The above ratio may be a mass ratio or a weight ratio.

[0100] As the oxide semiconductor layer 140, a metal oxide having semiconductor properties can be used. For example, as the oxide semiconductor layer 140, an oxide semiconductor containing two or more metals including indium (In) is used. The ratio of indium to the entire oxide semiconductor layer 140 is 50% or more. As the oxide semiconductor layer 140, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium oxide (Zr), and lanthanide elements can also be used. As the oxide semiconductor layer 140, elements other than the above can also be used.

[0101] In this embodiment, the oxide semiconductor layer 140 has a polycrystalline structure. That is, the oxide semiconductor layer 140 of this embodiment is composed of an oxide semiconductor formed using poly-OS (Poly-crystalline Oxide Semiconductor) technology. The poly-OS technology refers to a technology for forming an oxide semiconductor layer having a polycrystalline structure. In this embodiment, as described later, the oxide semiconductor layer 140 formed by sputtering is heat-treated, thereby crystallizing the oxide semiconductor layer 140.

[0102] [Problems Newly Recognized in the Process of Arriving at the Present Invention]

[0103] The high-mobility semiconductor device 10 is realized by setting the ratio of indium in the oxide semiconductor layer 140 to 50% or more. On the other hand, in such an oxide semiconductor layer 140 , oxygen contained in the oxide semiconductor layer 140 is easily reduced, so that oxygen vacancies are easily formed in the oxide semiconductor layer 140 .

[0104] In the semiconductor device 10, hydrogen is released from a layer (e.g., gate insulating layers 110 and 120) disposed closer to the substrate 100 than the oxide semiconductor layer 140 during a heat treatment process in the manufacturing process. Since the hydrogen reaches the oxide semiconductor layer 140, oxygen vacancies are generated in the oxide semiconductor layer 140. The generation of the oxygen vacancies is more significant when the pattern size of the oxide semiconductor layer 140 is larger. In order to suppress the generation of such oxygen vacancies, it is necessary to suppress the hydrogen from reaching the lower surface 142 of the oxide semiconductor layer 140. The above content is the first subject.

[0105] In addition to the above-mentioned problems, there is a second problem as shown below. The upper surface 141 of the oxide semiconductor layer 140 is affected by the process (e.g., patterning process or etching process) after the oxide semiconductor layer 140 is formed. On the other hand, the lower surface 142 of the oxide semiconductor layer 140 (the surface of the oxide semiconductor layer 140 on the substrate 100 side) is not affected as described above.

[0106] Therefore, the oxygen vacancies formed near the upper surface 141 of the oxide semiconductor layer 140 are more than the oxygen vacancies formed near the lower surface 142 of the oxide semiconductor layer 140. That is, the oxygen vacancies in the oxide semiconductor layer 140 are not uniformly present in the thickness direction of the oxide semiconductor layer 140, but are unevenly distributed in the thickness direction of the oxide semiconductor layer 140. Specifically, the oxygen vacancies in the oxide semiconductor layer 140 are less toward the lower surface 142 of the oxide semiconductor layer 140, and more toward the upper surface 141 of the oxide semiconductor layer 140.

[0107] In the case where the oxygen supply treatment is uniformly performed on the oxide semiconductor layer 140 having the above-described oxygen vacancy distribution, if the amount of oxygen required to repair the oxygen vacancy formed on the upper surface 141 side of the oxide semiconductor layer 140 is supplied, oxygen will be excessively supplied to the lower surface 142 side of the oxide semiconductor layer 140. As a result, on the lower surface 142 side, a defect energy level different from the oxygen vacancy is formed due to the excess oxygen. As a result, phenomena such as characteristic changes in reliability tests or a decrease in field effect mobility occur. Therefore, in order to suppress such a phenomenon, it is necessary to supply oxygen to the upper surface 141 side of the oxide semiconductor layer 140 while suppressing the oxygen supply to the lower surface 142 side of the oxide semiconductor layer 140.

[0108] The above-mentioned problems are newly recognized problems in the process of reaching the present invention, and are not problems that have been recognized in the past. In the previous structure and manufacturing method, even if the initial characteristics of the semiconductor device are improved by oxygen supply treatment to the oxide semiconductor layer, the characteristics change in the reliability test, and there is a trade-off relationship between the initial characteristics and the reliability test. However, the structure involved in this embodiment can solve the above-mentioned problems and obtain good initial characteristics and high reliability of the semiconductor device 10.

[0109] In addition, the surface of the film-forming oxide semiconductor layer 140 is a region close to the back channel in the transistor. That is, the region at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 affects the electrical characteristics of the transistor. Therefore, with respect to the surface of the metal oxide layer 130 forming the film-forming oxide semiconductor layer 140, it is more preferable that oxygen vacancies, hydrogen, etc., which adversely affect the electrical characteristics of the transistor, are reduced.

[0110] However, the metal oxide layer just after film formation by sputtering becomes a state with surface unevenness, and hydrogen bonding is easily caused by the influence of surface energy. Therefore, if an oxide semiconductor layer is formed on the metal oxide layer just after film formation, hydrogen will remain at the interface between the metal oxide layer and the oxide semiconductor layer. In addition, when the oxide semiconductor layer is formed, oxygen vacancies are easily generated. In this way, the oxygen vacancies and hydrogen present at the interface are difficult to remove even through subsequent annealing. If oxygen vacancies and hydrogen remain at the interface, the interface energy level density increases. In addition, the main reason for the reduction in the reliability of semiconductor devices is that electrons are captured by the interface energy level, resulting in, for example, transistor degradation based on reliability tests. In this way, there is room for further improvement in order to improve the reliability of semiconductor devices.

[0111] In one embodiment of the present invention, the upper surface of the metal oxide layer 130 is modified at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. The oxide semiconductor layer 140 is formed on the modified upper surface of the metal oxide layer 130, which will be described later. The water contact angle of the upper surface of the metal oxide layer 130 is 20° or less, preferably 15° or less, and more preferably 10° or less.

[0112] By having such a structure, the hydrogen and oxygen deficiencies of the oxide semiconductor layer 140 can be reduced at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. In particular, when the oxide semiconductor layer 140 having a relatively high indium ratio is used, the formation of oxygen deficiencies at the interface can also be suppressed. Therefore, the crystallinity of the oxide semiconductor layer 140 disposed on the metal oxide layer 130 is improved, and a polycrystalline with reduced defects can be formed. As a result, the field effect mobility of the semiconductor device 10 can be further improved. Specifically, the field effect mobility of the semiconductor device 10 can be set to 40 cm 2 / V·s or more. In addition, by suppressing the degradation of the transistors in the reliability test, the reliability of the semiconductor device is improved.

[0113] Here, the reliability test refers to, for example, an NGBT (Negative Gate Bias-Temperature) stress test in which a negative voltage is applied to the gate, or a PGBT (Positive Gate Bias-Temperature) stress test in which a positive voltage is applied to the gate. It should be noted that BT stress tests such as NGBT and PGBT are a type of accelerated test that can evaluate the characteristic changes (year-to-year changes) of transistors caused by long-term use in a short period of time. In particular, the change in the threshold voltage of the transistor before and after the BT stress test becomes an important indicator for studying reliability. It can be said that the smaller the change in the threshold voltage before and after the BT stress test, the more reliable the transistor is.

[0114] [Method of Manufacturing Semiconductor Device 10]

[0115] use Figure 3 to Figure 13 A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. Figure 3 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 4 to 13 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the following description of the manufacturing method, a method for manufacturing the semiconductor device 10 using aluminum oxide as the metal oxide layer 130 will be described.

[0116] like Figure 3 and Figure 4 As shown, a gate electrode 105 is formed on the substrate 100 as a bottom gate, and gate insulating layers 110 and 120 are formed on the gate electrode 105 ( Figure 3 The bottom GI / GE formation of step S1001 is performed. For example, silicon nitride is formed as the gate insulating layer 110. For example, silicon oxide is formed as the gate insulating layer 120. The gate insulating layers 110 and 120 are formed by CVD (Chemical Vapor Deposition).

[0117] By using silicon nitride as the gate insulating layer 110, the gate insulating layer 110 can block, for example, impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. Silicon oxide used as the gate insulating layer 120 has a property of releasing oxygen by heat treatment.

[0118] like Figure 3 and Figure 5 As shown, a metal oxide layer 130 is formed on the gate insulating layer 120 ( Figure 3The metal oxide layer 130 is formed by sputtering or atomic layer deposition (ALD: Atomic Layer Deposition).

[0119] The thickness of the metal oxide layer 130 during film formation is, for example, 2 nm to 51 nm, 2 nm to 31 nm, 2 nm to 21 nm or 2 nm to 11 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 130. Aluminum oxide has a high barrier property against gases such as oxygen or hydrogen. In other words, barrier property refers to the function of inhibiting the permeation of gases such as oxygen or hydrogen through aluminum oxide. That is, it means that even if gases such as oxygen or hydrogen exist from a layer disposed below the aluminum oxide layer, they will not move to a layer disposed above the aluminum oxide layer. Alternatively, it means that even if gases such as oxygen or hydrogen exist from a layer disposed above the aluminum oxide layer, they will not move to a layer disposed below the aluminum oxide layer. The metal oxide layer 130 is formed by sputtering. In this embodiment, aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the gate insulating layer 120, and inhibits the released hydrogen and oxygen from reaching the oxide semiconductor layer 140.

[0120] like Figure 3 and Figure 6 As shown, the metal oxide layer 130 is subjected to plasma treatment ( Figure 3 "AlOx plasma treatment" in step S1003).

[0121] In this specification, plasma treatment refers to a process in which a substrate to be treated is exposed to plasma by generating plasma in a space where the substrate to be treated is placed. Plasma treatment is performed, for example, by reverse sputtering using a sputtering device or etching using an inductively coupled plasma (ICP) device.

[0122] As a gas for generating plasma, it is preferred to use a gas that will not affect the physical properties of the oxide semiconductor layer 140 formed on the aluminum oxide layer. As a gas for plasma treatment, for example, a rare gas such as helium (He), neon (Ne), argon (Ar), krypton (Kr) or xenon (Xe) is used. As long as it does not affect the physical properties of the oxide semiconductor layer 140, the following gases may also be used. In the case of plasma treatment by reverse sputtering, oxygen gas may be used, or a mixed gas of oxygen gas and an inert gas may be used. Alternatively, in the case of plasma treatment by etching, halogen-based gases such as chlorine-based gases and fluorine-based gases may also be used. In this embodiment, the case of using argon gas in plasma treatment is described.

[0123] Reverse sputtering is a process in which a voltage is applied to the substrate side using an RF power supply in an argon atmosphere without applying a voltage to the target side, thereby forming plasma near the substrate and causing ions to collide with the surface of the substrate to modify the surface. When reverse sputtering is used for plasma processing, for example, before forming the oxide semiconductor layer 140 by sputtering, argon gas is introduced into the chamber to generate plasma.

[0124] As specific conditions for reverse sputtering, the upper / lower electrode side output is set to 25W to 270W under appropriate upper / lower RF power supply and in a vacuum environment, the temperature is set to 0°C to 100°C, the vacuum degree in the processing chamber is not excessively reduced, and the argon gas flow rate is set to be sufficient to generate plasma well, the surface of the aluminum oxide layer can be properly processed, and it is preferably carried out within a processing time that does not cause excessive film reduction. As a specific example, if the conditions are such that the upper RF power is 400kHz, the output is 25W, the lower RF power is 13.56MHz, the output is 25W, the argon gas flow rate is 5sccm, the temperature is room temperature, and the processing time is 143 seconds, then a scraping amount of about 1nm is obtained from the surface of the aluminum oxide layer.

[0125] Etching based on inductively coupled plasma is a process that uses ions and radicals present in the plasma to modify the surface of the substrate.

[0126] As specific conditions for etching based on inductively coupled plasma, the ICP power is set to 25W to 100W, the RF bias power is set to 25W to 100W, the temperature is set to 0°C to 100°C, the vacuum degree in the processing chamber is not excessively reduced, and the argon gas flow rate is set to be sufficient for good plasma generation, and the processing time is set to 40 seconds (when the RF bias power (Source / Bias) is 100W / 100W) to 1100 seconds (when the RF bias power (Source / Bias) is 25W / 25W). As a specific example, at an ICP power of 50W (power per unit electrode area = 0.81W / cm 2 ), pressure 4Pa, argon gas flow rate 50sccm, RF bias power (Source / Bias) 50W / 50W, temperature 65°C, and processing time 400 seconds.

[0127] The surface of the metal oxide layer 130 is modified by performing plasma treatment on the metal oxide layer 130. Here, the surface modification means that the chemical composition of the surface of the metal oxide layer 130 is changed or the surface roughness of the metal oxide layer 130 is reduced.

[0128] The state of the surface-modified metal oxide layer 130 can be confirmed based on the size of the water contact angle on the surface. The surface of the metal oxide layer 130 is plasma-treated, thereby reducing the water contact angle of the metal oxide layer 130. The water contact angle of the surface of the metal oxide layer 130 after plasma treatment is less than 20°, preferably less than 15°, and more preferably less than 10°. In this specification, etc., as the water contact angle, the value measured in accordance with ISO19403-2:2017 is used. When the metal oxide layer 130 is plasma-treated by reverse sputtering, the water contact angle becomes less than 20°. In addition, when the metal oxide layer 130 is etched by inductively coupled plasma, the water contact angle becomes less than 15°. It should be noted that the lower limit of the measurement of the water contact angle is 2°.

[0129] In addition, by performing plasma treatment on the metal oxide layer 130 using argon gas, for example, Ar atoms (atomic %) are included on the surface of the metal oxide layer 130. Here, the Ar atoms (atomic %) contained in the surface of the metal oxide layer 130 means that Ar atoms are detected in the X-ray photoelectron spectroscopy (XPS: Xray Photoelector on Spectroscopy) analysis of the surface of the metal oxide layer 130, that is, it is above the detection lower limit. The Ar concentration on the surface of the metal oxide layer 130 obtained based on the XPS analysis can be above the detection lower limit, but is preferably above 1 atomic %. The upper limit of the Ar concentration on the surface of the metal oxide layer 130 is not particularly specified, but is preferably, for example, below 3 atomic %. Therefore, even if Ar atoms are included on the surface of the metal oxide layer 130, the influence on the physical properties of the oxide semiconductor layer 140 can be reduced. For example, after plasma treatment using argon gas, the Ar atoms on the surface of the metal oxide layer 130 increase by more than 1 atomic %. It should be noted that, when plasma treatment is performed using other rare gases, atoms of the rare gas used in the plasma treatment may be included on the surface of the metal oxide layer 130 .

[0130] The surface of the metal oxide layer 130 may be removed by plasma treatment. The amount of the surface of the metal oxide layer 130 removed is, for example, 1 nm to 10 nm, or 1 nm to 5 nm.

[0131] In addition, the surface roughness of the metal oxide layer 130 may be reduced by plasma treatment. The surface roughness (for example, arithmetic mean roughness (Ra)) of the metal oxide layer 130 may be set to 1 nm or less. The surface roughness can be evaluated using an atomic force microscope (AFM: Atomic Force Microscope).

[0132] The thickness of the metal oxide layer 130 after the plasma treatment is greater than or equal to 1 nm and less than or equal to 50 nm, greater than or equal to 1 nm and less than or equal to 30 nm, greater than or equal to 1 nm and less than or equal to 20 nm, or greater than or equal to 1 nm and less than or equal to 10 nm.

[0133] like Figure 3 and Figure 7 As shown, an oxide semiconductor layer 140 is formed on the metal oxide layer 130 subjected to plasma treatment ( Figure 3 "OS film formation" in step S1004).

[0134] For example, the thickness of the oxide semiconductor layer 140 is 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. In this embodiment, an oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 140. The oxide semiconductor layer 140 before the heat treatment (OS annealing) described later is in an amorphous state.

[0135] When the oxide semiconductor layer 140 is crystallized by OS annealing described later, it is preferable that the oxide semiconductor layer 140 after film formation and before OS annealing is in an amorphous state (a state in which the crystalline component of the oxide semiconductor is small). That is, the film formation conditions of the oxide semiconductor layer 140 are preferably conditions under which the oxide semiconductor layer 140 immediately after film formation is not crystallized as much as possible. For example, when the oxide semiconductor layer 140 is formed by sputtering, the oxide semiconductor layer 140 is formed under a state in which the temperature of the film formation object (the substrate 100 and the structure formed thereon) is controlled.

[0136] When a film is formed on a film-forming object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target will collide with the film-forming object. Therefore, the temperature of the film-forming object will rise along with the film-forming process. If the temperature of the film-forming object rises during the film-forming process, the oxide semiconductor layer 140 contains microcrystals in the state just after the film is formed. Due to the microcrystals, the subsequent crystallization based on OS annealing is hindered. In order to control the temperature of the film-forming object as described above, the film can also be formed while cooling the film-forming object. For example, the film-forming object can also be cooled from the opposite side of the film-forming surface in a manner such that the temperature of the film-forming surface of the film-forming object (hereinafter referred to as "film-forming temperature") is below 100°C, below 70°C, below 50°C or below 30°C. By forming the oxide semiconductor layer 140 while cooling the film-forming object as described above, the oxide semiconductor layer 140 with a small crystalline component in the state just after the film is formed can be formed.

[0137] In this embodiment, the surface of the metal oxide layer 130 is subjected to plasma treatment before the oxide semiconductor layer 140 is formed. As a result, the surface of the metal oxide layer 130 is modified. The hydroxyl group and water in the modified surface of the metal oxide layer 130 can be reduced. When the oxide semiconductor layer 140 is formed, the atoms constituting the oxide semiconductor layer 140 are easily bonded to the surface of the metal oxide layer 130, and the interface energy level density at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 can be reduced.

[0138] like Figure 3 and Figure 8 As shown, the pattern of the oxide semiconductor layer 140 is formed ( Figure 3 Although not shown in the figure, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. The oxide semiconductor layer 140 can be etched by wet etching or dry etching. As wet etching, an acidic etchant can also be used for etching. For example, oxalic acid or hydrofluoric acid can also be used as an etchant.

[0139] After the patterning of the oxide semiconductor layer 140, the oxide semiconductor layer 140 is subjected to a heat treatment (OS annealing) ( Figure 3 In this embodiment, the oxide semiconductor layer 140 is crystallized by the OS annealing.

[0140] In this embodiment, the surface of the metal oxide layer 130 is modified. An oxide semiconductor layer 140 having a small amount of crystalline components is formed on the modified surface of the metal oxide layer 130. Afterwards, when the oxide semiconductor layer 140 is crystallized by OS annealing, it is possible to suppress the crystallization from being hindered by hydroxyl groups and water at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. That is, the interface energy level density at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 can be further reduced.

[0141] like Figure 3 and Fig. 9 As shown, the pattern of the metal oxide layer 130 is formed ( Figure 3 The metal oxide layer 130 is etched using the oxide semiconductor layer 140 patterned in the above process as a mask. As the etching of the metal oxide layer 130, wet etching or dry etching can be used. As the wet etching, for example, diluted hydrofluoric acid (DHF) can be used. As described above, by etching the metal oxide layer 130 with the oxide semiconductor layer 140 as a mask, the photolithography process can be omitted.

[0142] like Figure 3 and Fig.10 As shown, the gate insulating layer 150 ( Figure 3 ("GI formation" in step S1008 of the present invention). For example, silicon oxide is formed as the gate insulating layer 150. The gate insulating layer 150 is formed by a CVD method. For example, as the gate insulating layer 150, in order to form an insulating layer with few defects as described above, the gate insulating layer 150 may be formed at a film forming temperature of 350° C. or higher. For example, the thickness of the gate insulating layer 150 is between 50 nm and 300 nm, between 60 nm and 200 nm, or between 70 nm and 150 nm. After the gate insulating layer 150 is formed, a process of injecting oxygen into a portion of the gate insulating layer 150 may be performed.

[0143] In a state where the gate insulating layer 150 is formed on the oxide semiconductor layer 140, heat treatment (oxidation annealing) for supplying oxygen to the oxide semiconductor layer 140 is performed ( Figure 3 In the process from forming the oxide semiconductor layer 140 to forming the gate insulating layer 150 on the oxide semiconductor layer 140, a large number of oxygen vacancies are generated on the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. The above-mentioned oxidation annealing allows oxygen released from the gate insulating layers 120 and 150 to be supplied to the oxide semiconductor layer 140, thereby repairing the oxygen vacancies.

[0144] Oxygen released from the gate insulating layer 120 by the oxidation annealing is blocked by the metal oxide layer 130. Therefore, it is difficult for the oxygen to be supplied to the lower surface 142 of the oxide semiconductor layer 140. The oxygen released from the gate insulating layer 120 diffuses from the region where the metal oxide layer 130 is not formed to the gate insulating layer 150 provided on the gate insulating layer 120, and reaches the oxide semiconductor layer 140 via the gate insulating layer 150. As a result, it is difficult for the oxygen released from the gate insulating layer 120 to be supplied to the lower surface 142 of the oxide semiconductor layer 140, and it is mainly supplied to the side surface 143 and the upper surface 141 of the oxide semiconductor layer 140. In addition, the oxygen released from the gate insulating layer 150 by the oxidation annealing is supplied to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. Although hydrogen may be released from the gate insulating layers 110 and 120 by the above-mentioned oxidation annealing, the hydrogen is blocked by the metal oxide layer 130.

[0145] As described above, the oxidation annealing step can suppress supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140 having a small amount of oxygen vacancies and simultaneously supply oxygen to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140 having a large amount of oxygen vacancies.

[0146] like Figure 3 and Fig.11 As shown, a gate electrode 160 ( Figure 3 The gate electrode 160 is formed by forming a conductive film by sputtering or atomic layer deposition and patterning the conductive film through a photolithography process.

[0147] In the state where the gate electrode 160 is patterned, the resistance of the source region S and the drain region D of the oxide semiconductor layer 140 is reduced ( Figure 3 Specifically, impurities are injected into the oxide semiconductor layer 140 from the gate electrode 160 side through the gate insulating layer 150 by ion implantation. For example, argon (Ar), phosphorus (P), and boron (B) are injected into the oxide semiconductor layer 140 by ion implantation. Oxygen vacancies are formed in the oxide semiconductor layer 140 by ion implantation, thereby reducing the resistance of the oxide semiconductor layer 140. Since the gate electrode 160 is provided above the oxide semiconductor layer 140 that functions as the channel region CH of the semiconductor device 10, impurities are not injected into the oxide semiconductor layer 140 in the channel region CH.

[0148] like Figure 3 and Fig.12 As shown, insulating layers 170 and 180 are formed on the gate insulating layer 150 and the gate electrode 160 as interlayer films ( Figure 3 The insulating layers 170 and 180 are formed by CVD. For example, silicon nitride is formed as the insulating layer 170, and silicon oxide is formed as the insulating layer 180. The materials used for the insulating layers 170 and 180 are not limited to the above. The thickness of the insulating layer 170 is not less than 50 nm and not more than 500 nm. The thickness of the insulating layer 180 is not less than 50 nm and not more than 500 nm.

[0149] like Figure 3 and Fig.13 As shown, openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 ( Figure 3 The oxide semiconductor layer 140 of the source region S is exposed through the opening 171. The oxide semiconductor layer 140 of the drain region D is exposed through the opening 173. The source electrode or the drain electrode 200 ( Figure 3 Step S1014 of "SD formation"), thereby completing Figure 1 A semiconductor device 10 is shown.

[0150] Thus, in the semiconductor device 10, when the channel length L of the channel region CH is within a range of 2 μm to 4 μm and the channel width of the channel region CH is within a range of 2 μm to 25 μm, a mobility of 30 cm 2 / Vs or above, 35cm 2 / Vs or more, preferably 40cm 2 / Vs or more such electrical characteristics. The mobility in this embodiment refers to the field effect mobility in the saturation region of the semiconductor device 10. Specifically, the mobility means the maximum value of the field effect mobility in the region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the semiconductor device 10 from the voltage (Vg) supplied to the gate electrode.

[0151] In the case of the top-gate transistor shown in this embodiment, the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 becomes the back channel side of the transistor. By reducing the interface energy level density at the interface on the back channel side, it is possible to suppress electrons from being captured by the interface energy level. Thus, it is possible to suppress transistor degradation based on reliability testing. That is, the reliability of the semiconductor device 10 can be improved.

[0152] <Modification 1 of the first embodiment>

[0153] use Figure 14 to Figure 16 A first modification of the present embodiment will be described. The structure of the semiconductor device 10 according to the first modification is similar to Figure 1 Same, but its manufacturing method is different from Figure 3 to Figure 13 In the following description, Figure 3 to Figure 13 Description of the steps common to the manufacturing methods shown will be omitted, and the manufacturing methods related to the differences will be mainly described.

[0154] Fig.14 It is a flowchart showing a method for manufacturing a semiconductor device according to a modification of one embodiment of the present invention. Fig.15 and Fig.16 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. Fig.14 As shown, in Modification 1, the patterns of the metal oxide layer 130 and the oxide semiconductor layer 140 are formed simultaneously (“OS / AlOx pattern formation” in step S1020 ).

[0155] like Fig.15 As shown in FIG. 2 , after the metal oxide layer 130 and the oxide semiconductor layer 140 are formed, a resist mask 220 is formed on the oxide semiconductor layer 140. Then, as shown in FIG. Fig.16As shown, the resist mask 220 is used to form a pattern of the metal oxide layer 130 and the oxide semiconductor layer 140. As the etching of the metal oxide layer 130 and the oxide semiconductor layer 140, wet etching or dry etching can be used. When the metal oxide layer 130 and the oxide semiconductor layer 140 are etched by wet etching, the same etchant as described above can be used. In the modification example 1, OS annealing is performed in a state where the pattern of the metal oxide layer 130 and the oxide semiconductor layer 140 is formed (step S1006). The subsequent steps S1008 to S1014 are due to the Figure 3 Likewise, detailed description is therefore omitted.

[0156] <Modification 2 of the first embodiment>

[0157] use Fig.17 and Fig.18 A second modification of the present embodiment will be described. The structure and manufacturing method of the semiconductor device 10 according to the second modification are similar to those of Figure 1 and Figure 3 to Figure 13 In the following description, Figure 1 and Figure 3 to Figure 13 Description of the steps common to the manufacturing methods shown will be omitted, and the manufacturing methods related to the differences will be mainly described.

[0158] Fig.17 It is a cross-sectional view schematically showing a semiconductor device according to a modified example of one embodiment of the present invention. Fig.18 It is a flowchart showing a method for manufacturing a semiconductor device according to a modification of one embodiment of the present invention.

[0159] like Fig.17 As shown, the structure of the semiconductor device 10 according to the second modification is different from Figure 1 The structure of the semiconductor device 10 shown is similar to that of the semiconductor device 10, but the pattern of the metal oxide layer 130 is not formed. Figure 1 The structure of the semiconductor device 10 shown is different. That is, in Modification 2, the metal oxide layer 130 extends outward from the pattern of the oxide semiconductor layer 140 . The metal oxide layer 130 is in contact with the gate insulating layer 150 outside the pattern of the oxide semiconductor layer 140 .

[0160] like Fig.18 As shown, the manufacturing method of the semiconductor device 10 according to the modification example 2 is the same as Figure 3 The manufacturing method of the semiconductor device 10 is similar, but the patterning of the metal oxide layer 130 is omitted ( Figure 3 The process of step S1007) is similar to Figure 3The manufacturing method of the semiconductor device 10 shown in FIG. 1 is different from that of FIG. 1 . Figure 3 Likewise, detailed description is therefore omitted.

[0161] <Variation 3 of the First Embodiment>

[0162] use Figure 19 to Figure 23 The structure and manufacturing method of the semiconductor device 10 according to the modification example 3 are similar to those of the embodiment. Figures 1 to 13 In the following description, Figures 1 to 13 Description of the steps common to the manufacturing methods shown will be omitted, and the manufacturing methods related to the differences will be mainly described.

[0163] Fig.19 It is a cross-sectional view schematically showing a semiconductor device 10 according to an embodiment of the present invention. Fig. 20 It is a plan view schematically showing a semiconductor device 10 according to an embodiment of the present invention.

[0164] like Fig.19 and Fig. 20 As shown, the structure of the semiconductor device 10 according to the modification example 3 is different from Figure 1 and Figure 2 The structure of the semiconductor device 10 shown is similar to that of the semiconductor device 10, but the pattern of the metal oxide layer 130 is different from the pattern of the oxide semiconductor layer 140. Figure 1 The structure of the semiconductor device 10 shown is different. Specifically, Fig.19 In a cross-sectional view, the pattern of the oxide semiconductor layer 140 extends outward from the pattern of the metal oxide layer 130. That is, the oxide semiconductor layer 140 crosses the pattern of the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the gate insulating layer 120 outside the pattern of the metal oxide layer 130. The gate insulating layer 120 is sometimes referred to as a "first insulating layer".

[0165] The source electrode or drain electrode 200 is in contact with the oxide semiconductor layer 140 in a region where the metal oxide layer 130 is not provided. Fig. 20 In a plan view, the pattern of the metal oxide layer 130 is located inside the pattern of the oxide semiconductor layer 140. The openings 171 and 173 are provided in a region that does not overlap with the pattern of the metal oxide layer 130.

[0166] Fig.21 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Fig. 22 and Fig.23 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig.21As shown, in the third modification, after the metal oxide layer 130 is patterned (the "AlOx film formation" of step S1030 and the "AlOx pattern formation" of step S1031), the metal oxide layer 130 is subjected to plasma treatment (step S1032). Thereafter, the oxide semiconductor layer 140 is patterned (the "OS film formation" of step S1033 and the "OS pattern formation" of step S1034). Figure 3 The difference is that the OS annealing (“OS annealing” in step S1035 ) is performed after the gate insulating layer 150 is formed.

[0167] like Fig. 22 As shown, a metal oxide layer 130 is formed on the gate insulating layer 120 (step S1030), and a pattern of the metal oxide layer 130 is formed (step S1031). The patterning (etching) of the metal oxide layer 130 is performed by the same method as described above. Thereafter, the surface of the patterned metal oxide layer 130 is subjected to plasma treatment (step S1032).

[0168] like Fig.23 As shown in FIG. 1 , an oxide semiconductor layer 140 is formed on the patterned metal oxide layer 130 (step S1033), and a pattern of the oxide semiconductor layer 140 is formed (step S1034). The patterning (etching) of the oxide semiconductor layer 140 is performed in the same manner as described above. Fig.23 OS annealing is performed in the state shown (step S1035). The following steps S1008 to S1014 are related to Figure 3 Likewise, detailed description is therefore omitted.

[0169] In this modification, the pattern of the metal oxide layer 130 is subjected to plasma treatment. That is, not only the surface of the metal oxide layer 130 but also the side surface is subjected to surface modification. Thus, even at the interface between the side surface of the metal oxide layer 130 and the side surface of the oxide semiconductor layer 140, oxygen vacancies formed in the oxide semiconductor layer 140 can be reduced.

[0170] As described above, according to the semiconductor devices 10 according to Modifications 1 to 3 of the present embodiment, it is possible to obtain the same effects as those of the present embodiment.

[0171] <Second Embodiment>

[0172] use Figure 24 to Figure 35 A semiconductor device according to an embodiment of the present invention will be described.

[0173] [Configuration of Semiconductor Device 10]

[0174] The configuration of the semiconductor device 10 according to the present embodiment is the same as that of the first embodiment. Figure 1 and Figure 2 The semiconductor device 10 according to the present embodiment will be described. The semiconductor device 10 according to the present embodiment is different from the semiconductor device 10 according to the first embodiment in the manufacturing method. Therefore, in the present embodiment, the description of the structure of the semiconductor device 10 is omitted, and the manufacturing method thereof will be described. In the following description, as the metal oxide layer 190 (also referred to as the metal oxide layer), the same material as the metal oxide layer 130 is used.

[0175] [Method of Manufacturing Semiconductor Device 10]

[0176] use Figure 24 to Figure 35 A method for manufacturing the semiconductor device 10 according to an embodiment of the present invention will be described. Fig.24 It is a sequence diagram showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention. Figure 25 to Figure 35 1 is a cross-sectional view showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention. In the following description of the manufacturing method, a method for manufacturing the semiconductor device 10 using aluminum oxide as the metal oxide layers 130 and 190 will be described.

[0177] like Fig.24 and Fig.25 As shown, a gate electrode 105 is formed on the substrate 100 as a bottom gate, and gate insulating layers 110 and 120 are formed on the gate electrode 105 ( Fig.24 The gate insulating layer 110 may be formed of silicon nitride, for example. The gate insulating layer 120 may be formed of silicon oxide, for example. The gate insulating layers 110 and 120 are formed by CVD (Chemical Vapor Deposition).

[0178] By using silicon nitride as the gate insulating layer 110, the gate insulating layer 110 can block, for example, impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. Silicon oxide used as the gate insulating layer 120 is a silicon oxide having a physical property of releasing oxygen by heat treatment.

[0179] like Fig.24 and Fig.26 As shown, a metal oxide layer 130 and an oxide semiconductor layer 140 are formed on the gate insulating layer 120 ( Fig.24 The metal oxide layer 130 is formed by sputtering or atomic layer deposition (ALD: Atomic Layer Deposition).

[0180] The thickness of the metal oxide layer 130 during film formation is, for example, 2 nm to 51 nm, 2 nm to 31 nm, 2 nm to 21 nm, or 2 nm to 11 nm. The thickness of the metal oxide layer 130 may also be appropriately set according to the plasma treatment method to be described later. In this embodiment, aluminum oxide is used as the metal oxide layer 130. Aluminum oxide has a high barrier property against gases such as oxygen and hydrogen. The metal oxide layer 130 is formed by sputtering. In this embodiment, aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the gate insulating layer 120, and inhibits the released hydrogen and oxygen from reaching the oxide semiconductor layer 140.

[0181] like Fig.24 and Fig. 27 As shown, the metal oxide layer 130 is subjected to plasma treatment ( Figure 3 The plasma treatment may be the reverse sputtering described in the first embodiment or the etching performed by inductively coupled plasma.

[0182] The surface of the metal oxide layer 130 is modified by subjecting the metal oxide layer 130 to plasma treatment. For example, the water contact angle of the surface of the metal oxide layer 130 after the plasma treatment is 20° or less, preferably 15° or less, and more preferably 10° or less.

[0183] In addition, by performing plasma treatment on the metal oxide layer 130 using argon gas, for example, Ar atoms (atomic %) are included on the surface of the metal oxide layer 130. The concentration of Ar included on the surface of the metal oxide layer 130 is 1 atomic % to 3 atomic %.

[0184] The surface of the metal oxide layer 130 may be removed by plasma treatment. The amount of the surface of the metal oxide layer 130 removed is, for example, 1 nm to 10 nm, or 1 nm to 5 nm.

[0185] In addition, the surface roughness of the metal oxide layer 130 may be reduced by plasma treatment. The surface roughness (for example, arithmetic mean roughness (Ra)) of the metal oxide layer 130 may be set to 1 nm or less. The surface roughness can be evaluated using an atomic force microscope (AFM: Atomic Force Microscope).

[0186] The thickness of the metal oxide layer 130 after the plasma treatment is 1 nm to 50 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 1 nm to 10 nm.

[0187] like Fig.24 and Fig.28 As shown, an oxide semiconductor layer 140 is formed on the metal oxide layer 130 subjected to plasma treatment ( Figure 3 "OS film formation" in step S2004).

[0188] The thickness of the oxide semiconductor layer 140 is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. In this embodiment, an oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 140. The oxide semiconductor layer 140 before OS annealing described later is in an amorphous state.

[0189] When the oxide semiconductor layer 140 is crystallized by OS annealing described later, it is preferable that the oxide semiconductor layer 140 after film formation and before OS annealing is in an amorphous state (a state in which the crystalline component of the oxide semiconductor is small). That is, the film formation conditions of the oxide semiconductor layer 140 are preferably conditions under which the oxide semiconductor layer 140 immediately after film formation is not crystallized as much as possible. For example, when the oxide semiconductor layer 140 is formed by sputtering, the oxide semiconductor layer 140 is formed under a state in which the temperature of the film formation object (the substrate 100 and the structure formed thereon) is controlled.

[0190] When a film is formed on an object to be formed by sputtering, ions generated by the plasma and atoms recoiled by the sputtering target will collide with the object to be formed. Therefore, the temperature of the object to be formed will rise along with the film forming process. If the temperature of the object to be formed rises during the film forming process, the oxide semiconductor layer 140 contains microcrystals in the state just after the film is formed. Due to the microcrystals, the subsequent crystallization based on OS annealing is hindered. In order to control the temperature of the object to be formed as described above, the film can also be formed while cooling the object to be formed. For example, the object to be formed can also be cooled from the opposite side of the film forming surface in such a way that the temperature of the film forming surface of the object to be formed is below 100°C, below 70°C, below 50°C, or below 30°C. By forming the oxide semiconductor layer 140 while cooling the object to be formed as described above, an oxide semiconductor layer 140 with a small amount of crystalline components in the state just after the film is formed can be formed.

[0191] In this embodiment, the surface of the metal oxide layer 130 is subjected to plasma treatment before the oxide semiconductor layer 140 is formed. As a result, the surface of the metal oxide layer 130 is modified. The hydroxyl group and water in the modified surface of the metal oxide layer 130 can be reduced. When the oxide semiconductor layer 140 is formed, the atoms constituting the oxide semiconductor layer 140 are easily bonded to the surface of the metal oxide layer 130, and the interface energy level density at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 can be reduced.

[0192] like Fig.24 and Fig.29 As shown, the pattern of the oxide semiconductor layer 140 is formed ( Fig.24 Although not shown in the figure, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. The oxide semiconductor layer 140 can be etched by wet etching or dry etching. As wet etching, an acidic etchant can also be used for etching. For example, oxalic acid or hydrofluoric acid can also be used as an etchant.

[0193] After the patterning of the oxide semiconductor layer 140, the oxide semiconductor layer 140 is subjected to a heat treatment (OS annealing) ( Fig.24 In this embodiment, the oxide semiconductor layer 140 is crystallized by the OS annealing.

[0194] In this embodiment, the surface of the metal oxide layer 130 is modified. The oxide semiconductor layer 140 having a small amount of crystalline components is formed on the modified surface of the metal oxide layer 130. Thereafter, when the oxide semiconductor layer 140 is crystallized by performing OS annealing, it is possible to suppress the crystallization from being hindered by hydroxyl groups and water at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. That is, the interface energy level density at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 can be further reduced.

[0195] like Fig.24 and Fig.30 As shown, the pattern of the metal oxide layer 130 is formed ( Fig.24 The metal oxide layer 130 is etched using the oxide semiconductor layer 140 patterned in the above process as a mask. The metal oxide layer 130 can be etched by wet etching or dry etching. For wet etching, for example, diluted hydrofluoric acid (DHF) is used. By etching the metal oxide layer 130 using the oxide semiconductor layer 140 as a mask as described above, the photolithography process can be omitted.

[0196] like Fig.24 and Fig.31 As shown, the gate insulating layer 150 ( Fig.24 The gate insulating layer 150 is formed by a CVD method. For example, in order to form an insulating layer with few defects as described above, the gate insulating layer 150 may be formed at a film forming temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm. After forming the gate insulating layer 150, a process of injecting oxygen into a portion of the gate insulating layer 150 may be performed. A metal oxide layer 190 ( Fig.24 The metal oxide layer 190 is formed by a sputtering method. Oxygen is injected into the gate insulating layer 150 by the formation of the metal oxide layer 190 .

[0197] For example, the thickness of the metal oxide layer 190 is 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 190. Aluminum oxide has a high barrier property against gases such as oxygen and hydrogen. In this embodiment, aluminum oxide used as the metal oxide layer 190 is used to suppress the diffusion of oxygen injected into the gate insulating layer 150 to the outside when the metal oxide layer 190 is formed.

[0198] For example, when the metal oxide layer 190 is formed by sputtering, the process gas used for sputtering may remain in the film of the metal oxide layer 190. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the metal oxide layer 190. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis or XPS analysis performed on the metal oxide layer 190.

[0199] In a state where the gate insulating layer 150 is formed on the oxide semiconductor layer 140 and the metal oxide layer 190 is formed on the gate insulating layer 150, heat treatment (oxidation annealing) for supplying oxygen to the oxide semiconductor layer 140 is performed ( Fig.24In the process from forming the oxide semiconductor layer 140 to forming the gate insulating layer 150 on the oxide semiconductor layer 140, a large number of oxygen vacancies are generated on the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. The oxygen released from the gate insulating layers 120 and 150 by the above-mentioned oxidation annealing is supplied to the oxide semiconductor layer 140 to repair the oxygen vacancies.

[0200] Oxygen released from the gate insulating layer 120 by the oxidation annealing is blocked by the metal oxide layer 130. Therefore, the oxygen is not easily supplied to the lower surface 142 of the oxide semiconductor layer 140. The oxygen released from the gate insulating layer 120 diffuses from the region where the metal oxide layer 130 is not formed to the gate insulating layer 150 provided on the gate insulating layer 120, and reaches the oxide semiconductor layer 140 via the gate insulating layer 150. As a result, the oxygen released from the gate insulating layer 120 is not easily supplied to the lower surface 142 of the oxide semiconductor layer 140, but is mainly supplied to the side surface 143 and the upper surface 141 of the oxide semiconductor layer 140. In addition, the oxygen released from the gate insulating layer 150 by the oxidation annealing is supplied to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. Although hydrogen may be released from the gate insulating layers 110 and 120 by the above-mentioned oxidation annealing, the hydrogen is blocked by the metal oxide layer 130.

[0201] As described above, the oxidation annealing step can suppress supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140 having a small amount of oxygen vacancies and simultaneously supply oxygen to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140 having a large amount of oxygen vacancies.

[0202] Similarly, in the above-mentioned oxidation annealing, oxygen injected into the gate insulating layer 150 is blocked by the metal oxide layer 190, thereby preventing the oxygen from being released into the atmosphere. Therefore, the oxidation annealing efficiently supplies the oxygen to the oxide semiconductor layer 140 to repair oxygen vacancies.

[0203] like Fig.24 and Fig.32 As shown, after the oxidation annealing, the metal oxide layer 190 is etched (removed) ( Fig.24 (See "AlOx removal" in step S2011). As the etching of the metal oxide layer 190, wet etching or dry etching may be used. As the wet etching, for example, diluted hydrofluoric acid (DHF) is used.

[0204] like Fig.24 and Fig.33 As shown, the film-forming gate electrode 160 ( Fig.24The gate electrode 160 is formed by sputtering or atomic layer deposition and patterned by a photolithography process.

[0205] In the state where the gate electrode 160 is patterned, the resistance of the source region S and the drain region D of the oxide semiconductor layer 140 is reduced ( Fig.24 Specifically, impurities are injected into the oxide semiconductor layer 140 from the gate electrode 160 side through the gate insulating layer 150 by ion implantation. For example, argon (Ar), phosphorus (P), and boron (B) are injected into the oxide semiconductor layer 140 by ion implantation. Oxygen vacancies are formed in the oxide semiconductor layer 140 by ion implantation, thereby reducing the resistance of the oxide semiconductor layer 140. Since the gate electrode 160 is provided above the oxide semiconductor layer 140 that functions as the channel region CH of the semiconductor device 10, impurities are not injected into the oxide semiconductor layer 140 in the channel region CH.

[0206] like Fig.24 and Fig.34 As shown, insulating layers 170 and 180 are formed on the gate insulating layer 150 and the gate electrode 160 as interlayer films ( Fig.24 The insulating layers 170 and 180 are formed by CVD. For example, silicon nitride is formed as the insulating layer 170, and silicon oxide is formed as the insulating layer 180. The materials used as the insulating layers 170 and 180 are not limited to the above. The thickness of the insulating layer 170 is not less than 50 nm and not more than 500 nm. The thickness of the insulating layer 180 is not less than 50 nm and not more than 500 nm.

[0207] like Fig.24 and Fig.35 As shown, openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 ( Fig.24 The oxide semiconductor layer 140 in the source region S is exposed through the opening 171. The oxide semiconductor layer 140 in the drain region D is exposed through the opening 173. A source electrode or a drain electrode 200 ( Fig.24 Step S2016 of "SD formation"), thereby completing Figure 1 A semiconductor device 10 is shown.

[0208] Thus, in the semiconductor device 10, when the channel length L of the channel region CH is within a range of 2 μm to 4 μm and the channel width of the channel region CH is within a range of 2 μm to 25 μm, a mobility of 30 cm2 / Vs or above, 35cm 2 / Vs or more, preferably 40cm 2 / Vs or more such electrical characteristics. The mobility in this embodiment refers to the field effect mobility in the saturation region of the semiconductor device 10. Specifically, the mobility means the maximum value of the field effect mobility in the region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the semiconductor device 10 from the voltage (Vg) supplied to the gate electrode.

[0209] In the case of a top-gate transistor as shown in this embodiment, the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 becomes the back channel side of the transistor. By reducing the interface energy level density at the interface on the back channel side, it is possible to suppress electrons from being captured by the interface energy level. Thus, it is possible to suppress transistor degradation based on reliability testing. That is, it is possible to improve the reliability of the semiconductor device 10.

[0210] <Third Embodiment>

[0211] use Figures 36 to 40 A display device using a semiconductor device according to an embodiment of the present invention will be described. In the following embodiment, a circuit configuration in which the semiconductor device 10 described in the first and second embodiments is applied to a liquid crystal display device will be described.

[0212] [Overview of Display Device 20]

[0213] Fig.36 1 is a top view showing an overview of a display device according to an embodiment of the present invention. Fig.36 As shown, the display device 20 includes an array substrate 300, a sealing portion 310, an opposing substrate 320, a flexible printed circuit substrate 330 (FPC 330), and an IC chip 340. The array substrate 300 and the opposing substrate 320 are bonded together by the sealing portion 310. A plurality of pixel circuits 301 are arranged in a matrix in a liquid crystal region 22 surrounded by the sealing portion 310. The liquid crystal region 22 is a region that overlaps with a liquid crystal element 311 described later in a plan view.

[0214] The sealing region 24 provided with the sealing portion 310 is the region around the liquid crystal region 22. The FPC 330 is provided in the terminal region 26. The terminal region 26 is the region where the array substrate 300 is exposed from the counter substrate 320 and is provided outside the sealing region 24. The outside of the sealing region 24 means the region provided with the sealing portion 310 and the outside of the region surrounded by the sealing portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies a signal for driving each pixel circuit 301.

[0215] [Circuit Configuration of Display Device 20]

[0216] Fig.37 1 is a block diagram showing a circuit configuration of a display device 20 according to an embodiment of the present invention. Fig.37 As shown, a source driving circuit 302 is provided at a position adjacent to the liquid crystal region 22 in the first direction D1 (column direction) with respect to the pixel circuit 301, and a gate driving circuit 303 is provided at a position adjacent to the liquid crystal region 22 in the second direction D2 (row direction). The source driving circuit 302 and the gate driving circuit 303 are provided in the above-mentioned sealing region 24. However, the region where the source driving circuit 302 and the gate driving circuit 303 are provided is not limited to the sealing region 24, and may be any region as long as it is outside the region where the pixel circuit 301 is provided.

[0217] The source wiring 304 extends from the source driving circuit 302 along the first direction D1 and is connected to the plurality of pixel circuits 301 arranged in the first direction D1. The gate wiring 305 extends from the gate driving circuit 303 along the second direction D2 and is connected to the plurality of pixel circuits 301 arranged in the second direction D2.

[0218] The terminal region 26 is provided with a terminal portion 306. The terminal portion 306 and the source driver circuit 302 are connected via a connection wiring 307. Similarly, the terminal portion 306 and the gate driver circuit 303 are connected via a connection wiring 307. By connecting the FPC 330 to the terminal portion 306, an external device connected to the FPC 330 is connected to the display device 20, and each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device.

[0219] The semiconductor device 10 described in the first embodiment and the second embodiment is used as a transistor included in the pixel circuit 301 , the source driver circuit 302 , and the gate driver circuit 303 .

[0220] [Pixel Circuit 301 of Display Device 20]

[0221] Fig.38 1 is a circuit diagram showing a pixel circuit of a display device 20 according to an embodiment of the present invention. Fig.38As shown, the pixel circuit 301 includes elements such as the semiconductor device 10, the holding capacitor 350, and the liquid crystal element 311. The semiconductor device 10 has a gate electrode 160, a source electrode 201, and a drain electrode 203. The gate electrode 160 is connected to the gate wiring 305. The source electrode 201 is connected to the source wiring 304. The drain electrode 203 is connected to the holding capacitor 350 and the liquid crystal element 311. In this embodiment, for the sake of convenience of description, the electrode represented by the figure mark "201" is called the source electrode, and the electrode represented by the figure mark "203" is called the drain electrode, but it is also possible that the electrode represented by the figure mark "201" functions as a drain electrode and the electrode represented by the figure mark "203" functions as a source electrode.

[0222] [Cross-sectional structure of display device 20]

[0223] Fig.39 FIG. 1 is a cross-sectional view of a display device according to an embodiment of the present invention. Fig.39 As shown in FIG. 1 , the display device 20 is a display device using the semiconductor device 10. In this embodiment, the semiconductor device 10 is used in the pixel circuit 301, but the semiconductor device 10 can also be used in peripheral circuits including the source driver circuit 302 and the gate driver circuit 303. In the following description, the semiconductor device 10 is used in the pixel circuit 301. Figure 1 The semiconductor device 10 shown is the same and therefore its description is omitted.

[0224] An insulating layer 360 is provided on the source electrode 201 and the drain electrode 203. A common electrode 370 provided in common to a plurality of pixels is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. An opening 381 is provided on the insulating layers 360 and 380. A pixel electrode 390 is provided on the insulating layer 380 and inside the opening 381. The pixel electrode 390 is connected to the drain electrode 203.

[0225] Fig.40 FIG. 1 is a top view of a pixel electrode and a common electrode of a display device according to an embodiment of the present invention. Fig.40 As shown, the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in a plan view and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a transverse electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. The liquid crystal molecules included in the liquid crystal element 311 are moved by the transverse electric field, thereby determining the grayscale of the pixel.

[0226] The semiconductor device 10 according to one embodiment of the present invention has a small amount of change in threshold voltage due to aging. A display device using the semiconductor device 10 has high reliability and a long life.

[0227] <Fourth Embodiment>

[0228] use Fig.41 and Fig.42 A display device 20 using a semiconductor device 10 according to an embodiment of the present invention will be described. In this embodiment, a circuit configuration in which the semiconductor device 10 described in the first and second embodiments is applied to an organic EL display device will be described. The overview and circuit configuration of the display device 20 are related to Fig.36 and Fig.37 The contents shown are the same, so the description is omitted.

[0229] [Pixel Circuit 301 of Display Device 20]

[0230] Fig.41 FIG. 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. Fig.41 As shown, the pixel circuit 301 includes components such as a driving transistor 11, a selection transistor 12, a holding capacitor 210 and a light-emitting element DO. The driving transistor 11 and the selection transistor 12 have the same structure as the semiconductor device 10. The source electrode of the selection transistor 12 is connected to the signal line 211, and the gate electrode of the selection transistor 12 is connected to the gate line 212. The source electrode of the driving transistor 11 is connected to the anode power line 213, and the drain electrode of the driving transistor 11 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to the cathode power line 214. The gate electrode of the driving transistor 11 is connected to the drain electrode of the selection transistor 12. The holding capacitor 210 is connected to the gate electrode and the drain electrode of the driving transistor 11. A grayscale signal that determines the light intensity of the light-emitting element DO is supplied to the signal line 211. A signal for selecting a pixel row to which the above-mentioned grayscale signal is to be written is supplied to the gate line 212.

[0231] [Cross-sectional structure of display device 20]

[0232] Fig.42 It is a cross-sectional view of a display device 20 according to an embodiment of the present invention. Fig.42 The display device 20 shown in FIG. Fig.39 The display device 20 shown is similar, but Fig.42 The structure above the insulating layer 360 in the display device 20 and Fig.39 The structure above the insulating layer 360 in the display device 20 is different. Fig.42 The display device 20 is configured as follows: Fig.39 The description of the same structure as the display device 20 is omitted, and the differences between the two are described.

[0233] like Fig.42 As shown, the display device 20 has a pixel electrode 390, a light-emitting layer 392 and a common electrode 394 (light-emitting element DO) above the insulating layer 360. The pixel electrode 390 is arranged on the insulating layer 360 and inside the opening 381. An insulating layer 362 is arranged on the pixel electrode 390. An opening 363 is arranged in the insulating layer 362. The opening 363 corresponds to the light-emitting area. That is, the insulating layer 362 divides the pixel. The light-emitting layer 392 and the common electrode 394 are arranged on the pixel electrode 390 exposed through the opening 363. The pixel electrode 390 and the light-emitting layer 392 are arranged separately with respect to each pixel. On the other hand, the common electrode 394 is arranged in common with respect to a plurality of pixels. Different materials are used for the light-emitting layer 392 according to the display color of the pixel.

[0234] The semiconductor device 10 according to one embodiment of the present invention has a small amount of change in threshold voltage due to aging. The display device 20 using the semiconductor device 10 has high reliability and a long life.

[0235] In the third and fourth embodiments, the semiconductor device 10 described in the first and second embodiments is applied to a liquid crystal display device and an organic EL display device, but the semiconductor device 10 can also be applied to display devices other than the above display devices (for example, a self-luminous display device or an electronic paper display device other than an organic EL display device). In addition, unless otherwise specified, the semiconductor device 10 can be applied to display devices ranging from small to large display devices.

[0236] Example

[0237] In this embodiment, refer to Figures 43 to 48 The effect of plasma treatment on the surface of a metal oxide layer containing aluminum as a main component will be described.

[0238] [Relationship between the water contact angle of aluminum oxide layer and the electrical characteristics of semiconductor device]

[0239] In order to examine the water contact angle of the aluminum oxide layer, samples A to E were prepared under the following conditions.

[0240] First, an aluminum oxide layer with a thickness of 11 nm was formed on a glass substrate by sputtering.

[0241] (Condition 1)

[0242] As sample A, a sputtering device with a reverse sputtering function was used to perform reverse sputtering treatment on the surface of the aluminum oxide layer using argon gas. The reverse sputtering conditions were upper RF power 400kHz (1.5kV), lower RF power 13.56MHz (1.5kV), argon gas flow rate 5sccm, temperature at room temperature (25°C), and treatment time 40 seconds. The film thickness of the aluminum oxide layer after the reverse sputtering treatment was 10nm.

[0243] (Condition 2)

[0244] As sample B, the surface of the aluminum oxide layer was etched using an ICP etching device using an inductively coupled plasma with argon gas. The etching process was performed under the conditions of an ICP power of 50 W (power per unit electrode area (power density) of 0.81 W / cm 2 ), pressure 4 Pa, argon gas flow rate 50 sccm, RF bias power 50 W, temperature 65° C., and processing time 399.9 seconds. The film thickness of the aluminum oxide layer after etching was 10 nm.

[0245] (Condition 3)

[0246] As sample C, the surface of the aluminum oxide layer was etched using an ICP etching apparatus using an inductively coupled plasma using argon gas. The etching process was performed under the following conditions: ICP power 25 W, pressure 4 Pa, argon gas flow rate 50 sccm, RF bias power 25 W, temperature 65° C., and processing time 1100 seconds. The film thickness of the aluminum oxide layer after the etching process was 10 nm.

[0247] (Condition 4)

[0248] As sample D, the surface of the aluminum oxide layer was treated with a developing solution (TMAH) for 5 seconds.

[0249] (Condition 5)

[0250] In the case of Sample E, the surface of the aluminum oxide layer was not subjected to surface modification treatment.

[0251] Next, the water contact angle of the outermost surface of the aluminum oxide layer of Samples A to E was measured. The water contact angle of the aluminum oxide layer was measured using CA-S350 manufactured by Kyowa Interface Chemical Co., Ltd. In addition, pure water was dripped to a diameter of 1.5 mm to 2.0 mm, and the water contact angle was measured within 10 seconds from the time when the water contacted the surface of the aluminum oxide layer.

[0252] Table 1 shows the measurement results of the water contact angle of the outermost surface of the aluminum oxide layer of Samples A to E.

[0253] [Table 1]

[0254] Sample A Sample B Sample C Sample D Sample E Water contact angle (°) 19.0 7.0 8.0 37.4 33.8

[0255] As shown in Table 1, it was confirmed that the water contact angles of samples A to C, which had undergone plasma treatment on the aluminum oxide layer, were smaller than those of samples D and E. In addition, it was confirmed that the water contact angles of samples B and C, which had undergone etching treatment using inductively coupled plasma, were smaller than those of sample A, which had undergone reverse sputtering.

[0256] <Analysis by X-ray Photoelectron Spectroscopy (XPS)>

[0257] Next, regarding Sample A, Sample D, and Sample E, XPS analysis was performed on the film surface of the aluminum oxide layer to study the ratio of Al atoms, O atoms, F atoms, C atoms, Cl atoms, Si atoms, and Ar atoms present on the surface. The results of XPS analysis of Sample A, Sample D, and Sample E are shown in Table 2.

[0258] [Table 2]

[0259]

[0260] Fig.43 It is the O1s peak of oxygen atoms on the surface of the aluminum oxide layer in Sample A, Sample D and Sample E. As shown in Table 2 and Fig.43 As shown, it was confirmed that the oxygen concentration (atomic %) contained in the surface of the aluminum oxide layer in sample A was lower than the oxygen concentration (atomic %) contained in the surface of the aluminum oxide layer in sample D and sample E. In other words, it can be predicted that the hydroxyl group and water contained in the surface of the aluminum oxide layer in sample A will be less than the hydroxyl group and water contained in the surface of the aluminum oxide layer in sample D and sample E.

[0261] [Reliability test]

[0262] Next, refer to Figures 44 to 48 The results obtained by manufacturing semiconductor devices A to E and examining the reliability of each semiconductor device will be described.

[0263] according to Fig.24 The semiconductor device 10 is formed by following the sequence diagram of the manufacturing method shown in FIG. Fig.24Here, in the case of manufacturing semiconductor device A, plasma treatment of the aluminum oxide layer is performed using condition 1 in step S2003. In addition, in the case of manufacturing semiconductor device B, plasma treatment of the aluminum oxide layer is performed using condition 2 in step 2003. In addition, in the case of manufacturing semiconductor device C, plasma treatment of the aluminum oxide layer is performed using condition 3 in step S2003. In addition, in the case of manufacturing semiconductor device D, plasma treatment of the aluminum oxide layer is performed using condition 4 in step S2003. In the case of manufacturing semiconductor device E, step S2003 (condition 5) is omitted. In the present embodiment, the oxide semiconductor layer 140 is a polycrystalline oxide semiconductor containing two or more metals including indium and the ratio of indium in the two or more metals is 50% or more.

[0264] Afterwards, the semiconductor devices A to E were subjected to a PBTS reliability test.

[0265] The conditions of the PBTS reliability test are as follows.

[0266] ·Size of channel region CH: W / L=2.5μm / 2.5μm

[0267] Light irradiation conditions: No irradiation (dark room)

[0268] ·Gate voltage: +30V

[0269] Source and drain voltage: 0V

[0270] ·Workbench temperature when stress is applied: 85°C

[0271] Duration: 1000 seconds

[0272] Figures 44 to 48 is a graph showing the reliability test results of semiconductor devices A to E. Figures 44 to 48 In the graph, the thin solid line represents the drain current at 0 seconds (Initial), and the thick solid line represents the drain current at 1000 seconds (Stress). In addition, the thin dotted line represents the mobility at 0 seconds, and the thick dotted line represents the mobility after 1000 seconds. In addition, Table 3 shows the amount of threshold voltage shift (ΔVth) and mobility (μ) after 1000 seconds.

[0273] [Table 3]

[0274] Sample A Sample B Sample C Sample D Sample E ΔVth(V) 0.90 0.81 0.76 1.5 1.5 <![CDATA[μ(cm 2 / V·s)]]> 40 42 42 38 37

[0275] As shown in Table 3, it can be seen that in the case of semiconductor devices A to C, the threshold voltage is only shifted in the forward direction by 0.90 V, 0.81 V, and 0.76 V, respectively. In contrast, in the case of semiconductor devices D and E using samples D and E, the threshold voltage of each is shifted in the forward direction by 1.5 V. It is confirmed that the reliability of the semiconductor device is improved by plasma treatment of the aluminum oxide layer. In addition, it is confirmed that compared with semiconductor device A that has been subjected to plasma treatment based on reverse sputtering, semiconductor devices B and C that have been etched based on inductively coupled plasma can further suppress the change of the threshold.

[0276] As shown in Table 3, it can be seen that in the case of semiconductor devices D and E, the mobility is 38 cm 2 / V / s, 37cm 2 / V·s, on the other hand, in the case of semiconductor devices A to C, the mobility is 40 cm 2 / V / s, 42cm 2 / V·s, 42cm 2 / V·s. It was confirmed that the mobility of the semiconductor device was improved by plasma treatment of the aluminum oxide layer. In addition, it was confirmed that the mobility of the semiconductor devices B and C, which were etched by inductively coupled plasma, was further improved compared to the semiconductor device A, which was plasma treated by reverse sputtering.

[0277] According to the above results, it is confirmed that by plasma treating the aluminum oxide layer, the mobility and reliability of the semiconductor device are improved. In addition, it is confirmed that the smaller the water contact angle on the surface of the aluminum oxide layer, the more the electrical characteristics of the semiconductor device are improved. That is, it is believed that at the interface between the aluminum oxide layer and the oxide semiconductor layer, the water and oxygen deficiencies of the oxide semiconductor layer are reduced. It is believed that, especially in the case of using an oxide semiconductor layer with a relatively high indium ratio, the formation of oxygen deficiencies at the interface can also be suppressed. Therefore, it is believed that the crystallinity of the oxide semiconductor layer disposed on the aluminum oxide layer is improved, forming a polycrystalline with reduced defects. As a result, it is believed that the mobility and reliability of the semiconductor device are improved.

[0278] As embodiments of the present invention, the embodiments described above can be implemented in appropriate combination as long as they do not contradict each other. In addition, solutions obtained by adding, deleting or changing the design of components or adding, omitting or changing the conditions of processes based on the semiconductor devices and display devices of the embodiments by those skilled in the art are also included in the scope of the present invention as long as they have the gist of the present invention.

[0279] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they are of course understood to be the effects brought about by the present invention.

[0280] Description of Reference Numerals

[0281] 10: semiconductor device, 11: driving transistor, 12: selecting transistor, 20: display device, 22: liquid crystal region, 24: sealing region, 26: terminal region, 100: substrate, 105, 160: gate electrode, 110, 120, 150: gate insulating layer, 130, 190: metal oxide layer, 140: oxide semiconductor layer, 141: upper surface, 142: lower surface, 143: side surface, 170, 180: insulating layer, 171, 173: opening, 200: source electrode / drain electrode, 201: source electrode, 203: drain electrode, 210: holding capacitor, 211: signal line, 212: gate line, 213: anode 2: cathode power line, 214: cathode power line, 220: resist mask, 300: array substrate, 301: pixel circuit, 302: source driving circuit, 303: gate driving circuit, 304: source wiring, 305: gate wiring, 306: terminal portion, 307: connection wiring, 310: sealing portion, 311: liquid crystal element, 320: opposing substrate, 330: flexible printed circuit substrate (FPC), 340: IC chip, 350: holding capacitor, 360, 362: insulating layer, 363, 381: opening, 370: common electrode, 380: insulating layer, 390: pixel electrode, 392: light-emitting layer, 394: common electrode

Claims

1. A semiconductor device comprising: A metal oxide layer mainly composed of aluminum and disposed on the insulating surface; an oxide semiconductor layer disposed on the metal oxide layer; a gate electrode opposed to the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, The water contact angle of the upper surface of the metal oxide layer is 20° or less.

2. The semiconductor device according to claim 1, wherein The water contact angle of the upper surface of the metal oxide layer is 15° or less.

3. The semiconductor device according to claim 1, wherein The upper surface of the metal oxide layer contains argon in an amount of not less than 1 atomic % and not more than 3 atomic %.

4. The semiconductor device according to claim 1, wherein The thickness of the metal oxide layer is greater than or equal to 1 nm and less than or equal to 20 nm.

5. The semiconductor device according to claim 1, wherein The metal oxide layer has a barrier property against oxygen and hydrogen.

6. The semiconductor device according to claim 1, wherein The oxide semiconductor layer includes two or more metals including indium, and a ratio of indium in the two or more metals is 50% or more.

7. The semiconductor device according to claim 1, wherein The oxide semiconductor layer is a polycrystalline oxide semiconductor layer.

8. The semiconductor device according to claim 1, wherein the field effect mobility is 40 cm 2 / V·s or above.

9. A method for manufacturing a semiconductor device, wherein: A metal oxide layer mainly composed of aluminum is formed on the insulating surface. The surface of the metal oxide layer is subjected to plasma treatment so that the water contact angle of the surface of the metal oxide layer becomes 20° or less. forming an oxide semiconductor layer on the surface subjected to the plasma treatment, forming a gate insulating layer on the oxide semiconductor layer, A gate electrode is formed on the gate insulating layer to face the oxide semiconductor layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The plasma treatment is performed by reverse sputtering using argon gas.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: The water contact angle of the surface of the metal oxide layer is 15° or less.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The plasma treatment is performed by inductively coupled plasma etching using argon gas.

13. The method for manufacturing a semiconductor device according to claim 9, wherein: The thickness of the metal oxide layer after the plasma treatment is set to be 1 nm or more and 20 nm or less.

14. The method for manufacturing a semiconductor device according to claim 9, comprising: After forming the gate insulating layer, a metal oxide layer mainly composed of aluminum is formed on the gate insulating layer. performing heat treatment in a state where the metal oxide layer is formed on the gate insulating layer, The metal oxide layer is removed after the heat treatment.

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