Preparation method of MEMS bulk silicon structure and MEMS sensor

Abstract

The invention is applicable to the technical field of semiconductor devices, and provides a preparation method of an MEMS bulk silicon structure and an MEMS sensor, the MEMS bulk silicon structure comprises a first silicon substrate and a second silicon substrate, and the method comprises the following steps: etching and filling a first blind hole in the front surface of the first silicon substrate; the first blind hole has a first preset depth; etching a second blind hole in a position, opposite to the first blind hole, of the back surface of the first silicon substrate; the second blind hole has a second preset depth; the aperture of the second blind hole is greater than that of the first blind hole; the sum of the first preset depth and the second preset depth is the thickness of the first silicon substrate; filling the second blind hole to form a filled silicon through hole structure of a goblet structure; and bonding the front surface of the first silicon substrate and the second silicon substrate to form the MEMS bulk silicon structure. According to the application, an undercut or footing effect can be prevented from being generated at the bottom of the silicon substrate, and the covering quality of the through-silicon-via metal seed crystal layer is improved, so that the reliability of the electrical performance of the through-silicon via is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of semiconductor devices, and in particular, relates to a method for preparing a MEMS bulk silicon structure MEMS sensor. Background Art

[0002] In the field of semiconductor technology, 3D stacked packaging technology has been regarded as the key to manufacturing high-performance chips in smaller sizes. In the application of 3D stacked packaging technology, the bulk silicon structure involved is generally a multi-layer structure of silicon substrates and silicon substrates. By etching the bulk silicon structure, vertical conduction is made between chips and between silicon substrates, thereby realizing the interconnection between chips. In most cases, the production of through silicon vias (TSVs) requires opening up different material layers, and the through holes formed in this way must meet the contour control requirements, so the through silicon via etching process has become the key to the through silicon via production technology.

[0003] In the prior art, when one side of the silicon substrate is etched, in order to ensure that the silicon substrate is completely etched, an over-etching is usually performed for a certain period of time at the end of the etching process. Since the etching gas has a faster etching rate for silicon and a slower etching rate for the silicon oxide layer, the etching reaction will lateral-etch the bottom of the through silicon via (TSV), that is, the etched silicon substrate between the silicon substrates, and due to the influence of the oxide layer reflection between the silicon substrates on the etching, the silicon wafer is prone to "undercutting" or footing effect at the bottom of the through silicon via and the bottom of the silicon substrate, such as Figure 1 As shown, this not only weakens the coverage quality of the through silicon via metal seed layer, but also reduces the reliability of its electrical performance. Summary of the invention

[0004] To overcome the problems existing in the related art, the embodiment of the present application provides a method for preparing a MEMS bulk silicon structure MEMS sensor, which can solve the problem of "undercut" or footing effect at the bottom of the silicon substrate, resulting in reduced reliability of silicon through vias.

[0005] This application is implemented through the following technical solutions: In a first aspect, an embodiment of the present application provides a method for preparing a MEMS bulk silicon structure, wherein the MEMS bulk silicon structure includes a first silicon substrate and a second silicon substrate, and the method includes: Etching a first blind hole on the front side of the first silicon substrate; the first blind hole has a first preset depth; Filling the first blind hole; A second blind hole is etched at a position on the back side of the first silicon substrate opposite to the first blind hole; the second blind hole has a second preset depth; the aperture of the second blind hole is greater than the aperture of the first blind hole; the sum of the first preset depth and the second preset depth is the thickness of the first silicon substrate; Filling the second blind hole to form a filled through silicon via structure with a goblet structure; The front surface of the first silicon substrate having the filled through silicon via structure is bonded to one side of the second silicon substrate to form a MEMS bulk silicon structure.

[0006] In one embodiment, bonding a front surface of a first silicon substrate having a filled through silicon via structure to a side surface of a second silicon substrate includes: Preparing an oxide layer on the front side of the first silicon substrate having the filled through silicon via structure; The oxide layer is bonded to one side of the second silicon substrate.

[0007] In one embodiment, bonding the front surface of the first silicon substrate having the filled through silicon via structure to one side of the second silicon substrate further includes: preparing an oxide layer on one side of the second silicon substrate; The front side of the first silicon substrate having the filled through silicon via structure is bonded to the oxide layer.

[0008] In one embodiment, filling the first blind hole includes: depositing a first initial barrier layer in the first blind hole; Etching away the bottom of the first initial barrier layer to form a first final barrier layer; depositing a first seed layer on the first final barrier layer; Based on the first seed layer, the first blind hole is filled by electroplating.

[0009] In one embodiment, filling the second blind hole includes: depositing a second initial barrier layer in the second blind hole; Opening a connecting hole at the bottom of the second initial barrier layer to form a second final barrier layer; Depositing a second seed layer on the second final barrier layer; the second seed layer fills the communicating holes; Based on the second seed layer, the second blind hole is filled by electroplating.

[0010] In one embodiment, a connecting hole is formed on the bottom surface of the second initial barrier layer, comprising: A connecting hole is opened on the bottom surface of the second initial barrier layer by a preset method; the preset method includes laser spot ablation, ion milling or electrical corrosion.

[0011] In one embodiment, the ratio of the second preset depth to the first preset depth is in the range of [3, 10].

[0012] In one embodiment, after filling the second blind hole, the method for preparing the MEMS bulk silicon structure further includes: A fluorocarbon-based protective layer or a hydrocarbon-based protective layer is deposited on the back side of the first silicon substrate.

[0013] In one embodiment, the aperture ratio of the second blind hole to the first blind hole is in the range of [3,10].

[0014] In a second aspect, the present application provides a MEMS sensor provided with a MEMS bulk silicon structure prepared by the method for preparing a MEMS bulk silicon structure according to the second aspect.

[0015] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: In the embodiment of the present application, since etching through the silicon substrate requires depositing an oxide layer, the oxide layer is bound to be a poor conductor, causing charge accumulation, and further causing reverse etching. The present invention first etches a first blind hole with the front side as a small hole, and then etches a second blind hole with the back side as a large hole. The etching falls directly on the silicon layer without involving the oxide layer, avoiding the phenomenon of ion reflection causing the bottom of the hole to expand due to the landing of the general TSV in the dielectric area. Therefore, the process morphology and metal filling are easy to control, avoiding the "undercut" or footing effect at the bottom of the first silicon substrate. The reverse etching falls on the metal and silicon layers, and also avoids the "undercut" or footing effect at the bottom of the first silicon substrate, thereby improving the coverage quality of the metal seed layer of the silicon via, thereby improving the reliability of the electrical performance of the silicon via.

[0016] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 It is a schematic diagram of the "undercut" or footing effect generated between the silicon substrates provided by one embodiment of the present application; Figure 2 It is a schematic flow chart of a method for preparing a MEMS bulk silicon structure provided in one embodiment of the present application; Figure 3 This is a schematic diagram of a structure of etching a first blind hole on the front side provided by an embodiment of the present application; Figure 4 is a schematic diagram of the structure after the first blind hole is filled according to an embodiment of the present application; Figure 5 is a schematic diagram of a structure for etching a second blind hole provided in an embodiment of the present application; Figure 6 is a schematic diagram of the structure after the second blind hole is filled according to an embodiment of the present application; Figure 7 is a structural schematic diagram of a MEMS bulk silicon structure provided in an embodiment of the present application; Figure 8 is a structural schematic diagram of the morphology of through silicon via etching provided in an embodiment of the present application; wherein, Figure 8 (a), (b) and (c) are schematic diagrams of the structure of silicon vias without footing effect. Figure 8 (d), (e) and (f) are schematic diagrams of the structure of silicon vias with footing effect; Fig. 9 is a schematic diagram of a structure for filling a first blind hole provided by an embodiment of the present application; wherein, Fig. 9 (a) is a schematic diagram of the structure of depositing the first initial barrier layer. Fig. 9 (b) is a schematic diagram of the structure of forming the first final barrier layer. Fig. 9 (c) is a schematic diagram of a structure in which the first blind hole is filled based on the first seed layer; Fig.10 is a schematic diagram of a structure for filling a second blind hole provided by an embodiment of the present application; wherein, Fig.10 (a) is a schematic diagram of the structure for depositing the second initial barrier layer. Fig.10 (b) is a schematic diagram of the structure of forming the second final barrier layer. Fig.10 (c) is a schematic diagram of the structure of filling the second blind hole based on the second seed layer. DETAILED DESCRIPTION

[0019] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0020] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0021] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0022] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0023] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0024] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0025] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0026] Figure 2 is a flow chart of a method for preparing a MEMS bulk silicon structure according to an embodiment of the present application, referring to Figure 2 , the preparation method of the MEMS bulk silicon structure is described in detail as follows: The present application provides a method for preparing a MEMS bulk silicon structure, wherein the MEMS bulk silicon structure includes a first silicon substrate and a second silicon substrate, and the method includes: Step 101: etching a first blind hole on the front surface of a first silicon substrate.

[0027] The first blind hole has a first preset depth H1, such as Figure 3 shown.

[0028] Step 102, filling the first blind hole.

[0029] The structure after the first blind hole is filled is as follows Figure 4 shown.

[0030] Step 103: etching a second blind hole at a position on the back side of the first silicon substrate opposite to the first blind hole.

[0031] The second blind hole has a second preset depth H2; the aperture D2 of the second blind hole is greater than the aperture D1 of the first blind hole; the sum of the first preset depth and the second preset depth is the thickness of the first silicon substrate, such as Figure 5 shown.

[0032] Step 104 , filling the second blind hole to form a filled through silicon via structure of a goblet structure.

[0033] The structure after the second blind hole is filled is as follows Figure 6 As shown, the through silicon via structure is mainly used to connect the internal circuit of the first silicon substrate with the outside, and then the first silicon substrate is bonded with the second silicon substrate together.

[0034] Step 105 , bonding the front surface of the first silicon substrate having the filled through silicon via structure to one side of the second silicon substrate to form a MEMS bulk silicon structure.

[0035] Exemplarily, the front side of the first silicon substrate with the filled through silicon via structure is bonded to the second silicon substrate, an oxide layer is provided between the first silicon substrate and the second silicon substrate, the front side of the first silicon substrate is a surface adjacent to the oxide layer, and the back side of the first silicon substrate is a surface away from the oxide layer. During the bonding process, the oxide layer plays a key role in isolation and insulation. The front side of the first silicon substrate is bonded to the oxide layer, which ensures electrical isolation between the first silicon substrate and the second silicon substrate, prevents signal interference, and also provides stability for the entire structure to meet the performance requirements of MEMS sensors in different application scenarios, such as Figure 7 shown.

[0036] The MEMS bulk silicon structure in this embodiment is a part of a MEMS sensor. For example, in a micro acceleration sensor, a slight size change of the bulk silicon structure may cause a significant fluctuation in the sensitivity of the sensor.

[0037] This embodiment takes into account that etching of a transparent silicon substrate requires the deposition of an oxide layer, and the oxide layer is inevitably a poor conductor, causing charge accumulation, which in turn causes the reverse etching problem, such as Figure 8 As shown, Figure 8 (a) in the figure is the morphology of normal TSV etching. By adjusting the parameters, the angle can be changed within a certain range, for example Figure 8 (b) and (c) in the figure, but when there is a medium underneath, sputtering will occur from top to bottom, and the footing effect will definitely occur. Figure 8In the case of the incision in (d), (e) and (f), the metal process is difficult due to this small gap, and it is difficult to fully cover the metal seed layer, which will cause reliability problems later. In this application, the first blind hole with the front side as a small hole is first engraved, and the second blind hole with the back side as a large hole is then engraved. The etching falls directly on the silicon layer without involving the oxide layer, avoiding the phenomenon of ion reflection caused by the general TSV landing in the dielectric area causing the bottom of the hole to expand. Then the process morphology and metal filling are easy to control, avoiding the "undercut" or footing effect at the bottom of the first silicon substrate. The back etching falls on the metal and silicon layers, which also avoids the "undercut" or footing effect at the bottom of the first silicon substrate, improving the coverage quality of the metal seed layer of the silicon via, thereby improving the reliability of the electrical performance of the silicon via.

[0038] In one embodiment, see Fig. 9 , specifically introduce the detailed process of filling the first blind hole, step 102 includes: First, a first initial barrier layer is deposited in the first blind hole, such as Fig. 9 As shown in (a), a preliminary barrier is formed inside the blind hole to prevent the material from penetrating into the unwanted area during the subsequent deposition or electroplating process, ensuring that it can effectively isolate and protect the inner wall of the hole.

[0039] Then, the bottom of the first initial barrier layer is etched away to form a first final barrier layer, such as Fig. 9 As shown in (b) in the figure, the bottom part of the initial barrier layer is removed by etching process to prepare for the subsequent connection with the second blind hole.

[0040] Next, a first seed layer is deposited on the first final barrier layer. Based on the first seed layer, the first blind hole is filled by electroplating, such as Fig. 9 As shown in (c) in the figure. Based on the seed layer, a conductive material, such as copper, is filled into the blind hole through an electroplating process. During the electroplating process, the conductive material is precipitated from the electroplating solution under the action of the electric field and deposited on the seed layer, gradually filling the entire blind hole, preparing for the subsequent conductive connection with the second blind hole, thereby improving the overall performance and reliability of the sensor.

[0041] In one embodiment, see Fig.10 , specifically introduce the process of filling the second blind hole, including: First, a second initial barrier layer is deposited in the second blind hole, such as Fig.10 As shown in (a) in .

[0042] Then, a connecting hole is opened at the bottom of the second initial barrier layer to form a second final barrier layer, such as Fig.10 As shown in (b) in .

[0043] Next, a second seed layer is deposited on the second final barrier layer. Based on the second seed layer, the second blind hole is filled by electroplating, such as Fig.10 As shown in (c) in .

[0044] The second seed layer fills the connecting holes.

[0045] Exemplarily, the connecting holes are formed on the bottom surface of the second initial barrier layer, including: A connecting hole is opened on the bottom surface of the second initial barrier layer by a preset method; the preset method includes laser spot ablation, ion milling or electrical corrosion.

[0046] By opening a connecting hole on the bottom surface of the second initial barrier layer and filling it with metal, conductive connection between the first blind hole and the second blind hole can be achieved.

[0047] Exemplarily, the dielectric on the bottom surface of the first blind hole has been etched away before filling, and the second blind hole is entirely covered with an oxide layer, that is, an oxide layer. When realizing the conductive connection between the first blind hole and the second blind hole, if a general etching method is used, the oxide layer covering the second blind hole will be etched away, resulting in leakage. Therefore, how to realize the conductive connection between the first blind hole and the second blind hole requires special considerations. This embodiment uses laser spot ablation, ion milling to connect the hole dielectric, or back-side electrification to accelerate corrosion to achieve the dielectric area above the metal. Only a small hole is opened at the connection between the first blind hole and the second blind hole without affecting the oxide layer covering the inside of the second blind hole. Then, copper is deposited on the front side for metallization to realize the conductive connection between the first blind hole and the second blind hole while avoiding leakage.

[0048] In one embodiment, the main function of TSV is to provide a signal conduction link for the product, so this interlayer via can have a lower resistance and the shortest link than the in-plane wiring, which can effectively improve the aspects of avoiding signal interference and increasing power capacity, and is one of the ideal solutions for 2.5D and 3D packaging. By setting the first blind hole, the chip area can be effectively reduced and the density can be increased. At the same time, the isolation layer seed layer coverage and filling of the first blind hole are the main difficulties.

[0049] The ratio of the second preset depth to the first preset depth is in the range of [3,10]. By setting the ratio, the depth of the second blind hole as the large hole is reduced, while the required total depth of the silicon through hole remains unchanged, reducing the occurrence of undercuts and avoiding the coverage problem of the metal seed layer in the subsequent hole filling process. At the same time, by setting the aperture and depth ratio of the first blind hole and the second blind hole, the coverage and filling of the isolation layer seed layer of the first blind hole are controlled.

[0050] The aperture of the first blind hole as a small hole can be set at 8 microns to 10 microns, reflecting the advantage of small pitch. The bottom of the single-sided etched hole is all silicon, without a dielectric, and there will be no reflective etching phenomenon caused by charge accumulation. The isolation layer coverage and filling with a ratio of 10:1 between the second preset depth and the first preset depth is easy to achieve, and the depth of the small hole is controlled between 60 microns and 80 microns, which is easier to ensure quality.

[0051] The upper reverse side of the first silicon substrate does not involve the internal structure of the sensor, and the aperture size of the large hole can be relatively large. For example, based on a TSV with a total thickness of 300 microns, the depth of the large hole can be set to 240 microns, and the depth of the small hole is 40 microns, then the ratio of the second preset depth to the first preset depth is 4:1. The aperture of the large hole can be designed to be between 40 microns and 60 microns, which meets the aperture ratio range of the second blind hole and the first blind hole of [3,10]. For the process of etching the large hole, the small hole has been filled, the bottom of the large hole is all silicon, and there is no dielectric, so reverse etching will not occur, and the filling layer coverage and filling are easy to achieve.

[0052] In one embodiment, after filling the first blind hole, before etching the second blind hole at a position on the back side of the first silicon substrate opposite to the first blind hole, the front side of the first silicon substrate having the filled through silicon via structure and the one side of the second silicon substrate are bonded, including: preparing an oxide layer on the front side of the first silicon substrate having the filled through silicon via structure; and bonding the oxide layer to one side of the second silicon substrate.

[0053] Alternatively, bonding the front side of the first silicon substrate having the filled through silicon via structure to one side of the second silicon substrate further includes: preparing an oxide layer on one side of the second silicon substrate; and bonding the front side of the first silicon substrate having the filled through silicon via structure to the oxide layer.

[0054] For example, since bonding the front side of the first silicon substrate to the oxide layer after filling the first blind hole will not involve the problem of oxide layer reflection when etching the hole, both bonding times are possible, providing greater flexibility and operating space for the process flow.

[0055] In one embodiment, after filling the second blind hole, the method for preparing the MEMS bulk silicon structure further includes: A fluorocarbon-based protective layer or a hydrocarbon-based protective layer is deposited on the back side of the first silicon substrate.

[0056] Fluorocarbon-based and hydrocarbon-based protective layers have excellent chemical stability and hydrophobicity, which can effectively prevent the hole wall from chemical corrosion, water erosion and physical damage that may be encountered in subsequent process steps. These protective layers can tightly cover the hole wall to form a solid barrier to protect the structural integrity and functionality of the hole. Using dry film deposition or other automated deposition techniques for protective layer deposition usually has a faster deposition rate and a higher degree of automation, which can significantly improve production efficiency.

[0057] The preparation method of the MEMS bulk silicon structure of the embodiment of the present application first carves a first blind hole as a small hole on the front side, and then carves a second blind hole as a large hole on the back side. The etching falls directly on the silicon layer without involving the oxide layer, thereby avoiding the phenomenon of ion reflection causing the bottom of the hole to expand due to the landing of the general TSV in the dielectric area. Therefore, the process morphology and metal filling are easy to control, avoiding the "undercut" or footing effect at the bottom of the first silicon substrate. The back etching falls on the metal and silicon layers, which also avoids the "undercut" or footing effect at the bottom of the first silicon substrate, thereby improving the coverage quality of the metal seed layer of the silicon via, thereby improving the reliability of the electrical performance of the silicon via.

[0058] The present application provides a MEMS sensor provided with a MEMS bulk silicon structure prepared by the method for preparing the MEMS bulk silicon structure of the above embodiment.

[0059] The beneficial effects of a through silicon via and a MEMS sensor refer to the beneficial effects of a method for preparing a MEMS bulk silicon structure.

[0060] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0061] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for preparing a MEMS bulk silicon structure, characterized in that: The MEMS bulk silicon structure includes a first silicon substrate and a second silicon substrate, and the method includes: Etching a first blind hole on the front side of the first silicon substrate; the first blind hole has a first preset depth; filling the first blind hole; A second blind hole is etched at a position on the back side of the first silicon substrate facing the first blind hole; the second blind hole has a second preset depth; the aperture of the second blind hole is greater than the aperture of the first blind hole; the sum of the first preset depth and the second preset depth is the thickness of the first silicon substrate; Filling the second blind hole to form a filled through silicon via structure with a goblet structure; The front surface of the first silicon substrate having the filled through silicon via structure is bonded to one side of the second silicon substrate to form a MEMS bulk silicon structure.

2. The method for preparing a MEMS bulk silicon structure according to claim 1, characterized in that: The method of bonding the front side of the first silicon substrate having the filled through silicon via structure to one side of the second silicon substrate comprises: Preparing an oxide layer on the front side of the first silicon substrate having the filled through silicon via structure; The oxide layer is bonded to one side of the second silicon substrate.

3. The method for preparing a MEMS bulk silicon structure according to claim 2, characterized in that: The method of bonding the front surface of the first silicon substrate having the filled through silicon via structure to one side of the second silicon substrate further includes: preparing an oxide layer on one side of the second silicon substrate; The front side of the first silicon substrate having the filled through silicon via structure is bonded to the oxide layer.

4. The method for preparing a MEMS bulk silicon structure according to claim 1, characterized in that: The filling of the first blind hole comprises: depositing a first initial barrier layer in the first blind hole; Etching away the bottom of the first initial barrier layer to form a first final barrier layer; depositing a first seed layer on the first final barrier layer; Based on the first seed layer, the first blind hole is filled by electroplating.

5. The method for preparing a MEMS bulk silicon structure according to claim 1, characterized in that: The step of filling the second blind hole comprises: depositing a second initial barrier layer in the second blind hole; Opening a connecting hole at the bottom of the second initial barrier layer to form a second final barrier layer; Depositing a second seed layer on the second final barrier layer; the second seed layer fills the connecting hole; Based on the second seed layer, the second blind hole is filled by electroplating.

6. The method for preparing a MEMS bulk silicon structure according to claim 5, characterized in that: The step of opening a connecting hole on the bottom surface of the second initial barrier layer comprises: A connecting hole is opened on the bottom surface of the second initial barrier layer by a preset method; the preset method includes laser spot ablation, ion milling or electrochemical corrosion.

7. The method for preparing a MEMS bulk silicon structure according to claim 1, wherein: The ratio of the second preset depth to the first preset depth is in the range of [3, 10].

8. The method for preparing a MEMS bulk silicon structure according to any one of claims 1 to 7, characterized in that: After filling the second blind hole, the method for preparing the MEMS bulk silicon structure further includes: A fluorocarbon-based protective layer or a hydrocarbon-based protective layer is deposited on the back side of the first silicon substrate.

9. The method for preparing a MEMS bulk silicon structure according to any one of claims 1 to 7, characterized in that: The aperture ratio of the second blind hole to the first blind hole is in the range of [3, 10].

10. A MEMS sensor, characterized in that: A MEMS bulk silicon structure prepared by the method for preparing a MEMS bulk silicon structure according to any one of claims 1 to 9 is provided.

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