Electromagnetic valve average current measuring circuit and method

Abstract

The embodiment of the invention discloses a circuit and method for measuring the average current of an electromagnetic valve, and belongs to the technical field of automotive electronics. The circuit comprises an electromagnetic valve, a first power supply, a sampling resistor, a field effect transistor driving circuit, a current acquisition circuit, an integral circuit and an integral reset circuit, the field effect transistor driving circuit is used for controlling the on-off state of the first field effect transistor based on the pulse width modulation gating signal; the first power supply is used for providing driving current for the electromagnetic valve under the condition that the first field effect transistor is in a conducting state, and the driving current flows through the sampling resistor; the current acquisition circuit is used for sampling voltage signals on two sides of the sampling resistor and outputting the voltage signals to the integrating circuit; the integral circuit is used for performing integral processing on the voltage signal and determining the average current of the electromagnetic valve based on an integral result; and the integral reset circuit is used for performing periodic reset processing on the integral circuit based on the pulse width modulation gating signal.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of automotive electronics technology, and in particular to a circuit and method for measuring an average current of a solenoid valve. Background Art

[0002] For automotive hydraulic transmissions, whether it is a continuously variable transmission (CVT), dual clutch transmission (DCT), dedicated hybrid transmission (DHT), or 8AT transmission (8-Speed ​​Automatic Transmission), solenoid valves are used to control the main oil pressure, clutch oil pressure, synchronizer, cooling flow, etc. In order to obtain more precise pressure control, precise proportional solenoid valves are usually used, that is, the driving current of the solenoid valve is used as the control target, and the control is completed by the TCU (Transmission Control Unit).

[0003] In the related technology, a solenoid valve driving current software closed-loop control method is adopted, which is controlled by a combination of discrete MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) and microcontroller unit (Microcontroller Unit, MCU) microcontroller software. The MCU software collects the real-time driving current flowing through the solenoid valve and TCUMOS tube in real time, and then calculates the average current, and then uses the average value for closed-loop control of the software target current.

[0004] The transmission solenoid valve has a driving frequency of up to 1,000 Hz, which means that the TCU needs to collect current values ​​at multiple points in a short period of time for average calculation. When multiple solenoid valves need to be controlled simultaneously, the MCU software load rate will increase significantly, resulting in reduced control of the solenoid valves. Summary of the invention

[0005] The present application example provides a circuit and method for measuring the average current of a solenoid valve, and the technical solution is as follows.

[0006] On the one hand, an embodiment of the present application provides a circuit for measuring an average current of a solenoid valve, the circuit comprising a solenoid valve, a first power supply, a sampling resistor, a field effect transistor drive circuit, a current acquisition circuit, an integration circuit, and an integration reset circuit;

[0007] The field effect transistor driving circuit is used to control the on-off state of the first field effect transistor based on the pulse width modulation gate signal;

[0008] The first power supply is used to provide a driving current for the solenoid valve when the first field effect transistor is in an on state, and the driving current flows through the sampling resistor;

[0009] The current acquisition circuit is used to sample the voltage signal at both sides of the sampling resistor and output the voltage signal to the integration circuit;

[0010] The integration circuit is used to integrate the voltage signal and determine the average current of the solenoid valve based on the integration result;

[0011] The integration reset circuit is used to perform periodic reset processing on the integration circuit based on the pulse width modulation gating signal.

[0012] Optionally, the field effect transistor driving circuit includes the first field effect transistor, a gating signal source, a first inverter, a first gated clock, a first switch, a second gated clock and a second switch;

[0013] The positive electrode of the selection signal source is connected to the input end of the first inverter, the output end of the first inverter is connected to the control end of the first switch, the positive electrode of the selection signal source is connected to the control end of the second switch, and the negative electrode of the selection signal source is grounded;

[0014] The positive electrode of the first gated clock is connected to the first switch pin of the first switch, and the negative electrode of the first gated clock is grounded; the positive electrode of the second gated clock is connected to the first switch pin of the second switch, and the negative electrode of the second gated clock is grounded;

[0015] The second switch pin of the first switch is connected to the gate of the first field effect transistor, and the second switch pin of the second switch is connected to the gate of the first field effect transistor;

[0016] The selection signal source is used to output a selection signal to control the opening and closing states of the first switch and the second switch;

[0017] When the gating signal source does not output a gating signal, the first switch is in a closed state, the second switch is in an open state, and the first gating clock outputs a pulse width modulation gating signal with a high duty cycle to the gate of the first field effect transistor;

[0018] When the selection signal source outputs the selection signal, the first switch is in an open state, the second switch is in a closed state, and the second gating clock outputs a pulse width modulation gating signal with a low duty cycle to the gate of the first field effect transistor.

[0019] Optionally, the field effect transistor driving circuit further includes a freewheeling diode, an anode of the freewheeling diode is connected to the drain of the first field effect transistor, a cathode of the freewheeling diode is connected to the first power supply, and a source of the first field effect transistor is grounded;

[0020] The first power supply is connected to the first pin of the solenoid valve, the second pin of the solenoid valve is connected to the first resistor pin of the sampling resistor, and the second resistor pin of the sampling resistor is connected to the drain of the first field effect transistor;

[0021] When the pulse width modulation gate control signal is in a high level state, the first field effect transistor is in a conducting state, and the first power supply provides a driving current for the solenoid valve;

[0022] When the pulse width modulation gating signal is in a low level state, the first field effect transistor is in a disconnected state, and the first power supply does not provide the driving current to the solenoid valve.

[0023] Optionally, the current acquisition circuit includes a first operational amplifier, a feedback resistor, a voltage divider resistor, a filter capacitor and a second power supply, and the second power supply supplies power to the first operational amplifier;

[0024] The non-inverting input terminal and the inverting input terminal of the first operational amplifier are connected to the voltage-dividing resistor and the filter capacitor, and the output terminal of the first operational amplifier is connected to the integration circuit;

[0025] The first resistance pin of the feedback resistor is connected to the inverting input terminal of the first operational amplifier, and the second resistance pin of the feedback resistor is connected to the output terminal of the first operational amplifier;

[0026] The voltage dividing resistor is used to perform voltage dividing processing on the voltage signal and output the divided voltage signal to the first operational amplifier;

[0027] The first operational amplifier is used to amplify the voltage signal and output the amplified voltage signal to the integration circuit.

[0028] Optionally, the voltage-dividing resistor includes a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, and a fourth voltage-dividing resistor; the filter capacitor includes a first filter capacitor and a second filter capacitor;

[0029] The first resistor pin of the first voltage-dividing resistor is connected to the first resistor pin of the sampling resistor, and the second resistor pin of the first voltage-dividing resistor is connected to the non-inverting input terminal of the first operational amplifier; the first resistor pin of the second voltage-dividing resistor is connected to the second resistor pin of the sampling resistor, and the second resistor pin of the second voltage-dividing resistor is connected to the inverting input terminal of the first operational amplifier; the first resistor pin of the third voltage-dividing resistor is connected to the non-inverting input terminal of the first operational amplifier, and the second resistor pin of the third voltage-dividing resistor is grounded; the first resistor pin of the fourth voltage-dividing resistor is connected to the inverting input terminal of the first operational amplifier, and the second resistor pin of the fourth voltage-dividing resistor is grounded;

[0030] The first capacitor pin of the first filter capacitor is connected to the non-inverting input terminal of the first operational amplifier, and the second capacitor pin of the first filter capacitor is grounded; the first capacitor pin of the second filter capacitor is connected to the inverting input terminal of the first operational amplifier, and the second capacitor pin of the second filter capacitor is grounded;

[0031] The current acquisition circuit further includes a protection capacitor; a first capacitor pin of the protection capacitor is connected to a first resistor pin of the sampling resistor, and a second capacitor pin of the protection capacitor is grounded.

[0032] Optionally, the integration circuit includes a second operational amplifier, an integration resistor, an integration capacitor circuit, a multiplier, a third power supply and a fourth power supply, the third power supply supplies power for the second operational amplifier, and the fourth power supply supplies power for the multiplier;

[0033] The first resistance pin of the integrating resistor is connected to the current acquisition circuit, the second resistance pin of the integrating resistor is connected to the non-inverting input terminal of the second operational amplifier, the integrating capacitor circuit is connected to the non-inverting input terminal of the second operational amplifier, and the output terminal of the second operational amplifier is connected to the input terminal of the multiplier;

[0034] The integration circuit further includes a first proportional resistor, a second proportional resistor and a third proportional resistor; a first resistor pin of the first proportional resistor is connected to the inverting input terminal of the second operational amplifier, and a second resistor pin of the first proportional resistor is grounded; a first resistor pin of the second proportional resistor is connected to the inverting input terminal of the second operational amplifier, and a second resistor pin of the second proportional resistor is connected to the output terminal of the second operational amplifier; a first resistor pin of the third proportional resistor is connected to the non-inverting input terminal of the second operational amplifier, and a second resistor pin of the third proportional resistor is connected to the output terminal of the second operational amplifier;

[0035] The second operational amplifier is used to perform an integration operation on the voltage signal and output the voltage signal after the integration operation to the multiplier;

[0036] The multiplier is used to perform a multiplication operation on the voltage signal after the integration operation, and determine the average current of the solenoid valve based on the multiplication result.

[0037] Optionally, the integral capacitor circuit includes a second inverter, a second field effect transistor, a third field effect transistor, a first integral capacitor and a second integral capacitor;

[0038] The gate of the second field effect transistor is connected to the integral reset circuit, the source of the second field effect transistor is connected to the first capacitor pin of the first integral capacitor, and the drain of the second field effect transistor is connected to the second capacitor pin of the first integral capacitor;

[0039] The input end of the second inverter is connected to the integral reset circuit, and the output end of the second inverter is connected to the gate of the third field effect transistor;

[0040] The source of the third field effect transistor is connected to the first capacitor pin of the second integral capacitor, and the drain of the third field effect transistor is connected to the second capacitor pin of the second integral capacitor.

[0041] Optional,

[0042] When receiving the high level signal output by the integral reset circuit, the second field effect transistor is in the on state, the third field effect transistor is in the off state, the first integral capacitor is in the short circuit state, and the second integral capacitor is used for integral operation processing of the voltage signal;

[0043] When receiving a low-level signal output by the integral reset circuit, the second field effect transistor is in an off state, the third field effect transistor is in an on state, the second integral capacitor is in a short-circuit state, and the first integral capacitor is used for integral operation processing of the voltage signal.

[0044] Optionally, the integral reset circuit includes a D flip-flop and a protection resistor, the first resistor pin of the protection resistor is connected to the inverting output terminal of the D flip-flop, the second resistor pin of the protection resistor is grounded, and the clock input terminal of the D flip-flop is connected to the gate of the first field effect transistor;

[0045] The D flip-flop is a rising edge flip-flop, the data input terminal of the D flip-flop is connected to the inverting output terminal, and the inverting output terminal is connected to the integration circuit;

[0046] The D flip-flop is used to receive the pulse width modulation gating signal through the clock input terminal;

[0047] The D flip-flop is used to output the inverted signal of the inverted output terminal to the data input terminal to flip the signal state of the inverted output terminal when receiving the rising edge of the pulse width modulation gating signal.

[0048] On the other hand, an embodiment of the present application provides a method for measuring an average current of a solenoid valve, the method being used in a circuit for measuring an average current of a solenoid valve, the circuit comprising a solenoid valve, a first power supply, a sampling resistor, a field effect transistor drive circuit, a current acquisition circuit, an integration circuit, and an integration reset circuit;

[0049] The method comprises:

[0050] Based on the pulse width modulation gating signal, controlling the conduction state of the first field effect tube through the field effect tube driving circuit;

[0051] When the first field effect transistor is in an on state, the first power supply provides a driving current to the solenoid valve, and the driving current flows through the sampling resistor;

[0052] Sampling the voltage signals at both sides of the sampling resistor by the current acquisition circuit, and outputting the voltage signals to the integration circuit;

[0053] Integrating the voltage signal through the integration circuit, and determining the average current of the solenoid valve based on the integration result;

[0054] Based on the pulse width modulation gating signal, the integration circuit is periodically reset by the integration reset circuit.

[0055] In the embodiment of the present application, a measurement circuit of the average current of the solenoid valve is proposed, that is, the average current of the solenoid valve is measured directly by means of a hardware circuit, which can achieve the effective measurement of the average current of the solenoid valve while reducing the load rate of the control software. And the measurement circuit mainly includes a field effect tube drive circuit, a current acquisition circuit, an integration circuit and an integration reset circuit, which can simulate the software output behavior through a pulse width modulation gate signal in the field effect tube drive circuit, effectively control the on-off state of the first field effect tube in the field effect tube drive circuit, and when the first field effect tube is in the on state, the first power supply provides the driving current for the solenoid valve, so that when the driving current flows through the sampling resistor, the current sampling circuit is used for sampling, and the sampling voltage signal is integrated by the integration circuit, and finally the average current of the solenoid valve in a single cycle can be obtained according to the integration result. Obviously, only more conventional electronic components are used in the measurement circuit, which can reduce the cost of the measurement circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 A schematic diagram of a frame of a circuit for measuring an average current of a solenoid valve provided by an exemplary embodiment of the present application is shown;

[0058] Figure 2 A circuit structure diagram of a field effect transistor driving circuit provided by an exemplary embodiment of the present application is shown;

[0059] Figure 3 A circuit structure diagram of a current acquisition circuit provided by an exemplary embodiment of the present application is shown;

[0060] Figure 4 A circuit structure diagram of an integration circuit provided by an exemplary embodiment of the present application is shown;

[0061] Figure 5 A circuit structure diagram of an integral reset circuit provided by an exemplary embodiment of the present application is shown;

[0062] Figure 6 A circuit structure diagram of a solenoid valve average current measurement circuit provided by an exemplary embodiment of the present application is shown;

[0063] Figure 7 shows a waveform diagram of a voltage signal and a current signal provided by an exemplary embodiment of the present application;

[0064] Figure 8 A waveform variation diagram of a pulse width modulation gating signal with a decreasing duty cycle provided by an exemplary embodiment of the present application is shown;

[0065] Fig. 9 A waveform detail diagram of a voltage signal and a current signal provided by an exemplary embodiment of the present application is shown;

[0066] Fig.10 A flow chart of a method for measuring an average current of a solenoid valve provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0067] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0068] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0069] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0070] It should be understood that, although the terms first, second, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0071] In the related technology, the solenoid valve driving current software closed-loop control method is usually adopted to control the solenoid valve of the gearbox. And the discrete MOS and MCU single-chip software combined control is adopted. The MCU software collects the real-time driving current flowing through the solenoid valve and TCU MOS tube in real time, and then calculates the average current, and then uses the average value for the closed-loop control of the software target current.

[0072] The transmission solenoid valve has a driving frequency of up to 1,000 Hz, which means that the TCU needs to collect current values ​​at multiple points in a short period of time for average calculation. When multiple solenoid valves need to be controlled simultaneously, the MCU software load rate will increase significantly, resulting in reduced control of the solenoid valves.

[0073] Based on this, the embodiment of the present application proposes a solenoid valve average current measurement circuit, which uses a hardware circuit to measure the average current of the solenoid valve, so as to achieve effective measurement of the average current of the solenoid valve while reducing the load rate of the control software. The solenoid valve average current measurement circuit proposed in the present application will be described below through a specific embodiment.

[0074] Please refer to Figure 1 , which shows a schematic framework diagram of a measurement circuit for an average current of a solenoid valve provided by an exemplary embodiment of the present application.

[0075] Indicatively, Figure 1 As shown, the measurement circuit includes a solenoid valve 110, a first power supply 120, a sampling resistor (not shown), a field effect (MOS, MOSFET) tube drive circuit 130, a current acquisition circuit 140, an integration circuit 150 and an integration reset circuit 160.

[0076] The field effect transistor driving circuit 130 is used to control the on-off state of the first field effect transistor based on the pulse width modulation gate signal.

[0077] Optionally, for the solenoid valve in the hybrid vehicle gearbox, pulse width modulation (PWM) is usually used for control. PWM control parameters include frequency and duty cycle. The choice of frequency is related to the controlled object. For the automotive hydraulic system, a carrier frequency of several hundred hertz to several thousand hertz is usually used. The change of duty cycle and frequency directly affects the power loss, output pressure stability and dynamic response characteristics of the solenoid valve.

[0078] In some embodiments, a field effect transistor driving circuit can be set in the measurement circuit, and the pulse width modulation gating signal output by the field effect transistor driving circuit can be used to simulate the output behavior in the software control, thereby controlling the on and off state of the first field effect transistor according to the PWM gating signal.

[0079] The first power supply 120 is used to provide a driving current to the solenoid valve 110 when the first field effect tube is in a conducting state, and the driving current flows through the sampling resistor.

[0080] In some embodiments, when the first field effect transistor is in the on state, the first power supply can provide a driving current for the solenoid valve. At this time, the driving current can flow through the sampling resistor to facilitate sampling by the current acquisition circuit.

[0081] Optionally, the voltage of the first power supply can be set to 9V to 16V.

[0082] The current collection circuit 140 is used to sample the voltage signal at both sides of the sampling resistor and output the voltage signal to the integration circuit 150 .

[0083] In some embodiments, considering that it is difficult to directly measure the current in the circuit, while the voltage signal is relatively stable, the average current of the solenoid valve can be indirectly measured by sampling the voltage signal. Optionally, the current acquisition circuit is connected in parallel on both sides of the sampling resistor, so that the voltage signal on both sides of the sampling resistor can be sampled.

[0084] Furthermore, in order to determine the average current of the solenoid valve in a single cycle during the solenoid valve control process, the sampled voltage signal needs to be integrated. Therefore, the current acquisition circuit also needs to be connected to the integration circuit and output the collected voltage signal to the integration circuit.

[0085] The integration circuit 150 is used to integrate the voltage signal and determine the average current of the solenoid valve based on the integration result.

[0086] In some embodiments, after receiving the voltage signal output by the current acquisition circuit, the integration circuit can integrate the voltage signal, thereby obtaining the average voltage of the solenoid valve in a single cycle according to the integration result. Furthermore, according to the conversion relationship between voltage and current, the average current of the solenoid valve in a single cycle can be determined.

[0087] The integration reset circuit 160 is used to periodically reset the integration circuit 150 based on the pulse width modulation gating signal.

[0088] In some embodiments, in order to determine the average current of the solenoid valve in a single cycle and avoid the accumulation of multi-cycle voltage signals, after determining the average current of a single cycle through an integration circuit, it is also necessary to periodically reset the integration circuit through an integration reset circuit according to a PWM gating signal.

[0089] Optionally, the integration reset process refers to an operation in the integration circuit to reset the integration process by introducing an external signal or condition to return it to an initial state. In the embodiment of the present application, the integration reset is to discharge the integration capacitor in the integration circuit.

[0090] In summary, in the embodiment of the present application, a measurement circuit of the average current of the solenoid valve is proposed, that is, the average current of the solenoid valve is measured directly by means of a hardware circuit, which can achieve the effective measurement of the average current of the solenoid valve while reducing the load rate of the control software. And the measurement circuit mainly includes a field effect tube drive circuit, a current acquisition circuit, an integration circuit and an integration reset circuit, which can simulate the software output behavior through a pulse width modulation gate signal in the field effect tube drive circuit, effectively control the on-off state of the first field effect tube in the field effect tube drive circuit, and when the first field effect tube is in the on state, the first power supply provides the driving current for the solenoid valve, so that when the driving current flows through the sampling resistor, the current sampling circuit is used for sampling, and the sampled voltage signal is integrated by the integration circuit, and finally the average current of the solenoid valve in a single cycle can be obtained according to the integration result. Obviously, only more conventional electronic components are used in the measurement circuit, which can reduce the cost of the measurement circuit.

[0091] The internal circuit structure of each circuit will be described below.

[0092] Please refer to Figure 2 , which shows a circuit structure diagram of a field effect transistor driving circuit provided by an exemplary embodiment of the present application.

[0093] Indicatively, Figure 2 As shown, the field effect transistor driving circuit includes a first field effect transistor 250 , a gate signal source 260 , a first inverter 271 , a first gated clock 273 , a first switch 272 , a second gated clock 275 and a second switch 274 .

[0094] The first gated clock 273 is used to output a PWM gated signal with a high duty cycle, and the second gated clock 275 is used to output a PWM gated signal with a low duty cycle. Optionally, the output frequency of the PWM gated signal may be 3KHz.

[0095] Optionally, the positive electrode of the selection signal source 260 is connected to the input end of the first inverter 271, the output end of the first inverter 271 is connected to the control end of the first switch 272, the positive electrode of the selection signal source 260 is connected to the control end of the second switch 274, and the negative electrode of the selection signal source 260 is grounded.

[0096] Optionally, the positive electrode of the first gated clock 273 is connected to the first switch pin of the first switch 272, and the negative electrode of the first gated clock 273 is grounded. The positive electrode of the second gated clock 275 is connected to the first switch pin of the second switch 274, and the negative electrode of the second gated clock 275 is grounded.

[0097] Optionally, the second switch pin of the first switch 272 is connected to the gate of the first field effect transistor 250 , and the second switch pin of the second switch 274 is connected to the gate of the first field effect transistor 250 .

[0098] Optionally, the selection signal source 260 is used to output a selection signal to control the opening and closing states of the first switch and the second switch.

[0099] Optionally, the strobe signal is a high level signal, and the strobe signal is used to trigger the gated clock to send out a PWM gated signal. Optionally, the strobe signal source can send out a strobe signal every 5 ms.

[0100] Optionally, when the gating signal source does not output the gating signal, the first switch is closed and the second switch is opened; when the gating signal source outputs the gating signal, the first switch is opened and the second switch is closed. That is, the first gating clock and the second gating clock alternately output PWM gating signals to the first field effect transistor.

[0101] In one possible embodiment, when the selection signal source 260 does not output the selection signal, the control end of the second switch 274 does not receive a high-level signal, so the second switch 274 is in an open state, and the input end of the first inverter 271 is a low-level signal. After the control end of the first switch 272 receives the high level output by the first inverter 271, the first switch 272 is in a closed state, so that the positive electrode of the first gated clock 273 is connected to the gate of the first field effect transistor 250, and the first gated clock 273 can output a high-duty-cycle pulse width modulation gating signal to the first field effect transistor 250.

[0102] In another possible embodiment, when the selection signal source 260 outputs the selection signal, the control end of the second switch 274 receives a high-level signal, so the second switch 274 is in a closed state, and the input end of the first inverter 271 is a high-level signal. Then, after the control end of the first switch 272 receives the low-level signal output by the first inverter 271, the first switch 272 is in an open state, so that the positive electrode of the second gated clock 275 is connected to the gate of the first field effect transistor 250, and the second gated clock 275 can output a low-duty-cycle pulse width modulation gating signal to the first field effect transistor 250.

[0103] Optionally, considering that the first power supply periodically supplies power to the solenoid valve based on the PWM gating signal, and the solenoid valve is an inductive load and the current will not change suddenly, a freewheeling diode is also required to be connected in parallel on both sides of the solenoid valve so that the solenoid valve gradually releases current when no driving current is received.

[0104] Indicatively, Figure 2 As shown, the field effect tube driving circuit also includes a flyback diode 240, the anode of the flyback diode 240 is connected to the drain of the first field effect tube 250, and the cathode of the flyback diode 240 is connected to the first power supply 210, that is, to the solenoid valve 220 ( Figure 2 The first pin of the solenoid valve (in which the solenoid valve is represented by a combination of an inductor and a resistor) is connected to the first field effect transistor 250, and the source of the first field effect transistor 250 is grounded.

[0105] Optionally, the first power supply 210 is connected to the first pin of the solenoid valve 220, the second pin of the solenoid valve 220 is connected to the first resistor pin of the sampling resistor 230, and the second resistor pin of the sampling resistor 230 is connected to the drain of the first field effect transistor 250, that is, connected to the anode of the freewheeling diode 240.

[0106] In a possible manner, when the pulse width modulation gate control signal is in a high level state, the first field effect tube 250 is in a conducting state, and the first power supply 210 provides a driving current for the solenoid valve 220. Figure 2As shown, current flows out from the first power supply 210 and flows into the solenoid valve 220 , the current of the solenoid valve 220 rises, and then the current flows out from the solenoid valve 220 and flows through the sampling resistor 230 , and finally flows into the first field effect transistor 250 .

[0107] In another possible manner, when the pulse width modulation gate control signal is in a low level state, the first field effect transistor 250 is in a disconnected state, and the first power supply 210 does not provide a driving current for the solenoid valve 220. Figure 2 As shown, the solenoid valve 220 releases current, the current flows through the sampling resistor 230 and the freewheeling diode 240 and is slowly released, and the current decreases.

[0108] In the above embodiment, in the field effect tube driving circuit, the on-off state of the first field effect tube is controlled by the PWM gating signal, that is, the current of the solenoid valve can be controlled to rise and fall periodically. When a larger current is required, a PWM gating signal with a high duty cycle can be output through the first gating clock; when a smaller current is required, a PWM gating signal with a low duty cycle can be output through the second gating clock.

[0109] Please refer to Figure 3 , which shows a circuit structure diagram of a current acquisition circuit provided by an exemplary embodiment of the present application.

[0110] Indicatively, Figure 3 As shown, the current acquisition circuit includes a first operational amplifier 370 , a feedback resistor 350 , a voltage divider resistor, a filter capacitor and a second power supply 360 , and the second power supply 360 supplies power to the first operational amplifier 370 .

[0111] The non-inverting input terminal and the inverting input terminal of the first operational amplifier 370 are connected to the voltage divider resistor and the filter capacitor, and the output terminal of the first operational amplifier 370 is connected to the integration circuit. The first resistor pin of the feedback resistor 350 is connected to the inverting input terminal of the first operational amplifier 370, and the second resistor pin of the feedback resistor 350 is connected to the output terminal of the first operational amplifier 370.

[0112] The voltage dividing resistor is used to perform voltage dividing processing on the voltage signal and output the divided voltage signal to the first operational amplifier.

[0113] Optionally, considering that the sampled voltages on both sides of the sampling resistor may not meet the voltage input requirement of the first operational amplifier, a voltage divider resistor needs to be provided at the input end of the first operational amplifier to avoid damage to the first operational amplifier.

[0114] Optionally, a voltage-dividing resistor is connected in parallel on both sides of the sampling resistor, and voltage-dividing processing can be performed on the voltage signals on both sides of the sampling resistor, and the divided voltage signals are output to the first operational amplifier.

[0115] The first operational amplifier is used to amplify the voltage signal and output the amplified voltage signal to the integration circuit.

[0116] Optionally, after receiving the voltage signal, the first operational amplifier can amplify the voltage signal and output the amplified voltage signal to the integration circuit. Optionally, the amplification factor is determined based on the resistance values ​​of the voltage divider resistor and the feedback resistor. By setting the resistance values ​​of the voltage divider resistor and the feedback resistor, the amplification factor can be set to ten times.

[0117] Indicatively, Figure 3 As shown, the voltage-dividing resistor may include a first voltage-dividing resistor 321 , a second voltage-dividing resistor 322 , a third voltage-dividing resistor 323 and a fourth voltage-dividing resistor 324 .

[0118] Among them, the first resistor pin of the first voltage-dividing resistor 321 is connected to the first resistor pin of the sampling resistor 310, and the second resistor pin of the first voltage-dividing resistor 321 is connected to the non-inverting input terminal of the first operational amplifier 370. The first resistor pin of the second voltage-dividing resistor 322 is connected to the second resistor pin of the sampling resistor 310, and the second resistor pin of the second voltage-dividing resistor 322 is connected to the inverting input terminal of the first operational amplifier 370. The first resistor pin of the third voltage-dividing resistor 323 is connected to the non-inverting input terminal of the first operational amplifier 370, and the second resistor pin of the third voltage-dividing resistor 323 is grounded. The first resistor pin of the fourth voltage-dividing resistor 324 is connected to the inverting input terminal of the first operational amplifier 370, and the second resistor pin of the fourth voltage-dividing resistor 324 is grounded.

[0119] Indicatively, Figure 3 As shown, the filter capacitor includes a first filter capacitor 341 and a second filter capacitor 342 .

[0120] The first capacitor pin of the first filter capacitor 341 is connected to the non-inverting input terminal of the first operational amplifier 370, and the second capacitor pin of the first filter capacitor 341 is grounded. The first capacitor pin of the second filter capacitor 342 is connected to the inverting input terminal of the first operational amplifier 370, and the second capacitor pin of the second filter capacitor 342 is grounded.

[0121] Optionally, the current acquisition circuit further includes a protection capacitor 330 , a first capacitor pin of the protection capacitor 330 is connected to a first resistor pin of the sampling resistor 310 , and a second capacitor pin of the protection capacitor 330 is grounded.

[0122] In the above embodiment, in the current acquisition circuit, the voltage signal on both sides of the sampling resistor is first divided by a voltage divider resistor so that the divided voltage signal meets the input requirement of the first operational amplifier, and then the voltage signal is amplified by the first operational amplifier to facilitate the subsequent integration circuit to integrate the amplified voltage signal.

[0123] Please refer to Figure 4 , which shows a circuit structure diagram of an integration circuit provided by an exemplary embodiment of the present application.

[0124] Indicatively, Figure 4 As shown, the integration circuit includes a second operational amplifier 430, an integration resistor 410, an integration capacitor circuit 420, a multiplier 460, a third power supply 451 and a fourth power supply 452. The third power supply 451 supplies power to the second operational amplifier 430, and the fourth power supply 452 supplies power to the multiplier 460.

[0125] Optionally, the first resistance pin of the integrating resistor 410 is connected to the current collection circuit, and the second resistance pin of the integrating resistor 410 is connected to the non-inverting input terminal of the second operational amplifier 430. The integrating capacitor circuit 420 is connected to the non-inverting input terminal of the second operational amplifier 430, and the output terminal of the second operational amplifier 430 is connected to the input terminal of the multiplier 460.

[0126] Optionally, in an embodiment of the present application, by setting the integrating capacitor circuit at the input end of the second operational amplifier instead of between the input end and the output end, the integrating circuit can be powered by a single power supply, thereby simplifying the design of the integrating circuit.

[0127] Optionally, in order to implement an integration operation on the voltage signal, the integration circuit may further include a first proportional resistor 441 , a second proportional resistor 442 and a third proportional resistor 443 .

[0128] Indicatively, Figure 4 As shown, the first resistance pin of the first proportional resistor 441 is connected to the inverting input terminal of the second operational amplifier 430, and the second resistance pin of the first proportional resistor 441 is grounded. The first resistance pin of the second proportional resistor 442 is connected to the inverting input terminal of the second operational amplifier 430, and the second resistance pin of the second proportional resistor 442 is connected to the output terminal of the second operational amplifier 430. The first resistance pin of the third proportional resistor 443 is connected to the non-inverting input terminal of the second operational amplifier 430, and the second resistance pin of the third proportional resistor 443 is connected to the output terminal of the second operational amplifier 430.

[0129] The second operational amplifier is used to perform integration operation on the voltage signal and output the voltage signal after the integration operation to the multiplier.

[0130] Optionally, after receiving the voltage signal output by the current acquisition circuit and filtering the voltage signal through the integration resistor and the integration capacitor circuit, the second operational amplifier can perform an integration operation on the voltage signal to obtain an integrated voltage signal, which is an integral value including a proportional factor. Furthermore, in order to obtain the average voltage of a single cycle, the second operational amplifier also needs to output the integrated voltage signal to the multiplier.

[0131] The multiplier is used to perform multiplication processing on the voltage signal after the integration operation, and determine the average current of the solenoid valve based on the multiplication result.

[0132] Optionally, after receiving the voltage signal output by the second operational amplifier, the multiplier can use a multiplication factor to perform multiplication processing on the integral value to obtain a multiplication result, that is, the average voltage of the solenoid valve in a single cycle. Further, according to the conversion relationship between voltage and current, the average current of the solenoid valve in a single cycle can be obtained accordingly.

[0133] In some embodiments, in order to obtain the current average value of each cycle of the PWM gating signal, it is also necessary to reset the integration circuit after obtaining the current average value of each cycle, so as to measure the average current of the solenoid valve again in the next PWM cycle.

[0134] Optionally, resetting the integration circuit can be achieved by periodically discharging the integration capacitor. Optionally, the integration capacitor circuit can be connected to the second operational amplifier in series with two capacitors in turn. Under the control of the dual field effect transistors, the upper and lower capacitors take turns to participate in the integration circuit, that is, when one capacitor participates in the integration, the other capacitor is bypassed by the switch and discharged to zero through the switch. Then, when the next PWM cycle arrives, the discharged capacitor participates in the integration, and the other capacitor is bypassed and discharged. By repeating this, the voltage and current average values ​​of each PWM cycle can be determined through the integration circuit.

[0135] Indicatively, Figure 4 As shown, the integral capacitor circuit includes a second inverter 425 , a second field effect transistor 422 , a third field effect transistor 424 , a first integral capacitor 421 and a second integral capacitor 423 .

[0136] The gate of the second field effect transistor 422 is connected to the integral reset circuit, the source of the second field effect transistor 422 is connected to the first capacitor pin of the first integral capacitor 421, and the drain of the second field effect transistor 422 is connected to the second capacitor pin of the first integral capacitor 421. The input end of the second inverter 425 is connected to the integral reset circuit, and the output end of the second inverter 425 is connected to the gate of the third field effect transistor 424. The source of the third field effect transistor 424 is connected to the first capacitor pin of the second integral capacitor 423, and the drain of the third field effect transistor 424 is connected to the second capacitor pin of the second integral capacitor 423.

[0137] In a possible manner, when receiving a high-level signal output by the integral reset circuit, the second field effect transistor 422 is in a conducting state, that is, the first integral capacitor 421 is short-circuited and in a short-circuit state, and the first integral capacitor 421 is bypassed and discharged. The third field effect transistor 424 receives a low-level signal output by the second inverter 425, and the third field effect transistor 424 is in a disconnected state, so the second integral capacitor 423 can be used to perform an integral operation on the voltage signal in the integral circuit.

[0138] In another possible manner, when receiving the low level signal output by the integral reset circuit, the second field effect tube 422 is in the disconnected state, so the first integral capacitor 421 can be used to perform integral operation processing on the voltage signal in the integral circuit. When the third field effect tube 424 receives the high level signal output by the second inverter 425, the third field effect tube 424 is in the on state, that is, the second integral capacitor 423 is short-circuited and in the short-circuit state, and the second integral capacitor 423 is bypassed and discharged.

[0139] In the above embodiment, in the integration circuit, after the voltage signal is integrated by the second operational amplifier, the integrated voltage value is multiplied by the multiplier, so that the average voltage value of a single cycle of the solenoid valve can be obtained, and thus the average current value of a single cycle can be accurately obtained based on the conversion relationship between voltage and current.

[0140] Optionally, in order to realize the alternating discharge control of the dual capacitors in the integral capacitor circuit based on the PWM cycle, it is necessary to control the integral capacitor circuit in the integral circuit through the integral reset circuit. And the signal frequency of the level signal output by the integral reset circuit to the capacitor integral circuit (i.e., the capacitor switching frequency) needs to be equal to half of the PWM gate signal frequency, i.e., divided by two.

[0141] Please refer to Figure 5 , which shows a circuit structure diagram of an integral reset circuit provided by an exemplary embodiment of the present application.

[0142] Indicatively, Figure 5As shown, the integral reset circuit includes a D flip-flop 510 and a protection resistor 520. The first resistor pin of the protection resistor 520 is connected to the inverting output terminal of the D flip-flop 510, the second resistor pin of the protection resistor 520 is grounded, and the clock input terminal of the D flip-flop 510 is connected to the gate of the first field effect transistor, that is, the clock input terminal of the D flip-flop 510 receives the PWM gating signal.

[0143] Optionally, the D flip-flop is a rising edge flip-flop, the data input terminal of the D flip-flop is connected to the inverting output terminal, and the inverting output terminal is connected to the integration circuit.

[0144] Optionally, the D flip-flop 510 is used to receive a pulse width modulation gating signal through a clock input terminal.

[0145] Optionally, the D flip-flop 510 is used to output the inverted signal of the inverted output terminal to the data input terminal to flip the signal state of the inverted output terminal when receiving the rising edge of the pulse width modulation gating signal.

[0146] In one possible manner, the initial state of the data input terminal of the D flip-flop 510 is set to 0, and the inverting output terminal of the D flip-flop 510 is 1. When the clock input terminal receives a cycle of PWM gating signal (the PWM gating signal is high level first and then low level in a single cycle), since the D flip-flop is a rising edge trigger and the data input terminal of the D flip-flop is connected to the inverting output terminal, the 1 of the inverting output terminal is applied to the data input terminal, the state of the data input terminal is switched to 1, and the state of the inverting output terminal is switched to 0. Further, when the PWM gating signal of the next cycle is received, the 0 of the inverting output terminal is applied to the data input terminal, the state of the data input terminal is switched to 0, and the state of the inverting output terminal is switched to 1. This is repeated, that is, when a cycle of PWM gating signal is received, the D flip-flop flips the signal once to realize the two-frequency processing of the PWM gating signal, thereby controlling the integral capacitor circuit in the integral circuit to perform periodic alternating charging and discharging with the two-frequency division of the PWM gating signal.

[0147] Combining the circuit structure diagrams in the above embodiments, we can get Figure 6 The circuit structure diagram of the measurement circuit of the average current of the solenoid valve provided by an exemplary embodiment of the present application is shown in FIG. Figure 6 It can be seen that the current acquisition circuit 620 is connected in parallel with the sampling resistor R1 in the field effect transistor driving circuit 610 to acquire the voltage signal on both sides of the sampling resistor. In addition, the output end of the first operational amplifier in the current acquisition circuit 620 is connected to the integration circuit 630, and the collected voltage signal can be output to the integration circuit 630, and the integration circuit 630 performs integration operation processing on the voltage signal.

[0148] In addition, in order to calculate the average current of a single cycle, the integration circuit 630 also needs to be connected to the integration reset circuit 640, and the integration reset circuit 640 outputs a two-frequency signal of the PWM gating signal to achieve periodic discharge control of the dual capacitors in the integration capacitor circuit. At the same time, the integration reset circuit 640 also needs to be connected to the field effect transistor drive circuit 610 to receive the PWM gating signal from the field effect transistor drive circuit 610.

[0149] By connecting and controlling the field effect tube drive circuit, current acquisition circuit, integration circuit and integration reset circuit, the average current of the solenoid valve can be measured, while reducing the design cost of the measurement circuit and the load rate of the control software.

[0150] Please refer to Figure 7 , which shows a waveform diagram of a voltage signal and a current signal provided by an exemplary embodiment of the present application.

[0151] like Figure 7 As shown, from bottom to top, the first layer is the duty cycle waveform, which includes two duty cycles; the second layer is the waveform of the two-division control signal; the third layer is the waveform of the solenoid valve drive current; the fourth layer is the waveform of the converted voltage signal; the fifth layer is the waveform of the cycle-by-cycle average voltage value.

[0152] Please refer to Figure 8 , which shows a downward trend waveform change diagram of a pulse width modulation gating signal when the duty cycle becomes smaller, provided by an exemplary embodiment of the present application.

[0153] like Figure 8 As shown, as the duty cycle of the PWM gating signal decreases, the collected current and voltage are decreasing, and the average voltage value of each PWM cycle is also decreasing.

[0154] Please refer to Fig. 9 , which shows the waveform details of the voltage signal and the current signal provided by an exemplary embodiment of the present application.

[0155] like Fig. 9 As shown, at the end of each PWM cycle, the average value reaches the maximum, and this moment is the average value of the cycle, and then the average value is reset to zero instantly, and the average value is obtained again in the next cycle, and finally the average value of PWM cycle by cycle is obtained.

[0156] Please refer to Fig.10 , which shows a flow chart of a method for measuring the average current of a solenoid valve provided by an exemplary embodiment of the present application. The method is used in a circuit for measuring the average current of a solenoid valve, the circuit comprising a solenoid valve, a first power supply, a sampling resistor, a field effect transistor drive circuit, a current acquisition circuit, an integration circuit, and an integration reset circuit.

[0157] Step 1001, based on a pulse width modulation gating signal, controlling the conduction state of a first field effect transistor through a field effect transistor driving circuit.

[0158] Optionally, for the solenoid valve in the hybrid vehicle gearbox, pulse width modulation (PWM) is usually used for control. PWM control parameters include frequency and duty cycle. The choice of frequency is related to the controlled object. For the automotive hydraulic system, a carrier frequency of several hundred hertz to several thousand hertz is usually used. The change of duty cycle and frequency directly affects the power loss, output pressure stability and dynamic response characteristics of the solenoid valve.

[0159] In some embodiments, a field effect transistor driving circuit can be set in the measurement circuit, and the pulse width modulation gating signal output by the field effect transistor driving circuit can be used to simulate the output behavior in the software control, thereby controlling the on and off state of the first field effect transistor according to the PWM gating signal.

[0160] Step 1002: When the first field effect transistor is in an on state, a driving current is provided to the solenoid valve through a first power supply, and the driving current flows through a sampling resistor.

[0161] In some embodiments, when the first field effect transistor is in the on state, the first power supply can provide a driving current for the solenoid valve. At this time, the driving current can flow through the sampling resistor to facilitate sampling by the current acquisition circuit.

[0162] Optionally, the voltage of the first power supply can be set to 9V to 16V.

[0163] Step 1003: Sample the voltage signal on both sides of the sampling resistor through the current acquisition circuit, and output the voltage signal to the integration circuit.

[0164] In some embodiments, considering that it is difficult to directly measure the current in the circuit, while the voltage signal is relatively stable, the average current of the solenoid valve can be indirectly measured by sampling the voltage signal. Optionally, the current acquisition circuit is connected in parallel on both sides of the sampling resistor, so that the voltage signal on both sides of the sampling resistor can be sampled.

[0165] Furthermore, in order to determine the average current of the solenoid valve in a single cycle during the solenoid valve control process, the sampled voltage signal needs to be integrated. Therefore, the current acquisition circuit also needs to be connected to the integration circuit and output the collected voltage signal to the integration circuit.

[0166] Step 1004: integrating the voltage signal through an integration circuit, and determining the average current of the solenoid valve based on the integration result.

[0167] In some embodiments, after receiving the voltage signal output by the current acquisition circuit, the integration circuit can integrate the voltage signal, thereby obtaining the average voltage of the solenoid valve in a single cycle according to the integration result. Furthermore, according to the conversion relationship between voltage and current, the average current of the solenoid valve in a single cycle can be determined.

[0168] Step 1005: Based on the pulse width modulation gating signal, the integration circuit is periodically reset by the integration reset circuit.

[0169] In some embodiments, in order to determine the average current of the solenoid valve in a single cycle and avoid the accumulation of multi-cycle voltage signals, after determining the average current of a single cycle through an integration circuit, it is also necessary to periodically reset the integration circuit through an integration reset circuit according to a PWM gating signal.

[0170] Optionally, the integration reset process refers to an operation in the integration circuit to reset the integration process by introducing an external signal or condition to return it to an initial state. In the embodiment of the present application, the integration reset is to discharge the integration capacitor in the integration circuit.

[0171] In summary, in the embodiment of the present application, a measurement circuit of the average current of the solenoid valve is proposed, that is, the average current of the solenoid valve is measured directly by means of a hardware circuit, which can achieve the effective measurement of the average current of the solenoid valve while reducing the load rate of the control software. And the measurement circuit mainly includes a field effect tube drive circuit, a current acquisition circuit, an integration circuit and an integration reset circuit, which can simulate the software output behavior through a pulse width modulation gate signal in the field effect tube drive circuit, effectively control the on-off state of the first field effect tube in the field effect tube drive circuit, and when the first field effect tube is in the on state, the first power supply provides the driving current for the solenoid valve, so that when the driving current flows through the sampling resistor, the current sampling circuit is used for sampling, and the sampled voltage signal is integrated by the integration circuit, and finally the average current of the solenoid valve in a single cycle can be obtained according to the integration result. Obviously, only more conventional electronic components are used in the measurement circuit, which can reduce the cost of the measurement circuit.

[0172] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0173] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A circuit for measuring average current of a solenoid valve, characterized in that: The circuit includes a solenoid valve, a first power supply, a sampling resistor, a field effect tube drive circuit, a current collection circuit, an integration circuit and an integration reset circuit; The field effect transistor driving circuit is used to control the on-off state of the first field effect transistor based on the pulse width modulation gate signal; The first power supply is used to provide a driving current for the solenoid valve when the first field effect transistor is in an on state, and the driving current flows through the sampling resistor; The current acquisition circuit is used to sample the voltage signal at both sides of the sampling resistor and output the voltage signal to the integration circuit; The integration circuit is used to integrate the voltage signal and determine the average current of the solenoid valve based on the integration result; The integration reset circuit is used to perform periodic reset processing on the integration circuit based on the pulse width modulation gating signal.

2. The circuit according to claim 1, characterized in that The field effect transistor driving circuit includes the first field effect transistor, a gating signal source, a first inverter, a first gated clock, a first switch, a second gated clock and a second switch; The positive electrode of the selection signal source is connected to the input end of the first inverter, the output end of the first inverter is connected to the control end of the first switch, the positive electrode of the selection signal source is connected to the control end of the second switch, and the negative electrode of the selection signal source is grounded; The positive electrode of the first gated clock is connected to the first switch pin of the first switch, and the negative electrode of the first gated clock is grounded; the positive electrode of the second gated clock is connected to the first switch pin of the second switch, and the negative electrode of the second gated clock is grounded; The second switch pin of the first switch is connected to the gate of the first field effect transistor, and the second switch pin of the second switch is connected to the gate of the first field effect transistor; The selection signal source is used to output a selection signal to control the opening and closing states of the first switch and the second switch; When the gating signal source does not output a gating signal, the first switch is in a closed state, the second switch is in an open state, and the first gating clock outputs a pulse width modulation gating signal with a high duty cycle to the gate of the first field effect transistor; When the selection signal source outputs the selection signal, the first switch is in an open state, the second switch is in a closed state, and the second gating clock outputs a pulse width modulation gating signal with a low duty cycle to the gate of the first field effect transistor.

3. The circuit according to claim 2, characterized in that The field effect transistor drive circuit further includes a freewheeling diode, wherein the anode of the freewheeling diode is connected to the drain of the first field effect transistor, the cathode of the freewheeling diode is connected to the first power supply, and the source of the first field effect transistor is grounded; The first power supply is connected to the first pin of the solenoid valve, the second pin of the solenoid valve is connected to the first resistor pin of the sampling resistor, and the second resistor pin of the sampling resistor is connected to the drain of the first field effect transistor; When the pulse width modulation gate control signal is in a high level state, the first field effect transistor is in a conducting state, and the first power supply provides a driving current for the solenoid valve; When the pulse width modulation gating signal is in a low level state, the first field effect transistor is in a disconnected state, and the first power supply does not provide the driving current to the solenoid valve.

4. The circuit according to claim 1, characterized in that The current acquisition circuit includes a first operational amplifier, a feedback resistor, a voltage divider resistor, a filter capacitor and a second power supply, and the second power supply supplies power to the first operational amplifier; The non-inverting input terminal and the inverting input terminal of the first operational amplifier are connected to the voltage-dividing resistor and the filter capacitor, and the output terminal of the first operational amplifier is connected to the integration circuit; The first resistance pin of the feedback resistor is connected to the inverting input terminal of the first operational amplifier, and the second resistance pin of the feedback resistor is connected to the output terminal of the first operational amplifier; The voltage dividing resistor is used to perform voltage dividing processing on the voltage signal and output the divided voltage signal to the first operational amplifier; The first operational amplifier is used to amplify the voltage signal and output the amplified voltage signal to the integration circuit.

5. The circuit according to claim 4, characterized in that The voltage-dividing resistors include a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, and a fourth voltage-dividing resistor; the filter capacitors include a first filter capacitor and a second filter capacitor; The first resistor pin of the first voltage-dividing resistor is connected to the first resistor pin of the sampling resistor, and the second resistor pin of the first voltage-dividing resistor is connected to the non-inverting input terminal of the first operational amplifier; the first resistor pin of the second voltage-dividing resistor is connected to the second resistor pin of the sampling resistor, and the second resistor pin of the second voltage-dividing resistor is connected to the inverting input terminal of the first operational amplifier; the first resistor pin of the third voltage-dividing resistor is connected to the non-inverting input terminal of the first operational amplifier, and the second resistor pin of the third voltage-dividing resistor is grounded; the first resistor pin of the fourth voltage-dividing resistor is connected to the inverting input terminal of the first operational amplifier, and the second resistor pin of the fourth voltage-dividing resistor is grounded; The first capacitor pin of the first filter capacitor is connected to the non-inverting input terminal of the first operational amplifier, and the second capacitor pin of the first filter capacitor is grounded; the first capacitor pin of the second filter capacitor is connected to the inverting input terminal of the first operational amplifier, and the second capacitor pin of the second filter capacitor is grounded; The current acquisition circuit further includes a protection capacitor; a first capacitor pin of the protection capacitor is connected to a first resistor pin of the sampling resistor, and a second capacitor pin of the protection capacitor is grounded.

6. The circuit according to claim 1, characterized in that The integration circuit includes a second operational amplifier, an integration resistor, an integration capacitor circuit, a multiplier, a third power supply and a fourth power supply, the third power supply supplies power for the second operational amplifier, and the fourth power supply supplies power for the multiplier; The first resistance pin of the integrating resistor is connected to the current acquisition circuit, the second resistance pin of the integrating resistor is connected to the non-inverting input terminal of the second operational amplifier, the integrating capacitor circuit is connected to the non-inverting input terminal of the second operational amplifier, and the output terminal of the second operational amplifier is connected to the input terminal of the multiplier; The integration circuit further includes a first proportional resistor, a second proportional resistor and a third proportional resistor; a first resistor pin of the first proportional resistor is connected to the inverting input terminal of the second operational amplifier, and a second resistor pin of the first proportional resistor is grounded; a first resistor pin of the second proportional resistor is connected to the inverting input terminal of the second operational amplifier, and a second resistor pin of the second proportional resistor is connected to the output terminal of the second operational amplifier; a first resistor pin of the third proportional resistor is connected to the non-inverting input terminal of the second operational amplifier, and a second resistor pin of the third proportional resistor is connected to the output terminal of the second operational amplifier; The second operational amplifier is used to perform an integration operation on the voltage signal and output the voltage signal after the integration operation to the multiplier; The multiplier is used to perform multiplication processing on the voltage signal after the integration operation, and determine the average current of the solenoid valve based on the multiplication result.

7. The circuit according to claim 6, characterized in that The integral capacitor circuit comprises a second inverter, a second field effect transistor, a third field effect transistor, a first integral capacitor and a second integral capacitor; The gate of the second field effect transistor is connected to the integral reset circuit, the source of the second field effect transistor is connected to the first capacitor pin of the first integral capacitor, and the drain of the second field effect transistor is connected to the second capacitor pin of the first integral capacitor; The input end of the second inverter is connected to the integral reset circuit, and the output end of the second inverter is connected to the gate of the third field effect transistor; The source of the third field effect transistor is connected to the first capacitor pin of the second integral capacitor, and the drain of the third field effect transistor is connected to the second capacitor pin of the second integral capacitor.

8. The circuit according to claim 7, characterized in that When receiving the high level signal output by the integral reset circuit, the second field effect transistor is in the on state, the third field effect transistor is in the off state, the first integral capacitor is in the short circuit state, and the second integral capacitor is used for integral operation processing of the voltage signal; When receiving a low-level signal output by the integral reset circuit, the second field effect transistor is in an off state, the third field effect transistor is in an on state, the second integral capacitor is in a short-circuit state, and the first integral capacitor is used for integral operation processing of the voltage signal.

9. The circuit according to claim 1, characterized in that The integral reset circuit comprises a D flip-flop and a protection resistor, wherein a first resistor pin of the protection resistor is connected to an inverting output terminal of the D flip-flop, a second resistor pin of the protection resistor is grounded, and a clock input terminal of the D flip-flop is connected to a gate of the first field effect transistor; The D flip-flop is a rising edge flip-flop, the data input terminal of the D flip-flop is connected to the inverting output terminal, and the inverting output terminal is connected to the integration circuit; The D flip-flop is used to receive the pulse width modulation gating signal through the clock input terminal; The D flip-flop is used to output the inverted signal of the inverted output terminal to the data input terminal to flip the signal state of the inverted output terminal when receiving the rising edge of the pulse width modulation gating signal.

10. A method for measuring the average current of a solenoid valve, characterized in that: The method is used for a measurement circuit of an average current of a solenoid valve, wherein the circuit comprises a solenoid valve, a first power supply, a sampling resistor, a field effect tube drive circuit, a current acquisition circuit, an integration circuit and an integration reset circuit; The method comprises: Based on the pulse width modulation gating signal, controlling the conduction state of the first field effect tube through the field effect tube driving circuit; When the first field effect transistor is in an on state, the first power supply provides a driving current to the solenoid valve, and the driving current flows through the sampling resistor; Sampling the voltage signals at both sides of the sampling resistor by the current acquisition circuit, and outputting the voltage signals to the integration circuit; Integrating the voltage signal through the integration circuit, and determining the average current of the solenoid valve based on the integration result; Based on the pulse width modulation gating signal, the integration circuit is periodically reset by the integration reset circuit.

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