Time characteristic testing method, device, system, computer equipment and program product

Abstract

The present application relates to a time feature test method, device, computer equipment and computer program product. The method includes: receiving a test instruction, the test instruction carries test mode information and test information, each test mode corresponds to a time feature; sending the test information to the FPGA, the FPGA is used to test the chip to be tested based on the test information, and store the original test data obtained by the test; reading the original test data from the FPGA based on the test mode information, and storing the original test data locally; generating each independent time feature calculation thread based on the test mode information, each time feature calculation thread is used to calculate the time feature corresponding to a test mode; and calculating the time feature corresponding to the time feature calculation thread based on the original test data by each time feature calculation thread. The use of this method can improve the test efficiency.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a time characteristic testing method, device, computer equipment and computer program product. Background Art

[0002] TMU (Time Measurement Unit) means time test unit in Chinese. In the IC or chip testing industry, the main purpose of this module is to test the time information (period, frequency, high and low level time, rising and falling edge time, delay, jitter, etc.) of the input signal of the test machine board channel.

[0003] The traditional TMU test method is to use FPGA to perform tests and calculate results. Testing multiple time information of the same signal requires changing multiple test modes and triggering multiple TMU tests. This process actually includes repetitive tasks such as repeatedly sending parameters, repeatedly triggering tests, and repeatedly reading raw data, resulting in a loss of TMU test efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide a time characteristic testing method, apparatus, computer equipment, computer readable storage medium and computer program product that can improve testing efficiency in response to the above technical problems.

[0005] In a first aspect, the present application provides a time characteristic testing method, the method comprising:

[0006] Receive a test instruction, the test instruction carrying test mode information and test information, each test mode corresponding to a time feature;

[0007] The test information is sent to the FPGA, and the FPGA is used to test the chip to be tested based on the test information and store the original test data obtained by the test;

[0008] Reading original test data from the FPGA based on the test mode information, and locally storing the original test data;

[0009] Generate independent time feature calculation threads based on the test mode information, each of the time feature calculation threads is used to calculate the time feature corresponding to one of the test modes;

[0010] The time characteristics corresponding to the time characteristics calculation thread are calculated by each of the time characteristics calculation threads based on the original test data.

[0011] In one embodiment, receiving a test instruction includes:

[0012] Receive the test instructions sent by the API through parameter transparent transmission.

[0013] In one embodiment, reading original test data from the FPGA based on the test mode information includes:

[0014] Determine a mapping relationship between a test mode corresponding to the test mode information and a storage address of a storage space of the FPGA;

[0015] Based on the mapping relationship, determining a storage address corresponding to the test mode;

[0016] Original test data is read from the FPGA based on the storage address.

[0017] In one embodiment, the local storage of the original test data includes:

[0018] The original test data is locally stored according to the board, sub-board and channel as indexes;

[0019] Before generating each independent time feature calculation thread based on the test mode information, the method further includes:

[0020] Receive a result acquisition instruction, wherein the result acquisition instruction carries a board identifier and a channel identifier;

[0021] The locally stored original test data is acquired based on the board identifier and the channel identifier.

[0022] In one embodiment, the step of calculating the time feature corresponding to the time feature calculation thread based on the original test data by each of the time feature calculation threads includes:

[0023] Selecting at least one of the original test data as target test data through each of the time feature calculation threads;

[0024] The time feature corresponding to the time feature calculation thread is obtained by calculation based on the target test data.

[0025] In one embodiment, after obtaining the time feature corresponding to the time feature calculation thread by calculating the time feature calculation thread based on the original test data through each time feature calculation thread, the method includes:

[0026] When the time features corresponding to the time feature calculation threads are all calculated, the time features calculated by the time feature calculation threads are encapsulated, and the encapsulation results are returned to the API layer.

[0027] In a second aspect, the present application further provides a time characteristic testing device, the device comprising:

[0028] A parameter receiving module, used for receiving a test instruction, wherein the test instruction carries test mode information and test information, and each test mode corresponds to a time feature;

[0029] A parameter configuration module, used to send the test information to the FPGA, the FPGA is used to test the chip to be tested based on the test information, and store the original test data obtained by the test;

[0030] A cache management module, configured to read original test data from the FPGA based on the test mode information and store the original test data locally;

[0031] A thread creation module, used to generate independent time feature calculation threads based on the test mode information, each of which is used to calculate the time feature corresponding to one of the test modes;

[0032] The multi-thread result calculation module is used to calculate the time characteristics corresponding to the time characteristic calculation thread based on the original test data through each of the time characteristic calculation threads.

[0033] In a third aspect, the present application also provides a time characteristic testing system, comprising:

[0034] API layer, used to issue test instructions;

[0035] A driver layer, used to execute the method in any one of the above embodiments to obtain at least one time feature of the original test data;

[0036] The FPGA is used to test the chip to be tested based on the test information sent by the driver layer, and store the original test data obtained by the test.

[0037] In a fourth aspect, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method in any one of the above-mentioned embodiments when executing the computer program.

[0038] In a fifth aspect, the present application also provides a computer program product, including a computer program, which implements the steps of the method in any one of the above embodiments when executed by a processor.

[0039] The above-mentioned time feature test method, device, computer equipment and computer program product, after receiving the test instruction, send the test information to the FPGA, so that the FPGA tests the chip to be tested based on the test information and stores the original test data obtained by the test, reads the original test data from the FPGA based on the test mode information, and stores it locally, generates each independent time feature calculation thread based on the test mode information, each time feature calculation thread is used to calculate the time feature corresponding to a test mode, and the time feature corresponding to the time feature calculation thread is calculated by each of the time feature calculation threads based on the original test data. In this way, the FPGA only needs to be tested once to obtain the time features corresponding to multiple test modes, thereby improving the TMU test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 A schematic diagram of a time characteristic testing system in one embodiment;

[0042] Figure 2 A schematic diagram of a flow chart of a time characteristic testing method in one embodiment;

[0043] Figure 3 is a schematic diagram of original test data in one embodiment;

[0044] Figure 4 is a schematic diagram of TmuOrgData in one embodiment;

[0045] Figure 5 is a timing diagram of a method for calculating Delay in one embodiment;

[0046] Figure 6 is a structural block diagram of a time characteristic testing device in an embodiment;

[0047] Figure 7 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] The time characteristic testing method provided in the embodiment of the present application can be applied to Figure 1 In the time feature test system shown. The time feature test system includes an API layer, a driver layer and an FPGA, wherein the API layer is used to issue test instructions, the driver layer is used to execute the time feature test method below to obtain at least one time feature of the original test data, and the FPGA layer is used to test the chip to be tested based on the test information issued by the driver layer, and store the original test data obtained by the test.

[0050] The FPGA layer includes a TMU test module and a storage space management module of the FPGA layer, wherein the TMU test module is used to perform TMU testing and collect TMU original test data, and store the collected TMU original test data in the storage space management module of the FPGA layer.

[0051] The driver layer may include a parameter receiving module, a parameter configuration module, a test mode and storage space mapping management module, a storage space management module, an original test data cache management module and a multi-threaded result calculation module.

[0052] The parameter receiving module is used to receive the test instructions issued by the API layer. On the one hand, it configures the test parameters in the parameter configuration module based on the test information carried by the test instructions. On the other hand, it instructs each time feature calculation thread in the multi-threaded result calculation module to obtain the original test data of the corresponding board and channel based on the result acquisition instruction.

[0053] The test mode and storage space mapping management module stores the mapping relationship between each test mode and the storage address of the original test data, so that the parameter receiving module can transmit the test mode to the test mode and storage space mapping management module, and the test mode and storage space mapping management module can determine the storage address corresponding to the test mode based on the mapping relationship.

[0054] The storage space management module is used to obtain the original test data of a test from the FPGA based on the test mode and the storage address determined by the storage space mapping management module, and store the original test data in the original test data cache management module.

[0055] The multi-threaded result calculation module is used to generate independent time feature calculation threads based on the test mode information carried by the test instruction. Each time feature calculation thread is used to calculate the time feature corresponding to a test mode, and each time feature calculation thread is managed by the multi-threaded result calculation module. Specifically, each time feature calculation thread is used to obtain the corresponding original test data from the original test data cache management module, and calculate the corresponding time feature based on the original test data, and return the time feature to the API layer. In this way, the FPGA only needs to be tested once to obtain the time features corresponding to multiple test modes, which improves the TMU test efficiency.

[0056] In an exemplary embodiment, Figure 2 As shown, a time characteristic test method is provided, which is applied to Figure 1 The driving layer in FIG. 1 is taken as an example to illustrate, and the method includes the following steps 202 to 210. Among them:

[0057] S202: Receive a test instruction, where the test instruction carries test mode information and test information, and each test mode corresponds to a time feature.

[0058] The test instruction is sent from the API layer to the driver layer, and the test instruction carries test mode information and test information.

[0059] The test mode information includes at least one test mode. Optionally, the test mode information includes two test modes, three test modes, etc., which are not specifically limited here. Each test mode corresponds to a time feature. The types of time features may include but are not limited to period, frequency, high and low level time, rising edge and falling edge time, delay, Jitter, etc.

[0060] The test information includes the starting test position (StartNum) and the number of sampling points (SampleSize), and the cache container receives and stores all test modes (Mode Vector). The parameter receiving module of the driver layer stores the test information, and the cache container in the parameter receiving module stores the test mode (Measure Mode). N Measure Modes constitute the Mode Vector.

[0061] In some optional embodiments, receiving a test instruction includes: receiving a test instruction sent by an API by transparently transmitting parameters.

[0062] The API layer transparently transmits the test instructions and directly connects with the driver layer, so that the driver layer can perceive each test mode.

[0063] S204: Send the test information to the FPGA. The FPGA is used to test the chip to be tested based on the test information and store original test data obtained by the test.

[0064] FPGA splits the collected time information to obtain the original test data, including the time information of several cycles of the sampling point. The time information can be, for example, Figure 3 t1, t2, t3, t4 in the FPGA, the FPGA then stores the original test data obtained by the split in a distributed manner, for example, in each storage space managed by the storage space management module of the FPGA. Optionally, the time information collected by the FPGA may include 16 types of original test data. In other embodiments, the time information collected by the FPGA may include 8 types of original test data. Those skilled in the art may set the types of time information collected by the FPGA as needed, and no specific limitation is made here. In addition, generally, the classification of the original test data is greater than or equal to the type of test mode.

[0065] Specifically, the parameter configuration module of the driver layer configures the starting test position (StartNum), the number of sampling points (SampleSize), and any test mode (optionally configure the last test mode, which is configured here only to trigger the FPGA to perform the test). It should be noted that any test mode can be configured here because the original test data collected by the FPGA is the same in each test mode.

[0066] After the parameter configuration is completed, the driver layer notifies the FPGA to trigger the test and sends the configured test information to the FPGA. The TMU test module of the FPGA can test the chip under test according to the test information and collect the original test data. The collection object of the TMU test module of the FPGA is the time information of the sampling point cycles. Figure 1 For example, the collected time information is divided into 16 kinds of original test data and distributedly stored in 16 storage spaces of the storage space management module of the FPGA, namely RAM0-RAM15.

[0067] The signal to be tested is the signal whose time characteristics are to be obtained. Figure 3As shown, the blue line is the waveform of the signal to be tested. The signal to be tested includes a rising edge and a falling edge. VOH and VOL are two fixed voltages. Each cycle of the signal to be tested includes four lines: VOH, VOL, rising edge, and falling edge. The intersection of these four lines gives four time points: t1, t2, t3, and t4. For each time point, there are two time information, namely a coarse measurement value (the number of sampling clocks ClkNum) and a precise measurement value (the number of taps TapNum). Each Compare path corresponds to two TMU paths, namely TMU1 and TMU2. By arranging and combining the above split points, 16 (4*2*2) kinds of original test data can be obtained. For details, please refer to Table 1:

[0068] Table 1 16 kinds of original test data

[0069]

[0070] S206: Reading original test data from the FPGA based on the test mode information, and storing the original test data locally.

[0071] The test mode has a mapping relationship with the storage address of the storage space in the FPGA. Based on the mapping relationship, the original test data of the corresponding storage address can be read from the storage space management module of the FPGA, and the original test data can be stored in the original data cache management module of the driver layer. In this way, the driver layer can manage the TMU original test data of each board and support more complex test modes, such as Delay test and Jitter test between channels across boards.

[0072] Among them, the driver layer can pre-configure the mapping relationship between the FPGA storage space and the test mode, so that the driver layer can determine the address of the FPGA storage space based on the mapping relationship, and then read the original test data based on the address of the FPGA storage space and store it locally.

[0073] S208: Generate independent time feature calculation threads based on the test mode information, each time feature calculation thread is used to calculate the time feature corresponding to a test mode.

[0074] S210: Obtaining, by each time feature calculation thread, a time feature corresponding to the time feature calculation thread based on original test data through calculation.

[0075] The time feature calculation thread corresponds to the test mode information, and each time feature calculation thread is used to calculate the time feature corresponding to a test mode. Each time feature calculation thread is independent of each other and does not interfere with each other. Each time feature calculation thread can obtain the original test data stored locally, and process the original test data based on the corresponding algorithm to calculate the time feature. In other words, each time feature calculation thread can reuse the original test data stored locally, so that after testing the chip to be tested once according to the test information, multiple time feature calculations can be realized to improve the TMU test efficiency.

[0076] The multi-threaded result calculation module is used to create time feature calculation threads based on the test mode information. Specifically, as many threads as the number of test modes in the test mode information ModeVector is created.

[0077] Each time feature calculation thread in the multi-threaded result calculation module calculates the time feature corresponding to a test mode.

[0078] The above-mentioned time feature test method sends test information to FPGA, so that FPGA tests the chip to be tested based on the test information and stores the original test data obtained by the test, reads the original test data from FPGA based on the test mode information and stores it locally, generates independent time feature calculation threads based on the test mode information, each time feature calculation thread is used to calculate the time feature corresponding to a test mode, and the time feature corresponding to the time feature calculation thread is calculated by each time feature calculation thread based on the original test data. In this way, FPGA only needs to be tested once to obtain the time features corresponding to multiple test modes, thereby improving the TMU test efficiency.

[0079] In one of the optional embodiments, reading original test data from the FPGA based on test mode information includes: determining a mapping relationship between a test mode corresponding to the test mode information and a storage address of a storage space of the FPGA; based on the mapping relationship, determining a storage address corresponding to the test mode; and reading original test data from the FPGA based on the storage address.

[0080] The test mode and storage space mapping management module of the driver layer stores the mapping relationship between the test mode and the storage address of the storage space of the FPGA. The test mode and storage space mapping management module can determine the corresponding storage address based on the test mode information, so that the storage space management module of the driver layer can read the original test data from the FPGA based on the storage address.

[0081] For convenience, a queue is introduced. Specifically, the test mode and storage space mapping management module enqueues all storage addresses to generate a RAM address queue. The storage space management module receives the RAM address queue and dequeues the RAM addresses in sequence. The storage space management module sends a RAM read request to the FPGA according to the sequentially dequeued RAM addresses. After receiving the request, the storage space management module of the FPGA returns the original test data in the corresponding RAM to the storage space management module of the driver layer. The storage space management module of the driver layer passes the original test data to the original data cache management module.

[0082] In the above embodiment, based on the mapping relationship between the test mode and the storage addresses of the FPGA's storage space, the original test data can be read from the FPGA. The driver layer reuses and calculates the original test data, which is simpler and more scalable compared to the FPGA.

[0083] In one alternative embodiment, storing the original test data locally includes: locally storing the original test data indexed by the board, daughter board, and channel; before generating each independent time feature calculation thread based on the test mode information, it further includes: receiving a result acquisition instruction carrying the board identifier and channel identifier; obtaining the original test data locally stored based on the board identifier and channel identifier.

[0084] Among them, the storage of the original test data in the driver layer is a three-layer structure indexed by the board, daughter board, and channel. For example, the three-layer map structure is: <Slot (board) <Fe (daughter board) <Channel (channel), TmuOrgData (original test data)>>>.

[0085] TmuOrgData is a complex data structure that stores all types of original data for one channel. Specifically, it can be referred to Figure 4 as shown, which includes the original test data category number and SampleSize original test data.

[0086] The result acquisition instruction is sent to the driver layer by the API layer calling the result acquisition interface. The result acquisition instruction carries the board identifier and the channel identifier, which can be represented by pinlist, wherein pinlist includes pin1, pin2, pin3, and each pin can correspond to many channels, that is, pin1 represents slot1 CH1, slot1 CH3, and each channel has corresponding original test data. The parameter receiving module of the driver layer can parse the channel information from the pinlist, and the board information and channel information are given to the multi-threaded result calculation module. The multi-threaded result calculation module obtains the locally stored original test data based on the board identifier and channel identifier. For example, the multi-threaded result calculation module extracts the TmuOrgData of the corresponding board and channel from the original test data cache management module based on the board identifier and channel identifier.

[0087] In the above embodiment, the time characteristics of the corresponding boards and channels can be calculated separately based on user needs, thereby improving flexibility and being applicable to multiple channels of a single board and multiple channels across boards. The original test data of each channel may be different, and the driver layer can simultaneously and in parallel calculate multiple time characteristics of the original test data of multiple channels of a single board or multiple time characteristics of the original test data of multiple channels across boards.

[0088] In one of the optional embodiments, the time characteristics corresponding to the time characteristic calculation thread are calculated based on the original test data by each time characteristic calculation thread, including: selecting at least one of the original test data as target test data by each of the time characteristic calculation threads; and calculating the time characteristics corresponding to the time characteristic calculation thread based on the target test data.

[0089] Among them, each time feature calculation thread calculates the time feature of a test mode respectively. Specifically, at least one target test data is first selected from the original test data, and then the time feature corresponding to the time feature calculation thread is calculated based on the target test data.

[0090] Specifically, the start signal and the end signal are confirmed according to the signal characteristics (t1, t2, t3, t4) of each test mode. According to the characteristics of the start signal and the end signal (ACH / BCL, rising / falling, TMU1 / TMU2), the ClkNum and TapNum of the two signals are respectively extracted from the original test data stored in the driver layer, which is the target test data in this embodiment.

[0091] For example: if the test mode is rising edge time, then Figure 3As shown, the Start signal is t1 and the Stop signal is t2. The Start signal features are (TMU1, BCL, rising edge), and the Stop signal features are (TMU1, ACH, rising edge). Corresponding to the TMU original test data type number in Table 1, the original data types numbered 2, 10, 0, and 8 respectively store the Start signal's Start_TapNum, Start_ClkNum and the Stop signal's Stop_TapNum, Stop_ClkNum, which are the target test data in this embodiment.

[0092] Then calculate the Delay between the Start signal and the Stop signal. Specifically, all the test modes of TMU can be summarized as measuring the Delay between the Start signal and the Stop signal. The test unit of TMU is divided into two parts, the coarse test unit (TMU sampling clock Clk, recording ClkNum) and the fine test unit (carry chain, recording TapNum).

[0093] like Figure 5 As shown in the figure, the formula for TMU testing the delay between any two points is:

[0094] RoughTime = (Stop_ClkNum - Start_ClkNum) * Clk_Period;

[0095] FineTime = (Start_TapNum - Stop_TapNum) * Tap_Unit;

[0096] Delay = RoughTime + FineTime;

[0097] Among them, RoughTime is the coarse measurement time corresponding to the coarse measurement unit, Stop_ClkNum is the stop clock cycle, Start_ClkNum is the start clock cycle, and Clk_Period is the clock cycle length. FineTime is the fine measurement time corresponding to the fine measurement unit, Start_TapNum is the stop tap cycle, Stop_TapNum is the start tap cycle, Tap_Unit is the tap cycle length, and Delay is the delay.

[0098] In one of the optional embodiments, after each time feature calculation thread calculates the time features corresponding to the time feature calculation thread based on the original test data, it includes: when the time features corresponding to each time feature calculation thread are calculated, the time features calculated by each time feature calculation thread are encapsulated, and the encapsulated results are returned to the API.

[0099] Among them, in this embodiment, time features are calculated separately by multiple time feature calculation threads. After the multi-threaded result calculation module completes the calculation of each time feature calculation thread, it encapsulates the time features calculated by each time feature calculation thread and returns the encapsulated results to the API layer, so that multiple time features can be seen at the API layer.

[0100] In the above embodiment, the API layer parameters are transparently transmitted and sent, the driver layer uses a container to receive the test mode, the time information collected by the FPGA is split and distributedly stored, and finally the driver layer uniformly recycles and calculates the original test data, which solves the problem that a TMU test cannot return multiple mode results, fills the market gap, and improves the TMU test efficiency.

[0101] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0102] Based on the same inventive concept, the embodiment of the present application also provides a time feature test device for implementing the time feature test method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more time feature test device embodiments provided below can refer to the limitations of the time feature test method above, and will not be repeated here.

[0103] In an exemplary embodiment, Figure 6 As shown, a time feature testing device is provided, including: a parameter receiving module 601, a parameter configuration module 602, a cache management module 603, a thread creation module 604 and a multi-thread result calculation module 605, wherein:

[0104] The parameter receiving module 601 is used to receive a test instruction, the test instruction carries test mode information and test information, and each test mode corresponds to a time feature;

[0105] The parameter configuration module 602 is used to send the test information to the FPGA, and the FPGA is used to test the chip to be tested based on the test information and store the original test data obtained by the test;

[0106] The cache management module 603 is used to read the original test data from the FPGA based on the test mode information and store the original test data locally;

[0107] A thread creation module 604, used to generate independent time feature calculation threads based on the test mode information, each time feature calculation thread is used to calculate the time feature corresponding to a test mode;

[0108] The multi-thread result calculation module 605 is used to calculate the time characteristics corresponding to the time characteristics calculation thread based on the original test data through each time characteristics calculation thread.

[0109] In one of the optional embodiments, the parameter receiving module 601 is specifically used to receive the test instruction sent by the API through parameter transparent transmission.

[0110] In one of the optional embodiments, the cache management module 603 is specifically used to determine the mapping relationship between the test mode corresponding to the test mode information and the storage address of the storage space of the FPGA; based on the mapping relationship, determine the storage address corresponding to the test mode; and read the original test data from the FPGA based on the storage address.

[0111] In one of the optional embodiments, the cache management module 603 is specifically used to locally store the original test data according to the board, sub-board and channel as indexes; the parameter receiving module 601 is also used to receive the result acquisition instruction, which carries the board identifier and the channel identifier; the multi-threaded result calculation module 605 is also used to obtain the locally stored original test data based on the board identifier and the channel identifier.

[0112] In one of the optional embodiments, the multi-threaded result calculation module 605 is specifically used to select at least one of the original test data as target test data through each time feature calculation thread; and obtain the time feature corresponding to the time feature calculation thread based on the target test data.

[0113] In one of the optional embodiments, the multi-threaded result calculation module 605 is also specifically used to encapsulate the time features calculated by each time feature calculation thread when the time features corresponding to each time feature calculation thread are calculated, and return the encapsulated results to the API layer.

[0114] Each module in the above-mentioned time characteristic test device can be implemented in whole or in part by software, hardware and their combination. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each of the above modules.

[0115] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 7 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a time feature test method is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0116] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0117] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the following steps when executing the computer program: receiving a test instruction, the test instruction carries test mode information and test information, and each test mode corresponds to a time feature; sending the test information to an FPGA, the FPGA is used to test a chip to be tested based on the test information, and store original test data obtained by the test; reading original test data from the FPGA based on the test mode information, and storing the original test data locally; generating independent time feature calculation threads based on the test mode information, each time feature calculation thread is used to calculate the time feature corresponding to a test mode; and obtaining the time feature corresponding to the time feature calculation thread by calculating the original test data through each time feature calculation thread.

[0118] In one embodiment, the receiving of the test instruction implemented when the processor executes the computer program includes: receiving the test instruction sent by the API in a manner of parameter transparent transmission.

[0119] In one embodiment, when the processor executes a computer program, the processor reads original test data from the FPGA based on the test mode information, including: determining a mapping relationship between a test mode corresponding to the test mode information and a storage address of a storage space of the FPGA; based on the mapping relationship, determining a storage address corresponding to the test mode; and reading original test data from the FPGA based on the storage address.

[0120] In one embodiment, the local storage of original test data implemented when the processor executes a computer program includes: locally storing the original test data according to the board, sub-board and channel as indexes; before the processor generates each independent time feature calculation thread based on the test mode information when executing the computer program, it also includes: receiving a result acquisition instruction, the result acquisition instruction carries a board identifier and a channel identifier; and acquiring the locally stored original test data based on the board identifier and the channel identifier.

[0121] In one embodiment, when a processor executes a computer program, the method of obtaining the time characteristics corresponding to the time characteristic calculation thread based on the original test data through each time characteristic calculation thread includes: selecting at least one of the original test data as the target test data through each time characteristic calculation thread; and obtaining the time characteristics corresponding to the time characteristic calculation thread based on the target test data.

[0122] In one embodiment, when the processor executes the computer program, after each time feature calculation thread calculates the time feature corresponding to the time feature calculation thread based on the original test data, it includes: when the time features corresponding to each time feature calculation thread are calculated, the time features calculated by each time feature calculation thread are encapsulated, and the encapsulation results are returned to the API layer.

[0123] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: receiving a test instruction, the test instruction carries test mode information and test information, each test mode corresponds to a time feature; sending the test information to an FPGA, the FPGA is used to test a chip to be tested based on the test information, and store original test data obtained from the test; reading original test data from the FPGA based on the test mode information, and storing the original test data locally; generating independent time feature calculation threads based on the test mode information, each time feature calculation thread is used to calculate the time feature corresponding to a test mode; and obtaining the time feature corresponding to the time feature calculation thread by each time feature calculation thread based on the original test data.

[0124] In one embodiment, receiving a test instruction implemented when a computer program is executed by a processor includes: receiving a test instruction sent by an API in a manner of parameter transparent transmission.

[0125] In one embodiment, the computer program executed by the processor implements reading original test data from the FPGA based on test mode information, including: determining a mapping relationship between a test mode corresponding to the test mode information and a storage address of a storage space of the FPGA; based on the mapping relationship, determining a storage address corresponding to the test mode; and reading original test data from the FPGA based on the storage address.

[0126] In one embodiment, the local storage of original test data implemented when a computer program is executed by a processor includes: locally storing the original test data according to the board, sub-board and channel as indexes; before the computer program is executed by the processor and generates each independent time feature calculation thread based on the test mode information, it also includes: receiving a result acquisition instruction, the result acquisition instruction carries a board identifier and a channel identifier; and acquiring the locally stored original test data based on the board identifier and the channel identifier.

[0127] In one embodiment, when a computer program is executed by a processor, the method of obtaining the time characteristics corresponding to the time characteristic calculation thread by calculating the original test data through each time characteristic calculation thread includes: selecting at least one of the original test data as target test data through each time characteristic calculation thread; and obtaining the time characteristics corresponding to the time characteristic calculation thread by calculating the target test data.

[0128] In one embodiment, when a computer program is executed by a processor, after each time feature calculation thread calculates the time feature corresponding to the time feature calculation thread based on the original test data, the program includes: when the time features corresponding to each time feature calculation thread are calculated, the time features calculated by each time feature calculation thread are encapsulated, and the encapsulation results are returned to the API layer.

[0129] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: receiving a test instruction, the test instruction carries test mode information and test information, each test mode corresponds to a time feature; sending the test information to the FPGA, the FPGA is used to test the chip to be tested based on the test information, and store the original test data obtained from the test; reading the original test data from the FPGA based on the test mode information, and storing the original test data locally; generating each independent time feature calculation thread based on the test mode information, each time feature calculation thread is used to calculate the time feature corresponding to a test mode; and obtaining the time feature corresponding to the time feature calculation thread through each time feature calculation thread based on the original test data.

[0130] In one embodiment, receiving a test instruction implemented when a computer program is executed by a processor includes: receiving a test instruction sent by an API in a manner of parameter transparent transmission.

[0131] In one embodiment, the computer program executed by the processor implements reading original test data from the FPGA based on test mode information, including: determining a mapping relationship between a test mode corresponding to the test mode information and a storage address of a storage space of the FPGA; based on the mapping relationship, determining a storage address corresponding to the test mode; and reading original test data from the FPGA based on the storage address.

[0132] In one embodiment, the local storage of original test data implemented when a computer program is executed by a processor includes: locally storing the original test data according to the board, sub-board and channel as indexes; before the computer program is executed by the processor and generates each independent time feature calculation thread based on the test mode information, it also includes: receiving a result acquisition instruction, the result acquisition instruction carries a board identifier and a channel identifier; and acquiring the locally stored original test data based on the board identifier and the channel identifier.

[0133] In one embodiment, when a computer program is executed by a processor, the method of obtaining the time characteristics corresponding to the time characteristic calculation thread by calculating the original test data through each time characteristic calculation thread includes: selecting at least one of the original test data as target test data through each time characteristic calculation thread; and obtaining the time characteristics corresponding to the time characteristic calculation thread by calculating the target test data.

[0134] In one embodiment, when a computer program is executed by a processor, after each time feature calculation thread calculates the time feature corresponding to the time feature calculation thread based on the original test data, the program includes: when the time features corresponding to each time feature calculation thread are calculated, the time features calculated by each time feature calculation thread are encapsulated, and the encapsulation results are returned to the API layer.

[0135] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0136] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0137] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A time characteristic testing method, characterized in that: The method comprises: Receive a test instruction, the test instruction carries test mode information and test information, each test mode corresponds to a time feature, the time feature includes at least one of a period, a frequency, a high and low level time, a rising edge and a falling edge time, a delay, and a jitter; The test information is sent to the FPGA, and the FPGA is used to test the chip to be tested based on the test information and store the original test data obtained by the test, wherein the test information includes a starting test position and a number of sampling points, wherein the FPGA splits the collected time information to obtain the original test data, and then performs distributed storage on the split original test data, and stores the split original test data in each storage space managed by the storage space management module of the FPGA, and the classification of the original test data is greater than or equal to the type of the test mode; Reading original test data from the FPGA based on the test mode information, and locally storing the original test data; Generate independent time feature calculation threads based on the test mode information, each of the time feature calculation threads is used to calculate the time feature corresponding to one of the test modes; The time characteristics corresponding to the time characteristics calculation thread are calculated by each of the time characteristics calculation threads based on the original test data.

2. The method according to claim 1, characterized in that The receiving of the test instruction comprises: Receive the test instructions sent by the API through parameter transparent transmission.

3. The method according to claim 1, characterized in that The reading original test data from the FPGA based on the test mode information includes: Determine a mapping relationship between a test mode corresponding to the test mode information and a storage address of a storage space of the FPGA; Based on the mapping relationship, determining a storage address corresponding to the test mode; Original test data is read from the FPGA based on the storage address.

4. The method according to claim 1, characterized in that: The locally storing the original test data includes: The original test data is locally stored according to the board, sub-board and channel as indexes; Before generating each independent time feature calculation thread based on the test mode information, the method further includes: Receive a result acquisition instruction, wherein the result acquisition instruction carries a board identifier and a channel identifier; The locally stored original test data is acquired based on the board identifier and the channel identifier.

5. The method according to claim 1, characterized in that: The step of calculating the time feature corresponding to the time feature calculation thread based on the original test data by each of the time feature calculation threads includes: Selecting at least one of the original test data as target test data through each of the time feature calculation threads; The time feature corresponding to the time feature calculation thread is obtained by calculation based on the target test data.

6. The method according to claim 1, characterized in that After the time feature calculation thread calculates the time feature corresponding to the time feature calculation thread based on the original test data, the method includes: When the time features corresponding to the time feature calculation threads are all calculated, the time features calculated by the time feature calculation threads are encapsulated, and the encapsulation results are returned to the API layer.

7. A time characteristic testing device, characterized in that: The device comprises: A parameter receiving module, used for receiving a test instruction, wherein the test instruction carries test mode information and test information, each test mode corresponds to a time feature, and the time feature includes at least one of a period, a frequency, a high and a low level time, a rising edge and a falling edge time, a delay, and a jitter; A parameter configuration module is used to send the test information to the FPGA, and the FPGA is used to test the chip to be tested based on the test information and store the original test data obtained by the test, wherein the test information includes a starting test position and a number of sampling points, wherein the FPGA splits the collected time information to obtain the original test data, and then performs distributed storage on the split original test data, which is stored in each storage space managed by the storage space management module of the FPGA, and the classification of the original test data is greater than or equal to the type of the test mode; A cache management module, configured to read original test data from the FPGA based on the test mode information and store the original test data locally; A thread creation module, used to generate independent time feature calculation threads based on the test mode information, each of which is used to calculate the time feature corresponding to one of the test modes; The multi-thread result calculation module is used to calculate the time characteristics corresponding to the time characteristic calculation thread based on the original test data through each of the time characteristic calculation threads.

8. A time characteristic test system, characterized in that: include: API layer, used to issue test instructions; A driver layer, configured to execute the method according to any one of claims 1 to 6 to obtain at least one time feature of the original test data; The FPGA is used to test the chip to be tested based on the test information sent by the driver layer, and store the original test data obtained by the test.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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