Time measuring device based on pulse modulation and fine and rough timing

Abstract

The invention belongs to the field of time measurement, and provides a time measurement device based on pulse modulation and fine and rough timing, which is used for solving the problem that the existing time measurement device cannot meet the application requirements of large measurement range, good nonlinear error, low resource consumption and the like. According to the invention, an external modulation pulse generation module outputs a same-frequency modulation pulse and a clock signal to an FPGA; the FPGA receives a START signal and a STOP signal, the START signal and the STOP signal are input to the delay chain module to serve as a trigger, information of a modulation pulse signal on a delay chain is intercepted to serve as fine timing data, the START signal and the STOP signal are input to the counter module to serve as switching signals to count the rising edge of a clock signal to serve as coarse timing data, and the coarse timing data serve as the clock signal. And finally, the fine timing data and the rough timing data are decoded and calculated through a decoding module to obtain a time measurement result. In conclusion, the structure of multiple times of measurement in single time is adopted, the nonlinear error performance is improved, and the measurement effect of multiple times of measurement is achieved based on the single delay chain.

Description

Technical Field

[0001] The invention relates to a time measuring device, and in particular provides a time measuring device based on pulse modulation and fine and rough timing, which is suitable for various application fields such as sensor signal processing, measuring instruments and automatic control systems. Background Art

[0002] Time measurement devices are key components of many electronic systems and industrial products, such as all-digital phase-locked loops, time-of-flight mass spectrometers, and lidar or 3D ranging devices for robots, self-driving cars, and solar photovoltaic deployment optimization. The design and implementation of modern time measurement is heterogeneous and multi-directional, and is driven by CMOS (semiconductor) process degradation and application requirements. A lot of research work is focused on denser digital implementation, high-resolution technology optimization, increasing input range and linearity, reducing conversion time, power consumption and silicon area. In order to alleviate the defects of nanoscale CMOS technology, heat resistance and mismatch resistance as well as anti-PVT (process voltage temperature) variation and anti-migration design techniques are becoming increasingly important.

[0003] At present, time measurement devices mainly adopt direct counting structure and delay chain architecture. Under the direct counting structure, the simplest time interval measurement scheme in the time measurement device is realized by a counter, which is directly triggered or sampled by the signal to be measured; if the direct counting architecture is used to achieve high-resolution measurement, a stable high-frequency clock must be provided for the subdivision module. However, the ultra-high frequency clock cannot be stably implemented in the all-digital circuit at present, and the existing manufacturing process and technology do not support the development of counters with such a high flip speed; therefore, counters are generally used in time measurement systems to complete rough time measurement and can be used to expand the dynamic range of measurement. Under the delay chain architecture, the physical propagation delay unit of the predefined logic resources in the FPGA device is used as the basic component to achieve fine time measurement. According to the sampling results, the number of fixed delay units that the input signal passes through during the propagation process can be determined, so as to obtain the measurement interval between the START and STOP edges; however, due to the influence of process, voltage and temperature, the propagation delay of each logic unit in the FPGA is not consistent, which leads to uneven distribution of the size of the delay unit; therefore, in order to meet the specific requirements of different applications for the time resolution, accuracy and linearity of the delay chain architecture, the architecture of the traditional delay chain must be improved to expand the measurement range and compensate for nonlinear errors.

[0004] In summary, since the two architectures have their own advantages and disadvantages, even if the direct counting structure and the delay chain architecture are combined to obtain a higher measurement range and measurement accuracy, the delay chain architecture still has the problem of uneven distribution of delay unit sizes, which makes nonlinear errors still exist; in addition, although the method of using multiple delay chain architectures to perform multiple measurements and take the average value can solve this problem, it will cause a great burden on the resource usage of the FPGA; therefore, there is an urgent need for a time measurement device with a large measurement range, high resolution, good nonlinear error and low resource consumption. Summary of the invention

[0005] The purpose of the present invention is to provide a time measurement device based on pulse modulation and fine and rough timing, so as to solve the problem that the existing time measurement device cannot meet the application requirements such as large measurement range, good nonlinear error and low resource consumption.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] A time measurement device based on pulse modulation and fine and rough timing comprises: a pulse modulation generation module, a delay chain module, a counter module and a decoding module; the characteristics are:

[0008] A pulse modulation generation module is used to generate a modulation pulse and a clock signal to be input into the delay chain module and the counter module, wherein the multi-pulse period of the modulation pulse is consistent with the clock period of the clock signal;

[0009] The delay chain module is used to receive the modulated pulse, use the START signal and the STOP signal as triggers, respectively intercept the waveform data of the modulated pulse on the delay chain as detailed timing data, and output it to the decoding module;

[0010] The counter module is used to receive the clock signal, use the START signal and the STOP signal as the switch signal, count the rising edge of the clock, and output the counting result as the rough timing data to the decoding module;

[0011] The decoding module is used to receive and decode the fine timing data and the coarse timing data, and calculate and obtain the measurement time information.

[0012] Furthermore, in the pulse modulation generation module, the modulated pulse is a multi-pulse period signal, and the width of each positive pulse in the multi-pulse period is different, and the width of each negative pulse is the same.

[0013] Furthermore, in the delay chain module, the START signal and the STOP signal are used as triggers, and the clock cycle before the trigger moment is used as the interception cycle to obtain the waveform data of the modulated pulse on the delay chain within the interception cycle as the detailed timing data.

[0014] Furthermore, in the counter module, the rising edges of the clock are counted until the first rising edge of the clock after the STOP signal.

[0015] Furthermore, in the decoding module, the decoding process of the coarse timing data is:

[0016] TC=N×T,

[0017] Among them, TC represents the length of the rough timing time, T represents the clock cycle, and N represents the counting result of the clock rising edge.

[0018] Furthermore, in the decoding module, the decoding process of the detailed timing data is:

[0019] For START signal trigger or STOP signal trigger, any single pulse in the multi-pulse period of the modulated pulse is selected as the characteristic pulse, and any rising edge or falling edge of the modulated pulse in the interception period is used as the measurement edge. For the jth measurement edge:

[0020]

[0021] Among them, TA represents the time length from the triggering moment of the START signal to the first rising edge of the clock thereafter. j It represents the time length from the triggering moment of the START signal to the first rising edge of the subsequent clock when the jth measurement edge is used as the reference; TB represents the time length from the triggering moment of the STOP signal to the first rising edge of the subsequent clock. j It indicates the time length from the triggering moment of the STOP signal to the first rising edge of the clock after the jth measurement edge. A With M B Indicates the number of measured edges in the corresponding interception period, TE A With TE B Indicates the delay time length of the clock rising edge relative to the characteristic pulse in the corresponding interception period. and It represents the delay time length of the jth measurement edge relative to the characteristic pulse in the corresponding interception period. and It represents the number of delay units transmitted on the delay chain for the jth measurement edge in the corresponding interception period; T represents the clock period, and Tr represents the time length of the delay unit on the delay chain.

[0022] Furthermore, in the decoding module, the calculation process of the measurement time information is:

[0023] TIME=TA+TC-TB,

[0024] Among them, TIME represents the measurement time information, TC represents the coarse timing time length, TA represents the time length from the START signal triggering moment to the first rising edge of the subsequent clock, and TB represents the time length from the STOP signal triggering moment to the first rising edge of the subsequent clock.

[0025] Based on the above technical solution, the beneficial effects of the present invention are:

[0026] The present invention provides a time measurement device based on pulse modulation and fine and rough timing, which outputs the same-frequency modulated pulse and clock signal to FPGA through an external modulation pulse generation module; the FPGA receives a START signal and a STOP signal, inputs the START signal and the STOP signal to a delay chain module as a trigger, intercepts the information of the modulated pulse signal on the delay chain as fine timing data, inputs the START signal and the STOP signal to a counter module as a switch signal to count the rising edge of the clock signal as rough timing data, and finally decodes and calculates the fine timing data and the rough timing data through a decoding module to obtain a measurement result, that is, time information;

[0027] In summary, in the present invention, coarse timing is achieved through a counter module to provide time measurement with a wide measurement range; fine timing is achieved through a delay chain to improve the resolution of time measurement, and a single-time multiple-measurement structure is adopted in the fine timing process to improve the nonlinear error performance of the measurement, and the measurement effect of multiple measurements is achieved based on a single delay chain, which saves a large amount of FPGA resources and can realize multi-channel time measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a principle framework diagram of the time measurement device based on pulse modulation and fine and coarse timing in the present invention.

[0029] Figure 2 It is a schematic diagram of the fine timing data calculation principle of the time measurement device based on pulse modulation and fine and coarse timing in the present invention.

[0030] Figure 3 This is a signal diagram generated by a modulation pulse generating module of a time measurement device in an embodiment of the present invention.

[0031] Figure 4 Schematic diagram of the time measurement principle of a time measurement device based on pulse modulation and fine and coarse timing in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments; it should be noted that the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments, and based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0033] This embodiment provides a time measurement device based on pulse modulation and fine and rough timing, and its principle framework is as follows: Figure 1 As shown, it specifically includes: a pulse modulation generation module, a delay chain module, a counter module and a decoding module; each module is described in detail below:

[0034] The pulse modulation generation module is used to generate modulation pulses and clock signals and input them into the FPGA, and respectively provide them as references to the delay chain module and the counter module; wherein the multi-pulse period of the modulation pulse is consistent with the clock period of the clock signal, and the modulation pulse modulates the time to output a pulse train with a pulse width related to time;

[0035] The delay chain module uses the FPGA internal resource CARRY4 to form a delay chain, which is used to receive the modulation pulse generated by the pulse modulation generation module, the START signal and the STOP signal as triggers, and intercept the waveform data of the modulation pulse on the delay chain as the detailed timing data DATA TF , output to the decoding module;

[0036] The counter module receives the START signal and the STOP signal as gate signals, counts the rising edges of the clock signal, and uses the counting result as the rough timing data DATA TC , output to the decoding module;

[0037] Decoding module, receiving detailed timing data DATA TF Rough timing data DATA TC , and decode the two data to calculate the measurement time information TIME.

[0038] In terms of working principle:

[0039] In the present invention, a counter module is used to implement coarse timing and obtain coarse timing data; when the START signal and the STOP signal arrive, they are used as gate signals to count the rising edges of the clock signal until the first rising edge of the clock after the STOP signal; thereby, the number of rising edges N is obtained, which is the coarse timing data DATA TC ; Further, the length of the rough timing is counted as TC, then TC = N × T, T is the clock cycle;

[0040] On this basis, in order to achieve accurate time measurement, it is necessary to calculate the time length from the START signal triggering moment (time measurement start moment) to the first clock rising edge thereafter (recorded as TA) and the time length from the STOP signal triggering moment (time measurement end moment) to the first clock rising edge thereafter (recorded as TB), thereby obtaining the time measurement result TIME: TIME = TA + TC - TB;

[0041] Therefore, the present invention obtains the detailed timing data DATA through the pulse modulation generation module and the delay chain module. TF , and then the decoding module calculates the time length TA and the time length TB; specifically, the START signal and the STOP signal are used as triggers, and the clock cycle before the trigger moment is used as the interception cycle to obtain the waveform data of the modulated pulse on the delay chain within the interception cycle as the detailed timing data DATA TF ;

[0042] Taking the START signal as an example, a single pulse is randomly selected as the characteristic pulse in the multi-pulse cycle of the modulated pulse. In order to facilitate the calculation process of the detailed timing data, the minimum pulse MIN is used as the characteristic pulse; any rising edge or falling edge of the modulated pulse in the interception period is taken as the measurement edge, such as Figure 2 As shown, TE represents the delay time length of the rising edge of the clock relative to the characteristic pulse in the interception period, TI represents the delay time length of the measuring edge relative to the characteristic pulse, and Tr represents the time length of the delay unit in the delay chain;

[0043] Then the time length TA from the START signal triggering moment (time measurement start moment) to the first rising edge of the clock thereafter is specifically:

[0044]

[0045] Among them, TA j It represents the time length from the triggering moment of the START signal to the first rising edge of the clock after the jth measurement edge. A Indicates the delay time length of the clock rising edge relative to the characteristic pulse in the interception period. It indicates the delay time length of the measuring edge relative to the characteristic pulse when the jth measuring edge is used as the reference. It represents the number of delay units that the measurement edge transmits on the delay chain when the jth measurement edge is used as the reference;

[0046] In addition, it should be noted that: for the delay time length TE of the rising edge of the clock relative to the characteristic pulse in the interception period, when the characteristic pulse selects different single pulses, the rising edge of the clock in the interception period may be ahead of the characteristic pulse, then the delay time length TE is a negative value, and the time length TA can also be calculated by substituting it into the above formula; similarly, the delay time length TI of the measurement edge relative to the characteristic pulse may also be a negative value, which does not affect the correctness of the calculation result of the above formula;

[0047] Similarly, the calculation principle of the time length TB from the STOP signal triggering moment (time measurement end moment) to the first clock rising edge thereafter is exactly the same as the calculation principle of the above time length TA, such as Figure 2 As shown, it is specifically expressed as:

[0048]

[0049] Among them, TB j It indicates the time length from the triggering moment of the STOP signal to the first rising edge of the clock after the jth measurement edge. B Indicates the delay time length of the clock rising edge relative to the characteristic pulse in the interception period. It indicates the delay time length of the measuring edge relative to the characteristic pulse when the jth measuring edge is used as the reference. It represents the number of delay units that the measurement edge transmits on the delay chain when the jth measurement edge is used as the reference;

[0050] In order to overcome the nonlinear error and low precision caused by inconsistent delay time of delay units, in the calculation process of time length TB and time length TA, multiple measurement results are obtained by selecting the measurement edge. Taking the average value can reduce the nonlinear error, which is almost the same as the effect achieved by using multi-chain measurement.

[0051] More precisely: In this embodiment, if Figure 3 As shown in the figure, the multi-pulse period of the modulated pulse is consistent with the clock period of the clock signal, specifically T; the number of pulses of the modulated pulse is set to 4, the positive pulse width gradually decreases with time, and the generated positive pulse widths are Ta, Tb, Tc, and Td, respectively, while the negative pulse width Ti remains unchanged; taking the START signal as an example, the information on the delay chain is intercepted, and the total length of the delay chain is consistent with the clock signal period, which is T, and the minimum pulse is used as the characteristic pulse, as shown in Figure 4 As shown, according to the characteristic pulse position and information on the delay chain as detailed timing data DATA TF , the decoding module calculates TA as:

[0052]

[0053] TA1 =T-Ta-Ti-3×Tr;

[0054] TA 2 =T-Ta-5×Tr;

[0055] TA 3 =T-11×Tr;

[0056] TA 4 =T+Ti-13×Tr;

[0057] TA 5 =T+Td+Ti-16×Tr;

[0058] TA 6 =T+Td+2×Ti-18×Tr;

[0059] TA 7 =T+Tc+Td+2×Ti-22×Tr;

[0060] TA 8 =T+Tc+Td+3×Ti-24×Tr;

[0061] Wherein, M is the number of measured edges; in order to simplify the description, the length of the delay chain is shortened a lot in this embodiment, and the delay unit is also set to an ideal delay time; in fact, it is precisely because of the inconsistent delay time of the delay unit that the nonlinear error and low precision are caused. In this embodiment, the nonlinear error can be reduced by averaging multiple measurements; the measurement method of the time length TB is consistent with TA, thereby decoding the fine timing data DATA TF Time information in

[0062] In the coarse timing, the START signal and the STOP signal are used as gate signals to count the rising edges of the incoming clock signal. A total of 7 rising edges are counted and recorded as N as the coarse timing data DATA TC , then TC is expressed as: TC = 7 × T, thereby decoding the rough timing data DATA TC Time information;

[0063] Finally, the fine timing data and the coarse timing data are merged to obtain the final measured time TIME: TIME = TA + TC - TB.

[0064] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A time measurement device based on pulse modulation and fine and coarse timing, comprising: Pulse modulation generation module, delay chain module, counter module and decoding module; characterized in that: A pulse modulation generation module is used to generate a modulation pulse and a clock signal to be input into the delay chain module and the counter module, wherein the multi-pulse period of the modulation pulse is consistent with the clock period of the clock signal; The delay chain module is used to receive the modulated pulse, use the START signal and the STOP signal as triggers, respectively intercept the waveform data of the modulated pulse on the delay chain as detailed timing data, and output it to the decoding module; The counter module is used to receive the clock signal, use the START signal and the STOP signal as the switch signal, count the rising edge of the clock, and output the counting result as the rough timing data to the decoding module; The decoding module is used to receive and decode the fine timing data and the coarse timing data, and calculate and obtain the measurement time information.

2. The time measurement device based on pulse modulation and fine and coarse timing according to claim 1, characterized in that: In the pulse modulation generation module, the modulated pulse is a multi-pulse period signal, in which the widths of the positive pulses are different and the widths of the negative pulses are the same.

3. The time measurement device based on pulse modulation and fine and coarse timing according to claim 1, characterized in that: In the delay chain module, the START signal and the STOP signal are used as triggers, and the clock cycle before the trigger moment is used as the interception cycle to obtain the waveform data of the modulated pulse on the delay chain within the interception cycle as the detailed timing data.

4. The time measurement device based on pulse modulation and fine and coarse timing according to claim 1, characterized in that: In the counter module, the rising edges of the clock are counted until the first rising edge of the clock after the STOP signal.

5. The time measurement device based on pulse modulation and fine and coarse timing according to claim 1, characterized in that: In the decoding module, the decoding process of the coarse timing data is: TC=N×T, Among them, TC represents the length of the rough timing time, T represents the clock cycle, and N represents the counting result of the clock rising edge.

6. The time measurement device based on pulse modulation and fine and coarse timing according to claim 1, characterized in that: In the decoding module, the decoding process of the detailed timing data is: For START signal trigger or STOP signal trigger, any single pulse in the multi-pulse period of the modulated pulse is selected as the characteristic pulse, and any rising edge or falling edge of the modulated pulse in the interception period is used as the measurement edge. For the jth measurement edge: Among them, TA represents the time length from the triggering moment of the START signal to the first rising edge of the clock thereafter. j It represents the time length from the triggering moment of the START signal to the first rising edge of the subsequent clock when the jth measurement edge is used as the reference; TB represents the time length from the triggering moment of the STOP signal to the first rising edge of the subsequent clock. j It indicates the time length from the triggering moment of the STOP signal to the first rising edge of the clock after the jth measurement edge. A With M B Indicates the number of measured edges in the corresponding interception period, TE A With TE B Indicates the delay time length of the clock rising edge relative to the characteristic pulse in the corresponding interception period. and It represents the delay time length of the jth measurement edge relative to the characteristic pulse in the corresponding interception period. and It represents the number of delay units transmitted on the delay chain for the jth measurement edge in the corresponding interception period; T represents the clock period, and Tr represents the time length of the delay unit on the delay chain.

7. The time measurement device based on pulse modulation and fine and coarse timing according to claim 1, characterized in that: In the decoding module, the calculation process of the measurement time information is: TIME=TA+TC-TB, Among them, TIME represents the measurement time information, TC represents the coarse timing time length, TA represents the time length from the START signal triggering moment to the first subsequent clock rising edge, and TB represents the time length from the STOP signal triggering moment to the first subsequent clock rising edge.

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