FEC-based adaptive SerDes architecture and power consumption adjustment method thereof

Abstract

The invention provides a self-adaptive SerDes architecture based on FEC and a power consumption adjusting method, and the architecture comprises an analog front end, an analog-to-digital converter, a digital signal processor, a transmitting side forward error correction encoder, a receiving side forward error correction decoder, a microprogram controller and the like. Wherein the sending side forward error correction encoder adds additional error correction codes to transmission data to encode the data; the receiving side forward error correction decoder decodes the transmission data, and identifies and corrects errors occurring in the data transmission process through the added error correction codes; and the microprogram controller is used for monitoring the sending side forward error correction encoder and the receiving side forward error correction decoder in real time and reading back log information of the sending side forward error correction encoder and the receiving side forward error correction decoder. According to the technical scheme of the invention, the signal quality and power consumption of SerDes can be adaptively balanced, and the method has good applicability in different product scenes and different PVT states of a chip.

Description

Technical Field

[0001] The present application belongs to the field of communication technology, and in particular relates to an adaptive SerDes architecture based on FEC and a power consumption adjustment method thereof. Background Art

[0002] Power consumption has always been one of the important parameters in the chip application process. With the development of technology, the design size of chips is getting smaller and smaller, and the integration is getting higher and higher. As a result, the power consumption density of chips is also getting higher and higher. Especially after entering the FinFET process, the heat dissipation problem of chips has become an important factor restricting the continued improvement of chip integration.

[0003] In the communication and computing fields with high integration and high power density, the power consumption of SerDes (Serial-Deserial) IP has always been an important part of the power consumption ratio, especially in the high-bandwidth switching and routing chips. Due to the large signal bandwidth and the large number of SerDes ports used, the power consumption of SerDes can even exceed 50%. Therefore, reducing the power consumption of SerDes per unit bandwidth as much as possible is one of the important directions that need to be continuously worked on when solving the chip heat dissipation problem.

[0004] In the process of SerDes circuit design, typical circuit modules are designed with different power consumption levels. For example, the current level of AFE (Analog front end) is adjustable, the bit level of ADC (Analog to Digital converter) is adjustable, and the regulator output voltage V reg The gear is adjustable, so that different power consumption configuration gears can be used in different link application scenarios and different performance requirements, thereby achieving the goal of saving the most power according to different scenarios.

[0005] However, in the process of productization, the application scenarios of SerDes are usually very complex. The link conditions of the same SerDes chip channel in different applications may vary greatly. It is difficult to clearly define which scenarios use which power consumption configuration levels during chip development. In addition, due to the different PVT conditions of the chip, the performance of the SerDes itself will also fluctuate significantly, making the specific implementation plan of the power consumption configuration level even more difficult.

[0006] Therefore, a power consumption regulation method with higher performance and more flexible regulation is needed. Summary of the invention

[0007] The purpose of the present application is to provide an adaptive SerDes architecture based on FEC (Forward Error correction) and a power consumption adjustment method thereof, aiming to solve the problem of maximally saving the power consumption used by SerDes in different scenarios.

[0008] According to a first aspect of the present application, an adaptive SerDes architecture based on FEC is provided, comprising an analog front end, an analog-to-digital converter, a digital signal processor, a forward error correction encoder on a transmitting side, a forward error correction decoder on a receiving side, a microprogram controller, a phase-locked loop, a digital-to-analog converter and a forward equalizer, wherein:

[0009] The analog front end is used to perform preliminary inter-symbol interference compensation on the input signal;

[0010] The analog-to-digital converter is used to convert the signal after preliminary inter-symbol interference compensation of the analog front end into a digital signal;

[0011] The digital signal processor is used to further perform inter-symbol interference compensation on the digital signal digitized by the analog-to-digital converter, and then restore the data in the input signal;

[0012] The forward error correction encoder at the sending side adds an additional error correction code to the transmission data to encode the data;

[0013] The forward error correction decoder at the receiving side decodes the transmission data, and identifies and corrects errors occurring during the data transmission process by means of the added error correction code;

[0014] The microprogram controller is used to monitor the forward error correction encoder on the sending side and the forward error correction decoder on the receiving side in real time, and read back the log information of the forward error correction encoder on the sending side and the forward error correction decoder on the receiving side;

[0015] The phase-locked loop is used to generate a high-speed and high-performance local clock;

[0016] The digital-to-analog converter is used for sending high-speed signals at the local end;

[0017] The forward equalizer is used to pre-compensate the signal quality of the high-speed signal sent by the local end.

[0018] In an optional implementation, the microprogram controller includes a power consumption control algorithm module, and the power consumption control algorithm module includes a comparator, an accumulator, a threshold comparator, an accumulator and a lookup table.

[0019] In an optional implementation, the microprogram controller includes a FW software module for processing log information.

[0020] In an optional implementation, the microprogram controller controls the power consumption of the analog front end, phase-locked loop, analog-to-digital converter and digital signal processor.

[0021] In an optional embodiment, the microprogram controller dynamically adjusts the Bias current gear of the analog front end and the phase-locked loop, the V of the clock path, and the reg Power consumption is controlled by voltage levels, bit width levels of the analog-to-digital converter, and calculation accuracy levels of the digital signal processor.

[0022] According to a second aspect of the present application, a method for adjusting power consumption of an adaptive SerDes architecture based on FEC is provided, comprising the following steps:

[0023] The forward error correction encoder on the sending side adds additional error correction codes to the transmission data to encode the data; after the transmission data reaches the receiving side, the forward error correction decoder on the receiving side decodes the transmission data and identifies and corrects errors that occur during the data transmission process through the added error correction codes;

[0024] The microprogram controller monitors the forward error correction encoder on the sending side and the forward error correction decoder on the receiving side, and reads back and analyzes the log information therein to obtain the code data of the maximum symbol error correction of the link;

[0025] The Margin state of the link is evaluated according to the obtained code data of the maximum symbol error correction of the link, and the power consumption level of the main functional modules in the SerDes is dynamically adjusted according to the Margin state.

[0026] In an optional implementation, dynamically adjusting the power consumption levels of the main functional modules in the SerDes according to the Margin status includes adjusting the Bias current level of modules such as AFE / PLL, the Vreg voltage level of the Clock path, the bit width level of the ADC, and the calculation accuracy level of the DSP.

[0027] In an optional implementation, the microprogram controller uses a built-in FW software processing algorithm to analyze the log information therein.

[0028] In an optional embodiment, the FW software processing algorithm includes low-pass filtering.

[0029] In an optional implementation, after acquiring the code data of the link maximum symbol error correction, the microprogram controller performs algorithmic processing on the code data, and the algorithmic processing includes a comparison algorithm, an accumulation algorithm, a threshold comparison, an accumulator and a lookup table.

[0030] Compared with the related art, the technical solution of the present application has at least the following advantages:

[0031] The FEC-based adaptive SerDes architecture of the present application is compatible with the typical high-speed SerDes implementation architecture without adding too much extra cost. The present application can adaptively balance the signal quality and power consumption of SerDes, and can be implemented in different product scenarios and different PVT states of chips. At the same time, due to the use of software control, the optimization and debugging of the present application is also very flexible.

[0032] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 is a diagram of an FEC-based adaptive SerDes architecture according to an exemplary embodiment of the present application.

[0035] Figure 2 It is a schematic diagram of an MCU power consumption control algorithm according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] In order to save as much SerDes PHY (Physical Layer) power consumption as possible under a normal business environment, the present application proposes a technical solution that can adaptively adjust parameter configuration according to the performance margin of SerDes in the current link scenario and the current chip PVT (Process, voltage, temperature) characteristics, which can maximize the power consumption of SerDes in different scenarios.

[0038] like Figure 1 As shown, an adaptive SerDes architecture based on FEC is provided, including AFE (Aanlog frontend), ADC (Analog to Digital Converter), DSP (Digital Signal Process), FEC (Forward Error Correction) encoder on the sending side, FEC decoder on the receiving side, MCU (Microprogrammed Control Unit), PLL (Phase Lock Loop), DAC (Digital to Analog Converter), FFE (Feed-Forward Equalizer). AFE is used to perform preliminary inter-symbol interference compensation on the input signal, ADC is used to convert the signal after preliminary inter-symbol interference compensation of the analog front end into a digital signal, and DSP is used to perform further inter-symbol interference compensation on the digital signal digitized by the analog-to-digital converter, and then restore the data in the input signal;

[0039] The FEC encoder on the sending side adds additional error correction codes to the transmitted data to encode the data;

[0040] The receiving side FEC decoder decodes the transmission data, and identifies and corrects errors that occur during data transmission by adding error correction codes; the MCU is used to monitor the above-mentioned sending side FEC encoder and the receiving side FEC decoder in real time, and read back the log information of the sending side FEC encoder and the receiving side FEC decoder. LLC is used to generate a high-speed and high-performance local clock, and DAC is used to send high-speed signals at this end: FFE is used to pre-compensate the signal quality of the high-speed signal sent by this end.

[0041] Another embodiment of the present application provides an adaptive power consumption adjustment method based on FEC, comprising the following steps:

[0042] The FEC encoder on the sending side adds additional error correction codes to the transmission data to encode the data. This process enhances the error detection and correction capabilities of the data during transmission by adding additional error correction codes. After the transmission data reaches the receiving side, the FEC decoder on the receiving side decodes the transmission data and uses the added error correction codes to identify and correct errors that occur during the data transmission process, thereby reducing the original bit error rate and improving the reliability and efficiency of data transmission.

[0043] The MCU monitors the FEC encoder on the sending side and the FEC decoder on the receiving side. This process allows the system to have an immediate understanding of the functions and performance of the FEC module, providing data support for subsequent adjustments and optimizations. The log information is read back and analyzed to obtain the code data of the link's maximum symbol error correction; the above log information contains the code data about the link's maximum symbol error correction, which is crucial for analyzing and optimizing link performance.

[0044] like Figure 2 As shown in the figure, after obtaining the code data of the link maximum symbol error correction, the microprogram controller performs certain algorithm processing on the code, including comparison algorithm, accumulation algorithm, threshold comparison, accumulator and lookup table. After the above processing, the power consumption level of the main functional modules in the SerDes can be dynamically adjusted according to the preset Margin state, including adjusting the Bias current level of the AFE / PLL module, the V reg Voltage range, ADC bit width range, and DSP calculation accuracy range.

[0045] MCU uses built-in FW software processing algorithm to analyze the log information. FW software refers to software in the form of firmware, which is usually located between the operating system and application program of the hardware device and is used to control and manage the basic functions of the hardware.

[0046] In the normal service process of SerDes, the present application dynamically collects the performance margin of the data signal received by SerDes, and then dynamically adjusts the Bias current gear of the AFE (Aanlog front end, analog front end) / PLL (Phase Lock loop, phase-locked loop) and other modules, the V of the Clock path, etc. according to the state of the performance margin of the data signal. reg By means of voltage level, ADC bit width level and DSP calculation accuracy level, the power consumption of SerDes IP can be reduced at the expense of performance margin to a certain extent, so that SerDes can achieve a dynamic balance between power consumption and performance margin, and achieve the purpose of maximizing power saving.

[0047] In summary, through precise monitoring and dynamic adjustment, high-speed PMA4 (4-Level Pulse Amplitude Modulation) SerDes applications can optimize power consumption while ensuring data transmission performance. This not only improves the economy of the system, but also enhances its environmental friendliness, and is an indispensable part of modern high-speed communication systems.

[0048] Since the solution of this application can dynamically monitor the link margin status in real time and adaptively control the balance between power consumption and performance, it can be flexibly used in various complex scenarios and under different chip PVT conditions. At the same time, since the core control link is implemented using FW software, debugging is also very flexible.

[0049] Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that he or she may still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An adaptive SerDes architecture based on FEC, characterized in that: It includes an analog front end, an analog-to-digital converter, a digital signal processor, a forward error correction encoder on the transmitting side, a forward error correction decoder on the receiving side, a microprogram controller, a phase-locked loop, a digital-to-analog converter and a feedforward equalizer, wherein: The analog front end is used to perform preliminary inter-symbol interference compensation on the input signal; The analog-to-digital converter is used to convert the signal after preliminary inter-symbol interference compensation of the analog front end into a digital signal; The digital signal processor is used to further perform inter-symbol interference compensation on the digital signal digitized by the analog-to-digital converter, and then restore the data in the input signal; The forward error correction encoder at the sending side adds an additional error correction code to the transmission data to encode the data; The forward error correction decoder at the receiving side decodes the transmission data, and identifies and corrects errors occurring during the data transmission process by means of the added error correction code; The microprogram controller is used to monitor the forward error correction encoder on the sending side and the forward error correction decoder on the receiving side in real time, and read back the log information of the forward error correction encoder on the sending side and the forward error correction decoder on the receiving side; The phase-locked loop is used to generate a high-speed and high-performance local clock; The digital-to-analog converter is used for sending high-speed signals at the local end; The feedforward equalizer is used to pre-compensate the signal quality of the high-speed signal sent by the local end.

2. The FEC-based adaptive SerDes architecture as claimed in claim 1, characterized in that: The microprogram controller comprises a power consumption control algorithm module, and the power consumption control algorithm module comprises a comparator, an accumulator, a threshold comparator, an accumulator and a lookup table.

3. The FEC-based adaptive SerDes architecture as claimed in claim 1, characterized in that: The microprogram controller includes a FW software module for processing log information.

4. The FEC-based adaptive SerDes architecture as claimed in claim 1, characterized in that: The microprogram controller controls the power consumption of the analog front end, the phase-locked loop, the analog-to-digital converter and the digital signal processor.

5. The FEC-based adaptive SerDes architecture as claimed in claim 1, characterized in that: The microprogram controller dynamically adjusts the Bias current gear of the analog front end and the phase-locked loop, the Vreg voltage gear of the clock path, the bit width gear of the analog-to-digital converter and the calculation accuracy gear of the digital signal processor to achieve power consumption control according to the Margin state of the data signal.

6. A method for adjusting power consumption using the adaptive SerDes architecture based on FEC as claimed in any one of claims 1 to 5, characterized in that: The following steps are involved: The forward error correction encoder on the sending side adds additional error correction codes to the transmitted data to encode the data; After the transmission data reaches the receiving side, the forward error correction decoder at the receiving side decodes the transmission data and identifies and corrects errors that occur during the data transmission process through the added error correction code; The microprogram controller monitors the forward error correction encoder on the sending side and the forward error correction decoder on the receiving side, and reads back and analyzes the log information therein to obtain the code data of the maximum symbol error correction of the link; The Margin state of the link is evaluated according to the obtained code data of the maximum symbol error correction of the link, and the power consumption level of the main functional modules in the SerDes is dynamically adjusted according to the Margin state.

7. The power consumption adjustment method of the FEC-based adaptive SerDes architecture according to claim 6, characterized in that: The dynamic adjustment of the power consumption levels of the main functional modules in the SerDes according to the Margin state includes adjusting the Bias current level of the analog front end, the phase-locked loop module, the Vreg voltage level of the Clock path, the bit width level of the analog-to-digital converter, and the calculation accuracy level of the digital signal processor.

8. The power consumption adjustment method of the FEC-based adaptive SerDes architecture according to claim 6, characterized in that: The microprogram controller uses a built-in FW software processing algorithm to analyze the log information therein.

9. The power consumption adjustment method of the FEC-based adaptive SerDes architecture according to claim 8, characterized in that: The FW software processing algorithm includes a low-pass filtering process.

10. The power consumption adjustment method of the FEC-based adaptive SerDes architecture according to claim 6, characterized in that: After acquiring the code data of the link maximum symbol error correction, the microprogram controller performs algorithm processing on the code data, and the algorithm processing includes a comparison algorithm, an accumulation algorithm, a threshold comparison, an accumulator and a lookup table.

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