Data processing method, device and equipment, medium and recorder
By designing interrupt register and interrupt status identification in the data processing device, the problem of interrupt management caused by a large number of interrupt requests in existing technology has been solved, and high -efficiency management of multiple interruptions is realized, and system resources are reduced.
Patent Information
- Application Number
- CN202411610358.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-01-24
AI Technical Summary
In the prior art, when processing a large number of interrupt requests, the upper limit that the interrupt pin can handle is exceeded, resulting in difficulty in interrupt management.
A data processing device is designed, including the PS end and PL end. There is an interrupt register in the PL terminal to store interrupt requests and indicate whether interrupts are generated by interrupt status identification. PS reads the interrupt register, determines the target interrupt request according to the interrupt status identification, and removes the interrupt position after processing.
By storing multiple interrupts in registers and managing them through interrupt status identifiers, multiple interrupts can be managed through one interrupt pin, reducing the overhead of system resources.
Smart Images
Figure CN119356822A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of interrupt management, and in particular to a data processing method, device, equipment, medium and recorder. Background Art
[0002] Refers to the entire process of the processor handling emergency events that occur during program operation. During program operation, if an emergency event occurs outside the system, inside the system, or in the current program itself, the processor immediately stops the current program and automatically switches to the corresponding processing program (interrupt service program). After processing, it returns to the original program.
[0003] During the use of the CPU, a large number of interrupts are often encountered. When the number of interrupt requests exceeds the upper limit that the interrupt pin can handle, difficulties in interrupt management will arise. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, the present application provides a data processing method, device, equipment, medium and recorder to solve at least one defect in the prior art.
[0005] To achieve the above-mentioned purpose and other purposes, the present application provides a data processing device, the data processing device comprising a PS end and a PL end; an interrupt register is provided in the PL end, the interrupt register comprises an interrupt bit for storing an interrupt request, each interrupt bit has a first interrupt flag;
[0006] The PL terminal is used to generate multiple interrupt requests, store the multiple interrupt requests in the interrupt bits of the interrupt register according to a predetermined storage rule, and transform the first interrupt flag of the interrupt bit storing the interrupt request into a second interrupt flag;
[0007] The PS end is used to read the interrupt register in the PL end, obtain the first interrupt identifier and the second interrupt identifier of the interrupt bit, and determine the target interrupt request based on the first interrupt identifier and the second interrupt identifier; the PS end is also used to clear the interrupt bit after the target interrupt request is processed and convert the second interrupt identifier corresponding to the interrupt bit into the first interrupt identifier.
[0008] In one embodiment of the present application, the PS end includes a first core and a second core, and the interrupt register includes a first interrupt register and a second interrupt register;
[0009] The first kernel is used for determining a first target interrupt request according to a first interrupt flag and a second interrupt flag of an interrupt bit in a first interrupt register;
[0010] The second core is used for determining a second target interrupt request according to a first interrupt flag and a second interrupt flag of an interrupt bit in a second interrupt register.
[0011] In one embodiment of the present application, after determining the target interrupt request, the PS end executes an interrupt service program according to the target interrupt request, so as to perform data transmission through the interrupt service program.
[0012] In one embodiment of the present application, when the target interrupt request of the PS side is a data acquisition interrupt, the interrupt service program transmits the first type of data in a first manner; when the target interrupt request is a communication interrupt, the interrupt service program transmits the second type of data in a second manner.
[0013] In one embodiment of the present application, the first type of data is collected data, and the first method includes adding header information to the collected data; the second type of data is communication data, and the second method includes directly transmitting the communication data.
[0014] In one embodiment of the present application, the data acquisition interruption includes a LIN acquisition interruption, a CAN acquisition interruption, and an Ethernet acquisition interruption, and the communication interruption includes a LIN communication interruption and a CAN communication interruption; when the data acquisition interruption is a LIN acquisition interruption, the acquired data is obtained from the LIN bus through a LIN data acquisition module based on the LIN communication mode; when the data acquisition interruption is a CAN acquisition interruption, the acquired data is obtained from the CAN bus through a CAN data acquisition module based on the CAN communication mode; when the data acquisition interruption is an Ethernet acquisition interruption, the acquired data is obtained from the Ethernet through an Ethernet data acquisition module based on the Ethernet communication mode; when the communication interruption is a LIN communication interruption, the communication data is obtained from the LIN bus; when the communication interruption is a CAN communication interruption, the communication data is obtained from the CAN bus.
[0015] To achieve the above objectives and other related objectives, the present application provides a data processing method, which includes:
[0016] Generate multiple interrupt requests through the PL terminal, store the multiple interrupt requests in the interrupt bit of the interrupt register according to a predetermined storage rule, and transform the first interrupt flag of the interrupt bit storing the interrupt request into a second interrupt flag;
[0017] Using the PS end to read the interrupt register in the PL end, obtain the first interrupt flag and the second interrupt flag of the interrupt bit in the interrupt register, and determine the target interrupt request according to the first interrupt flag and the second interrupt flag;
[0018] After the interrupt request is processed, the interrupt bit is cleared using the PS terminal and the second interrupt flag corresponding to the interrupt bit is converted into the first interrupt flag.
[0019] To achieve the above-mentioned purpose and other related purposes, the present application provides a recorder, which includes the data processing device.
[0020] To achieve the above objectives and other related objectives, the present application provides a data processing device, including:
[0021] one or more processors; and
[0022] The memory is used to store one or more programs. When the one or more programs are executed by the one or more processors, the memory implements the data processing method.
[0023] To achieve the above objectives and other related objectives, the present application provides one or more machine-readable media on which instructions are stored, which, when executed by one or more processors, enable the processors to execute the data processing method.
[0024] Beneficial effects of this application:
[0025] The present application discloses a data processing device, comprising a PS end and a PL end; an interrupt register is provided in the PL end, the interrupt register comprises an interrupt bit for storing an interrupt request, each interrupt bit has a first interrupt flag; the PL end is used to generate multiple interrupt requests, store the multiple interrupt requests in the interrupt bit of the interrupt register according to a predetermined storage rule, and transform the first interrupt flag of the interrupt bit storing the interrupt request into a second interrupt flag; the PS end is used to read the interrupt register in the PL end, obtain the first interrupt flag and the second interrupt flag of the interrupt bit, and determine the target interrupt request according to the first interrupt flag and the second interrupt flag, and the PS end is also used to clear the interrupt bit after the interrupt request is processed and transform the second interrupt flag corresponding to the interrupt bit into the first interrupt flag; the present application stores multiple interrupts in a register, and indicates whether an interrupt is generated by an interrupt status flag, and then the PS end obtains the interrupt status flag of the interrupt register by reading the interrupt register, and determines the interrupt source according to the interrupt status flag, thereby managing multiple interrupts through one interrupt pin, reducing the overhead of system resources.
[0026] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:
[0028] Figure 1 is a schematic diagram of a data processing device according to an embodiment of the present application;
[0029] Figure 2 This is a principle block diagram of a CAN data acquisition module according to an embodiment of the present application;
[0030] Figure 3 This is a principle block diagram of a LIN data acquisition module according to an embodiment of the present application;
[0031] Figure 4 This is a principle block diagram of a network data acquisition module according to an embodiment of the present application;
[0032] Figure 5 A schematic diagram of the structure of a computer system suitable for implementing the memory of an embodiment of the present application is shown. DETAILED DESCRIPTION
[0033] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0034] The illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. Therefore, the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0035] Although the terms "first", "second", "A", and "B", etc. may be used herein to describe various elements, these elements should not be limited by these terms and are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the following technology. The term "and / or" includes a combination of multiple related items or any of the multiple related items.
[0036] As used herein, unless the context indicates otherwise, the singular form is intended to include the plural form, and it will be understood that the term "comprising" means the presence of stated features, quantities, steps, operations, elements, or combinations thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.
[0037] Before the detailed description, it is intended to clarify that the division of components in this specification is divided only by the main function of each component. That is, two or more components to be described below can be combined into one component, or can be divided into two or more components according to more detailed functions. In addition to the main function of the component, each component to be described below can also perform some or all of the functions of other components, and some of the main functions of each component can be exclusively performed by other components.
[0038] Since the interrupt pins between the PL (Progarmmable Logic) end and the PS (Processing System) end are limited, in order to process the corresponding interrupt request in time, the present application provides a data processing device to manage the interrupt request. Figure 1 As shown, a data processing device includes a PS end and a PL end; an interrupt register is set in the PL end, the interrupt register includes an interrupt bit for storing interrupt requests, and each interrupt bit has a first interrupt flag; the PL end is used to generate multiple interrupt requests, store the multiple interrupt requests in the interrupt bit of the interrupt register according to a predetermined storage rule, and transform the first interrupt flag of the interrupt bit storing the interrupt request into a second interrupt flag; the PS end is used to read the interrupt register in the PL end, obtain the first interrupt flag and the second interrupt flag of the interrupt bit, and determine the target interrupt request according to the first interrupt flag and the second interrupt flag, and the PS end is also used to clear the interrupt bit after the interrupt request is processed and transform the second interrupt flag corresponding to the interrupt bit into the first interrupt flag. The present application stores multiple interrupts in a register, and indicates whether an interrupt is generated by an interrupt status flag, and then the PS end obtains the interrupt status flag of the interrupt register by reading the interrupt register, and determines the interrupt source according to the interrupt status flag, thereby managing multiple interrupts through one interrupt pin, reducing the overhead of system resources.
[0039] An interrupt register is pre-set in the PL terminal. The interrupt register includes multiple interrupt bits for storing interrupt requests. The interrupt requests correspond to the interrupt bits one by one. At the same time, the interrupt bit also has an interrupt flag. When an interrupt request is stored in the interrupt bit, the interrupt flag is the second interrupt flag. When the interrupt request is not stored in the interrupt bit, the interrupt flag is the first interrupt flag. The first interrupt flag can be represented by "0" and the second interrupt flag can be represented by "1". In the initial state, the interrupt flags of all interrupt bits are the first interrupt flags, that is, at the beginning, all first interrupt flags can form a data structure "000000000000".
[0040] The PL terminal generates multiple interrupt requests, and each interrupt request is stored in the interrupt bit of the interrupt register according to a predetermined storage rule. The interrupt flag of the interrupt bit storing the interrupt request is the second interrupt flag, that is, "1". After the interrupt request is stored in the interrupt register, the data structure composed of the first interrupt flag and the second interrupt flag is "111000110101".
[0041] The predetermined storage rule refers to a preset interrupt storage rule, that is, the first type of interrupt request is stored in the first position of the interrupt register, the second type of interrupt request is stored in the second position of the interrupt register, and the third type of interrupt request is stored in the third position of the interrupt register. That is, after an interrupt request is generated at the PL end, the corresponding interrupt request is stored in the corresponding position of the interrupt register according to the type of the interrupt request. For example, for an interrupt register with twelve bits, the first 4 interrupt bits can be used to store the first type of interrupt request, the middle 4 interrupt bits can be used to store the second type of interrupt request, and the last 4 interrupt bits can be used to store the third type of interrupt request. At the same time, the storage bits of different interrupt requests in the same type of interrupt request can also be predetermined. For example, the first type of interrupt request includes 3 interrupt requests, then the storage positions of these 3 interrupt requests can also be preset.
[0042] After the PL generates an interrupt request and stores it in the interrupt register, it will change the interrupt flag of the corresponding interrupt bit, that is, change the first interrupt flag to the second interrupt flag. For example, change the interrupt flag "0" to the interrupt flag "1". If the interrupt flags of all interrupt bits in the start state are 0, the data structure composed of interrupt flags is "000000000000". If the first interrupt bit, the second interrupt bit, and the fifth interrupt bit store the interrupt request, the data structure composed of interrupt flags is "110010000000".
[0043] The PS end reads the interrupt register, obtains the interrupt request in the interrupt register, and obtains the interrupt identifiers of all interrupt bits, namely, the second interrupt identifier of the interrupt bit storing the interrupt request and the first interrupt identifier of the interrupt bit not storing the interrupt request. Then, the target interrupt request can be determined according to the first interrupt identifier and the second interrupt identifier. For example, if it is recognized that the data structure includes three second interrupt identifiers, namely, the interrupt identifier of the first interrupt bit, the interrupt identifier of the second interrupt bit, and the interrupt identifier of the fifth interrupt bit, the source of the interrupt request can be determined. Since the storage locations of different interrupt requests are predetermined, the PS end can determine the target interrupt request.
[0044] In some embodiments of the present application, the PS end includes a first core and a second core, and the interrupt register includes a first interrupt register and a second interrupt register; the first core is used to determine a first target interrupt request according to a first interrupt identifier and a second interrupt identifier of an interrupt bit in the first interrupt register; the second core is used to determine a second target interrupt request according to the first interrupt identifier and the second interrupt identifier of an interrupt bit in the second interrupt register. In the recorder, the data interaction between the PL end and the PS end includes multiple types of interrupt requests. In order to manage different types of interrupt requests, different cores can be set for management. For example, the first type of interrupt request is managed by the first core, and the second type of interrupt request is managed by the second core. Accordingly, when the PL end interacts with the PS end for data, different types of interrupt requests are generated, and the first interrupt register is set to store the first type of interrupt request, and the second interrupt register is set to store the second type of interrupt request.
[0045] In some embodiments of the present application, after the PS side determines the target interrupt request, it executes the interrupt service program according to the target interrupt request. The interrupt service program can be written into the device in advance. After the PS side determines the target interrupt request, the CPU will suspend the current task and jump to the interrupt service program for processing. After the processing is completed, the CPU will return to the position before the interrupt occurs and continue to execute the original task; at the same time, after the target interrupt request is processed, the interrupt bit is cleared and the second interrupt flag corresponding to the interrupt bit is converted to the first interrupt flag. The main function of the interrupt service program is to respond to and process external or internal events to ensure the stability and efficient operation of the system.
[0046] In some embodiments of the present application, if there are multiple target interrupt requests, the corresponding interrupt service routines are executed according to the preset interrupt priority. The interrupt with a higher priority is executed first, and the interrupt with a lower priority is executed later.
[0047] In some embodiments of the present application, when the target interrupt request of the PS side is a data acquisition interrupt, the interrupt service program transmits the first type of data in a first manner; when the target interrupt request is a communication interrupt, the interrupt service program transmits the second type of data in a second manner. The present application manages different types of interrupt requests through the first kernel and the second kernel, and different interrupt requests correspond to different interrupt service programs. When the target interrupt request is a data acquisition interrupt, the interrupt service program controls the corresponding data acquisition module to collect the corresponding data and perform corresponding data processing, that is, the data is processed in a first manner, and then the processed collected data is transmitted, such as transmitting the data to the first kernel. When the target interrupt request is a communication interrupt, the interrupt service program controls the corresponding data transceiver module to receive and send data, and then processes the received and sent data, that is, the data is processed in a second manner, and then the processed communication data is transmitted, such as being transmitted to the second kernel.
[0048] In some embodiments of the present application, the first type of data is collected data, and the first method includes adding header information to the collected data; the second type of data is communication data, and the second method includes directly transmitting the communication data. When the first type of data is collected data, the collected data collected by the data collection module is added with header information, and then the collected data with the added header information is transmitted; when the second type of data is communication data, the communication data is processed, and then the processed communication data is transmitted.
[0049] In some embodiments of the present application, data acquisition interruption includes LIN acquisition interruption, CAN acquisition interruption, Ethernet acquisition interruption, and communication interruption includes LIN communication interruption and CAN communication interruption; when the data acquisition interruption is LIN acquisition interruption, acquisition data is obtained from the LIN bus through a LIN data acquisition module based on the LIN communication mode; when the data acquisition interruption is CAN acquisition interruption, acquisition data is obtained from the CAN bus through a CAN data acquisition module based on the CAN communication mode; when the data acquisition interruption is Ethernet acquisition interruption, acquisition data is obtained from Ethernet through an Ethernet data acquisition module based on the Ethernet communication mode; when the communication interruption is LIN communication interruption, communication data is obtained from the LIN bus; when the communication interruption is CAN communication interruption, communication data is obtained from the CAN bus. In one embodiment, different interrupt requests are managed by different cores, and LIN acquisition interruption, CAN interruption, and Ethernet acquisition interruption are managed by the first core PS-A core, while LIN communication interruption and CAN communication interruption are managed by the second core PS-R core.
[0050] For the first interrupt register, it is used to store data acquisition interrupts; for the second interrupt register, it is used to store communication interrupts. If the PL end generates a LIN acquisition interrupt and a CAN acquisition interrupt, the LIN acquisition interrupt and the CAN acquisition interrupt are stored in the interrupt bit of the first interrupt register. The storage rules of the LIN acquisition interrupt, the CAN acquisition interrupt, and the Ethernet acquisition interrupt are pre-set in the first interrupt register. For example, the LIN acquisition interrupt needs to be stored in the first interrupt bit, the CAN acquisition interrupt needs to be stored in the second interrupt bit, and the Ethernet acquisition interrupt needs to be stored in the third interrupt bit. In the initial state, the data structure composed of the interrupt identifier is "000". When the LIN acquisition interrupt and the CAN acquisition interrupt are stored in the first interrupt register, the data structure composed of the interrupt identifier becomes "110". The PS end reads the data structure "110" of the first interrupt register to determine that the target interrupt request is the LIN acquisition interrupt and the CAN acquisition interrupt. Correspondingly, the PS calls the LIN acquisition interrupt service program to execute the LIN acquisition interrupt request, and calls the CAN acquisition interrupt service program to execute the CAN acquisition interrupt request.
[0051] For the second interrupt register, it is used to store communication interrupt requests. If the PL end generates a LIN communication interruption and a CAN communication interruption, the LIN communication interruption and the CAN communication interruption are stored in the interrupt bit of the second interrupt register. The storage rules of the LIN communication interruption, the CAN communication interruption, and the Ethernet communication interruption are pre-set in the second interrupt register. For example, the LIN communication interruption needs to be stored in the first interruption bit, the CAN communication interruption needs to be stored in the second interruption bit, and the Ethernet communication interruption needs to be stored in the third interruption bit. In some embodiments, each interruption in the LIN communication interruption, the CAN communication interruption, and the Ethernet communication interruption can be set multiple times. For example, the first interruption in the LIN communication interruption needs to be stored in the first interruption bit, the second interruption needs to be stored in the second interruption bit, the third interruption needs to be stored in the third interruption bit, and the fourth interruption needs to be stored in the fourth interruption bit, and so on, setting the storage locations of multiple LIN communication interruptions. Similarly, the storage interruption bits of the CAN communication interruption and the Ethernet communication interruption in the second register are set in a corresponding storage manner.
[0052] In the initial state, the data structure composed of the interrupt identifier is "000000000000". When the LIN communication interruption and the CAN communication interruption are stored in the second interrupt register, the data structure composed of the interrupt identifier becomes "110000010000". The PS end reads the data structure "110000010000" of the second interrupt register, and can determine that the target interrupt request is the LIN communication interruption and the CAN communication interruption. Specifically, data collection is required through the first LIN channel and the second LIN channel, and data collection is required through the fourth CNA channel. The LIN channel mentioned here refers to the data transmission channel between the PL end and the LIN bus, and the CAN channel refers to the data transmission channel between the PL end and the CAN bus. The first LIN channel refers to the data transmission channel between the first data transceiver submodule in multiple LIN data transceiver submodules and the LIN bus, and the second LIN channel refers to the data transmission channel between the second data transceiver submodule in multiple LIN data transceiver submodules and the LIN bus; and the fourth CNA channel refers to the data transmission channel between the fourth data transceiver submodule in multiple CAN data transceiver submodules and the CAN bus. Correspondingly, the PS calls the LIN communication interrupt service routine to execute the LIN communication interrupt request, and calls the CAN communication interrupt service routine to execute the CAN communication interrupt request.
[0053] See also Figure 2 , Figure 2 FIG. 1 is a block diagram of a CAN data acquisition module according to an embodiment of the present application. Figure 2As shown, the CAN data acquisition module includes a CAN data transceiver submodule CAN_FD, a CAN data interception submodule CAN_Bridge, and a CAN acquisition submodule CAN_Store. When the interrupt request is a CAN acquisition interrupt, the CAN data transceiver submodule communicates with the external CAN bus, the CAN data interception submodule CAN_Bridge intercepts data from the CAN data transceiver submodule, and transmits the intercepted acquisition data to the CAN acquisition submodule CAN_Store, the first core PS-A core controls the CAN acquisition submodule CAN_Store, and the CAN acquisition submodule CAN_Store transmits the collected data to DDR (Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory, referred to as DDR SDRAM) through the AXI interface. When the interrupt request is a CAN communication interrupt, the CAN data interception submodule CAN_Bridge transmits the communication data to the second core PS-R core under the control of the second core PS-R core. In one embodiment, the CAN data transceiver submodule can be provided with 12 CAN data transceiver units, and each CAN data transceiver unit obtains data from the CAN bus.
[0054] See also Figure 3 , Figure 3 FIG. 1 is a block diagram of a LIN data acquisition module according to an embodiment of the present application. Figure 3 As shown, the LIN data acquisition module includes: a LIN data transceiver submodule, a LIN acquisition submodule LIN_Store, and the LIN data transceiver submodule communicates with the external LIN bus. When the interrupt request is a CAN acquisition interrupt, the LIN data transceiver submodule transmits the received data to the LIN acquisition submodule LIN_Store, and the first core PS-A core controls the LIN acquisition submodule LIN_Store, and the LIN acquisition submodule LIN_Store transmits the collected data to the DDR through the AXI interface. When the interrupt request is a communication interrupt, the second core PS-R core controls the LIN data transceiver submodule to transmit the communication data to the second core PS-R core. In one embodiment, the LIN data transceiver submodule can be set with 6 LIN data transceiver units, and each LIN data transceiver unit obtains data from the LIN bus.
[0055] See also Figure 4 , Figure 4 FIG. 1 is a block diagram of an Ethernet data acquisition module according to an embodiment of the present application. Figure 4As shown, the Ethernet data acquisition module includes: an Ethernet layer 2 switching submodule L2_Search and a data acquisition submodule Eth_swh_cap. When the interrupt request is an Ethernet acquisition interrupt, the Ethernet layer 2 switching submodule L2_Search collects data from the Ethernet through layer 2 switching, and can store the collected data in the FIFO storage module for collection and storage. The data acquisition submodule Eth_swh_cap is used to store the data collected by the Ethernet layer 2 switching submodule L2_Search in the DDR of the PS end.
[0056] It should be noted that in actual applications, the data processing device provided in the above embodiment can distribute the above functions to different functional modules as needed, that is, divide the internal structure of the device into different functional modules to complete all or part of the functions described above, and this is not limited here.
[0057] An embodiment of the present application also provides a data processing method, which at least includes: generating multiple interrupt requests through the PL end, storing the multiple interrupt requests in the interrupt bits of the interrupt register according to a predetermined storage rule, and converting the first interrupt identifier of the interrupt bit storing the interrupt request into a second interrupt identifier; using the PS end to read the interrupt register in the PL end, obtaining the first interrupt identifier and the second interrupt identifier of the interrupt bit in the interrupt register, and determining the target interrupt request according to the first interrupt identifier and the second interrupt identifier.
[0058] The data processing method provided in the above embodiment and the data processing device provided in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs operations has been described in detail in the method embodiment and will not be repeated here.
[0059] An embodiment of the present application further provides a recorder, which includes a data processing device.
[0060] An embodiment of the present application also provides a data processing device, including: one or more processors; and a memory for storing one or more programs, when the one or more programs are executed by one or more processors, the memory implements the data processing method in the above embodiment.
[0061] The embodiments of the present application further provide one or more machine-readable media on which instructions are stored, which, when executed by one or more processors, enable the processors to execute the data processing method in the above embodiments.
[0062] Figure 5 The schematic diagram of the structure of a computer system suitable for implementing the memory of the embodiment of the present application is shown. It should be noted that: Figure 5The computer system of the memory shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.
[0063] like Figure 5 As shown, the computer system includes a central processing unit (CPU), which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) or the program loaded from the storage part to the random access memory (RAM), such as the method in the above embodiment. In the RAM, various programs and data required for system operation are also stored. The CPU, ROM and RAM are connected to each other through a bus. The input / output (I / O) interface is also connected to the bus.
[0064] The following components are connected to the I / O interface: an input part including a keyboard, a mouse, etc.; an output part including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage part including a hard disk, etc.; and a communication part including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication part performs communication processing via a network such as the Internet. A drive is also connected to the I / O interface as needed. Removable media, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive as needed so that a computer program read therefrom is installed into the storage part as needed.
[0065] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the data processing method implemented above. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), various functions defined in the system of the present application are executed.
[0066] The computer-readable medium shown in the embodiment of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium can include a data signal propagated in a baseband or as a part of a carrier wave, wherein a computer-readable computer program is carried. This propagated data signal can take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. A computer program contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.
[0067] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.
[0068] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.
[0069] Another aspect of the present application further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor of a computer, the computer executes the data processing method as described above. The computer-readable storage medium may be included in the memory described in the above embodiment, or may exist independently without being assembled into the memory.
[0070] Another aspect of the present application also provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the data processing method provided in each of the above embodiments.
[0071] The above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.
Claims
1. A data processing device, characterized in that: The data processing device includes a PS end and a PL end; an interrupt register is provided in the PL end, the interrupt register includes an interrupt bit for storing an interrupt request, and each interrupt bit has a first interrupt flag; The PL terminal is used to generate multiple interrupt requests, store the multiple interrupt requests in the interrupt bits of the interrupt register according to a predetermined storage rule, and transform the first interrupt flag of the interrupt bit storing the interrupt request into a second interrupt flag; The PS end is used to read the interrupt register in the PL end, obtain the first interrupt identifier and the second interrupt identifier of the interrupt bit, and determine the target interrupt request based on the first interrupt identifier and the second interrupt identifier; the PS end is also used to clear the interrupt bit after the target interrupt request is processed and convert the second interrupt identifier corresponding to the interrupt bit into the first interrupt identifier.
2. The data processing device according to claim 1, characterized in that: The PS end includes a first core and a second core, and the interrupt register includes a first interrupt register and a second interrupt register; The first kernel is used for determining a first target interrupt request according to a first interrupt flag and a second interrupt flag of an interrupt bit in a first interrupt register; The second core is used for determining a second target interrupt request according to a first interrupt flag and a second interrupt flag of an interrupt bit in a second interrupt register.
3. The data processing device according to claim 1, characterized in that: After determining the target interrupt request, the PS end executes an interrupt service program according to the target interrupt request, so as to perform data transmission through the interrupt service program.
4. The data processing device according to claim 3, characterized in that: When the target interrupt request of the PS side is a data acquisition interrupt, the interrupt service program transmits the first type of data in a first manner; when the target interrupt request is a communication interrupt, the interrupt service program transmits the second type of data in a second manner.
5. The data processing device according to claim 4, characterized in that: The first type of data is collected data, and the first method includes adding header information to the collected data; the second type of data is communication data, and the second method includes directly transmitting the communication data.
6. The data processing device according to claim 5, characterized in that: The data collection interruption includes LIN collection interruption, CAN collection interruption, and Ethernet collection interruption, and the communication interruption includes LIN communication interruption and CAN communication interruption; when the data collection interruption is a LIN collection interruption, the collection data is obtained from the LIN bus through a LIN data collection module based on a LIN communication mode; When the data acquisition interruption is a CAN acquisition interruption, the acquisition data is obtained from the CAN bus through a CAN data acquisition module based on the CAN communication mode; when the data acquisition interruption is an Ethernet acquisition interruption, the acquisition data is obtained from the Ethernet through an Ethernet data acquisition module based on the Ethernet communication mode; when the communication interruption is a LIN communication interruption, the communication data is obtained from the LIN bus; when the communication interruption is a CAN communication interruption, the communication data is obtained from the CAN bus.
7. A data processing method, characterized in that: The data processing method comprises: Generate multiple interrupt requests through the PL terminal, store the multiple interrupt requests in the interrupt bit of the interrupt register according to a predetermined storage rule, and transform the first interrupt flag of the interrupt bit storing the interrupt request into a second interrupt flag; Using the PS end to read the interrupt register in the PL end, obtain the first interrupt flag and the second interrupt flag of the interrupt bit in the interrupt register, and determine the target interrupt request according to the first interrupt flag and the second interrupt flag; After the target interrupt request is processed, the interrupt bit is cleared using the PS terminal and the second interrupt flag corresponding to the interrupt bit is converted into the first interrupt flag.
8. A recorder, characterized in that: The recorder comprises a data processing device as claimed in any one of claims 1 to 6.
9. A data processing device, characterized in that: Said include: one or more processors; and A memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the memory implements the data processing method according to claim 7.
10. A machine-readable medium, characterized in that Instructions are stored thereon, which, when executed by one or more processors, cause the processors to perform the data processing method as claimed in claim 7.