Full random test method, device and equipment of SGPIO master module, medium and product

Abstract

The invention provides a full random test method, device and equipment for an SGPIO master module, a medium and a product. A configuration object of the SGPIO master module is transmitted to an APB driving assembly, an SGPIO driving assembly and an SGPIO sampling assembly at the same time; if the APB write-in transaction is the SGPIO control register configuration transaction, analyzing parallel write-in data written by the APB to obtain configuration information; modifying a configuration object of the SGPIO master module according to the configuration information so as to enable the SGPIO driving component or the SGPIO sampling component to change a protocol mode in time; instantiating a plurality of reference models of the interrupt state in the basic test class; in the test case component, selecting a reference model by utilizing an override mechanism according to the currently verified interrupt triggering mode; by comparing the expected value of the interrupt state register with the actual value of the interrupt state register, full random verification of the interrupt state register value of the SGPIO master module can be realized. According to the scheme provided by the invention, the comprehensiveness and the effectiveness of the SGPIO master module test are improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a full random testing method, device, equipment, medium and product of an SGPIO master module. Background Art

[0002] Serial General-purpose Input / Output (SGPIO) is a communication method that serializes general-purpose input and output (IO) signals. It defines the data exchange method between the initiator device (such as a host bus adapter) and the target device (such as a backplane). SGPIO technology allows programming to configure multiple operating modes for each pin, including connection to the Advanced Peripheral Bus (APB) bus, collaboration with external TTL components, support for multiple master modules and ports, etc. The SGPIO bus can support up to 256 bits of output per master module. Each master module contains 4 ports and can be divided according to the APB clock to achieve flexible data transmission.

[0003] In the prior art, although SGPIO provides flexible configuration options, there are still limitations when performing full random testing, especially in the dynamic change of protocol mode and random testing of interrupt status records. In practical applications, it is impossible to update the test configuration in real time according to the actual configuration of the SGPIO register, resulting in the inability to meet the requirements of random testing of the SGPIO master module.

[0004] Therefore, the comprehensiveness and effectiveness of the SGPIO master module test in the prior art are relatively poor. Summary of the invention

[0005] The present invention provides a full random testing method, device, equipment, medium and product of an SGPIO master module, which are used to solve the defects of poor comprehensiveness and effectiveness of SGPIO master module testing in the prior art, realize full random testing of the SGPIOmaster module, and improve the comprehensiveness and effectiveness of the SGPIO master module testing.

[0006] The present invention provides a full random test method for an SGPIO master module, comprising: defining and instantiating a configuration object of each SGPIO master module protocol mode, and simultaneously transferring the configuration object of each SGPIO master module protocol mode to an APB driver component, an SGPIO driver component, and an SGPIO sampling component; after the APB driver component receives an APB bus write transaction generated by a sequencer, determining whether the APB bus write transaction is an SGPIO control register configuration transaction; if the APB bus write transaction is an SGPIO control register configuration transaction, parsing the parallel write data written by the APB bus to obtain configuration information; modifying the SGPIO according to the configuration information. The configuration object of the master module is used to enable the SGPIO driver component or the SGPIO sampling component to change the protocol mode in time; multiple reference models of interrupt status are instantiated in the basic test class; in the test case component, the override mechanism is used to select the reference model according to the currently verified interrupt triggering mode; the SGPIO serial port driver transaction is received twice according to the current reference model, and the expected value of the interrupt status register is calculated; the actual value of the interrupt status register is obtained by reading from the APB bus through the APB sampling component through the basic reference model, and the expected value of the interrupt status register and the actual value of the interrupt status register are compared to realize the full random verification of the interrupt status register value of the SGPIO master module.

[0007] According to a fully random test method of an SGPIO master module provided by the present invention, the configuration object of each SGPIO master module protocol mode is defined and instantiated, including: deriving an SGPIO configuration class from an object class of UVM, and defining members for configuring the protocol mode configurations of the SGPIO driver component and the SGPIO sampling component in the SGPIO configuration class; defining a handle of the SGPIO configuration class in the basic test class, the SGPIO driver component, the SGPIO sampling component and the APB driver component; and instantiating objects for configuring the protocol modes of the first SGPIO master module and the second SGPIO master module in the basic test class component to obtain a first instance and a second instance.

[0008] According to a fully random test method of an SGPIO master module provided by the present invention, the configuration object of the SGPIO master module is modified according to the configuration information so that the SGPIO driver component or the SGPIO sampling component changes the protocol mode in time, including: configuring the first instance and the second instance according to the configuration information; copying the object pointed to by the handle of the SGPIO configuration class in the task of serial port driving of the first SGPIO master module and the second SGPIO master module in the SGPIO driver component and the SGPIO sampling component; parsing the member of the object pointed to by the handle of the SGPIO configuration class, and configuring the protocol mode of this driving transaction, wherein the protocol mode of the driving transaction includes the big-endian mode between bytes and within bytes, the number of bytes to be sent, and the MCK or MLD signal flipping.

[0009] According to a fully random testing method for an SGPIO master module provided by the present invention, after the APB driver component receives an APB bus write transaction generated by a sequencer, it is determined whether the APB bus write transaction is an SGPIO control register configuration transaction, including: detecting the address of each APB bus write transaction through a task defined in the APB driver component; detecting whether the address is consistent with the control register address of the first SGPIO master module or the control register address of the second SGPIO master module, if consistent, determining that the APB bus write transaction is an SGPIO control register configuration transaction, otherwise, determining that the APB bus write transaction is not an SGPIO control register configuration transaction.

[0010] According to a fully random testing method of an SGPIO master module provided by the present invention, the method receives SGPIO serial port driver transactions twice according to the current reference model and calculates the expected value of the interrupt status register, including: obtaining the current SGPIO serial port transaction and the last SGPIO serial port transaction latched by the current reference model and sent by the SGPIO driver component to the current reference model; analyzing the current SGPIO serial port transaction and the last SGPIO serial port transaction to determine the interrupt triggering mode; determining the calculation method of the current interrupt status value according to the interrupt triggering mode; and calculating the expected value of the interrupt status register based on the current SGPIO serial port transaction and the last SGPIO serial port transaction according to the current interrupt status value calculation method.

[0011] According to a fully random test method for an SGPIO master module provided by the present invention, the multiple reference models include a high level reference model, a low level reference model, a rising edge reference model, a falling edge reference model and a double edge reference model; the multiple reference models of the interrupt state are instantiated in a basic test class, specifically including: deriving a basic reference model class in a UVM component class, and then deriving the high level reference model, the low level reference model, the rising edge reference model, the falling edge reference model and the double edge reference model from the basic reference model class, corresponding to five interrupt triggering modes of high level, low level, rising edge, falling edge and double edge respectively.

[0012] The present invention also provides a fully random test device for an SGPIO master module, comprising: a configuration module, used to define and instantiate a configuration object of each SGPIO master module protocol mode, and simultaneously transfer the configuration object of each SGPIO master module protocol mode to an APB driver component, an SGPIO driver component, and an SGPIO sampling component; a processing module, used to determine whether the APB bus write transaction is an SGPIO control register configuration transaction after the APB driver component receives the APB bus write transaction generated by a sequencer; if the APB bus write transaction is an SGPIO control register configuration transaction, then parse the parallel write data written by the APB bus to obtain configuration information; and a modification module, used to modify the SGPIO according to the configuration information. The configuration object of the master module is used to enable the SGPIO driver component or the SGPIO sampling component to change the protocol mode in time; the instantiation module is used to instantiate multiple reference models of interrupt status in the basic test class; the mode selection module is used to select the reference model in the test case component according to the currently verified interrupt triggering mode by using the override mechanism; the calculation module is used to receive the SGPIO serial port driver transaction twice according to the current reference model, and calculate the expected value of the interrupt status register; the verification module is used to receive the actual value of the interrupt status register read from the APB bus through the APB sampling component through the basic reference model, and compare the expected value of the interrupt status register with the actual value of the interrupt status register to realize the full random verification of the interrupt status register value of the SGPIO master module.

[0013] The present invention also provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, a fully random test method for the SGPIOmaster module as described above is implemented.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the fully random testing method of the SGPIO master module as described in any one of the above is implemented.

[0015] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned fully random testing methods for the SGPIO master module.

[0016] The fully random test method, device, equipment, medium and product of the SGPIO master module provided by the present invention define and instantiate the configuration object of each SGPIO master module protocol mode, and simultaneously transfer the configuration object of each SGPIO master module protocol mode to the APB driver component, the SGPIO driver component and the SGPIO sampling component; after the APB driver component receives the APB bus write transaction generated by the sequencer, if the APB bus write transaction is an SGPIO control register configuration transaction, the parallel write data written by the APB bus is parsed to obtain configuration information; the configuration object of the SGPIOmaster module is modified according to the configuration information, so that the SGPIO driver component or the SGPIO sampling component can change the protocol mode in time, so as to complete the SGPIO Verification of complex scenarios in which the configuration of the master module is randomly changed multiple times during the process of receiving or sending data; Instantiating multiple reference models of interrupt status in the basic test class; In the test case component, according to the currently verified interrupt triggering mode, the override mechanism is used to select the reference model; According to the current reference model, the SGPIO serial port driver transaction is received twice, and the expected value of the interrupt status register is calculated; The actual value of the interrupt status register is obtained by reading the interrupt status register from the APB bus through the APB sampling component through the basic reference model, and the expected value of the interrupt status register and the actual value of the interrupt status register are compared, so as to realize the full random verification of the interrupt status register value of the SGPIO master module. The scheme of the present invention can realize the verification of complex scenarios in which the configuration of the SGPIO master module is randomly changed multiple times during the process of receiving or sending data, the interrupt status records of different interrupt triggering modes, and the full random verification of the interrupt status register value of the SGPIO master module, thereby improving the comprehensiveness and effectiveness of the SGPIO master module test. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a schematic diagram of the overview of the SGPIO bus provided by the present invention.

[0019] Figure 2 It is a schematic diagram of the UVM-based SGPIO verification environment framework provided by the present invention.

[0020] Figure 3 It is a flow chart of the fully random testing method of the SGPIO master module provided by the present invention.

[0021] Figure 4 It is a flow chart of establishing a fully random test verification environment for multiple protocol mode changes of the SGPIO master module provided by the present invention.

[0022] Figure 5 It is a schematic diagram of establishing an SGPIO interrupt status register value verification environment provided by the present invention.

[0023] Figure 6 It is a structural schematic diagram of a fully random testing device for an SGPIO master module provided by the present invention.

[0024] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] The term "Serial General Purpose Input / Output (SGPIO)" used in the embodiments of the present application is a communication method for serializing general purpose input and output (IO) signals, which defines the data exchange method between the initiating device (such as a host bus adapter) and the target device (such as a backplane). The target device converts the output signal to a number of parallel LED signals and provides an input signal to the general purpose input signal line. The initiating device and the target device can be composed of one or more chips. If multiple chips are used, the signals of the driving bus should be arranged to meet this standard.

[0027] Figure 1 The schematic diagram of the SGPIO bus provided by the present invention is shown below. Figure 1 The working principle of the SGPIO bus is described. Figure 1 As shown in the figure, initiator is the initiator device (or master device), target is the target device (or slave device), SGPIOMCK (SGPIO Master Clock) is the SGPIO master clock signal, SGPIOMLD (SGPIO Master LatchData) is the master data loading signal, SGPIOMO (SGPIO Master Output) is the master output signal, and SGPIOMI (SGPIOMaster Input) is the master input signal.

[0028] In actual applications, the main functions of the initiator in the SGPIO bus include: data transmission control, protocol definition, signal generation, address and command issuance, error detection and processing, interrupt management, communication startup, data flow control, system synchronization, and configuration and status management. The main functions of the target in the SGPIO bus include: data reception and transmission, signal response, address recognition, data buffering, command execution, error reporting, interrupt generation, flow control response, and synchronization operation.

[0029] Specifically, SGPIOMCK is used to synchronize data transmission and ensure that data is correctly synchronized between the sender and the receiver. SGPIOMLD is used to indicate the timing of loading data into the shift register or to trigger the sampling of data during data transmission. SGPIOMO represents the data signal sent from the SGPIO master module and is used to send data to the target. SGPIOMI represents the data signal from the target received by the SGPIO master module.

[0030] like Figure 1As shown, each SGPIO pin can be programmed to implement the following functions: directly connect to the APB bus; work with external serial TTL components (74LV165 / 74LV595); support two masters, each with up to 256-bit output, and each master contains 4 ports; the shift clock comes from the APB clock pclk, divided by a programmable value; support interrupt options for each input and output port; support interrupt sensitivity options, including high level, low level, rising edge, falling edge and dual edge; support WDT (Watchdog Timer) reset.

[0031] Figure 2 This is a schematic diagram of the SGPIO verification environment framework based on UVM provided by the present invention. Figure 2 Describe the various components in the UVM SGPIO verification environment framework.

[0032] like Figure 2 As shown in the figure, the SGPIO verification environment framework of UVM (Universal Verification Methodology) includes apb_agt (apb agent), sgpio_mst1_agt (first sgpio master module agent), sgpio_mst2_agt (second sgpio master module agent), virtual sequencer (virtual sequence generator), refmod (reference model), scb (SystemC Bus), apb_intf (apb interface), sgpio_mst1_intf (first sgpio master module interface), sgpio_mst2_intf (first sgpio master module interface) and dut (Device Under Test).

[0033] like Figure 2 As shown, apb_agt, sgpio_mst2_agt and sgpio_mst1_agt all include sqr (sequencer) components, mon (Monitor) components and drv (Driver) components.

[0034] Specifically, apb_agt is used to drive and sample the apb3.0 interface. The drv in apb_agt can convert the transaction-level signal generated by sqr into a bus pin-level signal; mon can package the sampled signal into a transaction-level signal according to the apb bus protocol and send it to scb for data comparison.

[0035] Specifically, sgpio_mst1_agt is used to drive and sample the sgpio mst1 serial port. Among them, drv and mon are configurable components, which can be configured according to the sgpio protocol mode, such as endianness within bytes, endianness between bytes, ld signal mode, number of bytes sent, etc. sgpio_mst2_agt is the same as sgpio_mst1_agt, and is used to drive and sample the sgpio mst2 serial port.

[0036] Specifically, the virtual sequencer is used to coordinate the generation of transactions by apb sqr, sgpio mst1 sqr, and sgpio mst2sqr. Its internally defined handle points to the sqr that actually generates the transaction.

[0037] Specifically, Ref MOD is used to generate expected data at the behavioral level, that is, based on the data collected by the SGPIO MI serial port, the expected value of the interrupt status register is given, and then sent to the SCB for comparison with the actual value of the interrupt status register read by the APB bus.

[0038] In practical applications, the full random test of the SGPIO master module includes two aspects: the full random test of the SGPIO master module receiving and sending protocol mode and the random test of the SGPIO interrupt status record.

[0039] Specifically, for the full random test of the SGPIO master module receiving and sending protocol mode, the SGPIO master module supports changing the protocol mode during the serial port data sending or receiving process, including clk inverse (clock signal inversion), ld inverse (load signal inversion), the number of bytes sent or received, the big-endian mode of the sent or received data, and the MCK signal division coefficient. The configuration process of the above modes all needs to write data to SGPIO_CONTRAL_REGISTER (sgpio control register) through the apb interface. In the actual verification process, the driver component (drv) and sampling component (mon) in sgpio_mst1_agt and sgpio_mst2_agt must also respond in real time according to the protocol mode configured by the apb bus, so that they can be driven and sampled in time according to the protocol mode configured by the SGPIO master module. In the standard UVM verification environment, this process usually requires deriving a config item in the object base class, which contains configuration members for the driver component and sampling component of the SGPIO master module. Then, instantiate config in the case component, modify its properties according to the test points of this test case, and then use the config_db mechanism to pass the config object to the driver component and sampling component of the SGPIOmaster module. The problem with this method is that it cannot change the config properties in real time according to the actual configuration of the sgpio register, so it cannot meet the test requirements of fully randomizing the configuration mode of the SGPIO master module multiple times.

[0040] Specifically, for the random test of SGPIO interrupt status record, the first SGPIO master module (sgpiomst1) and the second SGPIO master module (sgpio mst2) each have 8 interrupt status registers, corresponding to each bit of the serial port data receiving register, and each bit is independent of each other. The SGPIO master module can implement different interrupt triggering modes by configuring the INT_SEN register, including falling edge, rising edge, low level trigger, high level trigger and double edge trigger. The interrupt status register can record the interrupt status according to the serial port data received twice and the interrupt triggering mode configured by INT_SEN. During the random test of interrupt status record, the verification environment needs to give the expected status value of each register and compare it with the value read from the apb bus.

[0041] It can be seen that the prior art cannot meet the requirements of randomized testing of the SGPIO master module. Therefore, the comprehensiveness and effectiveness of the SGPIO master module testing in the prior art are relatively poor.

[0042] The following specific embodiments are used to describe in detail the technical solution of the present application and how the technical solution of the present application solves the above technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. Figure 1-Figure 5 The full random testing method of the SGPIO master module of the present invention is described.

[0043] In practical applications, the execution subject of the full random test method of the SGPIO master module can be a full random test device of the SGPIO master module. There are many ways to implement the full random test device of the SGPIO master module, for example, it can be implemented by a computer program, such as application software, etc.; or, for example, a chip, etc. It can also be implemented as a medium storing relevant computer programs, such as a U disk, a cloud disk, etc.; or, it can also be implemented by a physical device integrated or installed with relevant computer programs, such as a server, etc.

[0044] Figure 3 FIG. 1 is a flow chart of a fully random testing method for an SGPIO master module provided by the present invention, such as Figure 3 As shown, the method includes the following steps 301 to 309.

[0045] Step 301: Define and instantiate a configuration object for each SGPIO master module protocol mode.

[0046] As an example, in one implementation, the above step 301 includes: Derive the SGPIO configuration class from the UVM object class, and define members for configuring the SGPIO driver component and the SGPIO sampling component protocol mode configuration in the SGPIO configuration class; Define the handle of the SGPIO configuration class in the basic test class, SGPIO driver component, SGPIO sampling component and APB driver component; Instantiate and configure the objects of the first SGPIO master module and the second SGPIO master module protocol mode in the basic test class component to obtain the first instance and the second instance.

[0047] The UVM object class is recorded as uvm_object class, and the SGPIO configuration class is recorded as sgpio_config. The SGPIO driver component is the sgpio_driver component, which is used to drive the serial port of the SGPIO master module. The SGPIO sampling component is the sgpio_monitor component, which is used to sample the serial port of the SGPIO master module.

[0048] Specifically, derive sgpio_config in uvm_object, and define members of the protocol mode configuration of the sgpio_driver component and the sgpio_monitor component in sgpio_config, including the endian and endian modes tm for sending data between bytes and within bytes; the endian and endian modes rm for receiving data between bytes and within bytes; the number of bytes sent and received, nb; the serial port MLD signal inversion configuration ld_inv and the serial port clock signal MCK signal inversion configuration clk_inv.

[0049] The basic test class is recorded as base_test, and the APB driver component is recorded as apb_driver. Further, a handle of the sgpio_config type is defined in the base_test, sgpio_driver component, sgpio_monitor component, and apb_driver component. In the bast_test component, the object of configuring the protocol mode of the first SGPIO master module and the second SGPIOmaster module is instantiated to obtain the first instance cfg1 and the second instance cfg2.

[0050] Step 302: Transfer the configuration object of each SGPIO master module protocol mode to the APB driver component, the SGPIO driver component and the SGPIO sampling component simultaneously.

[0051] In combination with the above description, by defining and instantiating the configuration object of each SGPIO master module protocol mode, an instance cfg1 and a second instance cfg2 can be obtained. Specifically, the first instance cfg1 and the second instance cfg2 are transferred to the sgpio_driver component, the sgpio_monitor component and the apb_driver using the config_db mechanism.

[0052] Step 303: After the APB driver component receives the APB bus write transaction generated by the sequencer, it determines whether the APB bus write transaction is an SGPIO control register configuration transaction.

[0053] In a possible implementation, the above step 303 includes: After the APB driver component receives the APB bus write transaction generated by the sequencer, the address of each APB bus write transaction is detected through the task defined in the APB driver component; Check whether the address is consistent with the control register address of the first SGPIO master module or the control register address of the second SGPIO master module. If consistent, determine that the APB bus write transaction is an SGPIO control register configuration transaction; otherwise, determine that the APB bus write transaction is not an SGPIO control register configuration transaction.

[0054] In actual applications, a task is defined in the apb_driver component to detect the address of each transaction that writes data to the APB bus.

[0055] Specifically, after the apb_driver component receives the APB bus write transaction generated by the sequencer, the address of the transaction of writing data to the APB bus is detected by defining a task task in the apb_driver component. Further, if the address is consistent with the control register address of the first SGPIO master module or the control register address of the second SGPIO master module, the APB bus write transaction is determined to be an SGPIO control register configuration transaction, otherwise, the APB bus write transaction is determined not to be an SGPIO control register configuration transaction.

[0056] Step 304: If the APB bus write transaction is an SGPIO control register configuration transaction, parse the parallel write data written by the APB bus to obtain configuration information.

[0057] Further, if it is determined that the APB bus write transaction is an SGPIO control register configuration transaction, the parallel write data pwdata written by the APB bus is parsed to obtain the configuration information.

[0058] Step 305: modify the configuration object of the SGPIO master module according to the configuration information, so that the SGPIO driver component or the SGPIO sampling component changes the protocol mode in time.

[0059] In a possible implementation, the above step 305 includes: Configure the first instance and the second instance according to the configuration information; In the SGPIO driver component and the SGPIO sampling component, in the task of driving the serial ports of the first SGPIO master module and the second SGPIOmaster module, copy the object pointed to by the handle of the configuration object; Parse the members of the object pointed to by the handle of the SGPIO configuration class and configure the protocol mode of this driver transaction. The protocol mode of the driver transaction includes the big-endian mode, the number of bytes sent, and the MCK or MLD signal flip.

[0060] In combination with the above description, the configuration information is obtained by parsing the parallel write data pwdata written by the APB bus. Further, based on the configuration information, the configuration of the first instance cfg1 and the second instance cfg2 is implemented.

[0061] Specifically, in sgpio_driver and sgpio_monitor, the object pointed to by the Configuration Object (cfg) handle is copied in the task of the serial port driver of the first SGPIO master module and the second SGPIO master module. The purpose of this operation is to avoid changing the configuration of the drive mode during the serial port driving or sampling process. Then, the members of the object pointed to by the cfg handle are parsed to configure the protocol mode of this drive transaction, including the big-endian mode between bytes and within bytes, the number of bytes sent, and the MCK or MLD signal flipping.

[0062] Figure 4 FIG. 1 is a flow chart of setting up a fully random test verification environment for the SGPIO master module to change the protocol mode multiple times provided by the present invention, such as Figure 4 As shown in the figure, the members of the protocol mode configuration of the SGPIO driver component and the SGPIO sampling component are defined in sgpio_config. In base_test, cfg1 and cfg2 are instantiated, and cfg1 and cfg2 are passed to the apb driver component, the sgpio driver component, and the sampling component. The apb driver parses the bus write transaction and modifies the cfg member according to the address information. The sgpio_driver driver task copies and parses cfg, and sgpio_driver drives the serial port in different protocol modes based on the cfg information. The sgpio_monitor sampling task copies and parses cfg, and sgpio_monitor samples in different protocol modes based on the cfg information.

[0063] It can be understood that steps 301 to 305 are steps for setting up a fully random verification environment in which the SGPIO master module simultaneously sends and receives data and changes the protocol mode multiple times. The present invention improves on the traditional UVM verification framework and simultaneously passes the config object to the apb driver component, the sgpio driver component and the sampling component. After the apb driver receives the total write transaction generated by the sequencer, it first performs address resolution. If the transaction is an SGPIO_CONTROL_REGISTER register configuration transaction, it parses the pwdata signal and modifies the config object according to the configuration information, so that the sgpio serial port driver or sampling component can change the protocol mode in time, thereby completing the verification of the complex scenario in which the configuration is randomly changed multiple times during the sgpio module receiving or sending data.

[0064] Step 306: Instantiate multiple reference models of interrupt status in the basic test class.

[0065] As an example, the above-mentioned multiple reference models include a high level reference model, a low level reference model, a rising edge reference model, a falling edge reference model and a double edge reference model. Specifically, step 306 specifically includes: The basic reference model class is derived from the UVM component class, and then the high level reference model, low level reference model, rising edge reference model, falling edge reference model and double edge reference model are derived from the basic reference model class, corresponding to the five interrupt trigger modes of high level, low level, rising edge, falling edge and double edge respectively.

[0066] Specifically, Figure 5 Schematic diagram of the SGPIO interrupt status register value verification environment provided by the present invention, such as Figure 5 As shown, in the UVM component class uvm_component, it is derived from the basic reference model class base_reference_model, and then the high level reference model reference_model_h, low level reference model referenct_model_l, rising edge reference model refenence_model_r, falling edge reference model reference_model_f and double edge reference model reference_model_d are derived from base_reference_model. These five models correspond to the five interrupt triggering modes of high level, low level, rising edge, falling edge and double edge respectively.

[0067] Step 307: In the test case component, the reference model is selected using the override mechanism according to the currently verified interrupt triggering mode.

[0068] It is understandable that the overried mechanism is used in the test case component to replace the interrupt triggering method required for selecting this test case, so as to complete the random test of the interrupt status record.

[0069] Step 308: Receive SGPIO serial port driver transactions twice according to the current reference model, and calculate the expected value of the interrupt status register.

[0070] In a possible implementation, the above step 308 includes: Obtain the current SGPIO serial port transaction and the last SGPIO serial port transaction latched by the current reference model and sent by the SGPIO driver component to the current reference model; Analyze the current SGPIO serial port transaction and the previous SGPIO serial port transaction to determine the interrupt triggering mode; According to the interrupt triggering mode, determine the calculation method of the current interrupt status value; According to the current interrupt status value calculation method, the expected value of the interrupt status register is calculated based on the current SGPIO serial port transaction and the last SGPIO serial port transaction.

[0071] In practical applications, the reference model has a latching function. Specifically, after the reference model receives the SGPIO serial port transaction sent by the SGPIO driver component, it latches the received SGPIO serial port transaction. On this basis, the current SGPIO serial port transaction and the last SGPIO serial port transaction sent by the SGPIO driver component to the current reference model latched by the current reference model can be obtained.

[0072] In practical applications, in each reference model, different calculation methods are defined for interrupt status values ​​of different triggering modes. Specifically, after obtaining the current SGPIO serial port transaction and the last SGPIO serial port transaction, the changes between the two transactions are analyzed to determine whether an event that satisfies the interrupt triggering condition has occurred, thereby determining the interrupt triggering mode. After determining the interrupt triggering mode, determine the calculation method of the interrupt status value corresponding to the interrupt triggering mode under the current reference model, and use it as the calculation method of the current interrupt status value. Furthermore, according to the current interrupt status value calculation method, the expected value of the interrupt status register is calculated based on the current SGPIO serial port transaction and the last SGPIO serial port transaction.

[0073] Step 309: receive the actual value of the interrupt status register read from the APB bus through the APB sampling component through the basic reference model, and compare the expected value of the interrupt status register with the actual value of the interrupt status register to achieve full random verification of the interrupt status register value of the SGPIOmaster module.

[0074] Combination Figure 5 , the actual value of the interrupt status register is obtained by receiving the base reference model base_reference_model from the APB bus through apb_monitor, and the expected value of the interrupt status register is compared with the actual value of the interrupt status register to achieve full random verification of the interrupt status register value of the SGPIO master module.

[0075] Specifically, the expected value of the interrupt status register is consistent with the actual value of the interrupt status register, indicating that the interrupt status register behavior of the SGPIOmaster module is as expected. If there is a difference between the expected value of the interrupt status register and the actual value of the interrupt status register, the cause needs to be analyzed. It may be a problem with the implementation of the SGPIO master module, or a problem with the test vector, reference model, or monitor implementation.

[0076] In addition, in a possible implementation manner, the above-mentioned full random test method of the SGPIO master module further includes: generating a full random test report of the SGPIO master module, and analyzing the full random test coverage of the SGPIO master module and the problems found.

[0077] In this implementation, a full random test report of the SGPIO master module is generated, and the full random test coverage and problems found of the SGPIO master module are analyzed, thereby improving the accuracy and reliability of the full random test of the SGPIO master module.

[0078] In the fully random test method of the SGPIO master module provided in this embodiment, the configuration object of each SGPIO master module protocol mode is defined and instantiated, and the configuration object of each SGPIO master module protocol mode is simultaneously passed to the APB driver component, the SGPIO driver component and the SGPIO sampling component; after the APB driver component receives the APB bus write transaction generated by the sequencer, if the APB bus write transaction is an SGPIO control register configuration transaction, the parallel write data written by the APB bus is parsed to obtain the configuration information; the SGPIO is modified according to the configuration information The configuration object of the master module is used to enable the SGPIO driver component or the SGPIO sampling component to change the protocol mode in time, so as to complete the verification of complex scenarios in which the SGPIOmaster module randomly changes the configuration multiple times during the process of receiving or sending data; multiple reference models of interrupt status are instantiated in the basic test class; in the test case component, the override mechanism is used to select the reference model according to the currently verified interrupt triggering mode; the SGPIO serial port driver transaction is received twice according to the current reference model, and the expected value of the interrupt status register is calculated; the actual value of the interrupt status register is obtained by reading the interrupt status register from the APB bus through the APB sampling component through the basic reference model, and the expected value of the interrupt status register and the actual value of the interrupt status register are compared, so as to realize the full random verification of the interrupt status register value of the SGPIO master module. The scheme of this embodiment can realize the verification of complex scenarios in which the SGPIOmaster module randomly changes the configuration multiple times during the process of receiving or sending data, the interrupt status record of different interrupt triggering modes, and the full random verification of the interrupt status register value of the SGPIO master module, thereby improving the comprehensiveness and effectiveness of the SGPIO master module test.

[0079] The fully random testing device of the SGPIO master module provided by the present invention is described below. The fully random testing device of the SGPIO master module described below and the fully random testing method of the SGPIO master module described above can be referred to each other.

[0080] Figure 6 FIG. 4 is a schematic diagram of the structure of the fully random test device for the SGPIO master module provided by the present invention. Figure 6 As shown, the fully random testing device of the SGPIO master module includes: a configuration module 61 , a processing module 62 , a modification module 63 , an instantiation module 64 , a mode selection module 65 , a calculation module 66 and a verification module 67 .

[0081] The configuration module 61 is used to define and instantiate the configuration object of each SGPIO master module protocol mode, and transmit the configuration object of each SGPIO master module protocol mode to the APB driver component, the SGPIO driver component and the SGPIO sampling component at the same time.

[0082] As an example, in one implementation, the configuration module 61 is used to define and instantiate the configuration object of each SGPIOmaster module protocol mode, specifically for: Derive the SGPIO configuration class from the UVM object class, and define members for configuring the SGPIO driver component and the SGPIO sampling component protocol mode configuration in the SGPIO configuration class; Define the handle of the SGPIO configuration class in the basic test class, SGPIO driver component, SGPIO sampling component and APB driver component; Instantiate and configure the objects of the first SGPIO master module and the second SGPIO master module protocol mode in the basic test class component to obtain the first instance and the second instance.

[0083] The UVM object class is recorded as uvm_object class, and the SGPIO configuration class is recorded as sgpio_config. The SGPIO driver component is the sgpio_driver component, which is used to drive the serial port of the SGPIO master module. The SGPIO sampling component is the sgpio_monitor component, which is used to sample the serial port of the SGPIO master module.

[0084] Specifically, derive sgpio_config in uvm_object, and define members of the protocol mode configuration of the sgpio_driver component and the sgpio_monitor component in sgpio_config, including the endian and endian modes tm for sending data between bytes and within bytes; the endian and endian modes rm for receiving data between bytes and within bytes; the number of bytes sent and received, nb; the serial port MLD signal inversion configuration ld_inv and the serial port clock signal MCK signal inversion configuration clk_inv.

[0085] The basic test class is recorded as base_test, and the APB driver component is recorded as apb_driver. Further, a handle of the sgpio_config type is defined in the base_test, sgpio_driver component, sgpio_monitor component, and apb_driver component. In the bast_test component, the object of configuring the protocol mode of the first SGPIO master module and the second SGPIOmaster module is instantiated to obtain the first instance cfg1 and the second instance cfg2.

[0086] In combination with the above description, the configuration module 61 can obtain an instance cfg1 and a second instance cfg2 by defining and instantiating the configuration object of each SGPIO master module protocol mode. Specifically, the configuration module 61 transfers the first instance cfg1 and the second instance cfg2 to the sgpio_driver component, the sgpio_monitor component and the apb_driver using the config_db mechanism.

[0087] The processing module 62 is used to determine whether the APB bus write transaction is an SGPIO control register configuration transaction after the APB driver component receives the APB bus write transaction generated by the sequencer; if the APB bus write transaction is an SGPIO control register configuration transaction, parse the parallel write data written by the APB bus to obtain configuration information.

[0088] In a possible implementation manner, the processing module 62 is used to determine whether the APB bus write transaction is an SGPIO control register configuration transaction after the APB driver component receives the APB bus write transaction generated by the sequencer, specifically to: Through the tasks defined in the APB driver component, the address of each transaction written to the APB bus is detected; Check whether the address is consistent with the control register address of the first SGPIO master module or the control register address of the second SGPIO master module. If consistent, determine that the APB bus write transaction is an SGPIO control register configuration transaction; otherwise, determine that the APB bus write transaction is not an SGPIO control register configuration transaction.

[0089] In actual applications, a task is defined in the apb_driver component to detect the address of each transaction that writes data to the APB bus.

[0090] Specifically, after the apb_driver component receives the APB bus write transaction generated by the sequencer, the processing module 62 detects the address of the APB bus write data transaction by defining the task task in the apb_driver component. Further, if the address is consistent with the control register address of the first SGPIO master module or the control register address of the second SGPIO master module, the processing module 62 determines that the APB bus write transaction is an SGPIO control register configuration transaction, otherwise, the processing module 62 determines that the APB bus write transaction is not an SGPIO control register configuration transaction.

[0091] Further, if the processing module 62 determines that the APB bus write transaction is an SGPIO control register configuration transaction, the processing module 62 parses the parallel write data pwdata written by the APB bus to obtain the configuration information.

[0092] The modification module 63 is used to modify the configuration object of the SGPIO master module according to the configuration information, so that the SGPIO driver component or the SGPIO sampling component can change the protocol mode in time.

[0093] In a possible implementation manner, the modification module 63 is specifically used to: Configure the first instance and the second instance according to the configuration information; In the SGPIO driver component and the SGPIO sampling component, in the task of driving the serial ports of the first SGPIO master module and the second SGPIOmaster module, copy the object pointed to by the handle of the configuration object; Parse the members of the object pointed to by the handle of the SGPIO configuration class and configure the protocol mode of this driver transaction. The protocol mode of the driver transaction includes the big-endian mode, the number of bytes sent, and the MCK or MLD signal flip.

[0094] In combination with the above description, the configuration information is obtained by parsing the parallel write data pwdata written by the APB bus. Further, based on the configuration information, the configuration of the first instance cfg1 and the second instance cfg2 is implemented.

[0095] Specifically, in sgpio_driver and sgpio_monitor, the object pointed to by the Configuration Object (cfg) handle is copied in the task of the serial port driver of the first SGPIO master module and the second SGPIO master module. The purpose of this operation is to avoid changing the configuration of the drive mode during the serial port driving or sampling process. Then, the members of the object pointed to by the cfg handle are parsed to configure the protocol mode of this drive transaction, including the big-endian mode between bytes and within bytes, the number of bytes sent, and the MCK or MLD signal flipping.

[0096] It is understandable that the present invention improves on the traditional UVM verification framework, and passes the config object to the apb driver component, the sgpio driver component and the sampling component at the same time. After the apb driver receives the total write transaction generated by the sequencer, it first performs address resolution. If the transaction is a SGPIO_CONTROL_REGISTER register configuration transaction, it parses the pwdata signal and modifies the config object according to the configuration information, so that the sgpio serial port driver or sampling component can change the protocol mode in time, thereby completing the verification of complex scenarios in which the configuration is randomly changed multiple times during the process of receiving or sending data by the sgpio module.

[0097] The instantiation module 64 is used to instantiate various reference models of interruption states in the basic test class.

[0098] As an example, the above-mentioned multiple reference models include a high level reference model, a low level reference model, a rising edge reference model, a falling edge reference model and a double edge reference model. Specifically, the instantiation module 64 is specifically used to: The basic reference model class is derived from the UVM component class, and then the high level reference model, low level reference model, rising edge reference model, falling edge reference model and double edge reference model are derived from the basic reference model class, corresponding to the five interrupt trigger modes of high level, low level, rising edge, falling edge and double edge respectively.

[0099] Specific, combined Figure 5The instantiation module 64 is derived from the basic reference model class base_reference_model in the UVM component class uvm_component, and then the high level reference model reference_model_h, the low level reference model referenct_model_l, the rising edge reference model refenence_model_r, the falling edge reference model reference_model_f and the double edge reference model reference_model_d are derived from the base_reference_model. These five models correspond to the five interrupt triggering modes of high level, low level, rising edge, falling edge and double edge respectively.

[0100] The mode selection module 65 is used to select the reference model in the test case component according to the currently verified interrupt trigger mode by using the override mechanism.

[0101] It is understandable that the mode selection module 65 utilizes the overried mechanism in the test case component to replace the interrupt trigger mode required for selecting the current test case, thereby completing the random test of the interrupt status record.

[0102] The calculation module 66 is used to receive SGPIO serial port driver transactions twice according to the current reference model, and calculate the expected value of the interrupt status register.

[0103] In a possible implementation manner, the calculation module 66 is specifically configured to: Obtain the current SGPIO serial port transaction and the last SGPIO serial port transaction latched by the current reference model and sent by the SGPIO driver component to the current reference model; Analyze the current SGPIO serial port transaction and the previous SGPIO serial port transaction to determine the interrupt triggering mode; According to the interrupt triggering mode, determine the calculation method of the current interrupt status value; According to the current interrupt status value calculation method, the expected value of the interrupt status register is calculated based on the current SGPIO serial port transaction and the last SGPIO serial port transaction.

[0104] In practical applications, the reference model has a latching function. Specifically, after the reference model receives the SGPIO serial port transaction sent by the SGPIO driver component, it latches the received SGPIO serial port transaction. On this basis, the calculation module 66 can obtain the current SGPIO serial port transaction and the last SGPIO serial port transaction latched by the current reference model and sent by the SGPIO driver component to the current reference model.

[0105] In practical applications, in each reference model, different calculation methods are defined for interrupt status values ​​of different triggering modes. Specifically, after obtaining the current SGPIO serial port transaction and the last SGPIO serial port transaction, the calculation module 66 analyzes the changes between the two transactions to determine whether an event that satisfies the interrupt triggering condition occurs, thereby determining the interrupt triggering mode. After determining the interrupt triggering mode, the calculation module 66 determines the calculation method of the interrupt status value corresponding to the interrupt triggering mode under the current reference model, and uses it as the calculation method of the current interrupt status value. Further, the calculation module 66 calculates the expected value of the interrupt status register based on the current SGPIO serial port transaction and the last SGPIO serial port transaction according to the current interrupt status value calculation method.

[0106] The verification module 67 is used to receive the actual value of the interrupt status register read from the APB bus through the APB sampling component through the basic reference model, and compare the expected value of the interrupt status register with the actual value of the interrupt status register to achieve full random verification of the interrupt status register value of the SGPIO master module.

[0107] Combination Figure 5 The verification module 67 receives the actual value of the interrupt status register read from the APB bus through the basic reference model base_reference_model through apb_monitor, and compares the expected value of the interrupt status register with the actual value of the interrupt status register to achieve full random verification of the interrupt status register value of the SGPIO master module.

[0108] Specifically, the expected value of the interrupt status register is consistent with the actual value of the interrupt status register, indicating that the interrupt status register behavior of the SGPIOmaster module is as expected. If there is a difference between the expected value of the interrupt status register and the actual value of the interrupt status register, the cause needs to be analyzed. It may be a problem with the implementation of the SGPIO master module, or a problem with the test vector, reference model, or monitor implementation.

[0109] In addition, in a possible implementation, the full random test device of the SGPIO master module further includes: a report generation module, which is used to generate a full random test report of the SGPIO master module and analyze the full random test coverage and problems found of the SGPIO master module.

[0110] In this implementation, a full random test report of the SGPIO master module is generated, and the full random test coverage and problems found of the SGPIO master module are analyzed, thereby improving the accuracy and reliability of the full random test of the SGPIO master module.

[0111] The fully random test device for the SGPIO master module provided in this embodiment comprises a configuration module that defines and instantiates a configuration object of each SGPIO master module protocol mode, and simultaneously transmits the configuration object of each SGPIO master module protocol mode to the APB driver component, the SGPIO driver component and the SGPIO sampling component; after the APB driver component receives the APB bus write transaction generated by the sequencer, if the APB bus write transaction is an SGPIO control register configuration transaction, the processing module parses the parallel write data written by the APB bus to obtain configuration information; and the modification module modifies the configuration object of the SGPIO master module according to the configuration information, so that the SGPIO driver component or the SGPIO sampling component can change the protocol mode in time, so as to complete the SGPIO Verification of complex scenarios in which the configuration is randomly changed multiple times during the master module receiving or sending data; the instantiation module instantiates multiple reference models of the interrupt status in the basic test class; the mode selection module uses the override mechanism in the test case component to select the reference model according to the currently verified interrupt triggering method; the calculation module receives the SGPIO serial port driver transaction twice according to the current reference model, and calculates the expected value of the interrupt status register; the verification module receives the actual value of the interrupt status register from the APB bus through the APB sampling component through the basic reference model, and compares the expected value of the interrupt status register with the actual value of the interrupt status register, which can realize the full random verification of the interrupt status register value of the SGPIO master module. The solution of this embodiment can realize the verification of complex scenarios in which the configuration is randomly changed multiple times during the SGPIO master module receiving or sending data, the interrupt status records of different interrupt triggering methods, and the full random verification of the interrupt status register value of the SGPIO master module, thereby improving the comprehensiveness and effectiveness of the SGPIO master module test.

[0112] Figure 7 is a schematic diagram of the structure of the electronic device provided by the present invention, such as Figure 7As shown, the electronic device may include: a processor 710, a communication interface 720, a memory 730 and a communication bus 740, wherein the processor 710, the communication interface 720 and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute the full random test method of the SGPIO master module, the method comprising: defining and instantiating the configuration object of each SGPIO master module protocol mode, and simultaneously passing the configuration object of each SGPIO master module protocol mode to the APB driver component, the SGPIO driver component and the SGPIO sampling component; after the APB driver component receives the APB bus write transaction generated by the sequencer, it determines whether the APB bus write transaction is an SGPIO control register configuration transaction; if the APB bus write transaction is an SGPIO control register configuration transaction, the parallel write data written by the APB bus is parsed to obtain configuration information; modify the SGPIO according to the configuration information The configuration object of the master module is used to enable the SGPIO driver component or the SGPIO sampling component to change the protocol mode in time; multiple reference models of interrupt status are instantiated in the basic test class; in the test case component, the override mechanism is used to select the reference model according to the currently verified interrupt triggering method; the SGPIO serial port driver transaction is received twice according to the current reference model, and the expected value of the interrupt status register is calculated; the actual value of the interrupt status register is obtained by reading from the APB bus through the APB sampling component through the basic reference model, and the expected value of the interrupt status register and the actual value of the interrupt status register are compared to realize the full random verification of the interrupt status register value of the SGPIO master module.

[0113] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0114] On the other hand, the present invention also provides a computer program product, the computer program product includes a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the full random test method of the SGPIO master module provided by the above methods, the method includes: defining and instantiating the configuration object of each SGPIO master module protocol mode, and simultaneously passing the configuration object of each SGPIO master module protocol mode to the APB driver component, the SGPIO driver component and the SGPIO sampling component; after the APB driver component receives the APB bus write transaction generated by the sequencer, determining whether the APB bus write transaction is an SGPIO control register configuration transaction; if the APB bus write transaction is an SGPIO control register configuration transaction, parsing the parallel write data written by the APB bus to obtain configuration information; modifying the SGPIO according to the configuration information The configuration object of the master module is used to enable the SGPIO driver component or the SGPIO sampling component to change the protocol mode in time; multiple reference models of interrupt status are instantiated in the basic test class; in the test case component, the override mechanism is used to select the reference model according to the currently verified interrupt triggering method; the SGPIO serial port driver transaction is received twice according to the current reference model, and the expected value of the interrupt status register is calculated; the actual value of the interrupt status register is obtained by reading from the APB bus through the APB sampling component through the basic reference model, and the expected value of the interrupt status register and the actual value of the interrupt status register are compared to realize the full random verification of the interrupt status register value of the SGPIOmaster module.

[0115] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to perform the fully random test method of the SGPIO master module provided by the above methods, the method comprising: defining and instantiating a configuration object of each SGPIO master module protocol mode, and The configuration object of the master module protocol mode is simultaneously passed to the APB driver component, the SGPIO driver component and the SGPIO sampling component; after the APB driver component receives the APB bus write transaction generated by the sequencer, it determines whether the APB bus write transaction is an SGPIO control register configuration transaction; if the APB bus write transaction is an SGPIO control register configuration transaction, the parallel write data written by the APB bus is parsed to obtain the configuration information; the configuration object of the SGPIOmaster module is modified according to the configuration information so that the SGPIO driver component or the SGPIO sampling component can change the protocol mode in time; multiple reference models of the interrupt status are instantiated in the basic test class; in the test case component, the override mechanism is used to select the reference model according to the currently verified interrupt triggering method; the SGPIO serial port driver transaction is received twice according to the current reference model, and the expected value of the interrupt status register is calculated; the actual value of the interrupt status register is obtained by reading from the APB bus through the APB sampling component through the basic reference model, and the expected value of the interrupt status register and the actual value of the interrupt status register are compared to realize the full random verification of the interrupt status register value of the SGPIO master module.

[0116] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0117] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or select equivalently some of the technical features therein. However, these modifications or selections do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fully random testing method for an SGPIO master module, characterized in that: include: Define and instantiate the configuration object of each SGPIO master module protocol mode, and pass the configuration object of each SGPIOmaster module protocol mode to the APB driver component, the SGPIO driver component and the SGPIO sampling component at the same time; After the APB driver component receives the APB bus write transaction generated by the sequencer, determining whether the APB bus write transaction is an SGPIO control register configuration transaction; If the APB bus write transaction is an SGPIO control register configuration transaction, parsing the parallel write data written by the APB bus to obtain configuration information; Modify the configuration object of the SGPIO master module according to the configuration information, so that the SGPIO driver component or the SGPIO sampling component changes the protocol mode in time; Instantiate various reference models of interrupt states in the base test class; In the test case component, the override mechanism is used to select the reference model according to the currently verified interrupt triggering mode; According to the current reference model, the SGPIO serial port driver transaction is received twice, and the expected value of the interrupt status register is calculated; The actual value of the interrupt status register is obtained by receiving the interrupt status register from the APB bus through the APB sampling component through the basic reference model, and the expected value of the interrupt status register is compared with the actual value of the interrupt status register to achieve full random verification of the interrupt status register value of the SGPIO master module.

2. The fully random testing method of the SGPIO master module according to claim 1, characterized in that: The configuration object for defining and instantiating each SGPIO master module protocol mode includes: Derive an SGPIO configuration class from the object class of UVM, and define members configuring the SGPIO driver component and the SGPIO sampling component protocol mode configuration in the SGPIO configuration class; Defining the handle of the SGPIO configuration class in the basic test class, the SGPIO driver component, the SGPIO sampling component and the APB driver component; In the basic test class component, objects of the first SGPIO master module and the second SGPIO master module protocol mode are instantiated and configured to obtain a first instance and a second instance.

3. The fully random testing method of the SGPIO master module according to claim 2, characterized in that: The step of modifying the configuration object of the SGPIO master module according to the configuration information so that the SGPIO driver component or the SGPIO sampling component changes the protocol mode in time includes: Configure the first instance and the second instance according to the configuration information; In the tasks of serial port driving of the first SGPIO master module and the second SGPIOmaster module in the SGPIO driver component and the SGPIO sampling component, copy the object pointed to by the handle of the SGPIO configuration class; Parse the member of the object pointed to by the handle of the SGPIO configuration class, and configure the protocol mode of this drive transaction, wherein the protocol mode of the drive transaction includes the big-endian mode between bytes and within bytes, the number of bytes sent, and the MCK or MLD signal flip.

4. The fully random testing method of the SGPIO master module according to claim 1, characterized in that: The determining whether the APB bus write transaction is an SGPIO control register configuration transaction includes: Detecting the address of each transaction written to the APB bus through the tasks defined in the APB driver component; Detect whether the address is consistent with the control register address of the first SGPIO master module or the control register address of the second SGPIO master module. If consistent, determine that the APB bus write transaction is an SGPIO control register configuration transaction; otherwise, determine that the APB bus write transaction is not an SGPIO control register configuration transaction.

5. The fully random testing method of the SGPIO master module according to any one of claims 1 to 4, characterized in that: The receiving SGPIO serial port driver transactions twice according to the current reference model and calculating the expected value of the interrupt status register include: Get the current SGPIO serial port transaction and the last SGPIO serial port transaction of the current reference model latched by the SGPIO driver component and sent to the current reference model; Analyze the current SGPIO serial port transaction and the previous SGPIO serial port transaction to determine an interrupt triggering mode; Determine a calculation method for a current interrupt status value according to the interrupt triggering mode; According to the calculation method of the current interrupt status value, the expected value of the interrupt status register is calculated based on the current SGPIO serial port transaction and the previous SGPIO serial port transaction.

6. The fully random testing method of the SGPIO master module according to any one of claims 1 to 4, characterized in that: The multiple reference models include a high level reference model, a low level reference model, a rising edge reference model, a falling edge reference model and a double edge reference model; the multiple reference models of the interrupt state instantiated in the basic test class specifically include: A basic reference model class is derived in the UVM component class, and then the high level reference model, the low level reference model, the rising edge reference model, the falling edge reference model and the double edge reference model are derived from the basic reference model class, corresponding to five interrupt trigger modes of high level, low level, rising edge, falling edge and double edge.

7. A fully random test device for an SGPIO master module, characterized in that: include: A configuration module, used to define and instantiate a configuration object of each SGPIO master module protocol mode, and simultaneously pass the configuration object of each SGPIO master module protocol mode to the APB driver component, the SGPIO driver component, and the SGPIO sampling component; The processing module is used to determine whether the APB bus write transaction is an SGPIO control register configuration transaction after the APB driver component receives the APB bus write transaction generated by the sequencer; if the APB bus write transaction is an SGPIO control register configuration transaction, parse the parallel write data written by the APB bus to obtain configuration information; A modification module, used to modify the configuration object of the SGPIO master module according to the configuration information, so that the SGPIO driver component or the SGPIO sampling component changes the protocol mode in time; Instantiation module, used to instantiate various reference models of interrupt status in the basic test class; The mode selection module is used to select the reference model in the test case component according to the currently verified interrupt trigger mode using the override mechanism; A calculation module, used for receiving SGPIO serial port driver transactions twice according to a current reference model, and calculating an expected value of an interrupt status register; The verification module is used to receive the actual value of the interrupt status register read from the APB bus through the APB sampling component through the basic reference model, and compare the expected value of the interrupt status register with the actual value of the interrupt status register to achieve full random verification of the interrupt status register value of the SGPIO master module.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the fully random testing method of the SGPIO master module according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the fully random testing method of the SGPIO master module according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the fully random testing method of the SGPIO master module according to any one of claims 1 to 6 is implemented.

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