Fully random testing method, device, equipment, medium and product for SGPIO master module

Abstract

This invention provides a fully randomized testing method, apparatus, device, medium, and product for an SGPIO master module. The method involves simultaneously transmitting the SGPIO master module's configuration object to the APB driver component, the SGPIO driver component, and the SGPIO sampling component. If the APB bus write transaction is an SGPIO control register configuration transaction, the parallel write data from the APB bus is parsed to obtain configuration information. The configuration object of the SGPIO master module is modified according to the configuration information, enabling the SGPIO driver component or the SGPIO sampling component to promptly change the protocol mode. Multiple reference models for interrupt states are instantiated in the basic test class. In the test case component, the reference model is selected using an override mechanism based on the currently verified interrupt triggering method. By comparing the expected value and the actual value of the interrupt status register, fully randomized verification of the SGPIO master module's interrupt status register value can be achieved. This invention improves the comprehensiveness and effectiveness of SGPIO master module testing.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a fully random testing method, apparatus, device, medium, and product for an SGPIO master module. Background Technology

[0002] Serial General-purpose Input / Output (SGPIO) is a communication method that serializes general-purpose input and output (IO) signals. It defines the data exchange method between the initiating device (such as a host bus adapter) and the target device (such as a backplane). SGPIO technology allows for the programming configuration of multiple operating modes for each pin, including connection to the Advanced Peripheral Bus (APB), collaboration with external TTL components, and support for multiple master modules and ports. The SGPIO bus can support up to 256 bits of output per master module, with each master module containing four ports, and can be frequency-divided according to the APB clock for flexible data transmission.

[0003] While SGPIO offers flexible configuration options, it still has limitations when performing fully randomized tests, particularly regarding dynamic changes in protocol modes and randomized testing of interrupt status records. In practical applications, it is impossible to update the test configuration in real time according to the actual configuration of the SGPIO registers, thus failing to meet the requirements for randomized testing of the SGPIO master module.

[0004] Therefore, the comprehensiveness and effectiveness of existing SGPIO master module testing are poor. Summary of the Invention

[0005] This invention provides a fully randomized testing method, apparatus, device, medium, and product for SGPIO master modules, which addresses the shortcomings of poor comprehensiveness and effectiveness in existing SGPIO master module testing, thereby achieving fully randomized testing of SGPIO master modules and improving the comprehensiveness and effectiveness of SGPIO master module testing.

[0006] This invention provides a fully randomized testing method for an SGPIO master module, comprising: defining and instantiating a configuration object for each SGPIO master module protocol mode, and simultaneously passing the configuration object for each SGPIO master module protocol mode to an APB driver component, an SGPIO driver component, and an SGPIO sampling component; after the APB driver component receives an APB bus write transaction generated by the sequencer, determining whether the APB bus write transaction is an SGPIO control register configuration transaction; if the APB bus write transaction is an SGPIO control register configuration transaction, parsing the parallel write data of the APB bus to obtain configuration information; and modifying the SGPIO according to the configuration information. The master module configuration object enables the SGPIO driver component or the SGPIO sampling component to change the protocol mode in a timely manner; multiple reference models of interrupt status are instantiated in the basic test class; in the test case component, the reference model is selected using the override mechanism according to the currently verified interrupt triggering method; the expected value of the interrupt status register is calculated by receiving SGPIO serial port driver transactions twice according to the current reference model; the actual value of the interrupt status register is read from the APB bus through the APB sampling component via the basic reference model, and the expected value and the actual value of the interrupt status register are compared to achieve fully random verification of the interrupt status register value of the SGPIO master module.

[0007] According to the present invention, a fully randomized testing method for an SGPIO master module includes defining and instantiating a configuration object for each SGPIO master module protocol mode, comprising: deriving an SGPIO configuration class from a UVM object class, and defining members in the SGPIO configuration class to configure the protocol modes of the SGPIO driver component and the SGPIO sampling component; defining handles of the SGPIO configuration class in the basic test class, the SGPIO driver component, the SGPIO sampling component, and the APB driver component; and instantiating objects configuring the protocol modes of the first SGPIO master module and the second SGPIO master module in the basic test class component to obtain a first instance and a second instance.

[0008] According to the present invention, a fully random testing method for an SGPIO master module is provided. The step of modifying the configuration object of the SGPIO master module according to configuration information to enable the SGPIO driver component or the SGPIO sampling component to change the protocol mode in a timely manner includes: configuring the first instance and the second instance according to the configuration information; copying the object pointed to by the handle of the SGPIO configuration class in the serial port driving tasks of the first SGPIO master module and the second SGPIO master module in the SGPIO driver component and the SGPIO sampling component; parsing the members of the object pointed to by the handle of the SGPIO configuration class, and configuring the protocol mode of the current driving transaction. The protocol mode of the driving transaction includes endianness between bytes and within bytes, number of bytes sent, and MCK or MLD signal toggling.

[0009] According to a fully random testing method for an SGPIO master module provided by the present invention, the step of determining whether the APB bus write transaction is an SGPIO control register configuration transaction after the APB driver component receives the APB bus write transaction generated by the sequencer includes: detecting the address of each APB bus write transaction through a task defined in the APB driver component; detecting whether the address is consistent with the control register address of the first SGPIO master module or the control register address of the second SGPIO master module; if consistent, determining that the APB bus write transaction is an SGPIO control register configuration transaction; otherwise, determining that the APB bus write transaction is not an SGPIO control register configuration transaction.

[0010] According to the fully random testing method of the SGPIO master module provided by the present invention, the step of calculating the expected value of the interrupt status register based on two received SGPIO serial port driver transactions of the current reference model includes: obtaining the current SGPIO serial port transaction and the previous SGPIO serial port transaction latched by the SGPIO driver component and sent to the current reference model; analyzing the current SGPIO serial port transaction and the previous SGPIO serial port transaction to determine the interrupt triggering mode; determining the calculation method of the current interrupt status value according to the interrupt triggering mode; and calculating the expected value of the interrupt status register based on the current SGPIO serial port transaction and the previous SGPIO serial port transaction according to the calculation method of the current interrupt status value.

[0011] According to the present invention, a fully random testing method for an SGPIO master module is provided, wherein the multiple reference models include a high-level reference model, a low-level reference model, a rising edge reference model, a falling edge reference model, and a double-edge reference model; the instantiation of the multiple reference models of interrupt states in the basic test class specifically includes: deriving a basic reference model class from the UVM component class, and then deriving the high-level reference model, the low-level reference model, the rising edge reference model, the falling edge reference model, and the double-edge reference model from the basic reference model class, respectively corresponding to the five interrupt triggering modes of high level, low level, rising edge, falling edge, and double-edge.

[0012] This invention also provides a fully randomized testing device for an SGPIO master module, comprising: a configuration module, used to define and instantiate a configuration object for each SGPIO master module protocol mode, and simultaneously transmit the configuration object for each SGPIO master module protocol mode to an APB driver component, an SGPIO driver component, and an SGPIO sampling component; a processing module, used to determine whether the APB bus write transaction is an SGPIO control register configuration transaction after the APB driver component receives the APB bus write transaction generated by the sequencer; if the APB bus write transaction is an SGPIO control register configuration transaction, then parse the parallel write data written by the APB bus to obtain configuration information; and a modification module, used to modify the SGPIO according to the configuration information. The master module includes a configuration object to enable the SGPIO driver component or the SGPIO sampling component to change the protocol mode in a timely manner; an instantiation module for instantiating multiple reference models of interrupt states in the basic test class; a mode selection module for selecting a reference model in the test case component based on the currently verified interrupt triggering method using the override mechanism; a calculation module for calculating the expected value of the interrupt status register by receiving SGPIO serial port driver transactions twice based on the current reference model; and a verification module for receiving the actual value of the interrupt status register read from the APB bus by the APB sampling component through the basic reference model, and comparing the expected value of the interrupt status register with the actual value of the interrupt status register to achieve fully random verification of the interrupt status register value of the SGPIO master module.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a fully randomized testing method for the SGPIOmaster module as described above.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a fully randomized testing method for the SGPIO master module as described above.

[0015] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements a fully randomized testing method for the SGPIO master module as described above.

[0016] This invention provides a fully random testing method, apparatus, device, medium, and product for SGPIO master modules. It defines and instantiates a configuration object for each SGPIO master module's protocol mode, and simultaneously transmits this configuration object to the APB driver component, the SGPIO driver component, and the SGPIO sampling component. After the APB driver component receives an APB bus write transaction generated by the sequencer, if the APB bus write transaction is an SGPIO control register configuration transaction, it parses the parallel write data of the APB bus to obtain configuration information. Based on this configuration information, it modifies the configuration object of the SGPIO master module, enabling the SGPIO driver component or the SGPIO sampling component to promptly change the protocol mode and complete the SGPIO test. This invention verifies complex scenarios involving multiple random configuration changes during data reception or transmission by the SGPIO master module. It instantiates various reference models for interrupt states in the basic test class. In the test case component, the reference model is selected using an override mechanism based on the currently verified interrupt triggering method. The expected value of the interrupt status register is calculated by receiving SGPIO serial port driver transactions twice based on the current reference model. The actual value of the interrupt status register is read from the APB bus via the APB sampling component through the basic reference model, and the expected value and actual value of the interrupt status register are compared, enabling fully random verification of the SGPIO master module's interrupt status register value. This invention improves the comprehensiveness and effectiveness of SGPIO master module testing by enabling verification of complex scenarios involving multiple random configuration changes during data reception or transmission by the SGPIO master module, recording interrupt states for different interrupt triggering methods, and fully randomizing the SGPIO master module's interrupt status register value. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the SGPIO bus provided by the present invention.

[0019] Figure 2 This is a schematic diagram of the UVM-based SGPIO verification environment framework provided by the present invention.

[0020] Figure 3 This is a flowchart illustrating the fully random testing method for the SGPIO master module provided by this invention.

[0021] Figure 4 This is a flowchart illustrating the process of setting up a fully random test and verification environment for the SGPIO master module to change protocol modes multiple times, as provided by this invention.

[0022] Figure 5 This is a schematic diagram of the SGPIO interrupt status register value verification environment setup provided by the present invention.

[0023] Figure 6 This is a schematic diagram of the structure of the fully random test device for the SGPIO master module provided by the present invention.

[0024] Figure 7 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0026] The term "Serial Universal Input / Output (SGPIO)" used in the embodiments of this application refers to a communication method for serializing universal input and output (I / O) signals. It defines the data exchange method between a startup device (such as a host bus adapter) and a target device (such as a backplane). The target device converts the output signal to several parallel LED signals and provides input signals to the universal input signal lines. The startup device and the target device can consist of one or more chips. If multiple chips are used, the signals driving the bus should be organized to conform to this standard.

[0027] Figure 1 This is a schematic diagram of the SGPIO bus provided by the present invention. The following is a summary diagram in conjunction with... Figure 1 Describe the working principle of the SGPIO bus. For example... Figure 1 As shown, initiator is the initiating device (or master device), target is the target device (or slave device), SGPIOMCK (SGPIO Master Clock) is the SGPIO master clock signal, SGPIOMLD (SGPIO Master LatchData) is the master data loading signal, SGPIOMO (SGPIO Master Output) is the master output signal, and SGPIOMI (SGPIO Master Input) is the master input signal.

[0028] In practical applications, the initiator's main functions on the SGPIO bus include: data transmission control, protocol definition, signal generation, address and command issuance, error detection and handling, interrupt management, communication initiation, data flow control, system synchronization, and configuration and status management. The target's main functions on the SGPIO bus include: data reception and transmission, signal response, address identification, data buffering, command execution, error reporting, interrupt generation, flow control response, and synchronization operations.

[0029] Specifically, SGPIOMCK is used to synchronize data transmission, ensuring correct data synchronization between the sending and receiving ends. SGPIOMLD is used to indicate when data is loaded into the shift register or to trigger data sampling during data transmission. SGPIOMO represents the data signal emitted from the SGPIO master module, used to send data to the target. SGPIOMI represents the data signal received from the target by the SGPIO master module.

[0030] like Figure 1As shown, each SGPIO pin can be programmed to perform the following functions: direct connection to the APB bus; working with external serial TTL components (74LV165 / 74LV595); support for two masters, each with up to 256 bits of output, and each master containing 4 ports; shift clock from the APB clock pclk divided by a programmable value; support for interrupt options for each input / output port; support for interrupt sensitivity options, including high, low, rising edge, falling edge, and double edge; and support for WDT (Watchdog Timer) reset.

[0031] Figure 2 This is a schematic diagram of the UVM-based SGPIO verification environment framework provided by the present invention. The following is in conjunction with... Figure 2 This section describes the various components within the UVM SGPIO verification environment framework.

[0032] like Figure 2 As shown, the SGPIO verification environment framework of UVM (Universal Verification Methodology) includes apb_agt (apb proxy), sgpio_mst1_agt (first SGPIO master module proxy), sgpio_mst2_agt (second SGPIO master module proxy), virtual sequencer, refmod (reference model), scb (SystemC Bus), apb_intf (apb interface), sgpio_mst1_intf (first SGPIO master module interface), sgpio_mst2_intf (first SGPIO master module interface), and dut (Device Under Test).

[0033] like Figure 2 As shown, apb_agt, sgpio_mst2_agt, and sgpio_mst1_agt all include the sqr (sequencer) component, the mon (monitor) component, and the drv (driver) component.

[0034] Specifically, apb_agt is used to drive and sample the APB 3.0 interface. drv in apb_agt can convert the transaction-level signals generated by sqr into bus pin-level signals; mon can package the sampled signals into transaction-level signals according to the APB bus protocol and send them to SCB for data comparison.

[0035] Specifically, `sgpio_mst1_agt` is used to drive and sample the sgpio mst1 serial port. `drv` and `mon` are configurable components that can be configured according to the sgpio protocol mode, such as intra-byte endianness, inter-byte endianness, ld signal mode, and the number of bytes sent. `sgpio_mst2_agt` is the same as `sgpio_mst1_agt`, used to drive and sample the sgpio mst2 serial port.

[0036] Specifically, the virtual sequencer is used to coordinate the creation of transactions by apb sqr, sgpio mst1 sqr, and sgpio mst2 sqr. Its internally defined handle points to the sqr that actually generates the transaction.

[0037] Specifically, `ref mod` is used to generate expected data at the behavioral level. That is, based on the data acquired by the sgpio mi serial port, it gives the expected value of the interrupt status register, and then sends it to the SCB for comparison with the actual value of the interrupt status register read from the APB bus.

[0038] In practical applications, the fully randomized testing of the SGPIO master module includes two aspects: fully randomized testing of the SGPIO master module's receive and transmit protocol modes and randomized testing of SGPIO interrupt status records.

[0039] Specifically, for fully random testing of the SGPIO master module's transmit and receive protocol modes, the SGPIO master module supports changing the protocol mode during serial data transmission or reception. This includes clk inverse (clock signal toggle), ld inverse (load signal toggle), the number of bytes transmitted or received, the endianness of transmitted or received data, and the MCK signal division factor. The configuration of these modes requires writing data to the SGPIO_CONTRAL_REGISTER (sgpio control register) via the APB interface. In actual verification, the driver components (drv) and sampling components (mon) in sgpio_mst1_agt and sgpio_mst2_agt must also respond in real time according to the protocol mode configured on the APB bus to ensure timely driving and sampling according to the protocol mode configured by the SGPIO master module. In a standard UVM verification environment, this process typically requires deriving a config item from the object base class, which contains configuration members for the driver and sampling components of the SGPIO master module. Then, the `config` object is instantiated in the `case` component, its properties are modified according to the test points of this test case, and then the `config_db` mechanism is used to pass the `config` object to the driver and sampling components of the SGPIO master module. The problem with this method is that it cannot change the `config` properties in real time according to the actual configuration of the SGPIO registers, thus failing to meet the test requirement of fully randomizing the configuration mode changes of the SGPIO master module multiple times.

[0040] Specifically, for random testing of SGPIO interrupt status recording, the first SGPIO master module (sgpiomst1) and the second SGPIO master module (sgpio mst2) each have 8 interrupt status registers, corresponding to each bit of the serial port data receive register, and each bit is independent of the others. The SGPIO master module can configure different interrupt triggering methods by configuring the INT_SEN register, including falling edge, rising edge, low-level trigger, high-level trigger, and double-edge trigger. The interrupt status register records the interrupt status based on two received serial port data entries and the interrupt triggering method configured in INT_SEN. During random testing of interrupt status recording, the verification environment needs to provide the expected status values ​​of each register and compare them with the values ​​read from the APB bus.

[0041] Therefore, existing technologies cannot meet the requirements for randomized testing of the SGPIO master module. Consequently, the comprehensiveness and effectiveness of existing SGPIO master module testing technologies are poor.

[0042] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The following is a combination of... Figure 1-Figure 5 This invention describes a fully randomized testing method for the SGPIO master module.

[0043] In practical applications, the execution entity of the fully randomized testing method for the SGPIO master module can be the fully randomized testing device of the SGPIO master module. There are various ways to implement the fully randomized testing device of the SGPIO master module. For example, it can be implemented through a computer program, such as application software; or, for example, a chip; it can also be implemented as a medium storing the relevant computer program, such as a USB flash drive or cloud storage; or, it can be implemented through a physical device that integrates or installs the relevant computer program, such as a server.

[0044] Figure 3 This is a flowchart illustrating the fully randomized testing method for the SGPIO master module provided by this invention, as shown below. Figure 3 As shown, the method includes the following steps 301 to 309.

[0045] Step 301: Define and instantiate the configuration object for the protocol mode of each SGPIO master module.

[0046] As an example, in one implementation, step 301 above includes:

[0047] Derive the SGPIO configuration class from the UVM object class, and define members in the SGPIO configuration class to configure the protocol mode of the SGPIO driver component and the SGPIO sampling component;

[0048] Define the handle of the SGPIO configuration class in the basic test class, SGPIO driver component, SGPIO sampling component, and APB driver component;

[0049] In the basic test class component, instantiate objects configuring the protocol modes of the first SGPIO master module and the second SGPIO master module to obtain the first instance and the second instance.

[0050] The UVM object class is denoted as `uvm_object`, and the SGPIO configuration class is denoted as `sgpio_config`. The SGPIO driver component, `sgpio_driver`, is used to drive the serial port of the SGPIO master module. The SGPIO sampling component, `sgpio_monitor`, is used to sample the serial port of the SGPIO master module.

[0051] Specifically, sgpio_config is derived from uvm_object, and members for the protocol mode configuration of the sgpio_driver and sgpio_monitor components are defined in sgpio_config, including endianness modes tm for transmitted data between big / small bytes and within big / small bytes; endianness modes rm for received data between big / small bytes and within big / small bytes; the number of bytes sent and received lb; the serial port MLD signal toggle configuration ld_inv; and the serial port clock signal MCK signal toggle configuration clk_inv.

[0052] The basic test class is denoted as `base_test`, and the APB driver component is denoted as `apb_driver`. Furthermore, handles of type `sgpio_config` are defined in the `base_test`, `sgpio_driver`, `sgpio_monitor`, and `apb_driver` components. In the `base_test` component, an object configuring the protocol modes of the first and second SGPIO master modules is instantiated, resulting in a first instance `cfg1` and a second instance `cfg2`.

[0053] Step 302: Pass the configuration object of each SGPIO master module protocol mode to the APB driver component, SGPIO driver component and SGPIO sampling component at the same time.

[0054] Based on the above explanation, by defining and instantiating the configuration object for each SGPIO master module's protocol mode, a first instance cfg1 and a second instance cfg2 can be obtained. Specifically, the first instance cfg1 and the second instance cfg2 are passed to the sgpio_driver component, the sgpio_monitor component, and the apb_driver using the config_db mechanism.

[0055] Step 303: After the APB driver component receives the APB bus write transaction generated by the sequencer, it determines whether the APB bus write transaction is an SGPIO control register configuration transaction.

[0056] In one possible implementation, step 303 above includes:

[0057] After the APB driver component receives the APB bus write transaction generated by the sequencer, it detects the address of each APB bus write transaction through the task defined in the APB driver component.

[0058] The system checks whether the address matches the control register address of the first SGPIO master module or the control register address of the second SGPIO master module. If they match, the APB bus write transaction is determined to be an SGPIO control register configuration transaction; otherwise, the APB bus write transaction is determined to be an SGPIO control register configuration transaction.

[0059] In practical applications, a task is defined in the apb_driver component to detect the address of each transaction that writes data to the APB bus.

[0060] Specifically, after the apb_driver component receives the APB bus write transaction generated by the sequencer, it detects the address of the APB bus write data transaction by defining a task in the apb_driver component. Further, if this address matches the control register address of either the first or second SGPIO master module, the APB bus write transaction is determined to be an SGPIO control register configuration transaction; otherwise, it is determined that the APB bus write transaction is not an SGPIO control register configuration transaction.

[0061] Step 304: If the APB bus write transaction is an SGPIO control register configuration transaction, then parse the parallel write data written by the APB bus to obtain the configuration information.

[0062] Furthermore, if the APB bus write transaction is determined to be an SGPIO control register configuration transaction, the parallel write data pwdata written by the APB bus is parsed to obtain the configuration information.

[0063] Step 305: Modify the configuration object of the SGPIO master module according to the configuration information so that the SGPIO driver component or SGPIO sampling component can change the protocol mode in a timely manner.

[0064] In one possible implementation, step 305 includes:

[0065] Configure the first instance and the second instance according to the configuration information;

[0066] In the SGPIO driver component and SGPIO sampling component, copy the object pointed to by the handle of the configuration object in the serial port driver task of the first SGPIO master module and the second SGPIO master module.

[0067] The SGPIO configuration class handle points to the members of the object and configures the protocol mode for this driving transaction. The protocol mode for driving the transaction includes endianness between bytes and within bytes, the number of bytes sent, and MCK or MLD signal toggling.

[0068] Based on the above explanation, configuration information is obtained by parsing the parallel write data pwdata written via the APB bus. Furthermore, based on this configuration information, the first instance cfg1 and the second instance cfg2 are configured.

[0069] Specifically, in `sgpio_driver` and `sgpio_monitor`, the objects pointed to by the configuration object (cfg) handles are copied in the serial port driver tasks of the first and second SGPIO master modules. The purpose of this operation is to avoid changing the driver mode configuration during the serial port driver or sampling process. Then, the members of the object pointed to by the cfg handle are parsed to configure the protocol mode of this driver transaction, including endianness between bytes and within bytes, the number of bytes sent, and MCK or MLD signal toggling, etc.

[0070] Figure 4 This is a flowchart illustrating the process of setting up a fully randomized test and verification environment for the SGPIO master module to change protocol modes multiple times, as provided in this invention. Figure 4 As shown, the `sgpio_config` defines the members for the protocol mode configuration of the SGPIO driver component and the SGPIO sampling component. `cfg1` and `cfg2` are instantiated in `base_test` and passed to the `apb` driver component, the `sgpio` driver component, and the sampling component. The `apb` driver parses the bus write transaction and modifies the `cfg` members according to the address information. The `sgpio_driver` task copies and parses the `cfg`, and then uses the `cfg` information to drive the serial port in different protocol modes. The `sgpio_monitor` task copies and parses the `cfg`, and then uses the `cfg` information to sample in different protocol modes.

[0071] It is understandable that steps 301 to 305 constitute the steps for setting up a fully random verification environment where the SGPIO master module simultaneously sends and receives data and changes the protocol mode multiple times. This invention improves upon the traditional UVM verification framework by simultaneously passing the config object to the appb driver component, the SGPIO driver component, and the sampling component. After receiving the total write transaction generated by the sequencer, the appb driver first performs address resolution. If the transaction is an SGPIO_CONTROL_REGISTER register configuration transaction, it parses the pwdata signal and modifies the config object according to the configuration information. This allows the SGPIO serial port driver or sampling component to change the protocol mode in a timely manner, thereby completing the verification of complex scenarios where the SGPIO module randomly changes its configuration multiple times during data reception or transmission.

[0072] Step 306: Instantiate multiple reference models of interruption states in the basic test class.

[0073] As an example, the aforementioned reference models include a high-level reference model, a low-level reference model, a rising edge reference model, a falling edge reference model, and a double-edge reference model. Specifically, step 306 includes:

[0074] A base reference model class is derived from the UVM component class, and then high-level reference model, low-level reference model, rising edge reference model, falling edge reference model and double-edge reference model are derived from the base reference model class, corresponding to five interrupt triggering methods: high level, low level, rising edge, falling edge and double-edge respectively.

[0075] Specifically, Figure 5 This is a schematic diagram of the SGPIO interrupt status register value verification environment setup provided by the present invention, as shown below. Figure 5 As shown, the UVM component class uvm_component derives from the base reference model class base_reference_model, and then derives from base_reference_model the high-level reference model reference_model_h, the low-level reference model reference_model_l, the rising edge reference model reference_model_r, the falling edge reference model reference_model_f, and the double-edge reference model reference_model_d. These five models correspond to the five interrupt triggering methods of high level, low level, rising edge, falling edge, and double-edge, respectively.

[0076] Step 307: In the test case component, select the reference model using the override mechanism based on the currently verified interruption triggering method.

[0077] It is understandable that the overridden mechanism can be used in the test case component to replace the interrupt triggering method to be selected for this test case, thereby enabling random testing of interrupt status records.

[0078] Step 308: Calculate the expected value of the interrupt status register by receiving SGPIO serial port drive transactions twice based on the current reference model.

[0079] In one possible implementation, step 308 above includes:

[0080] Retrieve the current SGPIO serial transaction and the previous SGPIO serial transaction latched by the SGPIO driver component and sent to the current reference model.

[0081] Analyze the current SGPIO serial port transaction and the previous SGPIO serial port transaction to determine the interrupt triggering method;

[0082] The calculation method for the current interrupt status value is determined based on the interrupt triggering method;

[0083] Based on the current interrupt status value calculation method, the expected value of the interrupt status register is calculated based on the current SGPIO serial port transaction and the previous SGPIO serial port transaction.

[0084] In practical applications, the reference model has a latching function. Specifically, after receiving an SGPIO serial transaction from the SGPIO driver component, the reference model latches the received SGPIO serial transaction. Based on this, it is possible to obtain the current SGPIO serial transaction and the previous SGPIO serial transaction latched by the SGPIO driver component and sent to the current reference model.

[0085] In practical applications, different calculation methods are defined for the interrupt status value under different triggering modes in each reference model. Specifically, after obtaining the current SGPIO serial port transaction and the previous SGPIO serial port transaction, the changes between the two transactions are analyzed to determine whether an event satisfying the interrupt triggering condition has occurred, thereby determining the interrupt triggering mode. After determining the interrupt triggering mode, the calculation method for the interrupt status value corresponding to that interrupt triggering mode under the current reference model is determined, and this method is used as the calculation method for the current interrupt status value. Furthermore, based on the current interrupt status value calculation method, the expected value of the interrupt status register is calculated based on the current SGPIO serial port transaction and the previous SGPIO serial port transaction.

[0086] Step 309: Receive the actual value of the interrupt status register obtained from the APB bus through the APB sampling component via the basic reference model, and compare the expected value of the interrupt status register with the actual value of the interrupt status register to achieve fully random verification of the interrupt status register value of the SGPIOmaster module.

[0087] Combination Figure 5 The base reference model receives the actual value of the interrupt status register read from the APB bus by apb_monitor, and compares the expected value of the interrupt status register with the actual value of the interrupt status register to achieve fully random verification of the interrupt status register value of the SGPIO master module.

[0088] Specifically, if the expected value and the actual value of the interrupt status register are consistent, it indicates that the interrupt status register behavior of the SGPIOmaster module is as expected. If there is a discrepancy between the expected and actual values, the cause needs to be analyzed. This could be due to an implementation issue with the SGPIO master module, or a problem with the test vector, reference model, or monitor implementation.

[0089] In addition, in one possible implementation, the above-mentioned fully randomized testing method for the SGPIO master module further includes: generating a fully randomized test report for the SGPIO master module, and analyzing the fully randomized test coverage and problems found in the SGPIO master module.

[0090] In this embodiment, a fully randomized test report of the SGPIO master module is generated, and the full randomized test coverage and problems found of the SGPIO master module are analyzed, thereby improving the accuracy and reliability of the full randomized test of the SGPIO master module.

[0091] In the fully random testing method for the SGPIO master module provided in this embodiment, a configuration object for each SGPIO master module protocol mode is defined and instantiated, and the configuration object for each SGPIO master module protocol mode is simultaneously passed to the APB driver component, the SGPIO driver component, and the SGPIO sampling component. After the APB driver component receives the APB bus write transaction generated by the sequencer, if the APB bus write transaction is an SGPIO control register configuration transaction, it parses the parallel write data of the APB bus to obtain the configuration information; and modifies the SGPIO according to the configuration information. The configuration object of the master module enables the SGPIO driver component or the SGPIO sampling component to change the protocol mode in a timely manner, thus verifying complex scenarios where the SGPIO master module randomly changes its configuration multiple times during data reception or transmission. Multiple reference models for interrupt states are instantiated in the basic test class. In the test case component, the reference model is selected using the override mechanism based on the currently verified interrupt triggering method. The expected value of the interrupt status register is calculated by receiving SGPIO serial port driver transactions twice based on the current reference model. The actual value of the interrupt status register is read from the APB bus through the APB sampling component using the basic reference model, and the expected value and the actual value of the interrupt status register are compared, enabling fully random verification of the SGPIO master module's interrupt status register value. This embodiment's solution can verify complex scenarios where the SGPIO master module randomly changes its configuration multiple times during data reception or transmission, record interrupt states for different interrupt triggering methods, and fully randomize the SGPIO master module's interrupt status register value, improving the comprehensiveness and effectiveness of SGPIO master module testing.

[0092] The following describes the fully random testing apparatus for the SGPIO master module provided by the present invention. The fully random testing apparatus for the SGPIO master module described below and the fully random testing method for the SGPIO master module described above can be referred to in correspondence.

[0093] Figure 6 This is a schematic diagram of the structure of the fully randomized test device for the SGPIO master module provided by the present invention, as shown below. Figure 6 As shown, the fully randomized test device for the SGPIO master module includes: a configuration module 61, a processing module 62, a modification module 63, an instantiation module 64, a mode selection module 65, a calculation module 66, and a verification module 67.

[0094] Configuration module 61 is used to define and instantiate the configuration object of each SGPIO master module protocol mode, and simultaneously pass the configuration object of each SGPIO master module protocol mode to the APB driver component, the SGPIO driver component and the SGPIO sampling component.

[0095] As an example, in one implementation, the configuration module 61 described above, when defining and instantiating the configuration object for each SGPIOmaster module protocol mode, is specifically used for:

[0096] Derive the SGPIO configuration class from the UVM object class, and define members in the SGPIO configuration class to configure the protocol mode of the SGPIO driver component and the SGPIO sampling component;

[0097] Define the handle of the SGPIO configuration class in the basic test class, SGPIO driver component, SGPIO sampling component, and APB driver component;

[0098] In the basic test class component, instantiate objects configuring the protocol modes of the first SGPIO master module and the second SGPIO master module to obtain the first instance and the second instance.

[0099] The UVM object class is denoted as `uvm_object`, and the SGPIO configuration class is denoted as `sgpio_config`. The SGPIO driver component, `sgpio_driver`, is used to drive the serial port of the SGPIO master module. The SGPIO sampling component, `sgpio_monitor`, is used to sample the serial port of the SGPIO master module.

[0100] Specifically, sgpio_config is derived from uvm_object, and members for the protocol mode configuration of the sgpio_driver and sgpio_monitor components are defined in sgpio_config, including endianness modes tm for transmitted data between big / small bytes and within big / small bytes; endianness modes rm for received data between big / small bytes and within big / small bytes; the number of bytes sent and received lb; the serial port MLD signal toggle configuration ld_inv; and the serial port clock signal MCK signal toggle configuration clk_inv.

[0101] The basic test class is denoted as `base_test`, and the APB driver component is denoted as `apb_driver`. Furthermore, handles of type `sgpio_config` are defined in the `base_test`, `sgpio_driver`, `sgpio_monitor`, and `apb_driver` components. In the `base_test` component, an object configuring the protocol modes of the first and second SGPIO master modules is instantiated, resulting in a first instance `cfg1` and a second instance `cfg2`.

[0102] Based on the above description, configuration module 61 can obtain an instance cfg1 and a second instance cfg2 by defining and instantiating the configuration object of each SGPIO master module protocol mode. Specifically, configuration module 61 uses the config_db mechanism to pass the first instance cfg1 and the second instance cfg2 to the sgpio_driver component, the sgpio_monitor component, and the apb_driver.

[0103] The aforementioned processing module 62 is used to determine whether the APB bus write transaction is an SGPIO control register configuration transaction after the APB driver component receives the APB bus write transaction generated by the sequencer; if the APB bus write transaction is an SGPIO control register configuration transaction, then the parallel write data written by the APB bus is parsed to obtain the configuration information.

[0104] In one possible implementation, the processing module 62 is used to determine whether the APB bus write transaction is an SGPIO control register configuration transaction after the APB driver component receives the APB bus write transaction generated by the sequencer. Specifically, it is used for:

[0105] The address of each write transaction to the APB bus is detected by a task defined in the APB driver component.

[0106] The system checks whether the address matches the control register address of the first SGPIO master module or the control register address of the second SGPIO master module. If they match, the APB bus write transaction is determined to be an SGPIO control register configuration transaction; otherwise, the APB bus write transaction is determined to be an SGPIO control register configuration transaction.

[0107] In practical applications, a task is defined in the apb_driver component to detect the address of each transaction that writes data to the APB bus.

[0108] Specifically, after the apb_driver component receives the APB bus write transaction generated by the sequencer, the processing module 62 detects the address of the APB bus write data transaction by defining a task in the apb_driver component. Further, if this address matches the control register address of either the first or second SGPIO master module, the processing module 62 determines that the APB bus write transaction is an SGPIO control register configuration transaction; otherwise, the processing module 62 determines that the APB bus write transaction is not an SGPIO control register configuration transaction.

[0109] Furthermore, if the processing module 62 determines that the APB bus write transaction is an SGPIO control register configuration transaction, then the processing module 62 parses the parallel write data pwdata written by the APB bus to obtain the configuration information.

[0110] The aforementioned modification module 63 is used to modify the configuration object of the SGPIO master module according to the configuration information, so that the SGPIO driver component or SGPIO sampling component can change the protocol mode in a timely manner.

[0111] In one possible implementation, the modified module 63 described above is specifically used for:

[0112] Configure the first instance and the second instance according to the configuration information;

[0113] In the SGPIO driver component and SGPIO sampling component, copy the object pointed to by the handle of the configuration object in the serial port driver task of the first SGPIO master module and the second SGPIO master module.

[0114] The SGPIO configuration class handle points to the members of the object and configures the protocol mode for this driving transaction. The protocol mode for driving the transaction includes endianness between bytes and within bytes, the number of bytes sent, and MCK or MLD signal toggling.

[0115] Based on the above explanation, configuration information is obtained by parsing the parallel write data pwdata written via the APB bus. Furthermore, based on this configuration information, the first instance cfg1 and the second instance cfg2 are configured.

[0116] Specifically, in `sgpio_driver` and `sgpio_monitor`, the objects pointed to by the configuration object (cfg) handles are copied in the serial port driver tasks of the first and second SGPIO master modules. The purpose of this operation is to avoid changing the driver mode configuration during the serial port driver or sampling process. Then, the members of the object pointed to by the cfg handle are parsed to configure the protocol mode of this driver transaction, including endianness between bytes and within bytes, the number of bytes sent, and MCK or MLD signal toggling, etc.

[0117] Understandably, this invention improves upon the traditional UVM verification framework by simultaneously passing the config object to the APB driver component, the SGPIO driver component, and the sampling component. After receiving the total write transaction generated by the sequencer, the APB driver first performs address resolution. If the transaction is an SGPIO_CONTROL_REGISTER register configuration transaction, it parses the pwdata signal and modifies the config object according to the configuration information. This allows the SGPIO serial port driver or sampling component to promptly change the protocol mode, thereby completing the verification of complex scenarios where the SGPIO module randomly changes its configuration multiple times during data reception or transmission.

[0118] The instantiation module 64 described above is used to instantiate various reference models of interruption states in the basic test class.

[0119] As an example, the aforementioned reference models include a high-level reference model, a low-level reference model, a rising-edge reference model, a falling-edge reference model, and a double-edge reference model. Specifically, instantiated module 64 is used for:

[0120] A base reference model class is derived from the UVM component class, and then high-level reference model, low-level reference model, rising edge reference model, falling edge reference model and double-edge reference model are derived from the base reference model class, corresponding to five interrupt triggering methods: high level, low level, rising edge, falling edge and double-edge respectively.

[0121] Specifically, in combination Figure 5Instantiation module 64 derives from the base reference model class base_reference_model in the UVM component class uvm_component, and then derives from base_reference_model the high-level reference model reference_model_h, the low-level reference model reference_model_l, the rising edge reference model reference_model_r, the falling edge reference model reference_model_f, and the double-edge reference model reference_model_d. These five models correspond to the five interrupt triggering methods of high level, low level, rising edge, falling edge, and double-edge, respectively.

[0122] The mode selection module 65 is used in the test case component to select a reference model based on the currently verified interruption triggering method using the override mechanism.

[0123] Understandably, the pattern selection module 65 uses the overridden mechanism in the test case component to replace the interrupt triggering method to be selected for this test case, thereby completing the random testing of interrupt status records.

[0124] The calculation module 66 is used to calculate the expected value of the interrupt status register based on the two SGPIO serial port drive transactions received from the current reference model.

[0125] In one possible implementation, the above-mentioned calculation module 66 is specifically used for:

[0126] Retrieve the current SGPIO serial transaction and the previous SGPIO serial transaction latched by the SGPIO driver component and sent to the current reference model.

[0127] Analyze the current SGPIO serial port transaction and the previous SGPIO serial port transaction to determine the interrupt triggering method;

[0128] The calculation method for the current interrupt status value is determined based on the interrupt triggering method;

[0129] Based on the current interrupt status value calculation method, the expected value of the interrupt status register is calculated based on the current SGPIO serial port transaction and the previous SGPIO serial port transaction.

[0130] In practical applications, the reference model has a latching function. Specifically, after receiving an SGPIO serial port transaction sent by the SGPIO driver component, the reference model latches the received SGPIO serial port transaction. Based on this, the calculation module 66 can obtain the current SGPIO serial port transaction and the previous SGPIO serial port transaction latched by the SGPIO driver component and sent to the current reference model.

[0131] In practical applications, different calculation methods are defined for the interrupt status value under different triggering modes in each reference model. Specifically, after obtaining the current SGPIO serial port transaction and the previous SGPIO serial port transaction, the calculation module 66 analyzes the changes between the two transactions to determine whether an event satisfying the interrupt triggering condition has occurred, thereby determining the interrupt triggering mode. After determining the interrupt triggering mode, the calculation module 66 determines the calculation method for the interrupt status value corresponding to that interrupt triggering mode under the current reference model, and uses it as the calculation method for the current interrupt status value. Further, based on the current interrupt status value calculation method, the calculation module 66 calculates the expected value of the interrupt status register based on the current SGPIO serial port transaction and the previous SGPIO serial port transaction.

[0132] The verification module 67 is used to receive the actual value of the interrupt status register read from the APB bus by the APB sampling component through the basic reference model, and compare the expected value of the interrupt status register with the actual value of the interrupt status register to realize the fully random verification of the interrupt status register value of the SGPIO master module.

[0133] Combination Figure 5 The verification module 67 receives the actual value of the interrupt status register read from the APB bus by the apb_monitor through the base reference model base_reference_model, and compares the expected value of the interrupt status register with the actual value of the interrupt status register to realize the fully random verification of the interrupt status register value of the SGPIO master module.

[0134] Specifically, if the expected value and the actual value of the interrupt status register are consistent, it indicates that the interrupt status register behavior of the SGPIOmaster module is as expected. If there is a discrepancy between the expected and actual values, the cause needs to be analyzed. This could be due to an implementation issue with the SGPIO master module, or a problem with the test vector, reference model, or monitor implementation.

[0135] In addition, in one possible implementation, the above-mentioned fully randomized test apparatus for the SGPIO master module further includes: a report generation module, used to generate a fully randomized test report for the SGPIO master module, and analyze the fully randomized test coverage and problems found in the SGPIO master module.

[0136] In this embodiment, a fully randomized test report of the SGPIO master module is generated, and the full randomized test coverage and problems found of the SGPIO master module are analyzed, thereby improving the accuracy and reliability of the full randomized test of the SGPIO master module.

[0137] The fully random testing device for the SGPIO master module provided in this embodiment includes a configuration module that defines and instantiates a configuration object for the protocol mode of each SGPIO master module, and simultaneously transmits the configuration object to the APB driver component, the SGPIO driver component, and the SGPIO sampling component. After the APB driver component receives the APB bus write transaction generated by the sequencer, the processing module, if the APB bus write transaction is an SGPIO control register configuration transaction, parses the parallel write data of the APB bus to obtain the configuration information. The modification module modifies the configuration object of the SGPIO master module according to the configuration information, so that the SGPIO driver component or the SGPIO sampling component can change the protocol mode in a timely manner to complete the SGPIO test. The implementation of this solution verifies complex scenarios involving multiple random configuration changes during data reception or transmission by the SGPIO master module. The instantiation module instantiates various reference models for interrupt states in the basic test class. The pattern selection module, within the test case component, selects the reference model based on the currently verified interrupt triggering method using an override mechanism. The calculation module calculates the expected value of the interrupt status register by receiving SGPIO serial port driver transactions twice based on the current reference model. The verification module receives the actual value of the interrupt status register from the APB bus via the APB sampling component through the basic reference model and compares it with the expected value, thus achieving fully random verification of the SGPIO master module's interrupt status register value. This embodiment's solution enables verification of complex scenarios involving multiple random configuration changes during data reception or transmission by the SGPIO master module, recording interrupt states for different interrupt triggering methods, and fully random verification of the SGPIO master module's interrupt status register value, improving the comprehensiveness and effectiveness of SGPIO master module testing.

[0138] Figure 7This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 7 As shown, the electronic device may include: a processor 710, a communications interface 720, a memory 730, and a communication bus 740. The processor 710, communications interface 720, and memory 730 communicate with each other via the communication bus 740. The processor 710 can call logical instructions in the memory 730 to execute a fully randomized test method for the SGPIO master module. This method includes: defining and instantiating a configuration object for each SGPIO master module protocol mode, and simultaneously passing the configuration object to the APB driver component, the SGPIO driver component, and the SGPIO sampling component; after the APB driver component receives the APB bus write transaction generated by the sequencer, it determines whether the APB bus write transaction is an SGPIO control register configuration transaction; if the APB bus write transaction is an SGPIO control register configuration transaction, it parses the parallel write data written by the APB bus to obtain configuration information; and modifies the SGPIO according to the configuration information. The master module's configuration object enables the SGPIO driver component or SGPIO sampling component to change the protocol mode in a timely manner; multiple reference models of interrupt status are instantiated in the basic test class; in the test case component, the reference model is selected using the override mechanism based on the currently verified interrupt triggering method; the expected value of the interrupt status register is calculated by receiving SGPIO serial port driver transactions twice based on the current reference model; the actual value of the interrupt status register is read from the APB bus through the APB sampling component via the basic reference model, and the expected value and the actual value of the interrupt status register are compared to achieve fully random verification of the interrupt status register value of the SGPIO master module.

[0139] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0140] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the fully random testing method for the SGPIO master module provided by the above methods. The method includes: defining and instantiating a configuration object for each SGPIO master module protocol mode, and simultaneously passing the configuration object for each SGPIO master module protocol mode to the APB driver component, the SGPIO driver component, and the SGPIO sampling component; after the APB driver component receives the APB bus write transaction generated by the sequencer, determining whether the APB bus write transaction is an SGPIO control register configuration transaction; if the APB bus write transaction is an SGPIO control register configuration transaction, parsing the parallel write data of the APB bus to obtain configuration information; and modifying the SGPIO according to the configuration information. The master module's configuration object enables the SGPIO driver component or SGPIO sampling component to change the protocol mode in a timely manner; multiple reference models of interrupt status are instantiated in the basic test class; in the test case component, the reference model is selected using the override mechanism based on the currently verified interrupt triggering method; the expected value of the interrupt status register is calculated by receiving SGPIO serial port driver transactions twice based on the current reference model; the actual value of the interrupt status register is read from the APB bus through the APB sampling component via the basic reference model, and the expected value and the actual value of the interrupt status register are compared to achieve fully random verification of the interrupt status register value of the SGPIO master module.

[0141] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a fully randomized testing method for the SGPIO master module provided by the methods described above. This method includes: defining and instantiating a configuration object for the protocol mode of each SGPIO master module, and configuring each SGPIO... The configuration object of the master module protocol mode is simultaneously passed to the APB driver component, SGPIO driver component, and SGPIO sampling component. After the APB driver component receives the APB bus write transaction generated by the sequencer, it determines whether the APB bus write transaction is an SGPIO control register configuration transaction. If the APB bus write transaction is an SGPIO control register configuration transaction, it parses the parallel write data written by the APB bus to obtain the configuration information. Based on the configuration information, it modifies the configuration object of the SGPIO master module so that the SGPIO driver component or SGPIO sampling component can change the protocol mode in a timely manner. Multiple reference models of interrupt status are instantiated in the basic test class. In the test case component, the reference model is selected using the override mechanism according to the currently verified interrupt triggering method. Based on the current reference model, the expected value of the interrupt status register is calculated by receiving the SGPIO serial port driver transaction twice. The actual value of the interrupt status register is read from the APB bus by the APB sampling component through the basic reference model, and the expected value and the actual value of the interrupt status register are compared to achieve fully random verification of the interrupt status register value of the SGPIO master module.

[0142] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0143] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent selections can be made to some of the technical features; and these modifications or selections do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fully randomized testing method for an SGPIO master module, characterized in that, include: Define and instantiate a configuration object for each SGPIO master module protocol mode, and pass the configuration object for each SGPIO master module protocol mode to the APB driver component, the SGPIO driver component, and the SGPIO sampling component simultaneously. After the APB driver component receives the APB bus write transaction generated by the sequencer, it determines whether the APB bus write transaction is an SGPIO control register configuration transaction. If the APB bus write transaction is an SGPIO control register configuration transaction, then parse the parallel write data written by the APB bus to obtain the configuration information; Modify the configuration object of the SGPIO master module according to the configuration information so that the SGPIO driver component or the SGPIO sampling component can change the protocol mode in a timely manner. Instantiate multiple reference models of interrupt states in the basic test class; In the test case component, the reference model is selected using the override mechanism based on the currently verified interruption triggering method. Based on the current reference model, the expected value of the interrupt status register is calculated by receiving SGPIO serial port drive transactions twice. The actual value of the interrupt status register is read from the APB bus by the APB sampling component through the basic reference model, and the expected value of the interrupt status register is compared with the actual value of the interrupt status register to achieve fully random verification of the interrupt status register value of the SGPIO master module.

2. The fully random testing method for the SGPIO master module according to claim 1, characterized in that, The definition and instantiation of the configuration object for the protocol mode of each SGPIO master module includes: Derive the SGPIO configuration class from the UVM object class, and define members in the SGPIO configuration class to configure the protocol mode of the SGPIO driver component and the SGPIO sampling component; The handle of the SGPIO configuration class is defined in the basic test class, SGPIO driver component, SGPIO sampling component, and APB driver component; In the basic test class component, instantiate objects configuring the protocol modes of the first SGPIO master module and the second SGPIO master module to obtain the first instance and the second instance.

3. The fully random testing method for the SGPIO master module according to claim 2, characterized in that, The step of modifying the configuration object of the SGPIO master module according to the configuration information, so that the SGPIO driver component or the SGPIO sampling component can change the protocol mode in a timely manner, includes: Configure the first instance and the second instance according to the configuration information; In the SGPIO driver component and SGPIO sampling component, the object pointed to by the handle of the SGPIO configuration class is copied in the task of serial port driving the first SGPIO master module and the second SGPIO master module; The members of the object pointed to by the handle of the SGPIO configuration class are parsed to configure the protocol mode of this driving transaction. The protocol mode of the driving transaction includes endianness between bytes and within bytes, number of bytes sent, and MCK or MLD signal toggling.

4. The fully random testing method for the SGPIO master module according to claim 1, characterized in that, The step of determining whether the APB bus write transaction is an SGPIO control register configuration transaction includes: The address of each write transaction to the APB bus is detected by the task defined in the APB driver component. The system checks whether the address matches the control register address of the first SGPIO master module or the control register address of the second SGPIO master module. If they match, the system determines that the APB bus write transaction is an SGPIO control register configuration transaction; otherwise, the system determines that the APB bus write transaction is not an SGPIO control register configuration transaction.

5. The fully randomized testing method for the SGPIO master module according to any one of claims 1-4, characterized in that, The step of receiving SGPIO serial port driver transactions twice based on the current reference model and calculating the expected value of the interrupt status register includes: Get the current SGPIO serial port transaction and the previous SGPIO serial port transaction of the current reference model, which are latched by the SGPIO driver component. Analyze the current SGPIO serial port transaction and the previous SGPIO serial port transaction to determine the interrupt triggering method; The calculation method for the current interrupt status value is determined based on the interrupt triggering method. Based on the calculation method of the current interrupt status value, the expected value of the interrupt status register is calculated based on the current SGPIO serial port transaction and the previous SGPIO serial port transaction.

6. The fully random testing method for the SGPIO master module according to any one of claims 1-4, characterized in that, The various reference models include a high-level reference model, a low-level reference model, a rising edge reference model, a falling edge reference model, and a double-edge reference model; the various reference models for instantiating interrupt states in the basic test class specifically include: A base reference model class is derived from the UVM component class, and then the high-level reference model, the low-level reference model, the rising edge reference model, the falling edge reference model, and the double-edge reference model are derived from the base reference model class, corresponding to the five interrupt triggering methods of high level, low level, rising edge, falling edge, and double-edge, respectively.

7. A fully random testing device for an SGPIO master module, characterized in that, include: The configuration module is used to define and instantiate the configuration object of each SGPIO master module protocol mode, and simultaneously pass the configuration object of each SGPIO master module protocol mode to the APB driver component, the SGPIO driver component, and the SGPIO sampling component. The processing module is used to determine whether the APB bus write transaction is an SGPIO control register configuration transaction after the APB driver component receives the APB bus write transaction generated by the sequencer; if the APB bus write transaction is an SGPIO control register configuration transaction, then the parallel write data of the APB bus is parsed to obtain the configuration information. The modification module is used to modify the configuration object of the SGPIO master module according to the configuration information, so that the SGPIO driver component or the SGPIO sampling component can change the protocol mode in a timely manner. The instantiation module is used to instantiate various reference models of interrupt states in the base test class; The pattern selection module is used in the test case component to select a reference model based on the currently verified interruption triggering method using the override mechanism. The calculation module is used to calculate the expected value of the interrupt status register based on the two SGPIO serial port drive transactions received from the current reference model. The verification module is used to receive the actual value of the interrupt status register read from the APB bus by the APB sampling component through the basic reference model, and compare the expected value of the interrupt status register with the actual value of the interrupt status register to realize the fully random verification of the interrupt status register value of the SGPIO master module.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the fully randomized testing method for the SGPIO master module as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the fully randomized testing method for the SGPIO master module as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the fully randomized testing method for the SGPIO master module as described in any one of claims 1 to 6.

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