1553B bus scheduling method and device, electronic equipment and storage medium

Abstract

The invention provides a 1553B bus scheduling method and device, electronic equipment and a storage medium, and particularly relates to the technical field of 1553B bus scheduling. The method comprises the steps that an application layer kernel generates a BC control command and writes the BC control command into an SRAM; the first driving layer kernel reads the BC control command from the SRAM and sends first 1553B bus data to the first data interaction device through the first 1553B bus according to the BC control command; the application layer kernel generates an RT control command and writes the RT control command into the SRAM; the kernel of the second driving layer reads the RT control command from the SRAM, and receives second 1553B bus data sent by second data interaction equipment through a second 1553B bus according to the RT control command; the application layer kernel generates an MT control command and writes the MT control command into the SRAM; and the kernel of the third driving layer reads the MT control command from the SRAM, and receives monitoring data sent by third data interaction equipment through a third 1553B bus according to the MT control command. According to the method, the universality, the multi-mode and the tailorability of the 1553B bus scheduling system are realized.

Description

Technical Field

[0001] The present application relates to the technical field of 1553B bus scheduling, and in particular to a 1553B bus scheduling method, device, electronic device and storage medium. Background Art

[0002] The 1553B (MIL-STD-1553B) bus is a time-division command / response multiplexed data bus inside an aircraft. The 1553B bus can connect 31 remote terminals and uses a command / response communication protocol. The terminal types of the 1553B bus include: BC (Bus Controller), RT (Remote Terminal) and MT (Monitor Terminal). The data information formats transmitted by the 1553B bus include BC to RT, RT to BC, RT to RT, broadcast mode and mode control mode. The transmission medium used by the 1553B bus is shielded twisted pair. The coupling modes of the 1553B bus include direct coupling and transformer coupling. The 1553B bus is a multi-redundancy bus topology with bidirectional transmission characteristics. Its transmission speed is 1Mbps, the transmission mode is half-duplex, and Manchester code is used for encoding and transmission. Due to the reliability of the 1553B bus, it is often used for communication between equipment in the aerospace field.

[0003] In the prior art, two processors are set up, one of which is responsible for processing the general functions of BC, RT and MT of the 1553B bus at the driver layer, and the other processor is responsible for processing the application of data transmitted on the 1553B bus at the application layer. In a multi-mode application scenario, the scheduling flexibility of the 1553B bus is poor.

[0004] Therefore, the poor scheduling flexibility of the processor for the 1553B bus at the driver layer is an existing problem.

[0005] Application Contents In view of this, the purpose of this application is to provide a 1553B bus scheduling method to solve the above problems, realize the common functions of processing BC, RT and MT of the 1553B bus separately at the driver layer, and process the application of data transmitted on the 1553B bus at the application layer.

[0006] In a first aspect, an embodiment of the present application provides a 1553B bus scheduling method, which is applied to a PS processing system: the PS processing system includes: an application layer kernel, a first driver layer kernel, a second driver layer kernel and a third driver layer kernel; the first driver layer kernel is connected to a first 1553B bus, the second driver layer kernel is connected to a second 1553B bus, and the third driver layer kernel is connected to a third 1553B bus; the method includes: The application layer kernel generates BC control commands, RT control commands, and MT control commands; The first driver layer core sends the first 1553B bus data to the first data interaction device through the first 1553B bus according to the BC control command; The second driver layer core receives the second 1553B bus data sent by the second data interaction device through the second 1553B bus according to the RT control command; The third driver layer core receives the monitoring data sent by the third data interaction device through the third 1553B bus according to the MT control command.

[0007] Preferably, the PS processing system further comprises an SRAM static random access memory; the SRAM static random access memory comprises a BC area; the BC area comprises a BC control command area and a BC data area; The step of the first driver layer core sending the first 1553B bus data to the first data interaction device through the first 1553B bus according to the BC control command includes: The first driver layer core reads the BC control command in the BC control command area; The first driver layer core reads the first 1553B bus data from the BC data area according to the BC control command, and sends the first 1553B bus data to the first data interaction device.

[0008] Preferably, the SRAM static random access memory further comprises an RT area; the RT area comprises an RT control command area and an RT data area; The step of the second driver layer core receiving the second 1553B bus data sent by the second data interaction device through the second 1553B bus according to the RT control command includes: The second driver layer core reads the RT control command from the RT control command area; The second driver layer core receives the second 1553B bus data sent by the second data interaction device according to the RT control command; The second driver layer core writes the second 1553B bus data into the RT data area.

[0009] Preferably, the SRAM static random access memory further comprises an MT area; the MT area comprises an MT control command area and an MT data area; The step of receiving, by the third driver layer core, monitoring data sent by the third data interaction device through the third 1553B bus according to the MT control command comprises: The third driver layer core reads the MT control command from the MT control command area; The third driver layer core receives the monitoring data sent by the third data interaction device according to the MT control command; The third driver layer core writes the monitoring data into the MT data area.

[0010] Preferably, the method further comprises: The first driver layer core receives the first 1553B bus data sent by the first data interaction device through the first 1553B bus according to the BC control command.

[0011] Preferably, the method further comprises: The second driver layer core sends the second 1553B bus data to the second data exchange device through the second 1553B bus according to the RT control command.

[0012] Preferably, the method further comprises: The application layer kernel updates the tail pointer; The first driver layer kernel updates the first head pointer; The second driver layer kernel updates the second head pointer; The third driver layer kernel updates the second head pointer.

[0013] The 1553B bus scheduling method provided by this application brings the following beneficial effects: The present application provides a 1553B bus scheduling method, in which the application layer kernel controls the first driver layer kernel to send the first 1553B bus data to the data interaction device through the first 1553B bus, controls the second driver layer kernel to receive the second 1553B bus data sent by the data interaction device through the second 1553B bus, and controls the third driver layer kernel to receive the monitoring data sent by the data interaction device through the third 1553B bus. In this method, the application layer kernel, the first driver layer kernel, the second driver layer kernel and the third driver layer kernel can perform processing work in parallel, realizing the universality, multi-mode and tailorability of the 1553B bus scheduling system, and does not require the support of the operating system, and has good application value.

[0014] In a second aspect, the present application further provides a 1553B bus scheduling device, the device comprising: an application layer kernel, a first driver layer kernel, a second driver layer kernel and a third driver layer kernel; the first driver layer kernel is connected to a first 1553B bus, the second driver layer kernel is connected to a second 1553B bus, and the third driver layer kernel is connected to a third 1553B bus; The application layer kernel is used to generate BC control commands, RT control commands, and MT control commands; The first driver layer core is used to send first 1553B bus data to the first data interaction device through the first 1553B bus according to the BC control command; The second driver layer core is used for receiving the second 1553B bus data sent by the second data interaction device through the second 1553B bus according to the RT control command; The third driver layer core is used to receive the monitoring data sent by the third data interaction device through the third 1553B bus according to the MT control command.

[0015] The 1553B bus scheduling device provided in the embodiment of the present application has the same technical features as the 1553B bus scheduling method provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0016] In a third aspect, the present application also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the beneficial effects of any of the methods described above are achieved, which will not be repeated here.

[0017] In a fourth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the beneficial effects of any of the methods described above are achieved, which will not be repeated here.

[0018] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0019] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A schematic diagram of a 1553B bus scheduling method flow chart provided in an embodiment of the present application; Figure 2 Schematic diagram of the PSOC structure provided for this application; Figure 3 A schematic diagram of the connection relationship between the layer core, the first drive layer core, the second drive layer core, the third drive layer core and the SRAM provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of the SRAM provided for this application; Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0023] To facilitate understanding of this embodiment, the embodiments of the present application are described in detail below.

[0024] The embodiment of the present application provides a 1553B bus scheduling method, which is applied to a PS processing system: the PS processing system includes: an application layer kernel, a first driver layer kernel, a second driver layer kernel and a third driver layer kernel; the first driver layer kernel is connected to a first 1553B bus, the second driver layer kernel is connected to a second 1553B bus, and the third driver layer kernel is connected to a third 1553B bus; Figure 1 As shown, Figure 1 A schematic flow chart of a 1553B bus scheduling method provided in an embodiment of the present application; the method comprises the following steps: S101, the application layer kernel generates a BC control command, a RT control command, and a MT control command.

[0025] Specifically, we take PSOC (Programmable System-on-Chip) of Fudan Microelectronics as an example. Figure 2 As shown, Figure 2 Schematic diagram of the PSOC structure provided for this application. The model of PSOC is JFMQL15T485. PSOC integrates the PS (Processing System) and PL (Programmable Logic) of a quad-core processor with rich features on a single chip. Among them, PS is the core of PSOC. PS works together with on-chip memory, DDR (Double Data Rate) interface, various system functional components, peripheral I / O (Input / Output) interface and PL to form a feature-rich programmable system-on-chip. SRAM300 (Static Random-Access Memory) is a power-off volatile memory that belongs to the internal memory of PSOC and can be accessed by a set of internal buses shared by the four cores on the PS side. The PL end and the PS end in the PSOC interact through the internal bus. The PL end is connected to the first 1553B protocol chip through SPI (Serial Peripheral Interface) 1, the second 1553B protocol chip through SPI2, and the third 1553B protocol chip through SPI3. Among them, the models of the first 1553B protocol chip, the second 1553B protocol chip and the third 1553B protocol chip are all HI-6131. ​​The PL end interacts with the first 1553B protocol chip, the second 1553B protocol chip and the third 1553B protocol chip.

[0026] like Figure 3 As shown, Figure 3 A schematic diagram of the connection relationship between the layer kernel, the first driver layer kernel, the second driver layer kernel, the third driver layer kernel and the SRAM provided in an embodiment of the present application. The above-mentioned application layer kernel 0 is in the PS and connected to the SRAM300. After the application layer kernel 0 generates a BC control command, the BC control command will be written into the SRAM300 so that the first driver layer kernel 1 can read the BC control command from the SRAM300 later. After the application layer kernel 0 generates an RT control command, the RT control command will be written into the SRAM300 so that the second driver layer kernel 2 can read the RT control command from the SRAM300 later. After the application layer kernel 0 generates an MT control command, the MT control command will be written into the SRAM300 so that the first driver layer kernel 3 can read the MT control command from the SRAM300 later.

[0027] S102: The first driver layer core sends first 1553B bus data to the first data interaction device through the first 1553B bus according to the BC control command.

[0028] Specifically, the first driver layer core 1 is pre-configured as BC mode by the application layer core 0, and in BC mode, the first driver layer core 1 is responsible for scheduling the first 1553B bus. The data transmission rate of the first 1553B bus is 1 Mbps.

[0029] With such configuration, the first driver layer core 1 can efficiently schedule the first 1553B bus, realize the general functions of BC, and quickly obtain the response of the first data interaction device, thereby ensuring the timeliness of data transmission on the first 1553B bus.

[0030] S103: The second driver layer core receives the second 1553B bus data sent by the second data interaction device through the second 1553B bus according to the RT control command.

[0031] Specifically, the second driver layer core is pre-configured by the application layer core as RT mode, and in RT mode, the second driver layer core can passively receive or send the second 1553B bus data. The transmission rate of the second 1553B bus data is 1Mbps.

[0032] With such configuration, the second driver layer core 2 can realize the general functions of RT, quickly respond to the second data interaction device, receive the second 1553B bus data, and ensure the timeliness of data transmission on the second 1553B bus during the data transmission process.

[0033] S104: The third driver layer core receives the monitoring data sent by the third data interaction device through the third 1553B bus according to the MT control command.

[0034] Specifically, the third driver layer core 3 is pre-configured by the application layer core 0 as MT mode. In MT mode, the third driver layer core 3 monitors various data streams (monitoring data) transmitted on the third 1553B bus, but does not participate in direct communication on the third 1553B bus. The transmission rate of the monitoring data is 1Mbps.

[0035] With such configuration, the third driver layer core 3 can realize the general functions of the MT, record (write) the monitoring data into the SRAM 300 , and provide the application layer core 0 to read the monitoring data.

[0036] An embodiment of the present application provides a 1553B bus scheduling method, in which the application layer kernel 0 controls the first driver layer kernel 1 to send first 1553B bus data to a data interaction device through a first 1553B bus, controls the second driver layer kernel 2 to receive second 1553B bus data sent by the data interaction device through a second 1553B bus, and controls the third driver layer kernel 3 to receive monitoring data sent by the data interaction device through a third 1553B bus. Compared with the prior art, in which one processor is responsible for processing the general functions of BC, RT and MT of the 1553B bus at the driver layer, and another processor is responsible for processing the application of data transmitted on the 1553B bus at the application layer, in this method, the first driver layer kernel 1, the second driver layer kernel 2, the third driver layer kernel 3 and the application layer kernel 0 can work in the driver layer and the application layer respectively, and the application layer kernel 0 performs writing work (writing BC control commands, RT control commands and MT control commands into SRAM300) or other work, such as data parsing, in the application layer, which does not affect the first driver layer kernel 1, the second driver layer kernel 2, and the third driver layer kernel 3 respectively realizing the general functions of BC, RT and MT in the driver layer. The first driver layer kernel 1, the second driver layer kernel 2, the third driver layer kernel 3 and the application layer kernel 0 do not conflict with each other. In this method, the application layer kernel 0, the first driver layer kernel 1, the second driver layer kernel 2 and the third driver layer kernel 3 can perform processing work in parallel, realizing the universality, multi-mode and tailorability of the 1553B bus scheduling system. In the multi-mode application scenarios of BC, RT and MT, the scheduling flexibility of the 1553B bus is improved, and no operating system support is required, which has good application value. In addition, no additional processor is required, reducing overhead.

[0037] In one embodiment, Figure 4 As shown, Figure 4 A schematic diagram of the structure of the SRAM provided in the present application. The PS processing system also includes an SRAM 300; the SRAM 300 includes a BC area 201, an RT area 202, and an MT area 203; the BC area 201 includes a BC control command area and a BC data area; the RT area 202 includes an RT control command area and an RT data area; the MT area 203 includes an MT control command area and an MT data area. The first driver layer kernel 1 reads the BC control command in the BC control command area, reads the first 1553B bus data from the BC data area according to the BC control command, and sends the first 1553B bus data to the first data interaction device; or receives the first 1553B bus data sent by the first data interaction device through the first 1553B bus according to the BC control command.

[0038] Specifically, the memory of the SRAM 300 is 128KB, the base address is 0xE1FE 0000, and 64KB of memory is reserved as a reserved storage area starting from the base address, wherein the reserved storage area is 0xE1FE 0000-0xE1FF 0000. The last 64KB of memory from 0xE1FF0000-0xE1FF FFFF is divided into BC area 201, RT area 202 and MT area 203 respectively.

[0039] The BC control command area is used to store the configuration parameters and BC control commands of the BC mode; in the RT mode, the application layer kernel 0 can control the first driver layer kernel 1 through the BC control command to implement the scheduling function of the first 1553B bus. The first driver layer kernel 1 can both receive the first 1553B bus data sent by the first data interaction device and send the first 1553B bus data to the first data interaction device. The BC control command is written into the BC control command area by the application layer kernel 0. The application layer kernel 0 can configure the BC mode of the first driver layer kernel 1 according to the configuration parameters of the BC mode.

[0040] With such configuration, the first driver layer core 1 can efficiently manage the receiving process of the first 1553B bus data, realize the general functions of BC, and quickly obtain the response of the first data interaction device, thereby ensuring the accuracy of the first 1553B bus data and the timeliness of the first 1553B bus transmission.

[0041] In one embodiment, the second driver layer core 2 reads the RT control command from the RT control command area; the second driver layer core 2 receives the second 1553B bus data sent by the second data exchange device according to the RT control command, and writes the second 1553B bus data to the RT data area; or the second driver layer core 2 sends the second 1553B bus data to the second data exchange device through the second 1553B bus according to the RT control command.

[0042] Specifically, the RT control command area is used to store the configuration parameters of the RT mode, the RT control command; in the RT mode, the application layer kernel 0 can control the second driver layer kernel 2 through the RT control command to implement the general functions of the RT. The second driver layer kernel 2 can passively receive the second 1553B bus data sent by the second data exchange device, and can also passively send the second 1553B bus data to the second data exchange device, and remain transparent to irrelevant data. The RT control command is written into the RT control command area by the application layer kernel 0. The application layer kernel 0 can configure the second driver layer kernel 2 for RT mode according to the configuration parameters of the RT mode.

[0043] In this manner, the second driver layer core 2 can implement the general functions of RT, quickly respond to the second data interaction device, send the second 1553B bus data to the second data interaction device, and ensure the accuracy of the second 1553B bus data and the timeliness of the second 1553B bus transmission during the data transmission process.

[0044] In one implementation, the third driver layer core 3 reads the MT control command from the MT control command area, receives the monitoring data sent by the third data interaction device according to the MT control command, and writes the monitoring data into the MT data area.

[0045] Specifically, the MT control command area is used to store the configuration parameters and MT control commands of the MT mode; in the MT mode, the third driver layer core 3 monitors various data streams (monitoring data) transmitted on the third 1553B bus; the MT control commands are written into the MT control command area by the application layer core 0; the application layer core 0 can configure the third driver layer core 3 for MT mode according to the configuration parameters of the MT mode.

[0046] In this way, the third driver layer core 3 monitors the data stream transmitted on the third 1553B bus, realizing the general function of MT. The third driver layer core 3 records (writes) the monitoring data into the MT data area, and the application layer core 0 reads the monitoring data.

[0047] In one implementation, the application layer kernel 0 updates the tail pointer; the first driver layer kernel 1 updates the first head pointer; the second driver layer kernel 2 updates the second head pointer; and the third driver layer kernel 3 updates the second head pointer.

[0048] Specifically, the tail pointer includes a first tail pointer, a second tail pointer and a third tail pointer. The first tail pointer and the first head pointer are stored in the BC control command area, the second tail pointer and the second head pointer are stored in the RT control command area, and the third tail pointer and the third head pointer are stored in the MT control command area. The application layer kernel 0 updates the first bit pointer to write the BC control command into the BC control command area; the application layer kernel 0 updates the second bit pointer to write the RT control command into the RT control command area; the application layer kernel 0 updates the third bit pointer to write the MT control command into the MT control command area. The first driver layer kernel 1 updates the first head pointer to read the first 1553B bus data from the BC data area; the second driver layer kernel 2 updates the second head pointer to read the second 1553B bus data from the RC data area; the third driver layer kernel 3 updates the second head pointer to write the monitoring data into the MT data area.

[0049] In this way, the application layer kernel 0 can quickly write the BC control command, RT control command and MT control command into the BC control command area, RT control command area and MT control command area respectively through the tail pointer, thereby improving the writing efficiency of the application layer kernel 0.

[0050] On the basis of the above method embodiment, the embodiment of the present application further provides a 1553B bus scheduling device, which includes: an application layer kernel 0, a first driver layer kernel 1, a second driver layer kernel 2 and a third driver layer kernel 3; the first driver layer kernel 1 is connected to the first 1553B bus, the second driver layer kernel 2 is connected to the second 1553B bus, and the third driver layer kernel 3 is connected to the third 1553B bus; Application layer kernel 0, used to generate BC control commands, RT control commands, and MT control commands; The first driver layer core 1 is used to send the first 1553B bus data to the first data interaction device through the first 1553B bus according to the BC control command; The second driver layer core 2 is used for receiving the second 1553B bus data sent by the second data interaction device through the second 1553B bus according to the RT control command; The third driver layer core 3 is used for receiving the monitoring data sent by the third data interaction device through the third 1553B bus according to the MT control command.

[0051] Preferably, the device further comprises an SRAM static random access memory; the SRAM static random access memory comprises a BC area; the BC area comprises a BC control command area and a BC data area; The first driver layer core 1 is specifically used to read the BC control command in the BC control command area; read the first 1553B bus data from the BC data area according to the BC control command, and send the first 1553B bus data to the first data interaction device.

[0052] Preferably, the SRAM static random access memory further comprises an RT area; the RT area comprises an RT control command area and an RT data area; The second driver layer core 2 is specifically used to read the RT control command from the RT control command area; receive the second 1553B bus data sent by the second data interaction device according to the RT control command; and write the second 1553B bus data into the RT data area.

[0053] Preferably, the SRAM static random access memory further comprises an MT area; the MT area comprises an MT control command area and an MT data area; The third driver layer core 3 is specifically used to read the MT control command from the MT control command area; receive the monitoring data sent by the third data interaction device according to the MT control command; and write the monitoring data into the MT data area.

[0054] Preferably, the first driver layer core 1 is further used to receive the first 1553B bus data sent by the first data interaction device through the first 1553B bus according to the BC control command.

[0055] Preferably, the second driver layer core 2 is further used to send the second 1553B bus data to the second data exchange device through the second 1553B bus according to the RT control command.

[0056] Preferably, the application layer kernel 0 is also used to update the tail pointer; The first driver layer kernel 1 is also used to update the first head pointer; The second driver layer kernel 2 is also used to update the second head pointer; The third driver layer kernel 3 is also used to update the second head pointer.

[0057] The 1553B bus scheduling device provided in the embodiment of the present application has the same technical features as the 1553B bus scheduling method provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0058] An embodiment of the present application also provides an electronic device, including a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement the above-mentioned 1553B bus scheduling method.

[0059] See also Figure 5 As shown, the electronic device includes a processor 100 and a memory 101, wherein the memory 101 stores machine executable instructions that can be executed by the processor 100, and the processor 100 executes the machine executable instructions to implement the above-mentioned 1553B bus scheduling method.

[0060] Further, Figure 5 The electronic device shown further includes a bus 102 and a communication interface 103 , and the processor 100 , the communication interface 103 and the memory 101 are connected via the bus 102 .

[0061] Among them, the memory 101 may include a high-speed random access memory (RAM), and may also include a non-volatile memory (non-volatile memory), such as at least one disk storage. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 103 (which can be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. can be used. The bus 102 can be an ISA (Industrial Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus or an EISA (Enhanced Industry Standard Architecture) bus, etc. The above-mentioned bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0062] The processor 100 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 100. The above processor 100 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution. The software module may be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 101, and the processor 100 reads the information in the memory 101 and completes the steps of the method of the above embodiment in combination with its hardware.

[0063] This embodiment also provides a machine-readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the above-mentioned 1553B bus scheduling method.

[0064] The computer program product of the 1553B bus scheduling method, device, and electronic device provided in the embodiments of the present application includes a computer-readable storage medium storing program code, and the instructions included in the program code can be used to execute the method described in the previous method embodiment. The specific implementation can refer to the method embodiment, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the previous method embodiment, which will not be repeated here.

[0065] In addition, in the description of the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium that can be executed by a processor. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0066] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0067] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A 1553B bus scheduling method, characterized in that: Applied to PS processing system: the PS processing system comprises: an application layer kernel, a first driver layer kernel, a second driver layer kernel and a third driver layer kernel; the first driver layer kernel is connected to a first 1553B bus, the second driver layer kernel is connected to a second 1553B bus, and the third driver layer kernel is connected to a third 1553B bus; the method comprises: The application layer kernel generates BC control commands, RT control commands, and MT control commands; The first driver layer core sends the first 1553B bus data to the first data interaction device through the first 1553B bus according to the BC control command; The second driver layer core receives the second 1553B bus data sent by the second data interaction device through the second 1553B bus according to the RT control command; The third driver layer core receives the monitoring data sent by the third data interaction device through the third 1553B bus according to the MT control command.

2. The 1553B bus scheduling method according to claim 1, characterized in that: The PS processing system further includes an SRAM static random access memory; the SRAM static random access memory includes a BC area; the BC area includes a BC control command area and a BC data area; The step of the first driver layer core sending the first 1553B bus data to the first data interaction device through the first 1553B bus according to the BC control command includes: The first driver layer core reads the BC control command in the BC control command area; The first driver layer core reads the first 1553B bus data from the BC data area according to the BC control command, and sends the first 1553B bus data to the first data interaction device.

3. The 1553B bus scheduling method according to claim 1 or 2, characterized in that: The SRAM static random access memory also includes an RT area; the RT area includes an RT control command area and an RT data area; The step of the second driver layer core receiving the second 1553B bus data sent by the second data interaction device through the second 1553B bus according to the RT control command includes: The second driver layer core reads the RT control command from the RT control command area; The second driver layer core receives the second 1553B bus data sent by the second data interaction device according to the RT control command; The second driver layer core writes the second 1553B bus data into the RT data area.

4. The 1553B bus scheduling method according to claim 1 or 2, characterized in that: The SRAM static random access memory also includes an MT area; the MT area includes an MT control command area and an MT data area; The step of receiving, by the third driver layer core, monitoring data sent by the third data interaction device through the third 1553B bus according to the MT control command comprises: The third driver layer core reads the MT control command from the MT control command area; The third driver layer core receives the monitoring data sent by the third data interaction device according to the MT control command; The third driver layer core writes the monitoring data into the MT data area.

5. The 1553B bus scheduling method according to claim 1, characterized in that: The method further comprises: The first driver layer core receives the first 1553B bus data sent by the first data interaction device through the first 1553B bus according to the BC control command.

6. The 1553B bus scheduling method according to claim 1, characterized in that: The method further comprises: The second driver layer core sends the second 1553B bus data to the second data exchange device through the second 1553B bus according to the RT control command.

7. The 1553B bus scheduling method according to claim 1, characterized in that: The method further comprises: The application layer kernel updates the tail pointer; The first driver layer kernel updates the first head pointer; The second driver layer kernel updates the second head pointer; The third driver layer kernel updates the second head pointer.

8. A 1553B bus scheduling device, characterized in that: The device comprises: an application layer kernel, a first driver layer kernel, a second driver layer kernel and a third driver layer kernel; the first driver layer kernel is connected to a first 1553B bus, the second driver layer kernel is connected to a second 1553B bus, and the third driver layer kernel is connected to a third 1553B bus; The application layer kernel is used to generate BC control commands, RT control commands, and MT control commands; The first driver layer core is used to send first 1553B bus data to the first data interaction device through the first 1553B bus according to the BC control command; The second driver layer core is used for receiving the second 1553B bus data sent by the second data interaction device through the second 1553B bus according to the RT control command; The third driver layer core is used to receive the monitoring data sent by the third data interaction device through the third 1553B bus according to the MT control command.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 7 are executed.

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