A bus communication module, method and device, electronic equipment, chip and medium

Abstract

The present disclosure provides a bus communication module and method, and relates to the field of bus flow control. The bus communication module comprises a bus interconnection component having a master device interface and a slave device interface, the master device interface being configured to receive bus signals, and the slave device interface being configured to output bus signals; a bridge component connected to the master device interface of the bus interconnection component, the bridge component comprising a command channel, the bus signals comprising command signals and pressure signals corresponding to the command signals, and the command channel being configured to transmit the command signals; and a pressure channel connected to the bridge component, the pressure channel being configured to transmit the pressure signals and adjust pressure values of the pressure signals, so that the slave device interface of the bus interconnection component outputs command signals of the highest priority in a command queue and command signals of a low priority before the command signals of the highest priority. By adding the pressure channel, the command signals of the high priority are output before the command signals of the low priority, and the tailing problem and the drop problem of the back pressure mechanism are further avoided.

Description

Technical Field

[0001] This disclosure relates to the field of electronic communications, and more particularly to a bus communication module, method and apparatus, electronic device, chip and medium. Background Technology

[0002] As the utilization rate of the chip's internal bus increases, the bus will remain constantly busy, causing slow responses to host-initiated transmission requests. Requests with high real-time requirements need to be completed as quickly as possible. However, some bus architectures lack pressure handling capabilities, resulting in high-priority requests going unanswered, thus increasing system bus transmission latency. Summary of the Invention

[0003] This disclosure provides a bus communication module, method, apparatus, electronic device, chip, and medium. By adding a pressure path to the bus architecture, the pressure path adjusts the pressure value of the pressure signal so that high-priority command signals in the command queue are not blocked by low-priority signals, thereby enabling high-priority signals to complete transmission as quickly as possible and reducing the latency of high real-time transmission requests.

[0004] A first aspect of this disclosure provides a bus communication module, comprising: a bus interconnect component having a master device interface and a slave device interface, the master device interface for receiving bus signals and the slave device interface for outputting bus signals; a bridging component connected to the master device interface of the bus interconnect component, the bridging component including a command path, the bus signals including a command signal and a pressure signal corresponding to the command signal, the command path for transmitting the command signal; and a pressure path connected to the bridging component, the pressure path for transmitting a pressure signal and adjusting the pressure value of the pressure signal so that the slave device interface of the bus interconnect component outputs the highest priority command signal in the command queue and the lower priority command signals preceding the highest priority command signal.

[0005] In some embodiments of this disclosure, the pressure path includes: a first buffer space, which is used to buffer a first pressure signal and a second pressure signal, wherein the first pressure signal is a pressure signal when there is back pressure in the command path, and the second pressure signal is a pressure signal when there is no back pressure in the command path.

[0006] In the above embodiments, by adding a pressure path connected by a bridging component to the original bus communication module, the pressure value of the pressure signal is adjusted through the pressure path so that the high-priority signal in the corresponding command signal is not blocked by the low-priority signal, so that the high-priority transmission request can be transmitted as soon as possible and the delay of the high real-time transmission request is reduced.

[0007] In some embodiments of this disclosure, the pressure path includes: a second buffer space for buffering a first pressure signal, the first pressure signal being a pressure signal in the absence of back pressure in the command path; and a third buffer space for buffering a second pressure signal, the second pressure signal being a pressure signal in the presence of back pressure in the command path.

[0008] In some embodiments of this disclosure, a first end of the bridging component is connected to the master device interface of a first bus interconnect component, and a second end of the bridging component is connected to the slave device interface of a second bus interconnect component.

[0009] In the above embodiments, by adding a pressure path with two buffer spaces to the bus communication module, high-priority transmission requests can be transmitted as quickly as possible, further avoiding trailing and drop problems.

[0010] A second aspect of this disclosure provides a bus communication method, comprising: receiving a first bus signal, the first bus signal including a first command signal and a first pressure signal corresponding to the first command signal; in a pressure signal queue, when at least one second pressure signal exists before the first pressure signal, and the second pressure value of the at least one second pressure signal is less than the first pressure value of the first pressure signal, adjusting the second pressure value to the first pressure value; and outputting at least one second command signal in the command queue and the first command signal, wherein the at least one second command signal corresponds to at least one second pressure signal.

[0011] In some embodiments of this disclosure, in a pressure signal queue, when at least one second pressure signal exists before a first pressure signal, and the second pressure value of the at least one second pressure signal is less than the first pressure value of the first pressure signal, adjusting the second pressure value to the first pressure value includes: adjusting the second pressure value to the first pressure value through a pressure path in a bridging component of a bus communication module, wherein the pressure path is connected to the bridging component of the bus communication module, and the bridging component includes a command path for transmitting command signals.

[0012] In some embodiments of this disclosure, adjusting a second pressure value to a first pressure value via a pressure path in a bridging component of a bus communication module includes: storing a first pressure signal in a first buffer space of the pressure path, wherein the first buffer space also stores at least one second pressure signal; determining the first pressure value to be the maximum value of all pressure signals in the first buffer space; and adjusting the second pressure value to the first pressure value.

[0013] In some embodiments of this disclosure, adjusting the second pressure value to the first pressure value via the pressure path in the bridging component of the bus communication module includes: storing the first pressure signal in a second buffer space when there is no back pressure in the command path, and storing the first pressure signal in a third buffer space when there is back pressure in the command path; determining the first maximum pressure value of all pressure signals in the second buffer space, and determining the second maximum pressure value of all pressure signals in the third buffer space; taking the larger of the first maximum pressure value and the second maximum pressure value as the first pressure value, and adjusting the second pressure value to the first pressure value.

[0014] In some embodiments of this disclosure, storing the first pressure signal in the second buffer space when there is no back pressure in the command path and storing the first pressure signal in the third buffer space when there is back pressure in the command path includes: storing the first pressure signal in the second buffer space when there is no back pressure in the command path; storing the first pressure signal in the third buffer space when there is back pressure in the command path and the third buffer space is not full; and discarding the first pressure signal when there is back pressure in the command path and the third buffer space is full.

[0015] In the above embodiments, by adjusting the larger pressure value in the pressure signal queue to the pressure value of the output pressure signal, the command channel outputs the corresponding command signal, enabling high-priority transmission requests to be transmitted as quickly as possible. Furthermore, by setting up two buffer spaces, the trailing and drop problems of a single buffer space are further avoided.

[0016] A third aspect of this disclosure provides a bus communication device, comprising: a receiving module for receiving a first bus signal, the first bus signal including a first command signal and a first pressure signal corresponding to the first command signal; a pressure module for adjusting a second pressure value to a first pressure value in a pressure signal queue when at least one second pressure signal precedes the first pressure signal and the second pressure value of the at least one second pressure signal is less than the first pressure value of the first pressure signal; and a command module for outputting at least one second command signal in a command queue and the first command signal, the at least one second command signal corresponding to at least one second pressure signal.

[0017] A fourth aspect of this disclosure provides an electronic device including: a processor and a memory for storing a computer program capable of running on the processor, wherein the processor, when running the computer program, performs the method described in any of the embodiments of the second aspect of this disclosure.

[0018] A fifth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the methods described in any of the embodiments of the second aspect of this disclosure.

[0019] A sixth aspect of this disclosure provides a chip including at least one processor and a communication interface, the communication interface being used to receive signals input to the chip or output signals from the chip, the processor communicating with the communication interface and implementing the methods described in any of the second aspects through logic circuits or executing code instructions.

[0020] In summary, the bus communication module, method, apparatus, electronic device, chip, and medium disclosed herein include: a bus interconnect component having a master device interface and a slave device interface, the master device interface for receiving bus signals and the slave device interface for outputting bus signals; a bridging component connected to the master device interface of the bus interconnect component, the bridging component including a command path, the bus signals including command signals and pressure signals corresponding to the command signals, the command path for transmitting command signals; and a pressure path connected to the bridging component, the pressure path for transmitting pressure signals and adjusting the pressure value of the pressure signals so that the slave device interface of the bus interconnect component outputs the highest priority command signal in the command queue and the lower priority command signals preceding the highest priority command signal. The bus communication module disclosed herein, by adding a pressure path connected to the bridging component, adjusts the pressure value of the pressure signal through the pressure path to ensure that high-priority signals in the command signals are not blocked by low-priority signals, enabling high-priority transmission requests to be transmitted as quickly as possible. Furthermore, by setting two buffer spaces, it avoids the tailing and dropout problems inherent in a single buffer space while achieving rapid transmission.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0023] Figure 1 This is a schematic diagram of the architecture of a bus communication module proposed in an embodiment of this disclosure;

[0024] Figure 2 This is a schematic diagram of the architecture of a bus communication module proposed in an embodiment of this disclosure;

[0025] Figure 3 This is a flowchart of a bus communication method proposed in an embodiment of the present disclosure;

[0026] Figure 4 This is a schematic diagram of the process for adjusting the pressure value according to an embodiment of this disclosure;

[0027] Figure 5 This is a schematic diagram of the process for adjusting the pressure value according to an embodiment of this disclosure;

[0028] Figure 6 This is a flowchart illustrating the bus communication method proposed in the embodiments of this disclosure;

[0029] Figure 7A This is a schematic diagram of an AXI bus architecture with pressure capability provided in this disclosure;

[0030] Figure 7B This is a schematic diagram of the push function provided in this disclosure;

[0031] Figure 8A A schematic diagram of a dual-buffered AXI bus architecture with pressure capability provided in this disclosure;

[0032] Figure 8B This is a schematic diagram of the push function provided in this disclosure;

[0033] Figure 9 This is a schematic diagram of the structure of a bus communication device according to an embodiment of the present disclosure;

[0034] Figure 10 This is a schematic diagram of the structure of the electronic device proposed in the embodiments of this disclosure;

[0035] Figure 11 This is a schematic diagram of the chip structure proposed in an embodiment of this disclosure. Detailed Implementation

[0036] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0037] In large-scale chips, Advanced eXtensible Interface (AXI) buses utilize Network Interface Controllers (NICs) and Network-on-Chip (NoC) buses. These NICs and NOCs link multiple master and slave interfaces, distributing bus transmission requests to different interfaces. AXI4 and later buses inherently possess Quality of Service (QoS) signals, which can be used to adjust the priority of bus transmission responses. However, QoS typically operates on controllers of storage devices such as Double Data Rate (DDR) memory and lacks the ability to regulate the internal transmission process of transmission requests. NOC buses generally have the ability to adjust the priority of transmission requests initiated by the master node in arbitration within the NOC via pressure signals. Higher priority requests are more likely to win arbitration and thus be transmitted from the NOC. The pressure signals required by the NOC originate from upstream of the bus. When the bus crosses clock and power domains, an AXI asynchronous bridge is typically used.

[0038] Common asynchronous bridges lack pressure capabilities. When a command with a lower priority header is blocked by other higher priority commands, subsequent higher priority commands cannot be transmitted, resulting in high-priority requests not receiving a response. Some asynchronous bridges can implement pressure capabilities, but there are limitations in their use cases. For example, there may be a trailing problem, where multiple higher priority pressure signals continue to be output after a high-priority pressure signal is output, thus affecting the transmission efficiency of the system bus.

[0039] In summary, to address the technical problems in the related technologies, this disclosure provides a bus communication module and a bus communication method. The bus communication module adds a pressure mechanism during signal transmission by the bridging component, which advances high-priority signals before low-priority signals, thereby increasing the priority of high-priority commands that are blocked in the subsequent stage to participate in arbitration. This allows low-priority commands to quickly win arbitration, thereby releasing the command path and enabling high-priority commands to complete transmission as soon as possible, reducing the latency of high real-time transmission requests.

[0040] The bus communication module and bus communication method provided in this application will be described in detail below with reference to the accompanying drawings.

[0041] First, let's introduce the technical terms used in this publication.

[0042] 1. AXI (Advanced eXtensible Interface): This is a bus protocol designed for high performance, high bandwidth, and low latency on-chip bus. Its address / control and data phases are separated, supporting unaligned data transmission. In burst transmissions, only the starting address is needed. It also features separate read / write data channels, supports outstanding transmission access and out-of-order access, and facilitates timing closure.

[0043] 2. Network-on-Chip (NoC): This is a network-based communication subsystem on an integrated circuit, used for connecting modules within a System on a Chip (SoC) via a router-based packet-switched network. Individual master and slave nodes are cascaded together; both NOC and NIC are used to implement this functionality.

[0044] 3. Clock Domain: This refers to the region controlled by the same clock signal. In a circuit, the clock domain is the area driven by the same clock signal. Signals that cross clock domains require special handling to ensure correct transmission.

[0045] 4. Power Domain: This refers to a region within a chip that contains a set of related circuits and logic that can be independently controlled by power. The concept of a power domain is related to, but different from, a voltage domain. A voltage domain refers to a collection of modules using the same voltage source, while a power domain refers to a collection of modules within the same voltage domain that share the same power switching logic. This means that modules within the same power domain are controlled by the same power switching logic and are powered on and off simultaneously. Modules within a voltage domain can be split into different power domains according to design requirements, thereby achieving more granular power management.

[0046] Figure 1 This is a schematic diagram of the architecture of a bus communication module proposed in an embodiment of this disclosure, as shown below. Figure 1 As shown, the bus communication module includes a bus interconnect component, a bridging component, and a pressure path.

[0047] In some embodiments, the bus interconnect component has a master interface and a slave interface, wherein the master interface is used to receive bus signals and the slave interface is used to output bus signals.

[0048] In some embodiments, the bus interconnect component can be a NOC bus, or a MATRIX bus, NIC bus, AXI bus, etc.

[0049] In some embodiments, the bridging component is connected to the master device interface of the bus interconnect component. The bridging component includes a command path, and the bus signals include command signals and pressure signals corresponding to the command signals. The command path is used to transmit command signals.

[0050] In some embodiments, the bridging component may be an AXI asynchronous bridge, a NOC asynchronous bridge, etc.

[0051] In some embodiments, the bus signal may include command signals, pressure signals, or data signals, and this disclosure does not limit the scope of the signal.

[0052] In some embodiments, a pressure path is connected to a bridging component, the pressure path being used to transmit a pressure signal and adjust the pressure value of the pressure signal so that the slave interface of the bus interconnect component outputs the highest priority command signal in the command queue and the lower priority command signals preceding the highest priority command signal.

[0053] In some embodiments, the pressure path and bridging component are connected upstream of the bus interconnect component, i.e., connected to the master interface of the bus interconnect component. This enables the transmission of the highest priority command signal and lower priority command signals preceding the highest priority command signal to the slave interface of the bus interconnect component, and output to the interface of the downstream component. The bridging component and pressure path can be connected to the master interface directly or indirectly.

[0054] In some embodiments, the pressure path and bridging component can also be connected to the slave interface of the bus interconnect component, i.e., connected downstream of the bus interconnect component. The connection method can be direct or indirect.

[0055] In some embodiments, the pressure path includes a first buffer space for buffering a first pressure signal and a second pressure signal. The first pressure signal is the pressure signal when back pressure exists in the command path, and the second pressure signal is the pressure signal when back pressure does not exist in the command path. The first pressure signal corresponds to the first command signal, and the second pressure signal corresponds to the second command signal.

[0056] Among them, reverse pressure refers to the process where, when the destination does not have the ability to receive signals, it sends a message to the superior to stop transmitting signals and waits until it has the ability to receive signals before transmitting again.

[0057] In some embodiments, the pressure path's cache space shares a set of read / write logic with the command path.

[0058] In some embodiments, the pressure path stores a pressure signal queue in a first buffer space, the pressure signal queue stores a first pressure signal and at least one second pressure signal, and the pressure path uses the maximum value of all pressure signals in the first buffer space as the first pressure value, and adjusts the second pressure value of at least one second pressure signal to the first pressure value.

[0059] In some embodiments, the command path in the bridging component outputs a first command signal corresponding to a first pressure signal and at least one second command signal corresponding to at least one second pressure signal.

[0060] For example, such as Figure 7A The schematic diagram of the bus communication module architecture shown includes a Master end, a Slave end, a Press channel, and a command channel. The Press channel includes a Press buffer for buffering Pressure signals. The Press buffer in the Press channel shares a set of read / write logic with the command channel.

[0061] In some embodiments, a first end of the bridging component is connected to the master interface of a first bus interconnect component, and a second end of the bridging component is connected to the slave interface of a second bus interconnect component.

[0062] In some embodiments, the first bus interconnect component and the second bus interconnect component may be in different clock domains or power domains, or they may be in the same clock domain or power domain, and this disclosure does not limit them.

[0063] For example, Figure 7A The Master and Slave terminals can be in the same clock domain or power domain, or they can be in different clock domains or power domains.

[0064] In the above embodiments, when the first bus interconnect component and the second bus interconnect component are in different clock domains or power domains, cross-domain signal transmission can be achieved.

[0065] In the above embodiments, by adding a pressure path to the bus communication module, the pressure path provides a push function to ensure that high-priority signals are not blocked by low-priority signals, and further enables high-priority signals to be transmitted to the subsequent stage as soon as possible, reducing the latency of high real-time transmission requests.

[0066] Figure 2 This is a schematic diagram of the architecture of a bus communication module proposed in an embodiment of this disclosure, as shown below. Figure 2 As shown, the bus communication module includes a bus interconnect component, a bridging component, and a pressure path. Figure 2 based on Figure 1 The architecture shown can be further improved to address the pressure pathways within it. Figure 1The architecture shown exhibits trailing and drop issues.

[0067] In some embodiments, the bus interconnect component has a master interface and a slave interface, wherein the master interface is used to receive bus signals and the slave interface is used to output bus signals.

[0068] In some embodiments, the bus interconnect component can be a NOC bus, or a MATRIX bus, NIC bus, AXI bus, etc.

[0069] In some embodiments, the bridging component is connected to the master device interface of the bus interconnect component. The bridging component includes a command path, and the bus signals include command signals and pressure signals corresponding to the command signals. The command path is used to transmit command signals.

[0070] In some embodiments, the bridging component may be an AXI asynchronous bridge, a NOC asynchronous bridge, an AXI synchronous bridge, a NOC synchronous bridge, etc.

[0071] In some embodiments, the bus signal may include command signals, pressure signals, and data signals, which are not limited herein.

[0072] In some embodiments, a pressure path is connected to a bridging component, the pressure path being used to transmit a pressure signal and adjust the pressure value of the pressure signal so that the slave interface of the bus interconnect component outputs the highest priority command signal in the command queue and the lower priority command signals preceding the highest priority command signal.

[0073] In some embodiments, the pressure path and bridging component are connected upstream of the bus interconnect component, i.e., connected to the master interface of the bus interconnect component. This enables the transmission of the highest priority command signal and all lower priority command signals preceding the highest priority command signal to the slave interface of the bus interconnect component, and output to the master interface of the downstream component. The bridging component and pressure path can be connected to the master interface directly or indirectly.

[0074] In some embodiments, the pressure path and bridging component can also be connected to the slave interface of the bus interconnect component, i.e., connected downstream of the bus interconnect component. The connection method can be direct or indirect.

[0075] In some embodiments, the pressure path includes a second buffer space and a third buffer space. The second buffer space is used to buffer a first pressure signal, which is the pressure signal when there is no back pressure in the command path. The third buffer space is used to buffer a second pressure signal, which is the pressure signal when there is back pressure in the command path. Back pressure refers to the situation where, when the destination end lacks receiving capability, it sends a feedback to the superior end to cease signal transmission and wait for receiving capability to resume transmission.

[0076] In some embodiments, the second cache space of the pressure path shares a set of read / write logic with the command path.

[0077] For example, such as Figure 8A The architecture diagram shows that the Press channel has two cache spaces. The two cache spaces are not the same standard asynchronous first-in-first-out (FIFO) data memory, but writing and reading data into the cache space follows the first-in-first-out principle. The cache space with backpressure needs to synchronize the write pointer to the read clock domain and the read pointer to the write clock domain. The cache space without backpressure shares a set of read and write logic with the command channel.

[0078] In some embodiments, when there is no back pressure in the command path, the pressure path stores the first pressure signal in the second buffer space, and when there is back pressure in the command path, the first pressure signal stores in the third buffer space; the first maximum pressure value of all pressure signals in the second buffer space is determined, and the second maximum pressure value of all pressure signals in the third buffer space is determined; the larger of the first maximum pressure value and the second maximum pressure value is taken as the first pressure value, and the second pressure value is adjusted to the first pressure value.

[0079] In some embodiments, valid data and invalid data exist in the second cache space and the third cache space. For the second cache space without back pressure, the valid space is divided by the address pointer of the command path. For the third cache space with back pressure, the valid data is determined by the flag signal generated during reading. The maximum value of the valid data in the second cache space and the third cache space is used as the first pressure value, which is the pressure signal that is finally output.

[0080] For example, such as Figure 8B The diagram illustrating the push function shows that the maximum values ​​are determined for both the press buffer with and without backpressure. The larger of the two maximum values ​​is used as the output of the press channel, and the corresponding command signal is output in the command channel. This achieves the goal of outputting high-priority signals as quickly as possible, and compared to... Figure 7A The architecture shown is a Press caching architecture that avoids trailing and drop issues.

[0081] In some embodiments, the command path in the bridging component outputs a first command signal corresponding to a first pressure signal and at least one second command signal corresponding to at least one second pressure signal.

[0082] In some embodiments, when there is no back pressure in the command path, the pressure path stores the first pressure signal in the second buffer space; when there is back pressure in the command path and the third buffer space is not full, the first pressure signal is stored in the third buffer space; when there is back pressure in the command path and the third buffer space is full, the first pressure signal is discarded.

[0083] For example, in such Figure 8A In the architecture shown, when there is no backpressure on the command channel, the pressure signal is synchronously entered into the buffer space without backpressure along with the command signal. When the command channel is backpressured, if the buffer space with backpressure is not full, the pressure signal is written into the buffer space with backpressure. If the buffer space is full at this time, the current pressure signal is discarded.

[0084] For example, such as Figure 8A The schematic diagram of the bus communication module architecture shown includes a Master end, a Slave end, a Press channel, and a command channel. The Press channel includes a Press buffer with and without reverse pressure, while the command channel includes a command buffer. The two Press buffers process data across clock domains, and the depth of the buffer space is consistent with that of the command channel. Data from both buffers needs to be directly fed into the read clock domain, where valid data is found using read / write pointers. The maximum value of the pressure signal is determined in each of the two buffer spaces, and the larger of the two maximum values ​​is used as the output of the Press channel. The command channel then outputs the corresponding command signal.

[0085] In some embodiments, a first end of the bridging component is connected to the master interface of a first bus interconnect component, and a second end of the bridging component is connected to the slave interface of a second bus interconnect component.

[0086] In some embodiments, the first bus interconnect component and the second bus interconnect component may be in different clock domains or power domains, or they may be in the same clock domain or power domain, and this disclosure does not limit them.

[0087] For example, Figure 8A The Master and Slave terminals can be in the same clock domain or power domain, or they can be in different clock domains or power domains.

[0088] In the above embodiment, by setting two buffer spaces in the pressure path to buffer the pressure signal when there is back pressure in the command path and the pressure signal when there is no back pressure in the command path, the maximum value of the pressure signal in the two buffer spaces is determined, and the larger value is used as the pressure value output by the pressure path. This ensures that the command signal of the corresponding command path can be output first, compared to... Figure 1 The bus communication module shown can avoid existing trailing and drop problems.

[0089] In the above embodiment, since the two cache spaces are divided into a cache space with reverse pressure and a cache space without reverse pressure, the deviation of the clock domain will cause the command path and the pressure path to not correspond one-to-one. However, the current cache space without reverse pressure is consistent with the command path. For example, if the pressure value of the pressure signal in the cache space is the maximum pressure value, it will be consistent with the command channel and there will be no drop. At the same time, the signal with the maximum pressure value can be cleared at the accurate time, thereby solving the trailing problem.

[0090] Figure 3 This is a flowchart illustrating a bus communication method proposed in an embodiment of this disclosure. Figure 3 As shown, the method includes the following steps:

[0091] Step 301: Receive the first bus signal.

[0092] In some embodiments, the first bus signal includes a first command signal and a first pressure signal corresponding to the first command signal.

[0093] In some embodiments, the first bus signal further includes a data signal.

[0094] In some embodiments, the first bus signal is currently input to the bus communication module via the bus and received by the master device interface of the bus interconnect component. It includes a first command signal and a first pressure signal. There is a one-to-one correspondence between the first command signal and the first pressure signal. The first pressure signal includes a first pressure value.

[0095] In some embodiments, before the first bus signal, the bus communication module also receives at least one bus signal, which includes a command signal and a pressure signal. The command signal and the pressure signal have a one-to-one correspondence, and the pressure signal includes a pressure value.

[0096] In some embodiments, via such Figure 1 The main device interface of the bus communication module shown receives a first bus signal and at least one second bus signal. The first bus signal and the second bus signal both include corresponding command signals and pressure signals, and the pressure signal includes a pressure value.

[0097] In some embodiments, via such Figure 2 The main device interface of the bus communication module shown receives a first bus signal and at least one second bus signal. The first bus signal and the second bus signal both include corresponding command signals and pressure signals, and the pressure signal includes a pressure value.

[0098] Step 302: In the pressure signal queue, when there is at least one second pressure signal before the first pressure signal, and the second pressure value of the at least one second pressure signal is less than the first pressure value of the first pressure signal, the second pressure value is adjusted to the first pressure value.

[0099] In some embodiments, the pressure signal in the bus signal will enter the pressure signal queue in the buffer space. When the first pressure signal enters the pressure signal queue, there is already at least one second pressure signal in the pressure signal queue, and the second pressure value of the second pressure signal is less than the first pressure value. Then, the second pressure value of at least one second pressure signal preceding the first pressure signal in the pressure signal queue is changed to the first pressure value.

[0100] In some embodiments, a higher pressure value indicates a higher priority. By adjusting the second pressure value to the first pressure value, a high-priority signal is pushed in front of a low-priority signal.

[0101] In some embodiments, the second pressure value is adjusted to the first pressure value through the pressure path in the bridging component of the bus communication module. The pressure path is connected to the bridging component of the bus communication module, and the bridging component includes a command path for transmitting command signals.

[0102] In some embodiments, the specific architecture of the bus communication module can be as follows: Figure 1 The architecture diagram shown can also be as follows: Figure 2 The architecture diagram shown.

[0103] In some embodiments, the pressure signal queue follows the first-in-first-out principle. When the first pressure signal enters the pressure signal queue, at least one second pressure signal already exists in the pressure signal queue. When the second pressure value corresponding to each second pressure signal is lower than the first pressure value, it indicates that the priority of at least one second pressure signal is lower than that of the first pressure signal. The second pressure value is adjusted to the first pressure value, so that the high-priority pressure signal is promoted to the lower end of the queue, that is, the position of entering the queue last is changed to the position of entering the queue first, so that the pressure signal of the first pressure value can be output from the pressure queue.

[0104] Step 303: Output at least one second command signal and the first command signal from the command queue.

[0105] In some embodiments, at least one second command signal corresponds to at least one second pressure signal.

[0106] In some embodiments, the command signals in the command queue correspond to the pressure signals. The second pressure value of the second pressure signal is adjusted to the first pressure value. Therefore, the pressure signal with the first pressure value is output first in the pressure signal queue, and the corresponding first command signal is output first in the command queue.

[0107] In some embodiments, the bridging component of the bus communication module is connected to the pressure path. The pressure path transmits a pressure signal and adjusts the pressure value of the pressure signal, that is, adjusts the second pressure value to the first pressure value. The command path in the bridging component transmits the corresponding command signal. Therefore, when the pressure signal queue in the pressure path outputs the first pressure signal of the first pressure value, the command path outputs the corresponding first pressure signal, that is, the slave interface of the bus interconnect component outputs the command signal with the highest priority in the command queue, as well as the command signal with a lower priority.

[0108] In the above embodiment, by increasing the adjustment of pressure values ​​in the pressure signal queue, the pressure signal with the highest pressure value among the existing pressure signals in the pressure signal queue is adjusted to the position of being output first, so that the high-priority command signal in the corresponding command signal is output first, thereby achieving the purpose of transmitting the high-priority pressure signal to the subsequent stage in advance, and thus achieving the purpose of transmitting the high-priority signal as soon as possible.

[0109] Figure 4 This is a schematic diagram of the process for adjusting the pressure value according to an embodiment of this disclosure. Based on Figure 3 The embodiment shown, Figure 4 right Figure 3 The 302 in the text is further restricted, such as... Figure 4 As shown, it includes:

[0110] Step 401: Store the first pressure signal in the first buffer space of the pressure path.

[0111] In some embodiments, at least one second pressure signal also exists in the first cache space.

[0112] In some embodiments, the pressure path includes a first buffer space for storing pressure signals in the bus signals, and the first buffer space follows the first-in-first-out principle.

[0113] In some embodiments, when the first pressure signal enters the first buffer space of the pressure path, at least one second pressure signal already exists in the first buffer space. The first pressure signal includes a first pressure value, the second pressure signal includes a second pressure value, the first pressure signal corresponds to the first command signal, and the second pressure signal corresponds to the second command signal.

[0114] In some embodiments, the first buffer space of the pressure path is used to store the pressure signal when the command path has back pressure and the pressure signal when the command path does not have back pressure. In other words, regardless of whether there is back pressure in the command path, the pressure signal in the bus signal will enter the first buffer space of the pressure path. When the pressure signal in the first buffer space is output, the corresponding command signal in the command path is output.

[0115] Among them, reverse pressure refers to the process where, when the destination does not have the ability to receive signals, it sends a message to the superior to stop transmitting signals and waits until it has the ability to receive signals before transmitting again.

[0116] In some embodiments, such as Figure 1 The pressure path of the bus communication module shown includes a first buffer space for buffering a first pressure signal and a second pressure signal. The first pressure signal is the pressure signal when there is back pressure in the command path, and the second pressure signal is the pressure signal when there is no back pressure in the command path.

[0117] Step 402: Determine the first pressure value as the maximum value of all pressure signals in the first buffer space.

[0118] In some embodiments, the first pressure value is determined to be the maximum value of all pressure signals in the first buffer space, that is, the first pressure value of the first pressure signal in the currently input first bus signal is the maximum pressure value among all pressure signals in the first buffer space.

[0119] In some embodiments, determining the maximum value of the pressure signal in the first buffer space is used to push the pressure signal with the maximum pressure value to the output position of the buffer space, so that the high-priority pressure signal can be output to the subsequent stage as soon as possible.

[0120] In some embodiments, such as Figure 1 In the first buffer space of the bus communication module shown, the maximum value of the pressure signal stored therein is determined.

[0121] For example, in Figure 7A In the Press channel of the bus communication module shown, the pressure signal enters the Press buffer, and the maximum value of the pressure signal in the Press buffer is determined. That is, as... Figure 7B The diagram shown illustrates the push function, where 15 is defined as the maximum value of the pressure signal in the Press buffer.

[0122] Step 403: Adjust the second pressure value to the first pressure value.

[0123] In some embodiments, the second pressure value is adjusted to the first pressure value, that is, the pressure value of the second pressure signal is adjusted to the pressure value of the first pressure signal. In other words, the pressure signal with higher priority is output to the subsequent stage before the signal with lower priority.

[0124] In some embodiments, Figure 1 The first buffer space of the bus communication module shown adjusts the pressure value of the pressure signal that is below the maximum value to the maximum value determined in step 402.

[0125] For example, in Figure 7A In the Press channel of the bus communication module shown, such as Figure 7B As shown, adjust the pressure value, which is below the maximum value of 15, to 15.

[0126] In the above embodiment, a pressure function is added to the bus communication module, which stores the pressure signal in the currently input bus signal into the pressure signal queue, determines the maximum pressure value in the pressure signal, adjusts the pressure value in the pressure signal queue, and prioritizes the output of the pressure signal with the maximum value, so as to achieve the purpose of outputting high-priority signals as soon as possible and reduce the delay of high real-time transmission requests.

[0127] Figure 5 This is a schematic diagram of the process for adjusting the pressure value according to an embodiment of this disclosure, based on Figure 3 The embodiment shown, Figure 5 right Figure 3 The 302 in the figure is further specified, as shown in the figure. Figure 5 As shown, it includes:

[0128] Step 501: If there is no back pressure in the command path, store the first pressure signal in the second buffer space, and if there is back pressure in the command path, store the first pressure signal in the third buffer space.

[0129] In some embodiments, reverse pressure refers to the process where, when the destination does not have receiving capability, it sends a signal back to the superior to stop transmitting signals and waits for receiving capability to be available before transmitting again.

[0130] In some embodiments, the bridging component of the bus communication module includes a pressure path, which is connected to the bridging component of the bus communication module. The bridging component includes a command path for transmitting command signals.

[0131] In some embodiments, the architecture diagram of the bus communication module can be as follows: Figure 2 As shown, the Press channel includes two buffer spaces: one for when there is no upstream backpressure and one for when there is upstream backpressure. These two buffer spaces can be in the same clock or power domain, or they can be in different clock or power domains. The depth of the buffer space without backpressure is consistent with that of the command channel. The two buffer spaces are independent of each other and have independent read / write logic. The buffer space without backpressure shares read / write logic with the command channel.

[0132] In some embodiments, the pressure path includes a second buffer space and a third buffer space. The second buffer space is used to store the pressure signal when there is no back pressure in the command path, and the third buffer space is used to store the pressure signal when there is back pressure in the command path.

[0133] For example, such as Figure 8A The diagram shows the architecture of the bus communication module. When there is back pressure, the pressure signal enters the Press buffer of the Press channel when there is back pressure, and when there is no back pressure, the pressure signal enters the Press buffer of the Press channel when there is no back pressure.

[0134] In some embodiments, such as Figure 2 In the architecture diagram of the bus communication module shown, the second buffer space is used to buffer the first pressure signal, which is the pressure signal when there is no back pressure in the command path, and the third buffer space is used to buffer the second pressure signal, which is the pressure signal when there is back pressure in the command path.

[0135] Step 502: Determine the first maximum pressure value of all pressure signals in the second buffer space, and determine the second maximum pressure value of all pressure signals in the third buffer space.

[0136] In some embodiments, the second cache space and the third cache space respectively determine the maximum pressure value of the pressure signal cached therein.

[0137] In some embodiments, the read / write logic of the second cache space and the third cache space is inconsistent, and the read / write logic of the second cache space is consistent with the read / write logic of the command path.

[0138] In some embodiments, the second buffer space is not a standard FIFO structure; data can be written to the second buffer when the command channel handshake is successful. Data cached in the second buffer space is directly transferred from the write clock domain to the read clock domain, and valid data is selected through the read / write pointers of the command channel's read clock domain. Data in the second buffer space does not need to be read from the buffer one by one; instead, valid data is directly selected through the read / write pointers of the command channel.

[0139] In some embodiments, the third buffer space is a standard asynchronous FIFO structure, following a first-in, first-out (FIFO) principle. Upstream backpressure writes to this buffer, and reading begins when the downstream buffer is not empty. The read data is then distributed to different address spaces to complete data selection. After data is read from the third buffer space, a flag signal is generated. This flag signal indicates whether the corresponding pressure data is valid, and the flag signal is cleared after the pressure signal from the second buffer space is passed downstream.

[0140] In some embodiments, the second cache space and the third cache space determine the maximum pressure value in different ways. The data in the second cache space and the third cache space contains valid data and invalid data. For the second cache space, valid data is divided by the address pointer of the command channel, while the third cache space determines the valid data by the flag signal generated after reading the data. The second cache space and the third cache space respectively determine the pressure signal of the maximum pressure value in the valid data.

[0141] In some embodiments, such as Figure 2 In the architecture diagram of the bus communication module shown, the second and third buffer spaces respectively determine the maximum pressure value in the pressure signal buffered therein.

[0142] For example, in Figure 8A In the architecture of the bus communication module shown, as Figure 8B As shown, the pressure signals for determining the maximum pressure value are obtained by buffers with and without back pressure.

[0143] Step 503: Take the larger of the first maximum pressure value and the second maximum pressure value as the first pressure value, and adjust the second pressure value to the first pressure value.

[0144] In some embodiments, the second pressure value is adjusted to the first pressure value via a pressure path in the bridging component of the bus communication module.

[0145] In some embodiments, the second and third cache spaces compare the determined maximum pressure values ​​and determine the larger one as the pressure value of the current pressure signal. That is, the pressure value of the second pressure signal preceding the first pressure signal stored in the cache space is adjusted to the determined pressure value of the current pressure signal. Specifically, the first maximum pressure value and the second maximum pressure value are compared, and the larger one is used as the first pressure value, and the second pressure value is adjusted to the first pressure value.

[0146] For example, such as Figure 8B The diagram of the pressure function shows that the maximum value 13 in the buffer without back pressure and the maximum value 12 in the buffer with back pressure are compared to determine that the maximum value of the pressure signal is 13. That is, all pressure values ​​before 13 are adjusted to 13.

[0147] In the above embodiment, by dividing the command path into two buffer spaces to store the pressure signal when there is back pressure and the pressure signal when there is no back pressure, respectively, and determining the maximum pressure value in each buffer space, the larger of the two maximum pressure values ​​is taken as the current output pressure value of the pressure signal queue and pushed to the output of the pressure signal queue, so that high-priority signals are output first, further avoiding... Figure 3 , Figure 4 The trailing and falling issues that occurred during the process.

[0148] Figure 6 This is a flowchart illustrating the bus communication method proposed in an embodiment of this disclosure. Based on Figure 5 The embodiment shown, Figure 6 right Figure 5 Step 501 in the document is further specified. For example... Figure 6 As shown, it includes:

[0149] Step 601: If there is no back pressure in the command path, store the first pressure signal in the second buffer space.

[0150] In some embodiments, when there is no back pressure in the command path, storing the first pressure signal in the second buffer space can be done as follows: Figure 2 In the bus communication module shown, the first pressure signal is stored in the second buffer space of the pressure path.

[0151] For example, in Figure 8A In the architecture, when there is no back pressure on the command channel, the pressure signal is stored in the Press buffer when there is no back pressure.

[0152] Step 602: If there is back pressure in the command path and the third buffer space is not full, store the first pressure signal in the third buffer space; if there is back pressure in the command path and the third buffer space is full, discard the first pressure signal.

[0153] In some embodiments, when there is back pressure in the command path and the third cache space is not full, that is, when there is back pressure in the command path and the pressure signal needs to be stored in the third cache space, and the current third cache space still has storage space.

[0154] In some embodiments, when there is back pressure in the command path and the third cache space is full, that is, when there is back pressure in the command path and the pressure signal needs to be stored in the third cache space, but the current third cache space has no storage space.

[0155] In some embodiments, if there is still storage space in the third buffer space, the pressure signal can be stored in the third buffer space. If there is no storage space in the third buffer space, the pressure signal needs to be discarded. The command signal corresponding to the pressure signal is upstream of the command channel. After the next pressure signal is output, when there is storage space in the third buffer space, it will enter the buffer of the command channel.

[0156] In the above embodiments, the buffer space without backpressure can be filled and filled at any time, while the buffer space with backpressure needs to wait for the buffer space to become available before it can be filled. If the buffer space with backpressure is full, the pressure signal that is currently entering can be discarded. If the command signal of the corresponding command channel has not yet entered, it can wait for the next pressure signal with backpressure to enter before entering the command channel buffer.

[0157] Figure 7A This is a schematic diagram of an AXI bus architecture with pressure capability provided in this disclosure, as shown below. Figure 7A As shown, a pressure signal channel is added around the AXI bus. By pre-transmitting the blocked high-priority pressure signal to the subsequent stage, the priority of the blocked low-priority commands participating in arbitration is increased, allowing the low-priority commands to win arbitration and thus release the command path. In this way, the high-priority commands can be transmitted smoothly. The core function of the AXI asynchronous bridge is: when back pressure downstream of the bus prevents commands from continuing to be transmitted to the subsequent stage, the pressure channel provided by the flow control function transmits the high pressure value of the back pressure to the downstream bus, increasing the priority of the low-priority commands blocking the high-priority commands. This allows the preceding low-priority commands to win arbitration as soon as possible and complete the transmission, thereby achieving the goal of fast transmission of high-priority commands.

[0158] like Figure 7A As shown, the bus communication module includes a Master end, a Slave end, a Press channel, and a command channel. After the bus signal enters, the pressure signal enters the Press channel, and the command signal enters the command channel. In the AXI bus architecture with pressure capability, a push function is added. The pressure buffer channel uses an asynchronous FIFO structure. After the upstream input `press_in` enters the buffer, it is read sequentially from the downstream, and the maximum value is selected from the read `press_out` as the pressure for subsequent commands. Since the output of the pressure buffer channel does not perform backpressure, data is retrieved from the buffer one by one as long as the buffer is not empty. This scheme uses the `pressure_max_up` signal to determine whether to update the `pressure_max` output value. However, the implementation logic of the `pressure_max_up` signal relies on the decrementing value of the counter `cnt`. When a high-priority pressure signal is pushed out in advance, multiple high-priority transmission requests will continue to be maintained after the corresponding command transmission is successful, which may lead to a trailing problem.

[0159] like Figure 7BThe diagram illustrates the push function. When a priority 15 transmission request is blocked by a priority 1 transmission request, the higher priority request is pushed to the next stage ahead of time. Ultimately, the priority 15 transmission request will be output from the bus earlier than a transmission request without the push function. However, after the priority 15 transmission request has passed normally, it will continue to participate in arbitration at priority 15 for a period of time. This will increase the delay of high-priority commands at input port 2, leading to tailing and dropout problems.

[0160] To address the aforementioned trailing and drop issues, this disclosure proposes a dual-buffered AXI bus architecture with pressure capability, such as... Figure 8A The diagram shows a dual-buffered AXI bus architecture with pressure capability. It includes a Press channel and a Command channel, where the Press channel includes a Press buffer for when there is backpressure and a Press buffer for when there is no backpressure.

[0161] like Figure 8A As shown, two buffer spaces are provided for the Pressure signal: one for when there is no upstream backpressure and one for when there is upstream backpressure. The two buffer spaces are processed across clock domains separately. The depth of the buffer space without backpressure is consistent with the command channel. The two buffer spaces are not a standard asynchronous FIFO (First Input First Output), but writing data to and reading data from the buffer follows a first-in, first-out principle. The pressure buffer with backpressure has independent read / write logic; data is written upstream and read downstream, and the downstream read pointer participates in the upstream write pointer logic. The pressure buffer without backpressure shares read / write logic with the command channel.

[0162] The backpressure buffer structure is a standard asynchronous FIFO structure, following the first-in, first-out (FIFO) principle. Upstream backpressure occurs, writing to this buffer. When the downstream buffer is not empty, reading begins, and the read data is distributed to different address spaces to complete data selection. After data is read from the backpressure buffer, a flag signal is generated. This flag signal indicates whether the corresponding pressure data is valid. The flag signal is cleared after the pressure signal for the non-backpressure channel is passed downstream.

[0163] The buffer without backpressure is not a standard FIFO structure; data can be written to it only after a successful handshake in the command channel. Data in the buffer without backpressure is directly transferred from the write clock domain to the read clock domain, and valid data is selected via the read / write pointers in the command channel's read clock domain. Data without backpressure does not need to be read from the buffer one by one; instead, valid data is directly selected using the read / write pointers in the command channel. Finally, the maximum pressure signal is selected from the valid data in both the backpressure and non-backpressure buffers and output to the downstream.

[0164] When there is no back pressure on the main command channel, the pressure signal is entered into the buffer space without back pressure in sync with the command. When the main command channel is under back pressure, if the buffer space with back pressure is not full, the pressure signal is written into the buffer space. If the buffer space is full, the current pressure signal is discarded.

[0165] like Figure 8B The diagram of the push function shows that the depth of the buffer space with back pressure and the buffer space without back pressure are the same, both being 8. When the command channel has no back pressure, pressure signals 0, 1, 1, 1, 1, 1, 2, and 3 enter the buffer space without back pressure. When the command channel has back pressure, pressure signals 4, 5, 6, 7, 8, 9, 10, 11, and 12 enter the buffer space with back pressure. When the current pressure signal 13 enters, and the command channel has no back pressure, it enters the buffer space without back pressure. The maximum value of the two buffer spaces is selected, which is 13. The pressure values ​​of the signals before pressure signal 13 will all be adjusted to 13, so the pressure channel outputs 13, and the corresponding command channel will output the command signal corresponding to 13.

[0166] The above are as follows Figure 8B The architecture diagram shown enables high-priority transmission commands to be delivered to the subsequent bus as quickly as possible, and solves the problem of... Figure 7A The trailing and falling issues that exist in the process.

[0167] Figure 9 This is a schematic diagram of the structure of a bus communication device 900 according to an embodiment of this disclosure. Figure 9 As shown, the device includes: a receiving module 910, a pressure module 920, and a command module 930.

[0168] The receiving module 910 is used to receive a first bus signal, which includes a first command signal and a first pressure signal corresponding to the first command signal.

[0169] The pressure module 920 is used to adjust the second pressure value to the first pressure value in a pressure signal queue when at least one second pressure signal exists before the first pressure signal and the second pressure value of the at least one second pressure signal is less than the first pressure value of the first pressure signal.

[0170] Command module 930 is used to output at least one second command signal in the command queue and the first command signal, wherein the at least one second command signal corresponds to at least one second pressure signal.

[0171] In some embodiments, the pressure module is further configured to adjust a second pressure value to a first pressure value via a pressure path in a bridging component of a bus communication module. The pressure path is connected to a bridging component of the bus communication module, and the bridging component includes a command path for transmitting command signals.

[0172] In some embodiments, the pressure module is further configured to store a first pressure signal into a first buffer space of the pressure path, the first buffer space also storing at least one second pressure signal; determine the first pressure value as the maximum value of all pressure signals in the first buffer space; and adjust the second pressure value to the first pressure value.

[0173] In some embodiments, the pressure module is further configured to store the first pressure signal in the second buffer space when there is no back pressure in the command path, and store the first pressure signal in the third buffer space when there is back pressure in the command path; determine the first maximum pressure value of all pressure signals in the second buffer space, and determine the second maximum pressure value of all pressure signals in the third buffer space; take the larger of the first maximum pressure value and the second maximum pressure value as the first pressure value, and adjust the second pressure value to the first pressure value.

[0174] In some embodiments, the pressure module is further configured to store the first pressure signal in the second buffer space when there is no back pressure in the command path; store the first pressure signal in the third buffer space when there is back pressure in the command path and the third buffer space is not full; and discard the first pressure signal when there is back pressure in the command path and the third buffer space is full.

[0175] In summary, the bus communication device proposed in this disclosure, by adding a pressure module to the bus communication device, adjusts the second pressure value to the first pressure value when the second pressure value of at least one second pressure signal existing before the first pressure signal is less than the first pressure value of the first pressure signal in the pressure signal queue, thereby outputting the corresponding pressure signal and command signal. This enables high-priority command signals to be transmitted to the subsequent bus as quickly as possible, reducing the latency of high real-time transmission requests. Furthermore, the addition of two buffer spaces in the bus communication transposition avoids the trailing and dropout problems that exist with a single buffer space.

[0176] Figure 10 This is a schematic diagram of the structure of an electronic device 1000 for implementing the above-described bus communication method, according to an exemplary embodiment.

[0177] Reference Figure 10 The electronic device 1000 may include one or more of the following components: a processing component 1002, a memory 1004, a power supply component 1006, a multimedia component 1008, an audio component 1010, an input / output (I / O) interface 1012, a sensor component 1014, and a communication component 1016.

[0178] Processing component 1002 typically controls the overall operation of electronic device 1000, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 1002 may include one or more processors 1020 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 1002 may include one or more modules to facilitate interaction between processing component 1002 and other components. For example, processing component 1002 may include a multimedia module to facilitate interaction between multimedia component 1008 and processing component 1002.

[0179] Memory 1004 is configured to store various types of data to support the operation of electronic device 1000. Examples of this data include instructions for any application or method operating on electronic device 1000, contact data, phonebook data, messages, pictures, videos, etc. Memory 1004 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0180] Power supply component 1006 provides power to various components of electronic device 1000. Power supply component 1006 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 1000.

[0181] Multimedia component 1008 includes a screen that provides an output interface between electronic device 1000 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 1008 includes a front-facing camera and / or a rear-facing camera. When electronic device 1000 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0182] Audio component 1010 is configured to output and / or input audio signals. For example, audio component 1010 includes a microphone (MIC) configured to receive external audio signals when electronic device 1000 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1004 or transmitted via communication component 1016. In some embodiments, audio component 1010 also includes a speaker for outputting audio signals.

[0183] I / O interface 1012 provides an interface between processing component 1002 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0184] Sensor assembly 1014 includes one or more sensors for providing state assessments of various aspects of electronic device 1000. For example, sensor assembly 1014 may detect the on / off state of electronic device 1000, the relative positioning of components such as the display and keypad of electronic device 1000, changes in position of electronic device 1000 or a component of electronic device 1000, the presence or absence of user contact with electronic device 1000, the orientation or acceleration / deceleration of electronic device 1000, and temperature changes of electronic device 1000. Sensor assembly 1014 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1014 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 1014 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0185] Communication component 1016 is configured to facilitate wired or wireless communication between electronic device 1000 and other devices. Electronic device 1000 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 1016 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 1016 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0186] In an exemplary embodiment, the electronic device 1000 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0187] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1004 including instructions, which can be executed by a processor 1020 of an electronic device 1000 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0188] Embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the bus communication method described in the above embodiments of this disclosure.

[0189] Embodiments of this disclosure also provide a computer program product, including a computer program that is executed by a processor using the bus communication method described in the above embodiments of this disclosure.

[0190] The embodiments of this disclosure also propose a chip, including at least one processor and a communication interface. The communication interface is used to receive signals input to the chip or output signals from the chip. The processor communicates with the communication interface and implements the bus communication method described in the above embodiments of this disclosure through logic circuits or executed code instructions.

[0191] Figure 11 This is a schematic diagram illustrating the structure of a chip 1000 for implementing the above-described bus communication method according to an exemplary embodiment. (Refer to...) Figure 11 The chip 1100 includes at least one communication interface 1101 and a processor 1102. The communication interface 1101 is used to receive signals input to the chip 1100 or signals output from the chip 1100. The processor 1102 communicates with the communication interface 1101 and implements the bus communication method described in the above embodiments of this disclosure through logic circuits or execution code instructions.

[0192] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0193] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0194] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of preferred embodiments of this disclosure includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this disclosure pertain.

[0195] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0196] It should be understood that various parts of the embodiments of this disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0197] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0198] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into a single processing module, or each unit can exist physically separately, or two or more units can be integrated into a single module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The aforementioned storage medium can be a read-only memory, a hard disk, or an optical disk, etc.

[0199] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A bus communication module, characterized by, The application relates to a bus communication module, comprising: a bus interconnection component having a master device interface for receiving bus signals and a slave device interface for outputting the bus signals; a bridge component connected to the master device interface of the bus interconnection component, the bridge component comprising a command channel, the bus signals comprising command signals and pressure signals corresponding to the command signals, the command channel being used for transmitting the command signals; a pressure channel comprising at least one buffer space for buffering pressure signals, the pressure signals comprising pressure signals in the case of back pressure in the command channel and / or pressure signals in the case of no back pressure in the command channel, the pressure channel being connected to the bridge component, the pressure channel being used for transmitting the pressure signals and adjusting the pressure values of the pressure signals so that the slave device interface of the bus interconnection component outputs command signals of high priority in the command queue, and high-priority signals are not blocked by low-priority signals.

2. The bus communication module according to claim 1, wherein, The pressure channel comprises: a first buffer space for buffering pressure signals in the case of back pressure in the command channel and pressure signals in the case of no back pressure in the command channel.

3. The bus communication module of claim 1, wherein, The pressure channel comprises: a second buffer space for buffering pressure signals in the case of no back pressure in the command channel; a third buffer space for buffering pressure signals in the case of back pressure in the command channel.

4. The bus communication module according to any one of claims 1 to 3, characterized in that, The first end of the bridge component is connected to the master device interface of the first bus interconnection component, and the second end of the bridge component is connected to the slave device interface of the second bus interconnection component.

5. A bus communication method characterized by, The method is executed by the bus communication module of any one of claims 1-4, comprising: receiving a first bus signal, the first bus signal comprising a first command signal and a first pressure signal corresponding to the first command signal; in the pressure signal queue, when at least one second pressure signal exists before the first pressure signal, and the second pressure value of the at least one second pressure signal is smaller than the first pressure value of the first pressure signal, adjusting the second pressure value to the first pressure value; outputting at least one second command signal in the command queue and the first command signal, the at least one second command signal corresponding to the at least one second pressure signal.

6. The method of claim 5, wherein, The method comprises: adjusting the second pressure value to the first pressure value through a pressure channel in the bridge component of the bus communication module, the pressure channel being connected to the bridge component of the bus communication module, the bridge component comprising a command channel, the command channel being used for transmitting command signals.

7. The method of claim 6, wherein, The adjusting the second pressure value to the first pressure value comprises: storing the first pressure signal in a first buffer space of the pressure passage, the first buffer space also storing the at least one second pressure signal; determining the first pressure value as a maximum value of all pressure signals in the first buffer space; adjusting the second pressure value to the first pressure value.

8. The method of claim 6, wherein, The adjusting the second pressure value to the first pressure value comprises: storing the first pressure signal in a second buffer space when the command passage has no back pressure, and storing the first pressure signal in a third buffer space when the command passage has back pressure; determining a first maximum pressure value of all pressure signals in the second buffer space, and determining a second maximum pressure value of all pressure signals in the third buffer space; taking the greater one of the first maximum pressure value and the second maximum pressure value as the first pressure value, and adjusting the second pressure value to the first pressure value.

9. The method of claim 8, wherein, The storing the first pressure signal in the second buffer space when the command passage has no back pressure, and storing the first pressure signal in the third buffer space when the command passage has back pressure comprises: storing the first pressure signal in the second buffer space when the command passage has no back pressure; storing the first pressure signal in the third buffer space when the command passage has back pressure and the third buffer space is not full; discarding the first pressure signal when the command passage has back pressure and the third buffer space is full.

10. An electronic device, comprising: comprising: a processor and a memory for storing a computer program capable of running on the processor, wherein the processor is configured to execute the computer program to perform the method of any one of claims 5-9.

11. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, The computer instructions are configured to cause a computer to perform the method of any one of claims 5-9.

12. A chip, characterized by comprising at least one processor and a communication interface; the communication interface is configured to receive a signal input into the chip or output from the chip, the processor is in communication with the communication interface and implements the method of any one of claims 5-9 through a logic circuit or execution of code instructions.

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