Method and system for improving SPI (Serial Peripheral Interface) data transmission rate

Abstract

The invention relates to a data communication technology in an automatic test equipment system, in particular to a method and a system for improving SPI (Serial Peripheral Interface) data transmission rate. The method comprises the following steps: outputting a CLKS signal from a slave to a host; and the slave outputs an MISO data signal to the host, and hopping and sampling of the MISO data signal are synchronized with the CLKS signal. The dependency of the MISO data signal on the CLK signal is decoupled by adding the CLKS signal output from the slave to the host, so that the data transmission rate of the SPI is improved.

Description

Technical Field

[0001] The invention relates to data communication technology in an automated test equipment system, in particular to a method and system for improving SPI data transmission rate. Background Art

[0002] In SPI (Serial Peripheral Interface) communication, the transmission rate and signal integrity are affected by the signal transmission delay. SPI is a synchronous, full-duplex, master-slave communication interface that relies on CLK (clock signal) to synchronize the data transmission between the master and the slave. In practical applications, the data transmission delay caused by the physical distance and the internal processing delay of the slave will limit the communication rate and transmission distance of SPI. The main problems faced by the existing technology include:

[0003] 1. Signal transmission delay: In complex systems, the communication distance between FPGAs (field programmable logic arrays) or CPLDs (complex programmable logic devices) is long, and signal transmission delays lead to timing errors in data transitions and sampling, affecting communication quality.

[0004] 2. Transmission rate limitation: In order to alleviate the delay problem, the existing technology reduces the transmission rate of SPI. Although it can increase the time margin and reduce timing errors, it will reduce the overall communication efficiency of the system.

[0005] 3. Trace length limitation: In order to reduce transmission delay, it is usually necessary to reduce the SPI trace length, but this is often limited by physical layout in practical applications. Summary of the invention

[0006] The object of the present invention is to provide a method and system for improving SPI data transmission rate.

[0007] In order to achieve the above object, on the one hand, the present invention provides a method for improving the SPI data transmission rate, the method comprising:

[0008] The slave device outputs the CLK_S signal to the host device;

[0009] The slave device outputs a MISO data signal to the host device, and the transition and sampling of the MISO data signal are synchronized with the CLK_S signal.

[0010] Furthermore, the CLK_S signal and the MISO data signal are routed with equal lengths on the PCB.

[0011] Furthermore, it also includes: the host outputs a MOSI data signal and a CLK signal to the slave, and the jump and sampling of the MOSI data signal are synchronized with the CLK signal.

[0012] Furthermore, the CLK signal and the MOSI data signal are routed with equal lengths on the PCB board.

[0013] Furthermore, the clock frequency of the CLK_S signal is consistent with that of the CLK signal.

[0014] Furthermore, the host also outputs a CS# signal to the slave.

[0015] Furthermore, when the host outputs the MOSI data signal, the CLK signal and the CS# signal, the MOSI data signal jumps at the rising edge of the CLK signal; when the slave receives the MOSI data signal, the CLK signal and the CS# signal, the MOSI data signal is sampled at the falling edge of the CLK signal.

[0016] Furthermore, the slave outputs the MISO data signal and the CLK_S signal, and the MISO data signal jumps at the rising edge of the CLK_S signal; when the host receives the MISO data signal and the CLK_S signal, the MISO data signal is sampled at the falling edge of the CLK_S signal.

[0017] Furthermore, the host and the slave are both FPGA or CPLD.

[0018] In addition, in another aspect of the present invention, a system for improving SPI data transmission rate is also proposed, the system comprising a host, a slave, a PCB trace and a controller;

[0019] The PCB wiring connects the host and the slave, and the controller is used to control the communication between the host and the slave;

[0020] The host comprises an input end and an output end, the output end is used to output a CLK signal and a MOSI data signal, and the input end is used to input the MISO data signal;

[0021] The slave includes an input end and an output end, the input end is used to receive the CLK signal and the MOSI data signal, and the output end is used to output the MISO data signal and the CLK_S signal.

[0022] Compared with the prior art, the present invention has at least the following technical effects:

[0023] The present invention provides a method and system for improving the SPI data transmission rate. By adding a CLK_S signal output by the slave to the host between the host and the slave, the MISO data signal output by the slave no longer depends on the CLK signal of the host, thereby reducing the dependence on clock synchronization during data transmission.

[0024] Furthermore, since the transition and sampling of the MOSI data signal output by the host are synchronized with the CLK signal, and the transition and sampling of the MISO data signal output by the slave are synchronized with the CLK_S signal, the MISO data signal received by the host no longer refers to the CLK signal, and there is no need to leave enough time margin for line delay and sampling and logic delay inside the slave, thereby improving the transmission rate of SPI.

[0025] Furthermore, by ensuring that the CLK signal and the MOSI data signal as well as the CLK_S signal and the MISO data signal are routed with equal length on the PCB, the impact of the delay caused by the routing length on data transmission can be reduced, thereby allowing the routing length of the SPI to be increased without affecting the communication quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the layout of an SPI communication system for a method of increasing the SPI data transmission rate in one embodiment of the present invention;

[0027] Figure 2 FIG. 1 is a schematic diagram of the layout of a prior art SPI communication system in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] A method and system for improving SPI data transmission rate of the present invention will be described in more detail below in conjunction with a schematic diagram, wherein a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation of the present invention.

[0029] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.

[0030] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.

[0031] As mentioned in the background technology, the serial peripheral interface (SPI) is a synchronous, full-duplex, master-slave interface. Data from the SPI Master or SPI Slave is synchronized on the rising or falling edge of the clock, and the host and slave can transmit data at the same time. The SPI device has four signals: CLK, provided by the host, for synchronous data transmission; CS# (chip select signal), used to activate the slave device; MOSI (host output / slave input signal), the host sends data to the slave; MISO (host input / slave output signal), the slave sends data to the host. The device that generates the clock signal is called the host, and the data transmitted between the host and the slave is synchronized with the clock generated by the host. The SPI interface samples or shifts data through the rising or falling edge of the clock.

[0032] For complex systems, multiple microcontrollers FPGA or CPLD are usually used. The communication between FPGA and CPLD often uses the relatively simple SPI. Generally, there is a certain distance between the two microcontrollers, and there is a signal transmission delay. Figure 2 As shown in the figure, the transmission delay of the MOSI data signal from the host to the slave is recorded as T1; the transmission delay of the MISO data signal from the slave to the host is recorded as T2. In addition, there will be a certain delay from the slave receiving the CLK, CS#, and MOSI data signals to the output of the MISO data signal, that is, the time required for internal sampling and logic processing of the slave, recorded as T3. The host samples the MISO signal output by the slave in synchronization with the CLK signal output by the host. In this way, the total transmission delay time between the CLK and MISO data signals is T1+T2+T3. When the delay exceeds the time margin of the MISO data relative to the CLK, it will cause timing errors, so that the microcontroller FPGA or CPLD cannot perform SPI communication normally. To avoid timing errors, the usual practice is to reduce the wiring length or reduce the transmission rate. Although reducing the wiring length helps to reduce the transmission delay, the physical layout will limit the reduction of the length; in addition, reducing the transmission rate can increase the time margin, but it will reduce the communication efficiency and dynamic performance of the system.

[0033] In view of this, if Figure 1 As shown, this embodiment proposes a method for improving the SPI data transmission rate, the method comprising:

[0034] The slave device outputs the CLK_S signal to the host device;

[0035] The slave device outputs a MISO data signal to the host device, and the transition and sampling of the MISO data signal are synchronized with the CLK_S signal.

[0036] Specifically, in this embodiment, a CLK_S signal is added between the host and the slave, the CLK_S signal is output by the slave and input by the host, and the clock frequency of the CLK_S clock signal must be consistent with the CLK signal, thereby ensuring that the frequency of the output signal and the input signal is the same.

[0037] Specifically, the transition and sampling of the MOSI data signal are synchronized with the CLK signal, and the transition and sampling of the MISO data signal are synchronized with the CLK_S signal, so that the transmission rate of the SPI is no longer limited by the time margin of the MISO data signal relative to the CLK signal, thereby shortening the clock cycle of the CLK signal, thereby greatly improving the transmission rate of the SPI.

[0038] In this embodiment, the host and the slave are both FPGA or CPLD. Using FPGA and CPLD as the host and slave for SPI communication can provide a high degree of flexibility, customizability and performance, which helps to achieve the purpose of the present invention, that is, to increase the data transmission rate, and also to increase the wiring length, while ensuring the stability and reliability of communication.

[0039] In this embodiment, the CLK signal is synchronously output from the host and input to the slave with the MOSI data signal. When the host outputs the MOSI, CLK and CS# signals, the MOSI data signal jumps at the rising edge of the CLK signal; when the slave receives the MOSI, CLK and CS# signals, the MOSI data signal is sampled at the falling edge of the CLK signal. During wiring, if the CLK signal and the MOSI data signal have equal lengths on the PCB board, the delays of the two on the routing are consistent, so the delay caused by the routing length does not affect the slave receiving data.

[0040] In this embodiment, the CLK_S signal and the MISO data signal are synchronously output by the slave and input by the host. At this time, the time required for sampling and logic processing of the CLK_S signal and the MISO data signal in the slave is equal. The slave outputs the MISO and CLK_S signals, and the MISO data signal jumps at the rising edge of the CLK_S signal; when the host receives the MISO and CLK_S signals, the MISO data signal is sampled at the falling edge of the CLK_S signal. When wiring, the CLK_S signal and the MISO data signal are routed with equal length on the PCB, so the delay of the two on the route is consistent, so the delay caused by the route length does not affect the host receiving data.

[0041] In this embodiment, the equipment and materials that need to be prepared include two FPGA or CPLD chips, a printed circuit board (PCB), an SPI communication interface, and electronic testing equipment.

[0042] In this embodiment, the following is a further detailed step description of the specific implementation of the present invention:

[0043] S1: PCB layout and wiring

[0044] In PCB design, plan appropriate locations for the two FPGA or CPLD chips and ensure that the distance between them meets system requirements. Plan the routing for the SPI communication interface, including CLK, CS#, MOSI, MISO, and the newly added CLK_S signal lines. Ensure that the lengths of the CLK, CS#, MOSI, MISO, and CLK_S signal lines are as equal as possible to reduce the delay differences caused by the routing length.

[0045] S2: Configure SPI communication interface

[0046] Configure the SPI interface of the host (an FPGA or CPLD) and set the appropriate transmission rate (for example, 100Mbps); configure the SPI interface of the slave (another FPGA or CPLD) to ensure that it is compatible with the configuration of the host.

[0047] S3: Implementing the CLK_S signal

[0048] Generate the CLK_S signal in the slave FPGA or CPLD and ensure that its frequency is consistent with the CLK signal output by the master. Synchronize the CLK_S signal and the MISO signal to ensure that their logic processing time in the slave is equal.

[0049] S4: Data transfer and sampling

[0050] The host sends the MOSI data signal on the rising edge of the CLK signal, and the slave samples the MOSI data signal on the falling edge of the CLK signal; the slave sends the MISO data signal on the rising edge of the CLK_S signal, and the host samples the MISO data signal on the falling edge of the CLK_S signal.

[0051] S5: SPI communication test

[0052] Use electronic test equipment to test SPI communication to ensure the accuracy and stability of data transmission. Adjust the PCB layout and signal line length to optimize communication performance until the expected transmission rate and trace length are achieved.

[0053] S6: Performance Evaluation

[0054] The actual transmission rate and trace length of the SPI communication are recorded and compared with the SPI communication performance without using the CLK_S signal to evaluate the effectiveness of this design method.

[0055] In addition, in another aspect of the present embodiment, a system for improving the SPI data transmission rate is proposed, the system comprising a host, a slave, a PCB trace and a controller; the PCB trace connects the host and the slave, and the controller is used to control the communication between the host and the slave; the host comprises an input end and an output end, the output end is used to output a CLK signal and a MOSI data signal, and the input end is used to input the MISO data signal; the slave comprises an input end and an output end, the input end is used to receive the CLK signal and the MOSI data signal, and the output end is used to output the MISO data signal and the CLK_S signal.

[0056] In summary, in a method and system for improving the SPI data transmission rate provided by an embodiment of the present invention, by adding a CLK_S signal output by the slave to the host between the host and the slave, the MISO data signal output by the slave no longer depends on the CLK signal of the host, thereby reducing the dependence on clock synchronization during data transmission. Since the jump and sampling of the MOSI data signal output by the host are synchronized with the CLK signal, the jump and sampling of the MISO output by the slave are synchronized with the CLK_S signal, and the MISO data signal received by the host no longer refers to the CLK signal, there is no need to leave enough time margin for line delay and sampling and logic delay inside the slave, thereby improving the transmission rate of SPI. In addition, by ensuring that the CLK signal and the MOSI data signal and the CLK_S signal and the MISO data signal are routed with equal length on the PCB, the delay of the routing length on the PCB and the delay of sampling and logic processing inside the slave will not affect the SPI communication, thereby increasing the routing length of the SPI.

[0057] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for improving SPI data transmission rate, characterized in that: The method comprises: The slave device outputs the CLK_S signal to the host device; The slave device outputs a MISO data signal to the host device, and the transition and sampling of the MISO data signal are synchronized with the CLK_S signal.

2. The method according to claim 1, characterized in that: The CLK_S signal and the MISO data signal are routed on the PCB with equal lengths.

3. The method according to claim 1, characterized in that Also includes: The host outputs a MOSI data signal and a CLK signal to the slave, and the transition and sampling of the MOSI data signal are synchronized with the CLK signal.

4. The method according to claim 3, characterized in that The CLK signal and the MOSI data signal are routed on the PCB board with equal length.

5. The method according to claim 3, characterized in that: The clock frequency of the CLK_S signal is consistent with the clock frequency of the CLK signal.

6. The method according to claim 3, characterized in that: The host also outputs a CS# signal to the slave.

7. The method according to claim 6, characterized in that When the host outputs the MOSI data signal, the CLK signal and the CS# signal, the MOSI data signal jumps at the rising edge of the CLK signal; when the slave receives the MOSI data signal, the CLK signal and the CS# signal, the MOSI data signal is sampled at the falling edge of the CLK signal.

8. The method according to claim 3, characterized in that The slave outputs the MISO data signal and the CLK_S signal, and the MISO data signal jumps at the rising edge of the CLK_S signal; when the host receives the MISO data signal and the CLK_S signal, the MISO data signal is sampled at the falling edge of the CLK_S signal.

9. The method according to claim 1, characterized in that: The host and the slave are both FPGA or CPLD.

10. A system using the method according to any one of claims 1 to 9, characterized in that: The system includes a host, a slave, a PCB trace and a controller; The PCB wiring connects the host and the slave, and the controller is used to control the communication between the host and the slave; The host comprises an input end and an output end, the output end is used to output a CLK signal and a MOSI data signal, and the input end is used to input the MISO data signal; The slave includes an input end and an output end, the input end is used to receive the CLK signal and the MOSI data signal, and the output end is used to output the MISO data signal and the CLK_S signal.

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